2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
28 * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.23 2007/04/12 18:35:09 swildner Exp $
33 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
41 #include <sys/param.h>
42 #include <sys/systm.h>
46 #include <sys/dkstat.h>
47 #include <sys/fcntl.h>
48 #include <sys/interrupt.h>
49 #include <sys/kernel.h>
50 #include <sys/thread2.h>
51 #include <machine/clock.h>
53 #include <bus/isa/i386/isa_device.h>
55 #include <machine_base/isa/ic/cd180.h>
59 static int rcprobe (struct isa_device *);
60 static int rcattach (struct isa_device *);
62 #define rcin(port) RC_IN (nec, port)
63 #define rcout(port,v) RC_OUT (nec, port, v)
65 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
66 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
68 #define RC_IBUFSIZE 256
69 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
70 #define RC_OBUFSIZE 512
71 #define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
72 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
73 #define LOTS_OF_EVENTS 64
75 #define RC_FAKEID 0x10
80 #define GET_UNIT(dev) (minor(dev) & 0x3F)
81 #define CALLOUT(dev) (minor(dev) & 0x80)
83 /* For isa routines */
84 struct isa_driver rcdriver = {
85 rcprobe, rcattach, "rc"
88 static d_open_t rcopen;
89 static d_close_t rcclose;
90 static d_ioctl_t rcioctl;
93 static struct dev_ops rc_ops = {
94 { "rc", CDEV_MAJOR, D_TTY | D_KQFILTER },
101 .d_kqfilter = ttykqfilter
104 /* Per-board structure */
105 static struct rc_softc {
106 u_int rcb_probed; /* 1 - probed, 2 - attached */
107 u_int rcb_addr; /* Base I/O addr */
108 u_int rcb_unit; /* unit # */
109 u_char rcb_dtr; /* DTR status */
110 struct rc_chans *rcb_baserc; /* base rc ptr */
113 /* Per-channel structure */
114 static struct rc_chans {
115 struct rc_softc *rc_rcb; /* back ptr */
116 u_short rc_flags; /* Misc. flags */
117 int rc_chan; /* Channel # */
118 u_char rc_ier; /* intr. enable reg */
119 u_char rc_msvr; /* modem sig. status */
120 u_char rc_cor2; /* options reg */
121 u_char rc_pendcmd; /* special cmd pending */
122 u_int rc_dtrwait; /* dtr timeout */
123 u_int rc_dcdwaits; /* how many waits DCD in open */
124 u_char rc_hotchar; /* end packed optimize */
125 struct tty *rc_tp; /* tty struct */
126 u_char *rc_iptr; /* Chars input buffer */
127 u_char *rc_hiwat; /* hi-water mark */
128 u_char *rc_bufend; /* end of buffer */
129 u_char *rc_optr; /* ptr in output buf */
130 u_char *rc_obufend; /* end of output buf */
131 struct callout rc_dtr_ch;
132 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
133 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
134 } rc_chans[NRC * CD180_NCHAN];
136 static int rc_scheduled_event = 0;
137 static struct callout rc_wakeup_ch;
140 static struct tty rc_tty[NRC * CD180_NCHAN];
141 static const int nrc_tty = NRC * CD180_NCHAN;
144 #define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
145 #define RC_ACTOUT 0x0002 /* Dial-out port active */
146 #define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
147 #define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
148 #define RC_DORXFER 0x0010 /* RXFER event planned */
149 #define RC_DOXXFER 0x0020 /* XXFER event planned */
150 #define RC_MODCHG 0x0040 /* Modem status changed */
151 #define RC_OSUSP 0x0080 /* Output suspended */
152 #define RC_OSBUSY 0x0100 /* start() routine in progress */
153 #define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
154 #define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
155 #define RC_SEND_RDY 0x0800 /* ready to send */
157 /* Table for translation of RCSR status bits to internal form */
158 static int rc_rcsrt[16] = {
160 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
161 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
162 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
163 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
164 TTY_BI|TTY_PE|TTY_FE|TTY_OE
167 /* Static prototypes */
168 static inthand2_t rcintr;
169 static void rc_hwreset (int, int, unsigned int);
170 static int rc_test (int, int);
171 static void rc_discard_output (struct rc_chans *);
172 static void rc_hardclose (struct rc_chans *);
173 static int rc_modctl (struct rc_chans *, int, int);
174 static void rc_start (struct tty *);
175 static void rc_stop (struct tty *, int rw);
176 static int rc_param (struct tty *, struct termios *);
177 static inthand2_t rcpoll;
178 static void rc_reinit (struct rc_softc *);
180 static void printrcflags();
182 static timeout_t rc_dtrwakeup;
183 static timeout_t rc_wakeup;
184 static void disc_optim (struct tty *tp, struct termios *t, struct rc_chans *);
185 static void rc_wait0 (int nec, int unit, int chan, int line);
187 /**********************************************/
189 /* Quick device probing */
191 rcprobe(struct isa_device *dvp)
193 int irq = ffs(dvp->id_irq) - 1;
194 int nec = dvp->id_iobase;
196 if (dvp->id_unit > NRC)
198 if (!RC_VALIDADDR(nec)) {
199 kprintf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
202 if (!RC_VALIDIRQ(irq)) {
203 kprintf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
206 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
207 rcout(CD180_PPRH, 0x11);
208 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
210 /* Now, test the board more thoroughly, with diagnostic */
211 if (rc_test(nec, dvp->id_unit))
213 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
219 rcattach(struct isa_device *dvp)
221 int chan, nec = dvp->id_iobase;
222 struct rc_softc *rcb = &rc_softc[dvp->id_unit];
223 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN];
224 static int rc_started = 0;
227 dvp->id_intr = rcintr;
229 /* Thorooughly test the device */
230 if (rcb->rcb_probed != RC_PROBED)
234 rcb->rcb_baserc = rc;
235 rcb->rcb_unit = dvp->id_unit;
236 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
237 kprintf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
238 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
240 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
241 callout_init(&rc->rc_dtr_ch);
244 rc->rc_iptr = rc->rc_ibuf;
245 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
246 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
247 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0;
248 rc->rc_cor2 = rc->rc_pendcmd = 0;
249 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
250 rc->rc_dtrwait = 3 * hz;
253 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
255 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
256 tp->t_cflag = TTYDEF_CFLAG;
257 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
259 rcb->rcb_probed = RC_ATTACHED;
261 dev_ops_add(&rc_ops, -1, rcb->rcb_unit);
262 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll", NULL);
263 callout_init(&rc_wakeup_ch);
270 /* RC interrupt handling */
272 rcintr(void *arg, void *frame)
275 struct rc_softc *rcb = &rc_softc[unit];
278 u_char val, iack, bsr, ucnt, *optr;
279 int good_data, t_state;
281 if (rcb->rcb_probed != RC_ATTACHED) {
282 kprintf("rc%d: bogus interrupt\n", unit);
287 bsr = ~(rcin(RC_BSR));
289 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
290 kprintf("rc%d: extra interrupt\n", unit);
291 rcout(CD180_EOIR, 0);
295 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
296 #ifdef RCDEBUG_DETAILED
297 kprintf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
298 (bsr & RC_BSR_TOUT)?"TOUT ":"",
299 (bsr & RC_BSR_RXINT)?"RXINT ":"",
300 (bsr & RC_BSR_TXINT)?"TXINT ":"",
301 (bsr & RC_BSR_MOINT)?"MOINT":"");
303 if (bsr & RC_BSR_TOUT) {
304 kprintf("rc%d: hardware failure, reset board\n", unit);
309 if (bsr & RC_BSR_RXINT) {
310 iack = rcin(RC_PILR_RX);
311 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
312 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
313 kprintf("rc%d: fake rxint: %02x\n", unit, iack);
316 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
317 t_state = rc->rc_tp->t_state;
318 /* Do RTS flow control stuff */
319 if ( (rc->rc_flags & RC_RTSFLOW)
320 || !(t_state & TS_ISOPEN)
322 if ( ( !(t_state & TS_ISOPEN)
323 || (t_state & TS_TBLOCK)
325 && (rc->rc_msvr & MSVR_RTS)
328 rc->rc_msvr &= ~MSVR_RTS);
329 else if (!(rc->rc_msvr & MSVR_RTS))
331 rc->rc_msvr |= MSVR_RTS);
333 ucnt = rcin(CD180_RDCR) & 0xF;
336 if (t_state & TS_ISOPEN) {
337 /* check for input buffer overflow */
338 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
340 ucnt = rc->rc_bufend - rc->rc_iptr;
342 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
343 rc->rc_flags |= RC_WAS_BUFOVFL;
344 rc_scheduled_event++;
348 /* check foor good data */
351 val = rcin(CD180_RDR);
353 optr[INPUT_FLAGS_SHIFT] = 0;
355 rc_scheduled_event++;
356 if (val != 0 && val == rc->rc_hotchar)
360 /* Store also status data */
362 iack = rcin(CD180_RCSR);
363 if (iack & RCSR_Timeout)
365 if ( (iack & RCSR_OE)
366 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
367 rc->rc_flags |= RC_WAS_SILOVFL;
368 rc_scheduled_event++;
370 val = rcin(CD180_RDR);
372 Don't store PE if IGNPAR and BREAK if IGNBRK,
373 this hack allows "raw" tty optimization
374 works even if IGN* is set.
376 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
377 || ((!(iack & (RCSR_PE|RCSR_FE))
378 || !(rc->rc_tp->t_iflag & IGNPAR))
379 && (!(iack & RCSR_Break)
380 || !(rc->rc_tp->t_iflag & IGNBRK)))) {
381 if ( (iack & (RCSR_PE|RCSR_FE))
382 && (t_state & TS_CAN_BYPASS_L_RINT)
385 && (rc->rc_tp->t_iflag & INPCK))))
387 else if (val != 0 && val == rc->rc_hotchar)
390 optr[INPUT_FLAGS_SHIFT] = iack;
392 rc_scheduled_event++;
397 rc->rc_flags |= RC_DORXFER;
400 /* Clear FIFO if necessary */
401 while (resid-- > 0) {
403 iack = rcin(CD180_RCSR);
406 if (iack & RCSR_Timeout)
408 (void) rcin(CD180_RDR);
412 if (bsr & RC_BSR_MOINT) {
413 iack = rcin(RC_PILR_MODEM);
414 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
415 kprintf("rc%d: fake moint: %02x\n", unit, iack);
418 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
419 iack = rcin(CD180_MCR);
420 rc->rc_msvr = rcin(CD180_MSVR);
423 printrcflags(rc, "moint");
425 if (rc->rc_flags & RC_CTSFLOW) {
426 if (rc->rc_msvr & MSVR_CTS)
427 rc->rc_flags |= RC_SEND_RDY;
429 rc->rc_flags &= ~RC_SEND_RDY;
431 rc->rc_flags |= RC_SEND_RDY;
432 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
433 rc_scheduled_event += LOTS_OF_EVENTS;
434 rc->rc_flags |= RC_MODCHG;
439 if (bsr & RC_BSR_TXINT) {
440 iack = rcin(RC_PILR_TX);
441 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
442 kprintf("rc%d: fake txint: %02x\n", unit, iack);
445 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
446 if ( (rc->rc_flags & RC_OSUSP)
447 || !(rc->rc_flags & RC_SEND_RDY)
450 /* Handle breaks and other stuff */
451 if (rc->rc_pendcmd) {
452 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
453 rcout(CD180_TDR, CD180_C_ESC);
454 rcout(CD180_TDR, rc->rc_pendcmd);
455 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
460 resid = rc->rc_obufend - optr;
461 if (resid > CD180_NFIFO)
464 rcout(CD180_TDR, *optr++);
467 /* output completed? */
468 if (optr >= rc->rc_obufend) {
469 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
471 kprintf("rc%d/%d: output completed\n", unit, rc->rc_chan);
473 if (!(rc->rc_flags & RC_DOXXFER)) {
474 rc_scheduled_event += LOTS_OF_EVENTS;
475 rc->rc_flags |= RC_DOXXFER;
481 rcout(CD180_EOIR, 0); /* end of interrupt */
483 bsr = ~(rcin(RC_BSR));
487 /* Feed characters to output buffer */
489 rc_start(struct tty *tp)
491 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
492 int nec = rc->rc_rcb->rcb_addr;
494 if (rc->rc_flags & RC_OSBUSY)
497 rc->rc_flags |= RC_OSBUSY;
499 if (tp->t_state & TS_TTSTOP)
500 rc->rc_flags |= RC_OSUSP;
502 rc->rc_flags &= ~RC_OSUSP;
503 /* Do RTS flow control stuff */
504 if ( (rc->rc_flags & RC_RTSFLOW)
505 && (tp->t_state & TS_TBLOCK)
506 && (rc->rc_msvr & MSVR_RTS)
508 rcout(CD180_CAR, rc->rc_chan);
509 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
510 } else if (!(rc->rc_msvr & MSVR_RTS)) {
511 rcout(CD180_CAR, rc->rc_chan);
512 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
515 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
518 printrcflags(rc, "rcstart");
522 kprintf("rcstart: outq = %d obuf = %d\n",
523 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
525 if (tp->t_state & TS_BUSY)
526 goto out; /* output still in progress ... */
528 if (tp->t_outq.c_cc > 0) {
531 tp->t_state |= TS_BUSY;
532 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
534 rc->rc_optr = rc->rc_obuf;
535 rc->rc_obufend = rc->rc_optr + ocnt;
537 if (!(rc->rc_ier & IER_TxRdy)) {
539 kprintf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
541 rcout(CD180_CAR, rc->rc_chan);
542 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
546 rc->rc_flags &= ~RC_OSBUSY;
550 /* Handle delayed events. */
552 rcpoll(void *dummy, void *frame)
555 struct rc_softc *rcb;
558 int chan, icnt, nec, unit;
560 if (rc_scheduled_event == 0)
563 for (unit = 0; unit < NRC; unit++) {
564 rcb = &rc_softc[unit];
565 rc = rcb->rcb_baserc;
566 nec = rc->rc_rcb->rcb_addr;
567 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
570 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
571 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
572 printrcflags(rc, "rcevent");
574 if (rc->rc_flags & RC_WAS_BUFOVFL) {
576 rc->rc_flags &= ~RC_WAS_BUFOVFL;
577 rc_scheduled_event--;
579 kprintf("rc%d/%d: interrupt-level buffer overflow\n",
582 if (rc->rc_flags & RC_WAS_SILOVFL) {
584 rc->rc_flags &= ~RC_WAS_SILOVFL;
585 rc_scheduled_event--;
587 kprintf("rc%d/%d: silo overflow\n",
590 if (rc->rc_flags & RC_MODCHG) {
592 rc->rc_flags &= ~RC_MODCHG;
593 rc_scheduled_event -= LOTS_OF_EVENTS;
595 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
597 if (rc->rc_flags & RC_DORXFER) {
599 rc->rc_flags &= ~RC_DORXFER;
601 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
602 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
607 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
608 rc->rc_iptr = rc->rc_ibuf;
609 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
610 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
612 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
613 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
615 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
617 if ( (rc->rc_flags & RC_RTSFLOW)
618 && (tp->t_state & TS_ISOPEN)
619 && !(tp->t_state & TS_TBLOCK)
620 && !(rc->rc_msvr & MSVR_RTS)
622 rcout(CD180_CAR, chan);
624 rc->rc_msvr |= MSVR_RTS);
626 rc_scheduled_event -= icnt;
630 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
633 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
634 && !(tp->t_state & TS_LOCAL)) {
635 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
636 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
637 && !(tp->t_state & TS_TBLOCK))
642 if (b_to_q(tptr, icnt, &tp->t_rawq))
643 kprintf("rc%d/%d: tty-level buffer overflow\n",
646 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
647 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
648 tp->t_state &= ~TS_TTSTOP;
649 tp->t_lflag &= ~FLUSHO;
653 for (; tptr < eptr; tptr++)
654 (*linesw[tp->t_line].l_rint)
656 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
660 if (rc->rc_flags & RC_DOXXFER) {
662 rc_scheduled_event -= LOTS_OF_EVENTS;
663 rc->rc_flags &= ~RC_DOXXFER;
664 rc->rc_tp->t_state &= ~TS_BUSY;
666 (*linesw[tp->t_line].l_start)(tp);
669 if (rc_scheduled_event == 0)
672 if (rc_scheduled_event >= LOTS_OF_EVENTS)
677 rc_stop(struct tty *tp, int rw)
679 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
683 kprintf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
684 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
687 rc_discard_output(rc);
690 rc->rc_flags &= ~RC_DORXFER;
692 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
693 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
694 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
697 rc->rc_iptr = rc->rc_ibuf;
699 rc_scheduled_event -= eptr - tptr;
701 if (tp->t_state & TS_TTSTOP)
702 rc->rc_flags |= RC_OSUSP;
704 rc->rc_flags &= ~RC_OSUSP;
709 rcopen(struct dev_open_args *ap)
711 cdev_t dev = ap->a_head.a_dev;
714 int unit, nec, error = 0;
716 unit = GET_UNIT(dev);
717 if (unit >= NRC * CD180_NCHAN)
719 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
721 rc = &rc_chans[unit];
724 nec = rc->rc_rcb->rcb_addr;
726 kprintf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
731 while (rc->rc_flags & RC_DTR_OFF) {
732 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
736 if (tp->t_state & TS_ISOPEN) {
738 if (!(rc->rc_flags & RC_ACTOUT)) {
743 if (rc->rc_flags & RC_ACTOUT) {
744 if (ap->a_oflags & O_NONBLOCK) {
748 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
754 if (tp->t_state & TS_XCLUDE &&
755 suser_cred(ap->a_cred, 0)) {
760 tp->t_oproc = rc_start;
761 tp->t_param = rc_param;
762 tp->t_stop = rc_stop;
766 tp->t_cflag |= CLOCAL;
768 tp->t_cflag &= ~CLOCAL;
770 error = rc_param(tp, &tp->t_termios);
773 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
775 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
776 (*linesw[tp->t_line].l_modem)(tp, 1);
778 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
779 && !(tp->t_cflag & CLOCAL) && !(ap->a_oflags & O_NONBLOCK)) {
781 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
787 error = (*linesw[tp->t_line].l_open)(dev, tp);
788 disc_optim(tp, &tp->t_termios, rc);
789 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
790 rc->rc_flags |= RC_ACTOUT;
794 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
801 rcclose(struct dev_close_args *ap)
803 cdev_t dev = ap->a_head.a_dev;
806 int unit = GET_UNIT(dev);
808 if (unit >= NRC * CD180_NCHAN)
810 rc = &rc_chans[unit];
813 kprintf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
816 (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
817 disc_optim(tp, &tp->t_termios, rc);
818 rc_stop(tp, FREAD | FWRITE);
826 rc_hardclose(struct rc_chans *rc)
828 int nec = rc->rc_rcb->rcb_addr;
829 struct tty *tp = rc->rc_tp;
832 rcout(CD180_CAR, rc->rc_chan);
834 /* Disable rx/tx intrs */
835 rcout(CD180_IER, rc->rc_ier = 0);
836 if ( (tp->t_cflag & HUPCL)
837 || (!(rc->rc_flags & RC_ACTOUT)
838 && !(rc->rc_msvr & MSVR_CD)
839 && !(tp->t_cflag & CLOCAL))
840 || !(tp->t_state & TS_ISOPEN)
842 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
843 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
844 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
845 if (rc->rc_dtrwait) {
846 callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
848 rc->rc_flags |= RC_DTR_OFF;
851 rc->rc_flags &= ~RC_ACTOUT;
852 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
853 wakeup(TSA_CARR_ON(tp));
857 /* Reset the bastard */
859 rc_hwreset(int unit, int nec, unsigned int chipid)
861 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */
863 WAITFORCCR(unit, -1);
865 rcout(RC_CTOUT, 0); /* Clear timeout */
866 rcout(CD180_GIVR, chipid);
867 rcout(CD180_GICR, 0);
869 /* Set Prescaler Registers (1 msec) */
870 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
871 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
873 /* Initialize Priority Interrupt Level Registers */
874 rcout(CD180_PILR1, RC_PILR_MODEM);
875 rcout(CD180_PILR2, RC_PILR_TX);
876 rcout(CD180_PILR3, RC_PILR_RX);
882 /* Set channel parameters */
884 rc_param(struct tty *tp, struct termios *ts)
886 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
887 int nec = rc->rc_rcb->rcb_addr;
888 int idivs, odivs, val, cflag, iflag, lflag, inpflow;
890 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800
891 || ts->c_ispeed < 0 || ts->c_ispeed > 76800
894 if (ts->c_ispeed == 0)
895 ts->c_ispeed = ts->c_ospeed;
896 odivs = RC_BRD(ts->c_ospeed);
897 idivs = RC_BRD(ts->c_ispeed);
902 rcout(CD180_CAR, rc->rc_chan);
904 /* If speed == 0, hangup line */
905 if (ts->c_ospeed == 0) {
906 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
907 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
908 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
911 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
917 rcout(CD180_RBPRL, idivs & 0xFF);
918 rcout(CD180_RBPRH, idivs >> 8);
921 rcout(CD180_TBPRL, odivs & 0xFF);
922 rcout(CD180_TBPRH, odivs >> 8);
925 /* set timeout value */
926 if (ts->c_ispeed > 0) {
927 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
929 if ( !(lflag & ICANON)
930 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
931 && ts->c_cc[VTIME] * 10 > itm)
932 itm = ts->c_cc[VTIME] * 10;
934 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
937 switch (cflag & CSIZE) {
938 case CS5: val = COR1_5BITS; break;
939 case CS6: val = COR1_6BITS; break;
940 case CS7: val = COR1_7BITS; break;
942 case CS8: val = COR1_8BITS; break;
944 if (cflag & PARENB) {
948 if (!(cflag & INPCK))
954 rcout(CD180_COR1, val);
956 /* Set FIFO threshold */
957 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
960 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
961 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
967 val |= COR3_SCDE|COR3_FCT;
969 rcout(CD180_COR3, val);
971 /* Initialize on-chip automatic flow control */
973 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
974 if (cflag & CCTS_OFLOW) {
975 rc->rc_flags |= RC_CTSFLOW;
978 rc->rc_flags |= RC_SEND_RDY;
979 if (tp->t_state & TS_TTSTOP)
980 rc->rc_flags |= RC_OSUSP;
982 rc->rc_flags &= ~RC_OSUSP;
983 if (cflag & CRTS_IFLOW)
984 rc->rc_flags |= RC_RTSFLOW;
986 rc->rc_flags &= ~RC_RTSFLOW;
989 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
990 rcout(CD180_SCHR1, ts->c_cc[VSTART]);
991 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
997 rcout(CD180_COR2, rc->rc_cor2 = val);
999 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1000 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1002 disc_optim(tp, ts, rc);
1005 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1006 if (cflag & CCTS_OFLOW)
1008 rcout(CD180_MCOR1, val);
1010 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1011 if (cflag & CCTS_OFLOW)
1013 rcout(CD180_MCOR2, val);
1015 /* enable i/o and interrupts */
1016 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1017 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1018 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1020 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1021 if (cflag & CCTS_OFLOW)
1022 rc->rc_ier |= IER_CTS;
1024 rc->rc_ier |= IER_RxData;
1025 if (tp->t_state & TS_BUSY)
1026 rc->rc_ier |= IER_TxRdy;
1027 if (ts->c_ospeed != 0)
1028 rc_modctl(rc, TIOCM_DTR, DMBIS);
1029 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1030 rc->rc_flags |= RC_SEND_RDY;
1031 rcout(CD180_IER, rc->rc_ier);
1036 /* Re-initialize board after bogus interrupts */
1038 rc_reinit(struct rc_softc *rcb)
1040 struct rc_chans *rc, *rce;
1043 nec = rcb->rcb_addr;
1044 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1045 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1046 rce = rc + CD180_NCHAN;
1047 for (; rc < rce; rc++)
1048 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1052 rcioctl(struct dev_ioctl_args *ap)
1054 cdev_t dev = ap->a_head.a_dev;
1055 struct rc_chans *rc = &rc_chans[GET_UNIT(dev)];
1057 struct tty *tp = rc->rc_tp;
1059 error = (*linesw[tp->t_line].l_ioctl)(tp, ap->a_cmd, ap->a_data,
1060 ap->a_fflag, ap->a_cred);
1061 if (error != ENOIOCTL)
1063 error = ttioctl(tp, ap->a_cmd, ap->a_data, ap->a_fflag);
1064 disc_optim(tp, &tp->t_termios, rc);
1065 if (error != ENOIOCTL)
1069 switch (ap->a_cmd) {
1071 rc->rc_pendcmd = CD180_C_SBRK;
1075 rc->rc_pendcmd = CD180_C_EBRK;
1079 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1083 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1087 *(int *) ap->a_data = rc_modctl(rc, 0, DMGET);
1091 (void) rc_modctl(rc, *(int *) ap->a_data, DMSET);
1095 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIC);
1099 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIS);
1103 error = suser_cred(ap->a_cred, 0);
1108 rc->rc_dtrwait = *(int *)ap->a_data * hz / 100;
1112 *(int *)ap->a_data = rc->rc_dtrwait * 100 / hz;
1124 /* Modem control routines */
1127 rc_modctl(struct rc_chans *rc, int bits, int cmd)
1129 int nec = rc->rc_rcb->rcb_addr;
1130 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1132 rcout(CD180_CAR, rc->rc_chan);
1136 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1137 ~(*dtr |= 1 << rc->rc_chan) :
1138 ~(*dtr &= ~(1 << rc->rc_chan)));
1139 msvr = rcin(CD180_MSVR);
1140 if (bits & TIOCM_RTS)
1144 if (bits & TIOCM_DTR)
1148 rcout(CD180_MSVR, msvr);
1152 if (bits & TIOCM_DTR)
1153 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1154 msvr = rcin(CD180_MSVR);
1155 if (bits & TIOCM_RTS)
1157 if (bits & TIOCM_DTR)
1159 rcout(CD180_MSVR, msvr);
1164 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1166 if (msvr & MSVR_RTS)
1168 if (msvr & MSVR_CTS)
1170 if (msvr & MSVR_DSR)
1172 if (msvr & MSVR_DTR)
1176 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1181 if (bits & TIOCM_DTR)
1182 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1183 msvr = rcin(CD180_MSVR);
1184 if (bits & TIOCM_RTS)
1186 if (bits & TIOCM_DTR)
1188 rcout(CD180_MSVR, msvr);
1191 rc->rc_msvr = rcin(CD180_MSVR);
1195 /* Test the board. */
1197 rc_test(int nec, int unit)
1201 unsigned int iack, chipid;
1202 unsigned short divs;
1203 static u_char ctest[] = "\377\125\252\045\244\0\377";
1206 kprintf("rc%d: ", unit); kprintf s ; kprintf("\n"); \
1207 crit_exit(); return 1; }
1210 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1211 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1212 int rxptr; /* RX pointer */
1213 int txptr; /* TX pointer */
1214 } tchans[CD180_NCHAN];
1220 /* First, reset board to inital state */
1221 rc_hwreset(unit, nec, chipid);
1223 divs = RC_BRD(19200);
1225 /* Initialize channels */
1226 for (chan = 0; chan < CD180_NCHAN; chan++) {
1228 /* Select and reset channel */
1229 rcout(CD180_CAR, chan);
1230 CCRCMD(unit, chan, CCR_ResetChan);
1231 WAITFORCCR(unit, chan);
1234 rcout(CD180_RBPRL, divs & 0xFF);
1235 rcout(CD180_RBPRH, divs >> 8);
1236 rcout(CD180_TBPRL, divs & 0xFF);
1237 rcout(CD180_TBPRH, divs >> 8);
1239 /* set timeout value */
1240 rcout(CD180_RTPR, 0);
1242 /* Establish local loopback */
1243 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1244 rcout(CD180_COR2, COR2_LLM);
1245 rcout(CD180_COR3, CD180_NFIFO);
1246 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1247 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1248 WAITFORCCR(unit, chan);
1249 rcout(CD180_MSVR, MSVR_RTS);
1251 /* Fill TXBUF with test data */
1252 for (i = 0; i < CD180_NFIFO; i++) {
1253 tchans[chan].txbuf[i] = ctest[i];
1254 tchans[chan].rxbuf[i] = 0;
1256 tchans[chan].txptr = tchans[chan].rxptr = 0;
1258 /* Now, start transmit */
1259 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1261 /* Pseudo-interrupt poll stuff */
1262 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1263 i = ~(rcin(RC_BSR));
1264 if (i & RC_BSR_TOUT)
1265 ERR(("BSR timeout bit set\n"))
1266 else if (i & RC_BSR_TXINT) {
1267 iack = rcin(RC_PILR_TX);
1268 if (iack != (GIVR_IT_TDI | chipid))
1269 ERR(("Bad TX intr ack (%02x != %02x)\n",
1270 iack, GIVR_IT_TDI | chipid));
1271 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1272 /* If no more data to transmit, disable TX intr */
1273 if (tchans[chan].txptr >= CD180_NFIFO) {
1274 iack = rcin(CD180_IER);
1275 rcout(CD180_IER, iack & ~IER_TxMpty);
1277 for (iack = tchans[chan].txptr;
1278 iack < CD180_NFIFO; iack++)
1280 tchans[chan].txbuf[iack]);
1281 tchans[chan].txptr = iack;
1283 rcout(CD180_EOIR, 0);
1284 } else if (i & RC_BSR_RXINT) {
1287 iack = rcin(RC_PILR_RX);
1288 if (iack != (GIVR_IT_RGDI | chipid) &&
1289 iack != (GIVR_IT_REI | chipid))
1290 ERR(("Bad RX intr ack (%02x != %02x)\n",
1291 iack, GIVR_IT_RGDI | chipid))
1292 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1293 ucnt = rcin(CD180_RDCR) & 0xF;
1294 while (ucnt-- > 0) {
1295 iack = rcin(CD180_RCSR);
1296 if (iack & RCSR_Timeout)
1299 ERR(("Bad char chan %d (RCSR = %02X)\n",
1301 if (tchans[chan].rxptr > CD180_NFIFO)
1302 ERR(("Got extra chars chan %d\n",
1304 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1307 rcout(CD180_EOIR, 0);
1310 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1311 if (tchans[chan].rxptr >= CD180_NFIFO)
1313 if (iack == CD180_NCHAN)
1316 for (chan = 0; chan < CD180_NCHAN; chan++) {
1317 /* Select and reset channel */
1318 rcout(CD180_CAR, chan);
1319 CCRCMD(unit, chan, CCR_ResetChan);
1323 ERR(("looses characters during local loopback\n"))
1324 /* Now, check data */
1325 for (chan = 0; chan < CD180_NCHAN; chan++)
1326 for (i = 0; i < CD180_NFIFO; i++)
1327 if (ctest[i] != tchans[chan].rxbuf[i])
1328 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1329 chan, i, ctest[i], tchans[chan].rxbuf[i]))
1336 printrcflags(struct rc_chans *rc, char *comment)
1338 u_short f = rc->rc_flags;
1339 int nec = rc->rc_rcb->rcb_addr;
1341 kprintf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1342 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1343 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1344 (f & RC_ACTOUT) ?"ACTOUT " :"",
1345 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1346 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1347 (f & RC_DORXFER)?"DORXFER " :"",
1348 (f & RC_DOXXFER)?"DOXXFER " :"",
1349 (f & RC_MODCHG) ?"MODCHG " :"",
1350 (f & RC_OSUSP) ?"OSUSP " :"",
1351 (f & RC_OSBUSY) ?"OSBUSY " :"",
1352 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1353 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1354 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1356 rcout(CD180_CAR, rc->rc_chan);
1358 kprintf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1359 rc->rc_rcb->rcb_unit, rc->rc_chan,
1364 #endif /* RCDEBUG */
1367 rc_dtrwakeup(void *chan)
1369 struct rc_chans *rc;
1371 rc = (struct rc_chans *)chan;
1372 rc->rc_flags &= ~RC_DTR_OFF;
1373 wakeup(&rc->rc_dtrwait);
1377 rc_discard_output(struct rc_chans *rc)
1380 if (rc->rc_flags & RC_DOXXFER) {
1381 rc_scheduled_event -= LOTS_OF_EVENTS;
1382 rc->rc_flags &= ~RC_DOXXFER;
1384 rc->rc_optr = rc->rc_obufend;
1385 rc->rc_tp->t_state &= ~TS_BUSY;
1387 ttwwakeup(rc->rc_tp);
1391 rc_wakeup(void *chan)
1393 if (rc_scheduled_event != 0) {
1398 callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
1402 disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc)
1405 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1406 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1407 && (!(t->c_iflag & PARMRK)
1408 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1409 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1410 && linesw[tp->t_line].l_rint == ttyinput)
1411 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1413 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1414 rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1418 rc_wait0(int nec, int unit, int chan, int line)
1422 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1425 kprintf("rc%d/%d: channel command timeout, rc.c line: %d\n",