2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_ifpoll.h"
35 #include <sys/param.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
52 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
83 #else /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85 #endif /* IGB_RSS_DEBUG */
87 #define IGB_NAME "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
92 static struct igb_device {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
125 /* required last entry */
129 static int igb_probe(device_t);
130 static int igb_attach(device_t);
131 static int igb_detach(device_t);
132 static int igb_shutdown(device_t);
133 static int igb_suspend(device_t);
134 static int igb_resume(device_t);
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140 static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
141 static void igb_add_sysctl(struct igb_softc *);
142 static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
143 static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
144 static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
145 static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
146 static int igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
147 static int igb_get_txring_inuse(const struct igb_softc *, boolean_t);
149 static int igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
150 static int igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
153 static void igb_vf_init_stats(struct igb_softc *);
154 static void igb_reset(struct igb_softc *);
155 static void igb_update_stats_counters(struct igb_softc *);
156 static void igb_update_vf_stats_counters(struct igb_softc *);
157 static void igb_update_link_status(struct igb_softc *);
158 static void igb_init_tx_unit(struct igb_softc *);
159 static void igb_init_rx_unit(struct igb_softc *);
161 static void igb_set_vlan(struct igb_softc *);
162 static void igb_set_multi(struct igb_softc *);
163 static void igb_set_promisc(struct igb_softc *);
164 static void igb_disable_promisc(struct igb_softc *);
166 static int igb_alloc_rings(struct igb_softc *);
167 static void igb_free_rings(struct igb_softc *);
168 static int igb_create_tx_ring(struct igb_tx_ring *);
169 static int igb_create_rx_ring(struct igb_rx_ring *);
170 static void igb_free_tx_ring(struct igb_tx_ring *);
171 static void igb_free_rx_ring(struct igb_rx_ring *);
172 static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
173 static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
174 static void igb_init_tx_ring(struct igb_tx_ring *);
175 static int igb_init_rx_ring(struct igb_rx_ring *);
176 static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
177 static int igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
178 static void igb_rx_refresh(struct igb_rx_ring *, int);
180 static void igb_stop(struct igb_softc *);
181 static void igb_init(void *);
182 static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
183 static void igb_media_status(struct ifnet *, struct ifmediareq *);
184 static int igb_media_change(struct ifnet *);
185 static void igb_timer(void *);
186 static void igb_watchdog(struct ifaltq_subque *);
187 static void igb_start(struct ifnet *, struct ifaltq_subque *);
189 static void igb_npoll(struct ifnet *, struct ifpoll_info *);
190 static void igb_npoll_rx(struct ifnet *, void *, int);
191 static void igb_npoll_tx(struct ifnet *, void *, int);
192 static void igb_npoll_status(struct ifnet *);
194 static void igb_serialize(struct ifnet *, enum ifnet_serialize);
195 static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
196 static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
198 static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
202 static void igb_intr(void *);
203 static void igb_intr_shared(void *);
204 static void igb_rxeof(struct igb_rx_ring *, int);
205 static void igb_txeof(struct igb_tx_ring *);
206 static void igb_set_eitr(struct igb_softc *, int, int);
207 static void igb_enable_intr(struct igb_softc *);
208 static void igb_disable_intr(struct igb_softc *);
209 static void igb_init_unshared_intr(struct igb_softc *);
210 static void igb_init_intr(struct igb_softc *);
211 static int igb_setup_intr(struct igb_softc *);
212 static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
213 static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
214 static void igb_set_intr_mask(struct igb_softc *);
215 static int igb_alloc_intr(struct igb_softc *);
216 static void igb_free_intr(struct igb_softc *);
217 static void igb_teardown_intr(struct igb_softc *);
218 static void igb_msix_try_alloc(struct igb_softc *);
219 static void igb_msix_free(struct igb_softc *, boolean_t);
220 static int igb_msix_setup(struct igb_softc *);
221 static void igb_msix_teardown(struct igb_softc *, int);
222 static void igb_msix_rx(void *);
223 static void igb_msix_tx(void *);
224 static void igb_msix_status(void *);
226 /* Management and WOL Support */
227 static void igb_get_mgmt(struct igb_softc *);
228 static void igb_rel_mgmt(struct igb_softc *);
229 static void igb_get_hw_control(struct igb_softc *);
230 static void igb_rel_hw_control(struct igb_softc *);
231 static void igb_enable_wol(device_t);
233 static device_method_t igb_methods[] = {
234 /* Device interface */
235 DEVMETHOD(device_probe, igb_probe),
236 DEVMETHOD(device_attach, igb_attach),
237 DEVMETHOD(device_detach, igb_detach),
238 DEVMETHOD(device_shutdown, igb_shutdown),
239 DEVMETHOD(device_suspend, igb_suspend),
240 DEVMETHOD(device_resume, igb_resume),
244 static driver_t igb_driver = {
247 sizeof(struct igb_softc),
250 static devclass_t igb_devclass;
252 DECLARE_DUMMY_MODULE(if_igb);
253 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
254 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
256 static int igb_rxd = IGB_DEFAULT_RXD;
257 static int igb_txd = IGB_DEFAULT_TXD;
258 static int igb_rxr = 0;
259 static int igb_txr = 0;
260 static int igb_msi_enable = 1;
261 static int igb_msix_enable = 1;
262 static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
263 static int igb_fc_setting = e1000_fc_full;
266 * DMA Coalescing, only for i350 - default to off,
267 * this feature is for power savings
269 static int igb_dma_coalesce = 0;
271 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
272 TUNABLE_INT("hw.igb.txd", &igb_txd);
273 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
274 TUNABLE_INT("hw.igb.txr", &igb_txr);
275 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
276 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
277 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
280 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
281 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
284 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
286 /* Ignore Checksum bit is set */
287 if (staterr & E1000_RXD_STAT_IXSM)
290 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
292 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
294 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
295 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
296 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
297 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
298 mp->m_pkthdr.csum_data = htons(0xffff);
303 static __inline struct pktinfo *
304 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
305 uint32_t hash, uint32_t hashtype, uint32_t staterr)
308 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
309 pi->pi_netisr = NETISR_IP;
311 pi->pi_l3proto = IPPROTO_TCP;
314 case E1000_RXDADV_RSSTYPE_IPV4:
315 if (staterr & E1000_RXD_STAT_IXSM)
319 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
320 E1000_RXD_STAT_TCPCS) {
321 pi->pi_netisr = NETISR_IP;
323 pi->pi_l3proto = IPPROTO_UDP;
331 m->m_flags |= M_HASH;
332 m->m_pkthdr.hash = toeplitz_hash(hash);
337 igb_probe(device_t dev)
339 const struct igb_device *d;
342 vid = pci_get_vendor(dev);
343 did = pci_get_device(dev);
345 for (d = igb_devices; d->desc != NULL; ++d) {
346 if (vid == d->vid && did == d->did) {
347 device_set_desc(dev, d->desc);
355 igb_attach(device_t dev)
357 struct igb_softc *sc = device_get_softc(dev);
358 uint16_t eeprom_data;
359 int error = 0, i, j, ring_max;
361 int offset, offset_def;
366 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
367 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
368 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
369 igb_sysctl_nvm_info, "I", "NVM Information");
370 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
371 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
372 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
373 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
376 callout_init_mp(&sc->timer);
377 lwkt_serialize_init(&sc->main_serialize);
379 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
380 device_get_unit(dev));
381 sc->dev = sc->osdep.dev = dev;
384 * Determine hardware and mac type
386 sc->hw.vendor_id = pci_get_vendor(dev);
387 sc->hw.device_id = pci_get_device(dev);
388 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
389 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
390 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
392 if (e1000_set_mac_type(&sc->hw))
395 /* Are we a VF device? */
396 if (sc->hw.mac.type == e1000_vfadapt ||
397 sc->hw.mac.type == e1000_vfadapt_i350)
403 * Configure total supported RX/TX ring count
405 switch (sc->hw.mac.type) {
407 ring_max = IGB_MAX_RING_82575;
410 ring_max = IGB_MAX_RING_82580;
413 ring_max = IGB_MAX_RING_I350;
416 ring_max = IGB_MAX_RING_82576;
419 ring_max = IGB_MIN_RING;
423 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
424 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
426 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
428 sc->rx_ring_inuse = sc->rx_ring_cnt;
430 sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
431 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, /* XXX ring_max */1);
433 sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
435 sc->tx_ring_inuse = sc->tx_ring_cnt;
437 if (sc->hw.mac.type == e1000_82575)
438 sc->flags |= IGB_FLAG_TSO_IPLEN0;
440 /* Enable bus mastering */
441 pci_enable_busmaster(dev);
446 sc->mem_rid = PCIR_BAR(0);
447 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
449 if (sc->mem_res == NULL) {
450 device_printf(dev, "Unable to allocate bus resource: memory\n");
454 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
455 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
457 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
459 /* Save PCI command register for Shared Code */
460 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
461 sc->hw.back = &sc->osdep;
463 /* Do Shared Code initialization */
464 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
465 device_printf(dev, "Setup of Shared code failed\n");
470 e1000_get_bus_info(&sc->hw);
472 sc->hw.mac.autoneg = DO_AUTO_NEG;
473 sc->hw.phy.autoneg_wait_to_complete = FALSE;
474 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
477 if (sc->hw.phy.media_type == e1000_media_type_copper) {
478 sc->hw.phy.mdix = AUTO_ALL_MODES;
479 sc->hw.phy.disable_polarity_correction = FALSE;
480 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
483 /* Set the frame limits assuming standard ethernet sized frames. */
484 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
486 /* Allocate RX/TX rings */
487 error = igb_alloc_rings(sc);
493 * NPOLLING RX CPU offset
495 if (sc->rx_ring_cnt == ncpus2) {
498 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
499 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
500 if (offset >= ncpus2 ||
501 offset % sc->rx_ring_cnt != 0) {
502 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
507 sc->rx_npoll_off = offset;
510 * NPOLLING TX CPU offset
512 if (sc->tx_ring_cnt == ncpus2) {
515 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
516 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
517 if (offset >= ncpus2 ||
518 offset % sc->tx_ring_cnt != 0) {
519 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
524 sc->tx_npoll_off = offset;
527 /* Allocate interrupt */
528 error = igb_alloc_intr(sc);
536 sc->serializes[i++] = &sc->main_serialize;
538 sc->tx_serialize = i;
539 for (j = 0; j < sc->tx_ring_cnt; ++j)
540 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
542 sc->rx_serialize = i;
543 for (j = 0; j < sc->rx_ring_cnt; ++j)
544 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
546 sc->serialize_cnt = i;
547 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
549 /* Allocate the appropriate stats memory */
551 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
553 igb_vf_init_stats(sc);
555 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
559 /* Allocate multicast array memory. */
560 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
563 /* Some adapter-specific advanced features */
564 if (sc->hw.mac.type >= e1000_i350) {
566 igb_set_sysctl_value(adapter, "dma_coalesce",
567 "configure dma coalesce",
568 &adapter->dma_coalesce, igb_dma_coalesce);
569 igb_set_sysctl_value(adapter, "eee_disabled",
570 "enable Energy Efficient Ethernet",
571 &adapter->hw.dev_spec._82575.eee_disable,
574 sc->dma_coalesce = igb_dma_coalesce;
575 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
577 e1000_set_eee_i350(&sc->hw);
581 * Start from a known state, this is important in reading the nvm and
584 e1000_reset_hw(&sc->hw);
586 /* Make sure we have a good EEPROM before we read from it */
587 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
589 * Some PCI-E parts fail the first check due to
590 * the link being in sleep state, call it again,
591 * if it fails a second time its a real issue.
593 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
595 "The EEPROM Checksum Is Not Valid\n");
601 /* Copy the permanent MAC address out of the EEPROM */
602 if (e1000_read_mac_addr(&sc->hw) < 0) {
603 device_printf(dev, "EEPROM read error while reading MAC"
608 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
609 device_printf(dev, "Invalid MAC address\n");
614 /* Setup OS specific network interface */
617 /* Add sysctl tree, must after igb_setup_ifp() */
620 /* Now get a good starting state */
623 /* Initialize statistics */
624 igb_update_stats_counters(sc);
626 sc->hw.mac.get_link_status = 1;
627 igb_update_link_status(sc);
629 /* Indicate SOL/IDER usage */
630 if (e1000_check_reset_block(&sc->hw)) {
632 "PHY reset is blocked due to SOL/IDER session.\n");
635 /* Determine if we have to control management hardware */
636 if (e1000_enable_mng_pass_thru(&sc->hw))
637 sc->flags |= IGB_FLAG_HAS_MGMT;
642 /* APME bit in EEPROM is mapped to WUC.APME */
643 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
645 sc->wol = E1000_WUFC_MAG;
646 /* XXX disable WOL */
650 /* Register for VLAN events */
651 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
652 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
653 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
654 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
658 igb_add_hw_stats(adapter);
661 error = igb_setup_intr(sc);
663 ether_ifdetach(&sc->arpcom.ac_if);
667 for (i = 0; i < sc->tx_ring_cnt; ++i) {
668 struct ifaltq_subque *ifsq =
669 ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
670 struct igb_tx_ring *txr = &sc->tx_rings[i];
672 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
673 ifsq_set_priv(ifsq, txr);
676 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
687 igb_detach(device_t dev)
689 struct igb_softc *sc = device_get_softc(dev);
691 if (device_is_attached(dev)) {
692 struct ifnet *ifp = &sc->arpcom.ac_if;
694 ifnet_serialize_all(ifp);
698 e1000_phy_hw_reset(&sc->hw);
700 /* Give control back to firmware */
702 igb_rel_hw_control(sc);
705 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
706 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
710 igb_teardown_intr(sc);
712 ifnet_deserialize_all(ifp);
715 } else if (sc->mem_res != NULL) {
716 igb_rel_hw_control(sc);
718 bus_generic_detach(dev);
720 if (sc->sysctl_tree != NULL)
721 sysctl_ctx_free(&sc->sysctl_ctx);
725 if (sc->msix_mem_res != NULL) {
726 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
729 if (sc->mem_res != NULL) {
730 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
737 kfree(sc->mta, M_DEVBUF);
738 if (sc->stats != NULL)
739 kfree(sc->stats, M_DEVBUF);
745 igb_shutdown(device_t dev)
747 return igb_suspend(dev);
751 igb_suspend(device_t dev)
753 struct igb_softc *sc = device_get_softc(dev);
754 struct ifnet *ifp = &sc->arpcom.ac_if;
756 ifnet_serialize_all(ifp);
761 igb_rel_hw_control(sc);
764 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
765 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
769 ifnet_deserialize_all(ifp);
771 return bus_generic_suspend(dev);
775 igb_resume(device_t dev)
777 struct igb_softc *sc = device_get_softc(dev);
778 struct ifnet *ifp = &sc->arpcom.ac_if;
781 ifnet_serialize_all(ifp);
786 for (i = 0; i < sc->tx_ring_inuse; ++i)
787 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
789 ifnet_deserialize_all(ifp);
791 return bus_generic_resume(dev);
795 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
797 struct igb_softc *sc = ifp->if_softc;
798 struct ifreq *ifr = (struct ifreq *)data;
799 int max_frame_size, mask, reinit;
802 ASSERT_IFNET_SERIALIZED_ALL(ifp);
806 max_frame_size = 9234;
807 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
813 ifp->if_mtu = ifr->ifr_mtu;
814 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
817 if (ifp->if_flags & IFF_RUNNING)
822 if (ifp->if_flags & IFF_UP) {
823 if (ifp->if_flags & IFF_RUNNING) {
824 if ((ifp->if_flags ^ sc->if_flags) &
825 (IFF_PROMISC | IFF_ALLMULTI)) {
826 igb_disable_promisc(sc);
832 } else if (ifp->if_flags & IFF_RUNNING) {
835 sc->if_flags = ifp->if_flags;
840 if (ifp->if_flags & IFF_RUNNING) {
841 igb_disable_intr(sc);
844 if (!(ifp->if_flags & IFF_NPOLLING))
852 * As the speed/duplex settings are being
853 * changed, we need toreset the PHY.
855 sc->hw.phy.reset_disable = FALSE;
857 /* Check SOL/IDER usage */
858 if (e1000_check_reset_block(&sc->hw)) {
859 if_printf(ifp, "Media change is "
860 "blocked due to SOL/IDER session.\n");
866 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
871 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
872 if (mask & IFCAP_RXCSUM) {
873 ifp->if_capenable ^= IFCAP_RXCSUM;
876 if (mask & IFCAP_VLAN_HWTAGGING) {
877 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
880 if (mask & IFCAP_TXCSUM) {
881 ifp->if_capenable ^= IFCAP_TXCSUM;
882 if (ifp->if_capenable & IFCAP_TXCSUM)
883 ifp->if_hwassist |= IGB_CSUM_FEATURES;
885 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
887 if (mask & IFCAP_TSO) {
888 ifp->if_capenable ^= IFCAP_TSO;
889 if (ifp->if_capenable & IFCAP_TSO)
890 ifp->if_hwassist |= CSUM_TSO;
892 ifp->if_hwassist &= ~CSUM_TSO;
894 if (mask & IFCAP_RSS)
895 ifp->if_capenable ^= IFCAP_RSS;
896 if (reinit && (ifp->if_flags & IFF_RUNNING))
901 error = ether_ioctl(ifp, command, data);
910 struct igb_softc *sc = xsc;
911 struct ifnet *ifp = &sc->arpcom.ac_if;
915 ASSERT_IFNET_SERIALIZED_ALL(ifp);
919 /* Get the latest mac address, User can use a LAA */
920 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
922 /* Put the address into the Receive Address Array */
923 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
926 igb_update_link_status(sc);
928 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
930 /* Configure for OS presence */
935 if (ifp->if_flags & IFF_NPOLLING)
939 /* Configured used RX/TX rings */
940 igb_set_ring_inuse(sc, polling);
942 /* Initialize interrupt */
945 /* Prepare transmit descriptors and buffers */
946 for (i = 0; i < sc->tx_ring_inuse; ++i)
947 igb_init_tx_ring(&sc->tx_rings[i]);
948 igb_init_tx_unit(sc);
950 /* Setup Multicast table */
955 * Figure out the desired mbuf pool
956 * for doing jumbo/packetsplit
958 if (adapter->max_frame_size <= 2048)
959 adapter->rx_mbuf_sz = MCLBYTES;
960 else if (adapter->max_frame_size <= 4096)
961 adapter->rx_mbuf_sz = MJUMPAGESIZE;
963 adapter->rx_mbuf_sz = MJUM9BYTES;
966 /* Prepare receive descriptors and buffers */
967 for (i = 0; i < sc->rx_ring_inuse; ++i) {
970 error = igb_init_rx_ring(&sc->rx_rings[i]);
972 if_printf(ifp, "Could not setup receive structures\n");
977 igb_init_rx_unit(sc);
979 /* Enable VLAN support */
980 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
983 /* Don't lose promiscuous settings */
986 ifp->if_flags |= IFF_RUNNING;
987 for (i = 0; i < sc->tx_ring_inuse; ++i) {
988 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
989 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
992 if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
993 sc->timer_cpuid = 0; /* XXX fixed */
995 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
996 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
997 e1000_clear_hw_cntrs_base_generic(&sc->hw);
999 /* This clears any pending interrupts */
1000 E1000_READ_REG(&sc->hw, E1000_ICR);
1003 * Only enable interrupts if we are not polling, make sure
1004 * they are off otherwise.
1007 igb_disable_intr(sc);
1009 igb_enable_intr(sc);
1010 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1013 /* Set Energy Efficient Ethernet */
1014 e1000_set_eee_i350(&sc->hw);
1016 /* Don't reset the phy next time init gets called */
1017 sc->hw.phy.reset_disable = TRUE;
1021 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1023 struct igb_softc *sc = ifp->if_softc;
1024 u_char fiber_type = IFM_1000_SX;
1026 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1028 igb_update_link_status(sc);
1030 ifmr->ifm_status = IFM_AVALID;
1031 ifmr->ifm_active = IFM_ETHER;
1033 if (!sc->link_active)
1036 ifmr->ifm_status |= IFM_ACTIVE;
1038 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1039 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1040 ifmr->ifm_active |= fiber_type | IFM_FDX;
1042 switch (sc->link_speed) {
1044 ifmr->ifm_active |= IFM_10_T;
1048 ifmr->ifm_active |= IFM_100_TX;
1052 ifmr->ifm_active |= IFM_1000_T;
1055 if (sc->link_duplex == FULL_DUPLEX)
1056 ifmr->ifm_active |= IFM_FDX;
1058 ifmr->ifm_active |= IFM_HDX;
1063 igb_media_change(struct ifnet *ifp)
1065 struct igb_softc *sc = ifp->if_softc;
1066 struct ifmedia *ifm = &sc->media;
1068 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1070 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1073 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1075 sc->hw.mac.autoneg = DO_AUTO_NEG;
1076 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1082 sc->hw.mac.autoneg = DO_AUTO_NEG;
1083 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1087 sc->hw.mac.autoneg = FALSE;
1088 sc->hw.phy.autoneg_advertised = 0;
1089 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1090 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1092 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1096 sc->hw.mac.autoneg = FALSE;
1097 sc->hw.phy.autoneg_advertised = 0;
1098 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1099 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1101 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1105 if_printf(ifp, "Unsupported media type\n");
1115 igb_set_promisc(struct igb_softc *sc)
1117 struct ifnet *ifp = &sc->arpcom.ac_if;
1118 struct e1000_hw *hw = &sc->hw;
1122 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1126 reg = E1000_READ_REG(hw, E1000_RCTL);
1127 if (ifp->if_flags & IFF_PROMISC) {
1128 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1129 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1130 } else if (ifp->if_flags & IFF_ALLMULTI) {
1131 reg |= E1000_RCTL_MPE;
1132 reg &= ~E1000_RCTL_UPE;
1133 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1138 igb_disable_promisc(struct igb_softc *sc)
1140 struct e1000_hw *hw = &sc->hw;
1144 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1147 reg = E1000_READ_REG(hw, E1000_RCTL);
1148 reg &= ~E1000_RCTL_UPE;
1149 reg &= ~E1000_RCTL_MPE;
1150 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1154 igb_set_multi(struct igb_softc *sc)
1156 struct ifnet *ifp = &sc->arpcom.ac_if;
1157 struct ifmultiaddr *ifma;
1158 uint32_t reg_rctl = 0;
1163 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1165 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1166 if (ifma->ifma_addr->sa_family != AF_LINK)
1169 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1172 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1173 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1177 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1178 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1179 reg_rctl |= E1000_RCTL_MPE;
1180 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1182 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1187 igb_timer(void *xsc)
1189 struct igb_softc *sc = xsc;
1191 lwkt_serialize_enter(&sc->main_serialize);
1193 igb_update_link_status(sc);
1194 igb_update_stats_counters(sc);
1196 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1198 lwkt_serialize_exit(&sc->main_serialize);
1202 igb_update_link_status(struct igb_softc *sc)
1204 struct ifnet *ifp = &sc->arpcom.ac_if;
1205 struct e1000_hw *hw = &sc->hw;
1206 uint32_t link_check, thstat, ctrl;
1208 link_check = thstat = ctrl = 0;
1210 /* Get the cached link value or read for real */
1211 switch (hw->phy.media_type) {
1212 case e1000_media_type_copper:
1213 if (hw->mac.get_link_status) {
1214 /* Do the work to read phy */
1215 e1000_check_for_link(hw);
1216 link_check = !hw->mac.get_link_status;
1222 case e1000_media_type_fiber:
1223 e1000_check_for_link(hw);
1224 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1227 case e1000_media_type_internal_serdes:
1228 e1000_check_for_link(hw);
1229 link_check = hw->mac.serdes_has_link;
1232 /* VF device is type_unknown */
1233 case e1000_media_type_unknown:
1234 e1000_check_for_link(hw);
1235 link_check = !hw->mac.get_link_status;
1241 /* Check for thermal downshift or shutdown */
1242 if (hw->mac.type == e1000_i350) {
1243 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1244 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1247 /* Now we check if a transition has happened */
1248 if (link_check && sc->link_active == 0) {
1249 e1000_get_speed_and_duplex(hw,
1250 &sc->link_speed, &sc->link_duplex);
1252 if_printf(ifp, "Link is up %d Mbps %s\n",
1254 sc->link_duplex == FULL_DUPLEX ?
1255 "Full Duplex" : "Half Duplex");
1257 sc->link_active = 1;
1259 ifp->if_baudrate = sc->link_speed * 1000000;
1260 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1261 (thstat & E1000_THSTAT_LINK_THROTTLE))
1262 if_printf(ifp, "Link: thermal downshift\n");
1263 /* This can sleep */
1264 ifp->if_link_state = LINK_STATE_UP;
1265 if_link_state_change(ifp);
1266 } else if (!link_check && sc->link_active == 1) {
1267 ifp->if_baudrate = sc->link_speed = 0;
1268 sc->link_duplex = 0;
1270 if_printf(ifp, "Link is Down\n");
1271 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1272 (thstat & E1000_THSTAT_PWR_DOWN))
1273 if_printf(ifp, "Link: thermal shutdown\n");
1274 sc->link_active = 0;
1275 /* This can sleep */
1276 ifp->if_link_state = LINK_STATE_DOWN;
1277 if_link_state_change(ifp);
1282 igb_stop(struct igb_softc *sc)
1284 struct ifnet *ifp = &sc->arpcom.ac_if;
1287 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1289 igb_disable_intr(sc);
1291 callout_stop(&sc->timer);
1293 ifp->if_flags &= ~IFF_RUNNING;
1294 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1295 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1296 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1299 e1000_reset_hw(&sc->hw);
1300 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1302 e1000_led_off(&sc->hw);
1303 e1000_cleanup_led(&sc->hw);
1305 for (i = 0; i < sc->tx_ring_cnt; ++i)
1306 igb_free_tx_ring(&sc->tx_rings[i]);
1307 for (i = 0; i < sc->rx_ring_cnt; ++i)
1308 igb_free_rx_ring(&sc->rx_rings[i]);
1312 igb_reset(struct igb_softc *sc)
1314 struct ifnet *ifp = &sc->arpcom.ac_if;
1315 struct e1000_hw *hw = &sc->hw;
1316 struct e1000_fc_info *fc = &hw->fc;
1320 /* Let the firmware know the OS is in control */
1321 igb_get_hw_control(sc);
1324 * Packet Buffer Allocation (PBA)
1325 * Writing PBA sets the receive portion of the buffer
1326 * the remainder is used for the transmit buffer.
1328 switch (hw->mac.type) {
1330 pba = E1000_PBA_32K;
1335 pba = E1000_READ_REG(hw, E1000_RXPBS);
1336 pba &= E1000_RXPBS_SIZE_MASK_82576;
1341 case e1000_vfadapt_i350:
1342 pba = E1000_READ_REG(hw, E1000_RXPBS);
1343 pba = e1000_rxpbs_adjust_82580(pba);
1345 /* XXX pba = E1000_PBA_35K; */
1351 /* Special needs in case of Jumbo frames */
1352 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1353 uint32_t tx_space, min_tx, min_rx;
1355 pba = E1000_READ_REG(hw, E1000_PBA);
1356 tx_space = pba >> 16;
1359 min_tx = (sc->max_frame_size +
1360 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1361 min_tx = roundup2(min_tx, 1024);
1363 min_rx = sc->max_frame_size;
1364 min_rx = roundup2(min_rx, 1024);
1366 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1367 pba = pba - (min_tx - tx_space);
1369 * if short on rx space, rx wins
1370 * and must trump tx adjustment
1375 E1000_WRITE_REG(hw, E1000_PBA, pba);
1379 * These parameters control the automatic generation (Tx) and
1380 * response (Rx) to Ethernet PAUSE frames.
1381 * - High water mark should allow for at least two frames to be
1382 * received after sending an XOFF.
1383 * - Low water mark works best when it is very near the high water mark.
1384 * This allows the receiver to restart by sending XON when it has
1387 hwm = min(((pba << 10) * 9 / 10),
1388 ((pba << 10) - 2 * sc->max_frame_size));
1390 if (hw->mac.type < e1000_82576) {
1391 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1392 fc->low_water = fc->high_water - 8;
1394 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1395 fc->low_water = fc->high_water - 16;
1397 fc->pause_time = IGB_FC_PAUSE_TIME;
1398 fc->send_xon = TRUE;
1400 /* Issue a global reset */
1402 E1000_WRITE_REG(hw, E1000_WUC, 0);
1404 if (e1000_init_hw(hw) < 0)
1405 if_printf(ifp, "Hardware Initialization Failed\n");
1407 /* Setup DMA Coalescing */
1408 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1411 hwm = (pba - 4) << 10;
1412 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1413 & E1000_DMACR_DMACTHR_MASK;
1415 /* transition to L0x or L1 if available..*/
1416 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1418 /* timer = +-1000 usec in 32usec intervals */
1420 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1422 /* No lower threshold */
1423 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1425 /* set hwm to PBA - 2 * max frame size */
1426 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1428 /* Set the interval before transition */
1429 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1430 reg |= 0x800000FF; /* 255 usec */
1431 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1433 /* free space in tx packet buffer to wake from DMA coal */
1434 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1435 (20480 - (2 * sc->max_frame_size)) >> 6);
1437 /* make low power state decision controlled by DMA coal */
1438 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1439 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1440 reg | E1000_PCIEMISC_LX_DECISION);
1441 if_printf(ifp, "DMA Coalescing enabled\n");
1444 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1445 e1000_get_phy_info(hw);
1446 e1000_check_for_link(hw);
1450 igb_setup_ifp(struct igb_softc *sc)
1452 struct ifnet *ifp = &sc->arpcom.ac_if;
1455 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1456 ifp->if_init = igb_init;
1457 ifp->if_ioctl = igb_ioctl;
1458 ifp->if_start = igb_start;
1459 ifp->if_serialize = igb_serialize;
1460 ifp->if_deserialize = igb_deserialize;
1461 ifp->if_tryserialize = igb_tryserialize;
1463 ifp->if_serialize_assert = igb_serialize_assert;
1465 #ifdef IFPOLL_ENABLE
1466 ifp->if_npoll = igb_npoll;
1469 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1470 ifq_set_ready(&ifp->if_snd);
1472 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1474 ifp->if_capabilities =
1475 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1476 if (IGB_ENABLE_HWRSS(sc))
1477 ifp->if_capabilities |= IFCAP_RSS;
1478 ifp->if_capenable = ifp->if_capabilities;
1479 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1482 * Tell the upper layer(s) we support long frames
1484 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1487 * Specify the media types supported by this adapter and register
1488 * callbacks to update media and link information
1490 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1491 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1492 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1493 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1495 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1497 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1498 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1500 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1501 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1503 if (sc->hw.phy.type != e1000_phy_ife) {
1504 ifmedia_add(&sc->media,
1505 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1506 ifmedia_add(&sc->media,
1507 IFM_ETHER | IFM_1000_T, 0, NULL);
1510 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1511 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1515 igb_add_sysctl(struct igb_softc *sc)
1520 sysctl_ctx_init(&sc->sysctl_ctx);
1521 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1522 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1523 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1524 if (sc->sysctl_tree == NULL) {
1525 device_printf(sc->dev, "can't add sysctl node\n");
1529 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1530 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1531 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1532 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1533 "# of RX rings used");
1534 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1535 OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1536 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1537 OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1538 "# of TX rings used");
1539 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1540 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1542 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1543 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1546 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1547 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1548 SYSCTL_CHILDREN(sc->sysctl_tree),
1549 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1550 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1552 for (i = 0; i < sc->msix_cnt; ++i) {
1553 struct igb_msix_data *msix = &sc->msix_data[i];
1555 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1556 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1557 SYSCTL_CHILDREN(sc->sysctl_tree),
1558 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1559 msix, 0, igb_sysctl_msix_rate, "I",
1560 msix->msix_rate_desc);
1564 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1565 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1566 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1567 "# of segments per TX interrupt");
1569 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1570 OID_AUTO, "tx_wreg_nsegs", CTLFLAG_RW,
1571 &sc->tx_rings[0].wreg_nsegs, 0,
1572 "# of segments before write to hardare register");
1574 #ifdef IFPOLL_ENABLE
1575 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1576 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1577 sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1578 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1579 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1580 sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1583 #ifdef IGB_RSS_DEBUG
1584 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1585 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1588 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1589 #ifdef IGB_RSS_DEBUG
1590 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1591 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1592 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1593 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1595 ksnprintf(node, sizeof(node), "rx%d_wreg", i);
1596 SYSCTL_ADD_INT(&sc->sysctl_ctx,
1597 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1598 CTLFLAG_RW, &sc->rx_rings[i].rx_wreg, 0,
1599 "# of segments before write to hardare register");
1604 igb_alloc_rings(struct igb_softc *sc)
1609 * Create top level busdma tag
1611 error = bus_dma_tag_create(NULL, 1, 0,
1612 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1613 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1616 device_printf(sc->dev, "could not create top level DMA tag\n");
1621 * Allocate TX descriptor rings and buffers
1623 sc->tx_rings = kmalloc_cachealign(
1624 sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1625 M_DEVBUF, M_WAITOK | M_ZERO);
1626 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1627 struct igb_tx_ring *txr = &sc->tx_rings[i];
1629 /* Set up some basics */
1632 lwkt_serialize_init(&txr->tx_serialize);
1634 error = igb_create_tx_ring(txr);
1640 * Allocate RX descriptor rings and buffers
1642 sc->rx_rings = kmalloc_cachealign(
1643 sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1644 M_DEVBUF, M_WAITOK | M_ZERO);
1645 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1646 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1648 /* Set up some basics */
1651 lwkt_serialize_init(&rxr->rx_serialize);
1653 error = igb_create_rx_ring(rxr);
1662 igb_free_rings(struct igb_softc *sc)
1666 if (sc->tx_rings != NULL) {
1667 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1668 struct igb_tx_ring *txr = &sc->tx_rings[i];
1670 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1672 kfree(sc->tx_rings, M_DEVBUF);
1675 if (sc->rx_rings != NULL) {
1676 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1677 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1679 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1681 kfree(sc->rx_rings, M_DEVBUF);
1686 igb_create_tx_ring(struct igb_tx_ring *txr)
1688 int tsize, error, i, ntxd;
1691 * Validate number of transmit descriptors. It must not exceed
1692 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1694 ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1695 if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1696 ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1697 device_printf(txr->sc->dev,
1698 "Using %d TX descriptors instead of %d!\n",
1699 IGB_DEFAULT_TXD, ntxd);
1700 txr->num_tx_desc = IGB_DEFAULT_TXD;
1702 txr->num_tx_desc = ntxd;
1706 * Allocate TX descriptor ring
1708 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1710 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1711 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1712 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1713 if (txr->txdma.dma_vaddr == NULL) {
1714 device_printf(txr->sc->dev,
1715 "Unable to allocate TX Descriptor memory\n");
1718 txr->tx_base = txr->txdma.dma_vaddr;
1719 bzero(txr->tx_base, tsize);
1721 tsize = __VM_CACHELINE_ALIGN(
1722 sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1723 txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1726 * Allocate TX head write-back buffer
1728 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1729 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1730 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1731 if (txr->tx_hdr == NULL) {
1732 device_printf(txr->sc->dev,
1733 "Unable to allocate TX head write-back buffer\n");
1738 * Create DMA tag for TX buffers
1740 error = bus_dma_tag_create(txr->sc->parent_tag,
1741 1, 0, /* alignment, bounds */
1742 BUS_SPACE_MAXADDR, /* lowaddr */
1743 BUS_SPACE_MAXADDR, /* highaddr */
1744 NULL, NULL, /* filter, filterarg */
1745 IGB_TSO_SIZE, /* maxsize */
1746 IGB_MAX_SCATTER, /* nsegments */
1747 PAGE_SIZE, /* maxsegsize */
1748 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1749 BUS_DMA_ONEBPAGE, /* flags */
1752 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1753 kfree(txr->tx_buf, M_DEVBUF);
1759 * Create DMA maps for TX buffers
1761 for (i = 0; i < txr->num_tx_desc; ++i) {
1762 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1764 error = bus_dmamap_create(txr->tx_tag,
1765 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1767 device_printf(txr->sc->dev,
1768 "Unable to create TX DMA map\n");
1769 igb_destroy_tx_ring(txr, i);
1775 * Initialize various watermark
1777 txr->spare_desc = IGB_TX_SPARE;
1778 txr->intr_nsegs = txr->num_tx_desc / 16;
1779 txr->wreg_nsegs = 8;
1780 txr->oact_hi_desc = txr->num_tx_desc / 2;
1781 txr->oact_lo_desc = txr->num_tx_desc / 8;
1782 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1783 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1784 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1785 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1791 igb_free_tx_ring(struct igb_tx_ring *txr)
1795 for (i = 0; i < txr->num_tx_desc; ++i) {
1796 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1798 if (txbuf->m_head != NULL) {
1799 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1800 m_freem(txbuf->m_head);
1801 txbuf->m_head = NULL;
1807 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1811 if (txr->txdma.dma_vaddr != NULL) {
1812 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1813 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1814 txr->txdma.dma_map);
1815 bus_dma_tag_destroy(txr->txdma.dma_tag);
1816 txr->txdma.dma_vaddr = NULL;
1819 if (txr->tx_hdr != NULL) {
1820 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1821 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1823 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1827 if (txr->tx_buf == NULL)
1830 for (i = 0; i < ndesc; ++i) {
1831 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1833 KKASSERT(txbuf->m_head == NULL);
1834 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1836 bus_dma_tag_destroy(txr->tx_tag);
1838 kfree(txr->tx_buf, M_DEVBUF);
1843 igb_init_tx_ring(struct igb_tx_ring *txr)
1845 /* Clear the old descriptor contents */
1847 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1849 /* Clear TX head write-back buffer */
1853 txr->next_avail_desc = 0;
1854 txr->next_to_clean = 0;
1857 /* Set number of descriptors available */
1858 txr->tx_avail = txr->num_tx_desc;
1862 igb_init_tx_unit(struct igb_softc *sc)
1864 struct e1000_hw *hw = &sc->hw;
1868 /* Setup the Tx Descriptor Rings */
1869 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1870 struct igb_tx_ring *txr = &sc->tx_rings[i];
1871 uint64_t bus_addr = txr->txdma.dma_paddr;
1872 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1873 uint32_t txdctl = 0;
1874 uint32_t dca_txctrl;
1876 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1877 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1878 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1879 (uint32_t)(bus_addr >> 32));
1880 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1881 (uint32_t)bus_addr);
1883 /* Setup the HW Tx Head and Tail descriptor pointers */
1884 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1885 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1887 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1888 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1889 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1892 * Don't set WB_on_EITR:
1893 * - 82575 does not have it
1894 * - It almost has no effect on 82576, see:
1895 * 82576 specification update errata #26
1896 * - It causes unnecessary bus traffic
1898 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1899 (uint32_t)(hdr_paddr >> 32));
1900 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1901 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1904 * WTHRESH is ignored by the hardware, since header
1905 * write back mode is used.
1907 txdctl |= IGB_TX_PTHRESH;
1908 txdctl |= IGB_TX_HTHRESH << 8;
1909 txdctl |= IGB_TX_WTHRESH << 16;
1910 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1911 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1917 e1000_config_collision_dist(hw);
1919 /* Program the Transmit Control Register */
1920 tctl = E1000_READ_REG(hw, E1000_TCTL);
1921 tctl &= ~E1000_TCTL_CT;
1922 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1923 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1925 /* This write will effectively turn on the transmit unit. */
1926 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1930 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1932 struct e1000_adv_tx_context_desc *TXD;
1933 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1934 int ehdrlen, ctxd, ip_hlen = 0;
1935 boolean_t offload = TRUE;
1937 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1940 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1942 ctxd = txr->next_avail_desc;
1943 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1946 * In advanced descriptors the vlan tag must
1947 * be placed into the context descriptor, thus
1948 * we need to be here just for that setup.
1950 if (mp->m_flags & M_VLANTAG) {
1953 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1954 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1955 } else if (!offload) {
1959 ehdrlen = mp->m_pkthdr.csum_lhlen;
1960 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1962 /* Set the ether header length */
1963 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1964 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1965 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1966 ip_hlen = mp->m_pkthdr.csum_iphlen;
1967 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1969 vlan_macip_lens |= ip_hlen;
1971 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1972 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1973 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1974 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1975 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1977 /* 82575 needs the queue index added */
1978 if (txr->sc->hw.mac.type == e1000_82575)
1979 mss_l4len_idx = txr->me << 4;
1981 /* Now copy bits into descriptor */
1982 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1983 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1984 TXD->seqnum_seed = htole32(0);
1985 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1987 /* We've consumed the first desc, adjust counters */
1988 if (++ctxd == txr->num_tx_desc)
1990 txr->next_avail_desc = ctxd;
1997 igb_txeof(struct igb_tx_ring *txr)
1999 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
2000 int first, hdr, avail;
2002 if (txr->tx_avail == txr->num_tx_desc)
2005 first = txr->next_to_clean;
2006 hdr = *(txr->tx_hdr);
2011 avail = txr->tx_avail;
2012 while (first != hdr) {
2013 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2016 if (txbuf->m_head) {
2017 bus_dmamap_unload(txr->tx_tag, txbuf->map);
2018 m_freem(txbuf->m_head);
2019 txbuf->m_head = NULL;
2022 if (++first == txr->num_tx_desc)
2025 txr->next_to_clean = first;
2026 txr->tx_avail = avail;
2029 * If we have a minimum free, clear OACTIVE
2030 * to tell the stack that it is OK to send packets.
2032 if (IGB_IS_NOT_OACTIVE(txr)) {
2033 ifsq_clr_oactive(txr->ifsq);
2036 * We have enough TX descriptors, turn off
2037 * the watchdog. We allow small amount of
2038 * packets (roughly intr_nsegs) pending on
2039 * the transmit ring.
2041 txr->tx_watchdog.wd_timer = 0;
2046 igb_create_rx_ring(struct igb_rx_ring *rxr)
2048 int rsize, i, error, nrxd;
2051 * Validate number of receive descriptors. It must not exceed
2052 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2054 nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2055 if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2056 nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2057 device_printf(rxr->sc->dev,
2058 "Using %d RX descriptors instead of %d!\n",
2059 IGB_DEFAULT_RXD, nrxd);
2060 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2062 rxr->num_rx_desc = nrxd;
2066 * Allocate RX descriptor ring
2068 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2070 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2071 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2072 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2073 &rxr->rxdma.dma_paddr);
2074 if (rxr->rxdma.dma_vaddr == NULL) {
2075 device_printf(rxr->sc->dev,
2076 "Unable to allocate RxDescriptor memory\n");
2079 rxr->rx_base = rxr->rxdma.dma_vaddr;
2080 bzero(rxr->rx_base, rsize);
2082 rsize = __VM_CACHELINE_ALIGN(
2083 sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2084 rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2087 * Create DMA tag for RX buffers
2089 error = bus_dma_tag_create(rxr->sc->parent_tag,
2090 1, 0, /* alignment, bounds */
2091 BUS_SPACE_MAXADDR, /* lowaddr */
2092 BUS_SPACE_MAXADDR, /* highaddr */
2093 NULL, NULL, /* filter, filterarg */
2094 MCLBYTES, /* maxsize */
2096 MCLBYTES, /* maxsegsize */
2097 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2100 device_printf(rxr->sc->dev,
2101 "Unable to create RX payload DMA tag\n");
2102 kfree(rxr->rx_buf, M_DEVBUF);
2108 * Create spare DMA map for RX buffers
2110 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2113 device_printf(rxr->sc->dev,
2114 "Unable to create spare RX DMA maps\n");
2115 bus_dma_tag_destroy(rxr->rx_tag);
2116 kfree(rxr->rx_buf, M_DEVBUF);
2122 * Create DMA maps for RX buffers
2124 for (i = 0; i < rxr->num_rx_desc; i++) {
2125 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2127 error = bus_dmamap_create(rxr->rx_tag,
2128 BUS_DMA_WAITOK, &rxbuf->map);
2130 device_printf(rxr->sc->dev,
2131 "Unable to create RX DMA maps\n");
2132 igb_destroy_rx_ring(rxr, i);
2138 * Initialize various watermark
2146 igb_free_rx_ring(struct igb_rx_ring *rxr)
2150 for (i = 0; i < rxr->num_rx_desc; ++i) {
2151 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2153 if (rxbuf->m_head != NULL) {
2154 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2155 m_freem(rxbuf->m_head);
2156 rxbuf->m_head = NULL;
2160 if (rxr->fmp != NULL)
2167 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2171 if (rxr->rxdma.dma_vaddr != NULL) {
2172 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2173 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2174 rxr->rxdma.dma_map);
2175 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2176 rxr->rxdma.dma_vaddr = NULL;
2179 if (rxr->rx_buf == NULL)
2182 for (i = 0; i < ndesc; ++i) {
2183 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2185 KKASSERT(rxbuf->m_head == NULL);
2186 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2188 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2189 bus_dma_tag_destroy(rxr->rx_tag);
2191 kfree(rxr->rx_buf, M_DEVBUF);
2196 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2198 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2199 rxd->wb.upper.status_error = 0;
2203 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2206 bus_dma_segment_t seg;
2208 struct igb_rx_buf *rxbuf;
2211 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2214 if_printf(&rxr->sc->arpcom.ac_if,
2215 "Unable to allocate RX mbuf\n");
2219 m->m_len = m->m_pkthdr.len = MCLBYTES;
2221 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2222 m_adj(m, ETHER_ALIGN);
2224 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2225 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2229 if_printf(&rxr->sc->arpcom.ac_if,
2230 "Unable to load RX mbuf\n");
2235 rxbuf = &rxr->rx_buf[i];
2236 if (rxbuf->m_head != NULL)
2237 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2240 rxbuf->map = rxr->rx_sparemap;
2241 rxr->rx_sparemap = map;
2244 rxbuf->paddr = seg.ds_addr;
2246 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2251 igb_init_rx_ring(struct igb_rx_ring *rxr)
2255 /* Clear the ring contents */
2257 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2259 /* Now replenish the ring mbufs */
2260 for (i = 0; i < rxr->num_rx_desc; ++i) {
2263 error = igb_newbuf(rxr, i, TRUE);
2268 /* Setup our descriptor indices */
2269 rxr->next_to_check = 0;
2273 rxr->discard = FALSE;
2279 igb_init_rx_unit(struct igb_softc *sc)
2281 struct ifnet *ifp = &sc->arpcom.ac_if;
2282 struct e1000_hw *hw = &sc->hw;
2283 uint32_t rctl, rxcsum, srrctl = 0;
2287 * Make sure receives are disabled while setting
2288 * up the descriptor ring
2290 rctl = E1000_READ_REG(hw, E1000_RCTL);
2291 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2295 ** Set up for header split
2297 if (igb_header_split) {
2298 /* Use a standard mbuf for the header */
2299 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2300 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2303 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2306 ** Set up for jumbo frames
2308 if (ifp->if_mtu > ETHERMTU) {
2309 rctl |= E1000_RCTL_LPE;
2311 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2312 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2313 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2314 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2315 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2316 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2318 /* Set maximum packet len */
2319 psize = adapter->max_frame_size;
2320 /* are we on a vlan? */
2321 if (adapter->ifp->if_vlantrunk != NULL)
2322 psize += VLAN_TAG_SIZE;
2323 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2325 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2326 rctl |= E1000_RCTL_SZ_2048;
2329 rctl &= ~E1000_RCTL_LPE;
2330 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2331 rctl |= E1000_RCTL_SZ_2048;
2334 /* Setup the Base and Length of the Rx Descriptor Rings */
2335 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2336 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2337 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2340 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2341 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2342 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2343 (uint32_t)(bus_addr >> 32));
2344 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2345 (uint32_t)bus_addr);
2346 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2347 /* Enable this Queue */
2348 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2349 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2350 rxdctl &= 0xFFF00000;
2351 rxdctl |= IGB_RX_PTHRESH;
2352 rxdctl |= IGB_RX_HTHRESH << 8;
2354 * Don't set WTHRESH to a value above 1 on 82576, see:
2355 * 82576 specification update errata #26
2357 rxdctl |= IGB_RX_WTHRESH << 16;
2358 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2361 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2362 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2365 * Receive Checksum Offload for TCP and UDP
2367 * Checksum offloading is also enabled if multiple receive
2368 * queue is to be supported, since we need it to figure out
2371 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2374 * PCSD must be enabled to enable multiple
2377 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2380 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2383 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2385 if (IGB_ENABLE_HWRSS(sc)) {
2386 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2387 uint32_t reta_shift;
2392 * When we reach here, RSS has already been disabled
2393 * in igb_stop(), so we could safely configure RSS key
2394 * and redirect table.
2400 toeplitz_get_key(key, sizeof(key));
2401 for (i = 0; i < IGB_NRSSRK; ++i) {
2404 rssrk = IGB_RSSRK_VAL(key, i);
2405 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2407 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2411 * Configure RSS redirect table in following fashion:
2412 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2414 reta_shift = IGB_RETA_SHIFT;
2415 if (hw->mac.type == e1000_82575)
2416 reta_shift = IGB_RETA_SHIFT_82575;
2419 for (j = 0; j < IGB_NRETA; ++j) {
2422 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2425 q = (r % sc->rx_ring_inuse) << reta_shift;
2426 reta |= q << (8 * i);
2429 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2430 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2434 * Enable multiple receive queues.
2435 * Enable IPv4 RSS standard hash functions.
2436 * Disable RSS interrupt on 82575
2438 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2439 E1000_MRQC_ENABLE_RSS_4Q |
2440 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2441 E1000_MRQC_RSS_FIELD_IPV4);
2444 /* Setup the Receive Control Register */
2445 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2446 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2447 E1000_RCTL_RDMTS_HALF |
2448 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2449 /* Strip CRC bytes. */
2450 rctl |= E1000_RCTL_SECRC;
2451 /* Make sure VLAN Filters are off */
2452 rctl &= ~E1000_RCTL_VFE;
2453 /* Don't store bad packets */
2454 rctl &= ~E1000_RCTL_SBP;
2456 /* Enable Receives */
2457 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2460 * Setup the HW Rx Head and Tail Descriptor Pointers
2461 * - needs to be after enable
2463 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2464 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2466 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2467 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2472 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2475 i = rxr->num_rx_desc - 1;
2476 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2480 igb_rxeof(struct igb_rx_ring *rxr, int count)
2482 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2483 union e1000_adv_rx_desc *cur;
2487 i = rxr->next_to_check;
2488 cur = &rxr->rx_base[i];
2489 staterr = le32toh(cur->wb.upper.status_error);
2491 if ((staterr & E1000_RXD_STAT_DD) == 0)
2494 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2495 struct pktinfo *pi = NULL, pi0;
2496 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2497 struct mbuf *m = NULL;
2500 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2505 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2507 struct mbuf *mp = rxbuf->m_head;
2508 uint32_t hash, hashtype;
2512 len = le16toh(cur->wb.upper.length);
2513 if (rxr->sc->hw.mac.type == e1000_i350 &&
2514 (staterr & E1000_RXDEXT_STATERR_LB))
2515 vlan = be16toh(cur->wb.upper.vlan);
2517 vlan = le16toh(cur->wb.upper.vlan);
2519 hash = le32toh(cur->wb.lower.hi_dword.rss);
2520 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2521 E1000_RXDADV_RSSTYPE_MASK;
2523 IGB_RSS_DPRINTF(rxr->sc, 10,
2524 "ring%d, hash 0x%08x, hashtype %u\n",
2525 rxr->me, hash, hashtype);
2527 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2528 BUS_DMASYNC_POSTREAD);
2530 if (igb_newbuf(rxr, i, FALSE) != 0) {
2536 if (rxr->fmp == NULL) {
2537 mp->m_pkthdr.len = len;
2541 rxr->lmp->m_next = mp;
2542 rxr->lmp = rxr->lmp->m_next;
2543 rxr->fmp->m_pkthdr.len += len;
2551 m->m_pkthdr.rcvif = ifp;
2554 if (ifp->if_capenable & IFCAP_RXCSUM)
2555 igb_rxcsum(staterr, m);
2557 if (staterr & E1000_RXD_STAT_VP) {
2558 m->m_pkthdr.ether_vlantag = vlan;
2559 m->m_flags |= M_VLANTAG;
2562 if (ifp->if_capenable & IFCAP_RSS) {
2563 pi = igb_rssinfo(m, &pi0,
2564 hash, hashtype, staterr);
2566 #ifdef IGB_RSS_DEBUG
2573 igb_setup_rxdesc(cur, rxbuf);
2575 rxr->discard = TRUE;
2577 rxr->discard = FALSE;
2578 if (rxr->fmp != NULL) {
2587 ether_input_pkt(ifp, m, pi);
2589 /* Advance our pointers to the next descriptor. */
2590 if (++i == rxr->num_rx_desc)
2593 if (ncoll >= rxr->rx_wreg) {
2594 igb_rx_refresh(rxr, i);
2598 cur = &rxr->rx_base[i];
2599 staterr = le32toh(cur->wb.upper.status_error);
2601 rxr->next_to_check = i;
2604 igb_rx_refresh(rxr, i);
2609 igb_set_vlan(struct igb_softc *sc)
2611 struct e1000_hw *hw = &sc->hw;
2614 struct ifnet *ifp = sc->arpcom.ac_if;
2618 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2622 reg = E1000_READ_REG(hw, E1000_CTRL);
2623 reg |= E1000_CTRL_VME;
2624 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2627 /* Enable the Filter Table */
2628 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2629 reg = E1000_READ_REG(hw, E1000_RCTL);
2630 reg &= ~E1000_RCTL_CFIEN;
2631 reg |= E1000_RCTL_VFE;
2632 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2636 /* Update the frame size */
2637 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2638 sc->max_frame_size + VLAN_TAG_SIZE);
2641 /* Don't bother with table if no vlans */
2642 if ((adapter->num_vlans == 0) ||
2643 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2646 ** A soft reset zero's out the VFTA, so
2647 ** we need to repopulate it now.
2649 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2650 if (adapter->shadow_vfta[i] != 0) {
2651 if (adapter->vf_ifp)
2652 e1000_vfta_set_vf(hw,
2653 adapter->shadow_vfta[i], TRUE);
2655 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2656 i, adapter->shadow_vfta[i]);
2662 igb_enable_intr(struct igb_softc *sc)
2664 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2665 lwkt_serialize_handler_enable(&sc->main_serialize);
2669 for (i = 0; i < sc->msix_cnt; ++i) {
2670 lwkt_serialize_handler_enable(
2671 sc->msix_data[i].msix_serialize);
2675 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2676 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2677 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2679 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2680 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2681 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2682 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2684 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2686 E1000_WRITE_FLUSH(&sc->hw);
2690 igb_disable_intr(struct igb_softc *sc)
2692 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2693 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2694 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2696 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2697 E1000_WRITE_FLUSH(&sc->hw);
2699 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2700 lwkt_serialize_handler_disable(&sc->main_serialize);
2704 for (i = 0; i < sc->msix_cnt; ++i) {
2705 lwkt_serialize_handler_disable(
2706 sc->msix_data[i].msix_serialize);
2712 * Bit of a misnomer, what this really means is
2713 * to enable OS management of the system... aka
2714 * to disable special hardware management features
2717 igb_get_mgmt(struct igb_softc *sc)
2719 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2720 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2721 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2723 /* disable hardware interception of ARP */
2724 manc &= ~E1000_MANC_ARP_EN;
2726 /* enable receiving management packets to the host */
2727 manc |= E1000_MANC_EN_MNG2HOST;
2728 manc2h |= 1 << 5; /* Mng Port 623 */
2729 manc2h |= 1 << 6; /* Mng Port 664 */
2730 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2731 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2736 * Give control back to hardware management controller
2740 igb_rel_mgmt(struct igb_softc *sc)
2742 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2743 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2745 /* Re-enable hardware interception of ARP */
2746 manc |= E1000_MANC_ARP_EN;
2747 manc &= ~E1000_MANC_EN_MNG2HOST;
2749 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2754 * Sets CTRL_EXT:DRV_LOAD bit.
2756 * For ASF and Pass Through versions of f/w this means that
2757 * the driver is loaded.
2760 igb_get_hw_control(struct igb_softc *sc)
2767 /* Let firmware know the driver has taken over */
2768 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2769 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2770 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2774 * Resets CTRL_EXT:DRV_LOAD bit.
2776 * For ASF and Pass Through versions of f/w this means that the
2777 * driver is no longer loaded.
2780 igb_rel_hw_control(struct igb_softc *sc)
2787 /* Let firmware taken over control of h/w */
2788 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2789 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2790 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2794 igb_is_valid_ether_addr(const uint8_t *addr)
2796 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2798 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2804 * Enable PCI Wake On Lan capability
2807 igb_enable_wol(device_t dev)
2809 uint16_t cap, status;
2812 /* First find the capabilities pointer*/
2813 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2815 /* Read the PM Capabilities */
2816 id = pci_read_config(dev, cap, 1);
2817 if (id != PCIY_PMG) /* Something wrong */
2821 * OK, we have the power capabilities,
2822 * so now get the status register
2824 cap += PCIR_POWER_STATUS;
2825 status = pci_read_config(dev, cap, 2);
2826 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2827 pci_write_config(dev, cap, status, 2);
2831 igb_update_stats_counters(struct igb_softc *sc)
2833 struct e1000_hw *hw = &sc->hw;
2834 struct e1000_hw_stats *stats;
2835 struct ifnet *ifp = &sc->arpcom.ac_if;
2838 * The virtual function adapter has only a
2839 * small controlled set of stats, do only
2843 igb_update_vf_stats_counters(sc);
2848 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2849 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2851 E1000_READ_REG(hw,E1000_SYMERRS);
2852 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2855 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2856 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2857 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2858 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2860 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2861 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2862 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2863 stats->dc += E1000_READ_REG(hw, E1000_DC);
2864 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2865 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2866 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2869 * For watchdog management we need to know if we have been
2870 * paused during the last interval, so capture that here.
2872 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2873 stats->xoffrxc += sc->pause_frames;
2874 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2875 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2876 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2877 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2878 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2879 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2880 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2881 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2882 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2883 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2884 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2885 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2887 /* For the 64-bit byte counters the low dword must be read first. */
2888 /* Both registers clear on the read of the high dword */
2890 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2891 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2892 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2893 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2895 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2896 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2897 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2898 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2899 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2901 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2902 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2904 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2905 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2906 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2907 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2908 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2909 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2910 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2911 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2912 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2913 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2915 /* Interrupt Counts */
2917 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2918 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2919 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2920 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2921 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2922 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2923 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2924 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2925 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2927 /* Host to Card Statistics */
2929 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2930 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2931 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2932 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2933 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2934 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2935 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2936 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2937 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2938 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2939 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2940 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2941 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2942 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2944 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2945 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2946 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2947 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2948 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2949 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2951 ifp->if_collisions = stats->colc;
2954 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2955 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2958 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2960 /* Driver specific counters */
2961 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2962 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2963 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2964 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2965 sc->packet_buf_alloc_tx =
2966 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2967 sc->packet_buf_alloc_rx =
2968 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2972 igb_vf_init_stats(struct igb_softc *sc)
2974 struct e1000_hw *hw = &sc->hw;
2975 struct e1000_vf_stats *stats;
2978 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2979 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2980 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2981 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2982 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2986 igb_update_vf_stats_counters(struct igb_softc *sc)
2988 struct e1000_hw *hw = &sc->hw;
2989 struct e1000_vf_stats *stats;
2991 if (sc->link_speed == 0)
2995 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2996 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2997 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2998 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2999 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3002 #ifdef IFPOLL_ENABLE
3005 igb_npoll_status(struct ifnet *ifp)
3007 struct igb_softc *sc = ifp->if_softc;
3010 ASSERT_SERIALIZED(&sc->main_serialize);
3012 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3013 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3014 sc->hw.mac.get_link_status = 1;
3015 igb_update_link_status(sc);
3020 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3022 struct igb_tx_ring *txr = arg;
3024 ASSERT_SERIALIZED(&txr->tx_serialize);
3027 if (!ifsq_is_empty(txr->ifsq))
3028 ifsq_devstart(txr->ifsq);
3032 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3034 struct igb_rx_ring *rxr = arg;
3036 ASSERT_SERIALIZED(&rxr->rx_serialize);
3038 igb_rxeof(rxr, cycle);
3042 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3044 struct igb_softc *sc = ifp->if_softc;
3045 int i, txr_cnt, rxr_cnt;
3047 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3052 info->ifpi_status.status_func = igb_npoll_status;
3053 info->ifpi_status.serializer = &sc->main_serialize;
3055 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3056 off = sc->tx_npoll_off;
3057 for (i = 0; i < txr_cnt; ++i) {
3058 struct igb_tx_ring *txr = &sc->tx_rings[i];
3061 KKASSERT(idx < ncpus2);
3062 info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3063 info->ifpi_tx[idx].arg = txr;
3064 info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3065 ifsq_set_cpuid(txr->ifsq, idx);
3068 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3069 off = sc->rx_npoll_off;
3070 for (i = 0; i < rxr_cnt; ++i) {
3071 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3074 KKASSERT(idx < ncpus2);
3075 info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3076 info->ifpi_rx[idx].arg = rxr;
3077 info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3080 if (ifp->if_flags & IFF_RUNNING) {
3081 if (rxr_cnt == sc->rx_ring_inuse &&
3082 txr_cnt == sc->tx_ring_inuse)
3083 igb_disable_intr(sc);
3088 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3089 struct igb_tx_ring *txr = &sc->tx_rings[i];
3091 ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3094 if (ifp->if_flags & IFF_RUNNING) {
3095 txr_cnt = igb_get_txring_inuse(sc, FALSE);
3096 rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3098 if (rxr_cnt == sc->rx_ring_inuse &&
3099 txr_cnt == sc->tx_ring_inuse)
3100 igb_enable_intr(sc);
3107 #endif /* IFPOLL_ENABLE */
3112 struct igb_softc *sc = xsc;
3113 struct ifnet *ifp = &sc->arpcom.ac_if;
3116 ASSERT_SERIALIZED(&sc->main_serialize);
3118 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3123 if (ifp->if_flags & IFF_RUNNING) {
3124 struct igb_tx_ring *txr = &sc->tx_rings[0];
3127 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3128 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3130 if (eicr & rxr->rx_intr_mask) {
3131 lwkt_serialize_enter(&rxr->rx_serialize);
3133 lwkt_serialize_exit(&rxr->rx_serialize);
3137 if (eicr & txr->tx_intr_mask) {
3138 lwkt_serialize_enter(&txr->tx_serialize);
3140 if (!ifsq_is_empty(txr->ifsq))
3141 ifsq_devstart(txr->ifsq);
3142 lwkt_serialize_exit(&txr->tx_serialize);
3146 if (eicr & E1000_EICR_OTHER) {
3147 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3149 /* Link status change */
3150 if (icr & E1000_ICR_LSC) {
3151 sc->hw.mac.get_link_status = 1;
3152 igb_update_link_status(sc);
3157 * Reading EICR has the side effect to clear interrupt mask,
3158 * so all interrupts need to be enabled here.
3160 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3164 igb_intr_shared(void *xsc)
3166 struct igb_softc *sc = xsc;
3167 struct ifnet *ifp = &sc->arpcom.ac_if;
3170 ASSERT_SERIALIZED(&sc->main_serialize);
3172 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3175 if (reg_icr == 0xffffffff)
3178 /* Definitely not our interrupt. */
3182 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3185 if (ifp->if_flags & IFF_RUNNING) {
3187 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3190 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3191 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3193 lwkt_serialize_enter(&rxr->rx_serialize);
3195 lwkt_serialize_exit(&rxr->rx_serialize);
3199 if (reg_icr & E1000_ICR_TXDW) {
3200 struct igb_tx_ring *txr = &sc->tx_rings[0];
3202 lwkt_serialize_enter(&txr->tx_serialize);
3204 if (!ifsq_is_empty(txr->ifsq))
3205 ifsq_devstart(txr->ifsq);
3206 lwkt_serialize_exit(&txr->tx_serialize);
3210 /* Link status change */
3211 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3212 sc->hw.mac.get_link_status = 1;
3213 igb_update_link_status(sc);
3216 if (reg_icr & E1000_ICR_RXO)
3221 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3222 int *segs_used, int *idx)
3224 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3226 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3227 union e1000_adv_tx_desc *txd = NULL;
3228 struct mbuf *m_head = *m_headp;
3229 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3230 int maxsegs, nsegs, i, j, error;
3231 uint32_t hdrlen = 0;
3233 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3234 error = igb_tso_pullup(txr, m_headp);
3240 /* Set basic descriptor constants */
3241 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3242 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3243 if (m_head->m_flags & M_VLANTAG)
3244 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3247 * Map the packet for DMA.
3249 tx_buf = &txr->tx_buf[txr->next_avail_desc];
3250 tx_buf_mapped = tx_buf;
3253 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3254 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3255 if (maxsegs > IGB_MAX_SCATTER)
3256 maxsegs = IGB_MAX_SCATTER;
3258 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3259 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3261 if (error == ENOBUFS)
3262 txr->sc->mbuf_defrag_failed++;
3264 txr->sc->no_tx_dma_setup++;
3270 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3275 * Set up the TX context descriptor, if any hardware offloading is
3276 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3279 * Unlike these chips' predecessors (em/emx), TX context descriptor
3280 * will _not_ interfere TX data fetching pipelining.
3282 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3283 igb_tso_ctx(txr, m_head, &hdrlen);
3284 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3285 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3286 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3289 } else if (igb_txcsum_ctx(txr, m_head)) {
3290 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3291 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3292 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3293 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3298 *segs_used += nsegs;
3299 txr->tx_nsegs += nsegs;
3300 if (txr->tx_nsegs >= txr->intr_nsegs) {
3302 * Report Status (RS) is turned on every intr_nsegs
3303 * descriptors (roughly).
3306 cmd_rs = E1000_ADVTXD_DCMD_RS;
3309 /* Calculate payload length */
3310 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3311 << E1000_ADVTXD_PAYLEN_SHIFT);
3313 /* 82575 needs the queue index added */
3314 if (txr->sc->hw.mac.type == e1000_82575)
3315 olinfo_status |= txr->me << 4;
3317 /* Set up our transmit descriptors */
3318 i = txr->next_avail_desc;
3319 for (j = 0; j < nsegs; j++) {
3321 bus_addr_t seg_addr;
3323 tx_buf = &txr->tx_buf[i];
3324 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3325 seg_addr = segs[j].ds_addr;
3326 seg_len = segs[j].ds_len;
3328 txd->read.buffer_addr = htole64(seg_addr);
3329 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3330 txd->read.olinfo_status = htole32(olinfo_status);
3331 if (++i == txr->num_tx_desc)
3333 tx_buf->m_head = NULL;
3336 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3337 txr->next_avail_desc = i;
3338 txr->tx_avail -= nsegs;
3340 tx_buf->m_head = m_head;
3341 tx_buf_mapped->map = tx_buf->map;
3345 * Last Descriptor of Packet needs End Of Packet (EOP)
3347 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3350 * Defer TDT updating, until enough descrptors are setup
3359 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3361 struct igb_softc *sc = ifp->if_softc;
3362 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3363 struct mbuf *m_head;
3364 int idx = -1, nsegs = 0;
3366 KKASSERT(txr->ifsq == ifsq);
3367 ASSERT_SERIALIZED(&txr->tx_serialize);
3369 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3372 if (!sc->link_active) {
3377 if (!IGB_IS_NOT_OACTIVE(txr))
3380 while (!ifsq_is_empty(ifsq)) {
3381 if (IGB_IS_OACTIVE(txr)) {
3382 ifsq_set_oactive(ifsq);
3383 /* Set watchdog on */
3384 txr->tx_watchdog.wd_timer = 5;
3388 m_head = ifsq_dequeue(ifsq, NULL);
3392 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3397 if (nsegs >= txr->wreg_nsegs) {
3398 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3403 /* Send a copy of the frame to the BPF listener */
3404 ETHER_BPF_MTAP(ifp, m_head);
3407 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3411 igb_watchdog(struct ifaltq_subque *ifsq)
3413 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3414 struct ifnet *ifp = ifsq_get_ifp(ifsq);
3415 struct igb_softc *sc = ifp->if_softc;
3418 KKASSERT(txr->ifsq == ifsq);
3419 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3422 * If flow control has paused us since last checking
3423 * it invalidates the watchdog timing, so dont run it.
3425 if (sc->pause_frames) {
3426 sc->pause_frames = 0;
3427 txr->tx_watchdog.wd_timer = 5;
3431 if_printf(ifp, "Watchdog timeout -- resetting\n");
3432 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3433 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3434 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3435 if_printf(ifp, "TX(%d) desc avail = %d, "
3436 "Next TX to Clean = %d\n",
3437 txr->me, txr->tx_avail, txr->next_to_clean);
3440 sc->watchdog_events++;
3443 for (i = 0; i < sc->tx_ring_inuse; ++i)
3444 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3448 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3453 if (sc->hw.mac.type == e1000_82575) {
3454 eitr = 1000000000 / 256 / rate;
3457 * Document is wrong on the 2 bits left shift
3460 eitr = 1000000 / rate;
3461 eitr <<= IGB_EITR_INTVL_SHIFT;
3465 /* Don't disable it */
3466 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3467 } else if (eitr > IGB_EITR_INTVL_MASK) {
3468 /* Don't allow it to be too large */
3469 eitr = IGB_EITR_INTVL_MASK;
3472 if (sc->hw.mac.type == e1000_82575)
3475 eitr |= E1000_EITR_CNT_IGNR;
3476 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3480 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3482 struct igb_softc *sc = (void *)arg1;
3483 struct ifnet *ifp = &sc->arpcom.ac_if;
3484 int error, intr_rate;
3486 intr_rate = sc->intr_rate;
3487 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3488 if (error || req->newptr == NULL)
3493 ifnet_serialize_all(ifp);
3495 sc->intr_rate = intr_rate;
3496 if (ifp->if_flags & IFF_RUNNING)
3497 igb_set_eitr(sc, 0, sc->intr_rate);
3500 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3502 ifnet_deserialize_all(ifp);
3508 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3510 struct igb_msix_data *msix = (void *)arg1;
3511 struct igb_softc *sc = msix->msix_sc;
3512 struct ifnet *ifp = &sc->arpcom.ac_if;
3513 int error, msix_rate;
3515 msix_rate = msix->msix_rate;
3516 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3517 if (error || req->newptr == NULL)
3522 lwkt_serialize_enter(msix->msix_serialize);
3524 msix->msix_rate = msix_rate;
3525 if (ifp->if_flags & IFF_RUNNING)
3526 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3529 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3533 lwkt_serialize_exit(msix->msix_serialize);
3539 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3541 struct igb_softc *sc = (void *)arg1;
3542 struct ifnet *ifp = &sc->arpcom.ac_if;
3543 struct igb_tx_ring *txr = &sc->tx_rings[0];
3546 nsegs = txr->intr_nsegs;
3547 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3548 if (error || req->newptr == NULL)
3553 ifnet_serialize_all(ifp);
3555 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3556 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3560 txr->intr_nsegs = nsegs;
3563 ifnet_deserialize_all(ifp);
3568 #ifdef IFPOLL_ENABLE
3571 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3573 struct igb_softc *sc = (void *)arg1;
3574 struct ifnet *ifp = &sc->arpcom.ac_if;
3577 off = sc->rx_npoll_off;
3578 error = sysctl_handle_int(oidp, &off, 0, req);
3579 if (error || req->newptr == NULL)
3584 ifnet_serialize_all(ifp);
3585 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3589 sc->rx_npoll_off = off;
3591 ifnet_deserialize_all(ifp);
3597 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3599 struct igb_softc *sc = (void *)arg1;
3600 struct ifnet *ifp = &sc->arpcom.ac_if;
3603 off = sc->tx_npoll_off;
3604 error = sysctl_handle_int(oidp, &off, 0, req);
3605 if (error || req->newptr == NULL)
3610 ifnet_serialize_all(ifp);
3611 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3615 sc->tx_npoll_off = off;
3617 ifnet_deserialize_all(ifp);
3622 #endif /* IFPOLL_ENABLE */
3625 igb_init_intr(struct igb_softc *sc)
3627 igb_set_intr_mask(sc);
3629 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3630 igb_init_unshared_intr(sc);
3632 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3633 igb_set_eitr(sc, 0, sc->intr_rate);
3637 for (i = 0; i < sc->msix_cnt; ++i)
3638 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3643 igb_init_unshared_intr(struct igb_softc *sc)
3645 struct e1000_hw *hw = &sc->hw;
3646 const struct igb_rx_ring *rxr;
3647 const struct igb_tx_ring *txr;
3648 uint32_t ivar, index;
3652 * Enable extended mode
3654 if (sc->hw.mac.type != e1000_82575) {
3658 gpie = E1000_GPIE_NSICR;
3659 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3660 gpie |= E1000_GPIE_MSIX_MODE |
3664 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3669 switch (sc->hw.mac.type) {
3671 ivar_max = IGB_MAX_IVAR_82580;
3675 ivar_max = IGB_MAX_IVAR_I350;
3679 case e1000_vfadapt_i350:
3680 ivar_max = IGB_MAX_IVAR_VF;
3684 ivar_max = IGB_MAX_IVAR_82576;
3688 panic("unknown mac type %d\n", sc->hw.mac.type);
3690 for (i = 0; i < ivar_max; ++i)
3691 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3692 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3696 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3697 ("82575 w/ MSI-X"));
3698 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3699 tmp |= E1000_CTRL_EXT_IRCA;
3700 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3704 * Map TX/RX interrupts to EICR
3706 switch (sc->hw.mac.type) {
3710 case e1000_vfadapt_i350:
3712 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3713 rxr = &sc->rx_rings[i];
3716 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3721 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3725 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3727 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3730 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3731 txr = &sc->tx_rings[i];
3734 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3739 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3743 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3745 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3747 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3748 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3749 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3755 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3756 rxr = &sc->rx_rings[i];
3758 index = i & 0x7; /* Each IVAR has two entries */
3759 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3764 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3768 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3770 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3773 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3774 txr = &sc->tx_rings[i];
3776 index = i & 0x7; /* Each IVAR has two entries */
3777 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3782 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3786 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3788 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3790 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3791 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3792 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3798 * Enable necessary interrupt bits.
3800 * The name of the register is confusing; in addition to
3801 * configuring the first vector of MSI-X, it also configures
3802 * which bits of EICR could be set by the hardware even when
3803 * MSI or line interrupt is used; it thus controls interrupt
3804 * generation. It MUST be configured explicitly; the default
3805 * value mentioned in the datasheet is wrong: RX queue0 and
3806 * TX queue0 are NOT enabled by default.
3808 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3812 panic("unknown mac type %d\n", sc->hw.mac.type);
3817 igb_setup_intr(struct igb_softc *sc)
3821 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3822 return igb_msix_setup(sc);
3824 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3825 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3826 sc, &sc->intr_tag, &sc->main_serialize);
3828 device_printf(sc->dev, "Failed to register interrupt handler");
3831 sc->tx_rings[0].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
3837 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3839 if (txr->sc->hw.mac.type == e1000_82575) {
3840 txr->tx_intr_bit = 0; /* unused */
3843 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3846 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3849 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3852 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3855 panic("unsupported # of TX ring, %d\n", txr->me);
3858 int intr_bit = *intr_bit0;
3860 txr->tx_intr_bit = intr_bit % intr_bitmax;
3861 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3863 *intr_bit0 = intr_bit + 1;
3868 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3870 if (rxr->sc->hw.mac.type == e1000_82575) {
3871 rxr->rx_intr_bit = 0; /* unused */
3874 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3877 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3880 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3883 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3886 panic("unsupported # of RX ring, %d\n", rxr->me);
3889 int intr_bit = *intr_bit0;
3891 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3892 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3894 *intr_bit0 = intr_bit + 1;
3899 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3901 struct igb_softc *sc = ifp->if_softc;
3903 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3904 sc->tx_serialize, sc->rx_serialize, slz);
3908 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3910 struct igb_softc *sc = ifp->if_softc;
3912 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3913 sc->tx_serialize, sc->rx_serialize, slz);
3917 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3919 struct igb_softc *sc = ifp->if_softc;
3921 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3922 sc->tx_serialize, sc->rx_serialize, slz);
3928 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3929 boolean_t serialized)
3931 struct igb_softc *sc = ifp->if_softc;
3933 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3934 sc->tx_serialize, sc->rx_serialize, slz, serialized);
3937 #endif /* INVARIANTS */
3940 igb_set_intr_mask(struct igb_softc *sc)
3944 sc->intr_mask = sc->sts_intr_mask;
3945 for (i = 0; i < sc->rx_ring_inuse; ++i)
3946 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3947 for (i = 0; i < sc->tx_ring_inuse; ++i)
3948 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3950 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3956 igb_alloc_intr(struct igb_softc *sc)
3958 int i, intr_bit, intr_bitmax;
3961 igb_msix_try_alloc(sc);
3962 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3966 * Allocate MSI/legacy interrupt resource
3968 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3969 &sc->intr_rid, &intr_flags);
3971 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3974 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3976 sc->flags |= IGB_FLAG_SHARED_INTR;
3978 device_printf(sc->dev, "IRQ shared\n");
3980 intr_flags &= ~RF_SHAREABLE;
3982 device_printf(sc->dev, "IRQ unshared\n");
3986 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3987 &sc->intr_rid, intr_flags);
3988 if (sc->intr_res == NULL) {
3989 device_printf(sc->dev, "Unable to allocate bus resource: "
3995 * Setup MSI/legacy interrupt mask
3997 switch (sc->hw.mac.type) {
3999 intr_bitmax = IGB_MAX_TXRXINT_82575;
4002 intr_bitmax = IGB_MAX_TXRXINT_82580;
4005 intr_bitmax = IGB_MAX_TXRXINT_I350;
4008 intr_bitmax = IGB_MAX_TXRXINT_82576;
4011 intr_bitmax = IGB_MIN_TXRXINT;
4015 for (i = 0; i < sc->tx_ring_cnt; ++i)
4016 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4017 for (i = 0; i < sc->rx_ring_cnt; ++i)
4018 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4019 sc->sts_intr_bit = 0;
4020 sc->sts_intr_mask = E1000_EICR_OTHER;
4022 /* Initialize interrupt rate */
4023 sc->intr_rate = IGB_INTR_RATE;
4025 igb_set_ring_inuse(sc, FALSE);
4026 igb_set_intr_mask(sc);
4031 igb_free_intr(struct igb_softc *sc)
4033 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4034 if (sc->intr_res != NULL) {
4035 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4038 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4039 pci_release_msi(sc->dev);
4041 igb_msix_free(sc, TRUE);
4046 igb_teardown_intr(struct igb_softc *sc)
4048 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4049 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4051 igb_msix_teardown(sc, sc->msix_cnt);
4055 igb_msix_try_alloc(struct igb_softc *sc)
4057 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4059 struct igb_msix_data *msix;
4060 boolean_t aggregate, setup = FALSE;
4063 * Don't enable MSI-X on 82575, see:
4064 * 82575 specification update errata #25
4066 if (sc->hw.mac.type == e1000_82575)
4069 /* Don't enable MSI-X on VF */
4073 msix_enable = device_getenv_int(sc->dev, "msix.enable",
4078 msix_cnt = pci_msix_count(sc->dev);
4079 #ifdef IGB_MSIX_DEBUG
4080 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4082 if (msix_cnt <= 1) {
4083 /* One MSI-X model does not make sense */
4088 while ((1 << (i + 1)) <= msix_cnt)
4093 device_printf(sc->dev, "MSI-X count %d/%d\n",
4094 msix_cnt2, msix_cnt);
4097 KKASSERT(msix_cnt2 <= msix_cnt);
4098 if (msix_cnt == msix_cnt2) {
4099 /* We need at least one MSI-X for link status */
4101 if (msix_cnt2 <= 1) {
4102 /* One MSI-X for RX/TX does not make sense */
4103 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4104 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4107 KKASSERT(msix_cnt > msix_cnt2);
4110 device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4111 msix_cnt2, msix_cnt);
4115 sc->rx_ring_msix = sc->rx_ring_cnt;
4116 if (sc->rx_ring_msix > msix_cnt2)
4117 sc->rx_ring_msix = msix_cnt2;
4119 sc->tx_ring_msix = sc->tx_ring_cnt;
4120 if (sc->tx_ring_msix > msix_cnt2)
4121 sc->tx_ring_msix = msix_cnt2;
4123 if (msix_cnt >= sc->tx_ring_msix + sc->rx_ring_msix + 1) {
4125 * Independent TX/RX MSI-X
4129 device_printf(sc->dev, "independent TX/RX MSI-X\n");
4130 alloc_cnt = sc->tx_ring_msix + sc->rx_ring_msix;
4133 * Aggregate TX/RX MSI-X
4137 device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4138 alloc_cnt = msix_cnt2;
4139 if (alloc_cnt > ncpus2)
4141 if (sc->rx_ring_msix > alloc_cnt)
4142 sc->rx_ring_msix = alloc_cnt;
4144 ++alloc_cnt; /* For link status */
4147 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4148 alloc_cnt, sc->rx_ring_msix);
4151 sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4152 sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4153 &sc->msix_mem_rid, RF_ACTIVE);
4154 if (sc->msix_mem_res == NULL) {
4155 device_printf(sc->dev, "Unable to map MSI-X table\n");
4159 sc->msix_cnt = alloc_cnt;
4160 sc->msix_data = kmalloc_cachealign(
4161 sizeof(struct igb_msix_data) * sc->msix_cnt,
4162 M_DEVBUF, M_WAITOK | M_ZERO);
4163 for (x = 0; x < sc->msix_cnt; ++x) {
4164 msix = &sc->msix_data[x];
4166 lwkt_serialize_init(&msix->msix_serialize0);
4168 msix->msix_rid = -1;
4169 msix->msix_vector = x;
4170 msix->msix_mask = 1 << msix->msix_vector;
4171 msix->msix_rate = IGB_INTR_RATE;
4176 int offset, offset_def;
4178 if (sc->rx_ring_msix == ncpus2) {
4181 offset_def = (sc->rx_ring_msix *
4182 device_get_unit(sc->dev)) % ncpus2;
4184 offset = device_getenv_int(sc->dev,
4185 "msix.rxoff", offset_def);
4186 if (offset >= ncpus2 ||
4187 offset % sc->rx_ring_msix != 0) {
4188 device_printf(sc->dev,
4189 "invalid msix.rxoff %d, use %d\n",
4190 offset, offset_def);
4191 offset = offset_def;
4196 for (i = 0; i < sc->rx_ring_msix; ++i) {
4197 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4199 KKASSERT(x < sc->msix_cnt);
4200 msix = &sc->msix_data[x++];
4201 rxr->rx_intr_bit = msix->msix_vector;
4202 rxr->rx_intr_mask = msix->msix_mask;
4204 msix->msix_serialize = &rxr->rx_serialize;
4205 msix->msix_func = igb_msix_rx;
4206 msix->msix_arg = rxr;
4207 msix->msix_cpuid = i + offset;
4208 KKASSERT(msix->msix_cpuid < ncpus2);
4209 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4210 "%s rx%d", device_get_nameunit(sc->dev), i);
4211 msix->msix_rate = IGB_MSIX_RX_RATE;
4212 ksnprintf(msix->msix_rate_desc,
4213 sizeof(msix->msix_rate_desc),
4214 "RX%d interrupt rate", i);
4217 offset_def = device_get_unit(sc->dev) % ncpus2;
4218 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4219 if (offset >= ncpus2) {
4220 device_printf(sc->dev, "invalid msix.txoff %d, "
4221 "use %d\n", offset, offset_def);
4222 offset = offset_def;
4226 for (i = 0; i < sc->tx_ring_msix; ++i) {
4227 struct igb_tx_ring *txr = &sc->tx_rings[i];
4229 KKASSERT(x < sc->msix_cnt);
4230 msix = &sc->msix_data[x++];
4231 txr->tx_intr_bit = msix->msix_vector;
4232 txr->tx_intr_mask = msix->msix_mask;
4234 msix->msix_serialize = &txr->tx_serialize;
4235 msix->msix_func = igb_msix_tx;
4236 msix->msix_arg = txr;
4237 msix->msix_cpuid = i + offset;
4238 txr->tx_intr_cpuid = msix->msix_cpuid;
4239 KKASSERT(msix->msix_cpuid < ncpus2);
4240 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4241 "%s tx%d", device_get_nameunit(sc->dev), i);
4242 msix->msix_rate = IGB_MSIX_TX_RATE;
4243 ksnprintf(msix->msix_rate_desc,
4244 sizeof(msix->msix_rate_desc),
4245 "TX%d interrupt rate", i);
4256 KKASSERT(x < sc->msix_cnt);
4257 msix = &sc->msix_data[x++];
4258 sc->sts_intr_bit = msix->msix_vector;
4259 sc->sts_intr_mask = msix->msix_mask;
4261 msix->msix_serialize = &sc->main_serialize;
4262 msix->msix_func = igb_msix_status;
4263 msix->msix_arg = sc;
4264 msix->msix_cpuid = 0; /* TODO tunable */
4265 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4266 device_get_nameunit(sc->dev));
4267 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4268 "status interrupt rate");
4270 KKASSERT(x == sc->msix_cnt);
4272 error = pci_setup_msix(sc->dev);
4274 device_printf(sc->dev, "Setup MSI-X failed\n");
4279 for (i = 0; i < sc->msix_cnt; ++i) {
4280 msix = &sc->msix_data[i];
4282 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4283 &msix->msix_rid, msix->msix_cpuid);
4285 device_printf(sc->dev,
4286 "Unable to allocate MSI-X %d on cpu%d\n",
4287 msix->msix_vector, msix->msix_cpuid);
4291 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4292 &msix->msix_rid, RF_ACTIVE);
4293 if (msix->msix_res == NULL) {
4294 device_printf(sc->dev,
4295 "Unable to allocate MSI-X %d resource\n",
4302 pci_enable_msix(sc->dev);
4303 sc->intr_type = PCI_INTR_TYPE_MSIX;
4306 igb_msix_free(sc, setup);
4310 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4314 KKASSERT(sc->msix_cnt > 1);
4316 for (i = 0; i < sc->msix_cnt; ++i) {
4317 struct igb_msix_data *msix = &sc->msix_data[i];
4319 if (msix->msix_res != NULL) {
4320 bus_release_resource(sc->dev, SYS_RES_IRQ,
4321 msix->msix_rid, msix->msix_res);
4323 if (msix->msix_rid >= 0)
4324 pci_release_msix_vector(sc->dev, msix->msix_rid);
4327 pci_teardown_msix(sc->dev);
4330 kfree(sc->msix_data, M_DEVBUF);
4331 sc->msix_data = NULL;
4335 igb_msix_setup(struct igb_softc *sc)
4339 for (i = 0; i < sc->msix_cnt; ++i) {
4340 struct igb_msix_data *msix = &sc->msix_data[i];
4343 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4344 INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4345 &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4347 device_printf(sc->dev, "could not set up %s "
4348 "interrupt handler.\n", msix->msix_desc);
4349 igb_msix_teardown(sc, i);
4357 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4361 for (i = 0; i < msix_cnt; ++i) {
4362 struct igb_msix_data *msix = &sc->msix_data[i];
4364 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4369 igb_msix_rx(void *arg)
4371 struct igb_rx_ring *rxr = arg;
4373 ASSERT_SERIALIZED(&rxr->rx_serialize);
4376 E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4380 igb_msix_tx(void *arg)
4382 struct igb_tx_ring *txr = arg;
4384 ASSERT_SERIALIZED(&txr->tx_serialize);
4387 if (!ifsq_is_empty(txr->ifsq))
4388 ifsq_devstart(txr->ifsq);
4390 E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4394 igb_msix_status(void *arg)
4396 struct igb_softc *sc = arg;
4399 ASSERT_SERIALIZED(&sc->main_serialize);
4401 icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4402 if (icr & E1000_ICR_LSC) {
4403 sc->hw.mac.get_link_status = 1;
4404 igb_update_link_status(sc);
4407 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4411 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4413 sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4414 sc->tx_ring_inuse = igb_get_txring_inuse(sc, polling);
4416 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d, TX rings %d/%d\n",
4417 sc->rx_ring_inuse, sc->rx_ring_cnt,
4418 sc->tx_ring_inuse, sc->tx_ring_cnt);
4423 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4425 if (!IGB_ENABLE_HWRSS(sc))
4429 return sc->rx_ring_cnt;
4430 else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4431 return IGB_MIN_RING_RSS;
4433 return sc->rx_ring_msix;
4437 igb_get_txring_inuse(const struct igb_softc *sc, boolean_t polling)
4439 if (!IGB_ENABLE_HWTSS(sc))
4443 return sc->tx_ring_cnt;
4444 else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4445 return IGB_MIN_RING;
4447 return sc->tx_ring_msix;
4451 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4453 int hoff, iphlen, thoff;
4457 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4459 iphlen = m->m_pkthdr.csum_iphlen;
4460 thoff = m->m_pkthdr.csum_thlen;
4461 hoff = m->m_pkthdr.csum_lhlen;
4463 KASSERT(iphlen > 0, ("invalid ip hlen"));
4464 KASSERT(thoff > 0, ("invalid tcp hlen"));
4465 KASSERT(hoff > 0, ("invalid ether hlen"));
4467 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4468 m = m_pullup(m, hoff + iphlen + thoff);
4475 if (txr->sc->flags & IGB_FLAG_TSO_IPLEN0) {
4478 ip = mtodoff(m, struct ip *, hoff);
4486 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4488 struct e1000_adv_tx_context_desc *TXD;
4489 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4490 int hoff, ctxd, iphlen, thoff;
4492 iphlen = m->m_pkthdr.csum_iphlen;
4493 thoff = m->m_pkthdr.csum_thlen;
4494 hoff = m->m_pkthdr.csum_lhlen;
4496 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4498 ctxd = txr->next_avail_desc;
4499 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4501 if (m->m_flags & M_VLANTAG) {
4504 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4505 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4508 vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4509 vlan_macip_lens |= iphlen;
4511 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4512 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4513 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4515 mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4516 mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4517 /* 82575 needs the queue index added */
4518 if (txr->sc->hw.mac.type == e1000_82575)
4519 mss_l4len_idx |= txr->me << 4;
4521 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4522 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4523 TXD->seqnum_seed = htole32(0);
4524 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4526 /* We've consumed the first desc, adjust counters */
4527 if (++ctxd == txr->num_tx_desc)
4529 txr->next_avail_desc = ctxd;
4532 *hlen = hoff + iphlen + thoff;