2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * __FBSDID("$FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $");
30 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
47 #include <machine/smp.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 static uint32_t pci_mapbase(unsigned mapreg);
74 static const char *pci_maptype(unsigned mapreg);
75 static int pci_mapsize(unsigned testval);
76 static int pci_maprange(unsigned mapreg);
77 static void pci_fixancient(pcicfgregs *cfg);
79 static int pci_porten(device_t pcib, int b, int s, int f);
80 static int pci_memen(device_t pcib, int b, int s, int f);
81 static void pci_assign_interrupt(device_t bus, device_t dev,
83 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
84 int b, int s, int f, int reg,
85 struct resource_list *rl, int force, int prefetch);
86 static int pci_probe(device_t dev);
87 static int pci_attach(device_t dev);
88 static void pci_load_vendor_data(void);
89 static int pci_describe_parse_line(char **ptr, int *vendor,
90 int *device, char **desc);
91 static char *pci_describe_device(device_t dev);
92 static int pci_modevent(module_t mod, int what, void *arg);
93 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
95 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
96 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
97 int reg, uint32_t *data);
99 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
100 int reg, uint32_t data);
102 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
103 static void pci_disable_msi(device_t dev);
104 static void pci_enable_msi(device_t dev, uint64_t address,
106 static void pci_enable_msix(device_t dev, u_int index,
107 uint64_t address, uint32_t data);
108 static void pci_mask_msix(device_t dev, u_int index);
109 static void pci_unmask_msix(device_t dev, u_int index);
110 static int pci_msi_blacklisted(void);
111 static void pci_resume_msi(device_t dev);
112 static void pci_resume_msix(device_t dev);
114 static device_method_t pci_methods[] = {
115 /* Device interface */
116 DEVMETHOD(device_probe, pci_probe),
117 DEVMETHOD(device_attach, pci_attach),
118 DEVMETHOD(device_detach, bus_generic_detach),
119 DEVMETHOD(device_shutdown, bus_generic_shutdown),
120 DEVMETHOD(device_suspend, pci_suspend),
121 DEVMETHOD(device_resume, pci_resume),
124 DEVMETHOD(bus_print_child, pci_print_child),
125 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
126 DEVMETHOD(bus_read_ivar, pci_read_ivar),
127 DEVMETHOD(bus_write_ivar, pci_write_ivar),
128 DEVMETHOD(bus_driver_added, pci_driver_added),
129 DEVMETHOD(bus_setup_intr, pci_setup_intr),
130 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
132 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
133 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
134 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
135 DEVMETHOD(bus_delete_resource, pci_delete_resource),
136 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
137 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
138 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
139 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
140 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
141 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
144 DEVMETHOD(pci_read_config, pci_read_config_method),
145 DEVMETHOD(pci_write_config, pci_write_config_method),
146 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
147 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
148 DEVMETHOD(pci_enable_io, pci_enable_io_method),
149 DEVMETHOD(pci_disable_io, pci_disable_io_method),
150 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
151 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
152 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
153 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
154 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
155 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
156 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
157 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
158 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
159 DEVMETHOD(pci_release_msi, pci_release_msi_method),
160 DEVMETHOD(pci_msi_count, pci_msi_count_method),
161 DEVMETHOD(pci_msix_count, pci_msix_count_method),
166 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
168 static devclass_t pci_devclass;
169 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
170 MODULE_VERSION(pci, 1);
172 static char *pci_vendordata;
173 static size_t pci_vendordata_size;
177 uint32_t devid; /* Vendor/device of the card */
179 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
180 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
185 struct pci_quirk pci_quirks[] = {
186 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
187 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
188 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
189 /* As does the Serverworks OSB4 (the SMBus mapping register) */
190 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
193 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
194 * or the CMIC-SL (AKA ServerWorks GC_LE).
196 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
197 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
200 * MSI doesn't work on earlier Intel chipsets including
201 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
203 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
204 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
205 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
206 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
207 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
209 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
212 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
215 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
220 /* map register information */
221 #define PCI_MAPMEM 0x01 /* memory map */
222 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
223 #define PCI_MAPPORT 0x04 /* port map */
225 struct devlist pci_devq;
226 uint32_t pci_generation;
227 uint32_t pci_numdevs = 0;
228 static int pcie_chipset, pcix_chipset;
231 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
233 static int pci_enable_io_modes = 1;
234 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
235 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
236 &pci_enable_io_modes, 1,
237 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
238 enable these bits correctly. We'd like to do this all the time, but there\n\
239 are some peripherals that this causes problems with.");
241 static int pci_do_power_nodriver = 0;
242 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
243 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
244 &pci_do_power_nodriver, 0,
245 "Place a function into D3 state when no driver attaches to it. 0 means\n\
246 disable. 1 means conservatively place devices into D3 state. 2 means\n\
247 agressively place devices into D3 state. 3 means put absolutely everything\n\
250 static int pci_do_power_resume = 1;
251 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
252 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
253 &pci_do_power_resume, 1,
254 "Transition from D3 -> D0 on resume.");
256 static int pci_do_msi = 1;
257 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
258 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
259 "Enable support for MSI interrupts");
261 static int pci_do_msix = 1;
262 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
263 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
264 "Enable support for MSI-X interrupts");
266 static int pci_honor_msi_blacklist = 1;
267 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
268 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
269 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
271 /* Find a device_t by bus/slot/function in domain 0 */
274 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
277 return (pci_find_dbsf(0, bus, slot, func));
280 /* Find a device_t by domain/bus/slot/function */
283 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
285 struct pci_devinfo *dinfo;
287 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
288 if ((dinfo->cfg.domain == domain) &&
289 (dinfo->cfg.bus == bus) &&
290 (dinfo->cfg.slot == slot) &&
291 (dinfo->cfg.func == func)) {
292 return (dinfo->cfg.dev);
299 /* Find a device_t by vendor/device ID */
302 pci_find_device(uint16_t vendor, uint16_t device)
304 struct pci_devinfo *dinfo;
306 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
307 if ((dinfo->cfg.vendor == vendor) &&
308 (dinfo->cfg.device == device)) {
309 return (dinfo->cfg.dev);
316 /* return base address of memory or port map */
319 pci_mapbase(uint32_t mapreg)
322 if (PCI_BAR_MEM(mapreg))
323 return (mapreg & PCIM_BAR_MEM_BASE);
325 return (mapreg & PCIM_BAR_IO_BASE);
328 /* return map type of memory or port map */
331 pci_maptype(unsigned mapreg)
334 if (PCI_BAR_IO(mapreg))
336 if (mapreg & PCIM_BAR_MEM_PREFETCH)
337 return ("Prefetchable Memory");
341 /* return log2 of map size decoded for memory or port map */
344 pci_mapsize(uint32_t testval)
348 testval = pci_mapbase(testval);
351 while ((testval & 1) == 0)
360 /* return log2 of address range supported by map register */
363 pci_maprange(unsigned mapreg)
367 if (PCI_BAR_IO(mapreg))
370 switch (mapreg & PCIM_BAR_MEM_TYPE) {
371 case PCIM_BAR_MEM_32:
374 case PCIM_BAR_MEM_1MB:
377 case PCIM_BAR_MEM_64:
384 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
387 pci_fixancient(pcicfgregs *cfg)
389 if (cfg->hdrtype != 0)
392 /* PCI to PCI bridges use header type 1 */
393 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
397 /* extract header type specific config data */
400 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
402 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
403 switch (cfg->hdrtype) {
405 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
406 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
407 cfg->nummaps = PCI_MAXMAPS_0;
410 cfg->nummaps = PCI_MAXMAPS_1;
413 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
414 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
415 cfg->nummaps = PCI_MAXMAPS_2;
421 /* read configuration header into pcicfgregs structure */
423 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
425 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
426 pcicfgregs *cfg = NULL;
427 struct pci_devinfo *devlist_entry;
428 struct devlist *devlist_head;
430 devlist_head = &pci_devq;
432 devlist_entry = NULL;
434 if (REG(PCIR_DEVVENDOR, 4) != -1) {
435 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
436 if (devlist_entry == NULL)
439 cfg = &devlist_entry->cfg;
445 cfg->vendor = REG(PCIR_VENDOR, 2);
446 cfg->device = REG(PCIR_DEVICE, 2);
447 cfg->cmdreg = REG(PCIR_COMMAND, 2);
448 cfg->statreg = REG(PCIR_STATUS, 2);
449 cfg->baseclass = REG(PCIR_CLASS, 1);
450 cfg->subclass = REG(PCIR_SUBCLASS, 1);
451 cfg->progif = REG(PCIR_PROGIF, 1);
452 cfg->revid = REG(PCIR_REVID, 1);
453 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
454 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
455 cfg->lattimer = REG(PCIR_LATTIMER, 1);
456 cfg->intpin = REG(PCIR_INTPIN, 1);
457 cfg->intline = REG(PCIR_INTLINE, 1);
461 * If using the APIC the intpin is probably wrong, since it
462 * is often setup by the BIOS with the PIC in mind.
464 if (cfg->intpin != 0) {
467 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
469 /* PCI specific entry found in MP table */
470 if (airq != cfg->intline) {
471 undirect_pci_irq(cfg->intline);
476 * PCI interrupts might be redirected to the
477 * ISA bus according to some MP tables. Use the
478 * same methods as used by the ISA devices
479 * devices to find the proper IOAPIC int pin.
481 airq = isa_apic_irq(cfg->intline);
482 if ((airq >= 0) && (airq != cfg->intline)) {
483 /* XXX: undirect_pci_irq() ? */
484 undirect_isa_irq(cfg->intline);
491 cfg->mingnt = REG(PCIR_MINGNT, 1);
492 cfg->maxlat = REG(PCIR_MAXLAT, 1);
494 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
495 cfg->hdrtype &= ~PCIM_MFDEV;
498 pci_hdrtypedata(pcib, b, s, f, cfg);
500 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
501 pci_read_extcap(pcib, cfg);
503 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
505 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
506 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
507 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
508 devlist_entry->conf.pc_sel.pc_func = cfg->func;
509 devlist_entry->conf.pc_hdr = cfg->hdrtype;
511 devlist_entry->conf.pc_subvendor = cfg->subvendor;
512 devlist_entry->conf.pc_subdevice = cfg->subdevice;
513 devlist_entry->conf.pc_vendor = cfg->vendor;
514 devlist_entry->conf.pc_device = cfg->device;
516 devlist_entry->conf.pc_class = cfg->baseclass;
517 devlist_entry->conf.pc_subclass = cfg->subclass;
518 devlist_entry->conf.pc_progif = cfg->progif;
519 devlist_entry->conf.pc_revid = cfg->revid;
524 return (devlist_entry);
529 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
531 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
532 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
533 #if defined(__i386__) || defined(__amd64__)
537 int ptr, nextptr, ptrptr;
539 switch (cfg->hdrtype & PCIM_HDRTYPE) {
542 ptrptr = PCIR_CAP_PTR;
545 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
548 return; /* no extended capabilities support */
550 nextptr = REG(ptrptr, 1); /* sanity check? */
553 * Read capability entries.
555 while (nextptr != 0) {
558 kprintf("illegal PCI extended capability offset %d\n",
562 /* Find the next entry */
564 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
566 /* Process this entry */
567 switch (REG(ptr + PCICAP_ID, 1)) {
568 case PCIY_PMG: /* PCI power management */
569 if (cfg->pp.pp_cap == 0) {
570 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
571 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
572 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
573 if ((nextptr - ptr) > PCIR_POWER_DATA)
574 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
578 #if defined(__i386__) || defined(__amd64__)
579 case PCIY_HT: /* HyperTransport */
580 /* Determine HT-specific capability type. */
581 val = REG(ptr + PCIR_HT_COMMAND, 2);
582 switch (val & PCIM_HTCMD_CAP_MASK) {
583 case PCIM_HTCAP_MSI_MAPPING:
584 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
585 /* Sanity check the mapping window. */
586 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
589 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
591 if (addr != MSI_INTEL_ADDR_BASE)
593 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
594 cfg->domain, cfg->bus,
595 cfg->slot, cfg->func,
598 addr = MSI_INTEL_ADDR_BASE;
600 cfg->ht.ht_msimap = ptr;
601 cfg->ht.ht_msictrl = val;
602 cfg->ht.ht_msiaddr = addr;
607 case PCIY_MSI: /* PCI MSI */
608 cfg->msi.msi_location = ptr;
609 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
610 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
611 PCIM_MSICTRL_MMC_MASK)>>1);
613 case PCIY_MSIX: /* PCI MSI-X */
614 cfg->msix.msix_location = ptr;
615 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
616 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
617 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
618 val = REG(ptr + PCIR_MSIX_TABLE, 4);
619 cfg->msix.msix_table_bar = PCIR_BAR(val &
621 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
622 val = REG(ptr + PCIR_MSIX_PBA, 4);
623 cfg->msix.msix_pba_bar = PCIR_BAR(val &
625 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
628 case PCIY_VPD: /* PCI Vital Product Data */
629 cfg->vpd.vpd_reg = ptr;
632 /* Should always be true. */
633 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
634 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
635 cfg->subvendor = val & 0xffff;
636 cfg->subdevice = val >> 16;
639 case PCIY_PCIX: /* PCI-X */
641 * Assume we have a PCI-X chipset if we have
642 * at least one PCI-PCI bridge with a PCI-X
643 * capability. Note that some systems with
644 * PCI-express or HT chipsets might match on
645 * this check as well.
647 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
650 case PCIY_EXPRESS: /* PCI-express */
652 * Assume we have a PCI-express chipset if we have
653 * at least one PCI-express device.
661 /* REG and WREG use carry through to next functions */
665 * PCI Vital Product Data
668 #define PCI_VPD_TIMEOUT 1000000
671 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
673 int count = PCI_VPD_TIMEOUT;
675 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
677 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
679 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
682 DELAY(1); /* limit looping */
684 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
691 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
693 int count = PCI_VPD_TIMEOUT;
695 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
697 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
698 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
699 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
702 DELAY(1); /* limit looping */
709 #undef PCI_VPD_TIMEOUT
711 struct vpd_readstate {
721 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
726 if (vrs->bytesinval == 0) {
727 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
729 vrs->val = le32toh(reg);
731 byte = vrs->val & 0xff;
734 vrs->val = vrs->val >> 8;
735 byte = vrs->val & 0xff;
745 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
749 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
750 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
751 panic("%s: invalid max read request size 0x%02x\n",
752 device_get_nameunit(dev), rqsize);
754 #warning "this code is incorrect, I think"
755 pci_find_extcap_method(device_get_parent(dev), dev, PCIY_EXPRESS, &expr_ptr);
757 panic("%s: not PCI Express\n", device_get_nameunit(dev));
758 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
759 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
761 device_printf(dev, "adjust device control 0x%04x", val);
762 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
764 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
767 kprintf(" -> 0x%04x\n", val);
772 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
774 struct vpd_readstate vrs;
779 int alloc, off; /* alloc/off for RO/W arrays */
785 /* init vpd reader */
793 name = remain = i = 0; /* shut up stupid gcc */
794 alloc = off = 0; /* shut up stupid gcc */
795 dflen = 0; /* shut up stupid gcc */
798 if (vpd_nextbyte(&vrs, &byte)) {
803 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
804 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
805 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
808 case 0: /* item name */
810 if (vpd_nextbyte(&vrs, &byte2)) {
815 if (vpd_nextbyte(&vrs, &byte2)) {
819 remain |= byte2 << 8;
820 if (remain > (0x7f*4 - vrs.off)) {
823 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
824 cfg->domain, cfg->bus, cfg->slot,
830 name = (byte >> 3) & 0xf;
833 case 0x2: /* String */
834 cfg->vpd.vpd_ident = kmalloc(remain + 1,
842 case 0x10: /* VPD-R */
845 cfg->vpd.vpd_ros = kmalloc(alloc *
846 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
850 case 0x11: /* VPD-W */
853 cfg->vpd.vpd_w = kmalloc(alloc *
854 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
858 default: /* Invalid data, abort */
864 case 1: /* Identifier String */
865 cfg->vpd.vpd_ident[i++] = byte;
868 cfg->vpd.vpd_ident[i] = '\0';
873 case 2: /* VPD-R Keyword Header */
875 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
876 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
877 M_DEVBUF, M_WAITOK | M_ZERO);
879 cfg->vpd.vpd_ros[off].keyword[0] = byte;
880 if (vpd_nextbyte(&vrs, &byte2)) {
884 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
885 if (vpd_nextbyte(&vrs, &byte2)) {
891 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
894 * if this happens, we can't trust the rest
898 "pci%d:%d:%d:%d: bad keyword length: %d\n",
899 cfg->domain, cfg->bus, cfg->slot,
904 } else if (dflen == 0) {
905 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
906 sizeof(*cfg->vpd.vpd_ros[off].value),
908 cfg->vpd.vpd_ros[off].value[0] = '\x00';
910 cfg->vpd.vpd_ros[off].value = kmalloc(
912 sizeof(*cfg->vpd.vpd_ros[off].value),
916 /* keep in sync w/ state 3's transistions */
917 if (dflen == 0 && remain == 0)
925 case 3: /* VPD-R Keyword Value */
926 cfg->vpd.vpd_ros[off].value[i++] = byte;
927 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
928 "RV", 2) == 0 && cksumvalid == -1) {
934 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
935 cfg->domain, cfg->bus,
936 cfg->slot, cfg->func,
945 /* keep in sync w/ state 2's transistions */
947 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
948 if (dflen == 0 && remain == 0) {
949 cfg->vpd.vpd_rocnt = off;
950 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
951 off * sizeof(*cfg->vpd.vpd_ros),
952 M_DEVBUF, M_WAITOK | M_ZERO);
954 } else if (dflen == 0)
964 case 5: /* VPD-W Keyword Header */
966 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
967 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
968 M_DEVBUF, M_WAITOK | M_ZERO);
970 cfg->vpd.vpd_w[off].keyword[0] = byte;
971 if (vpd_nextbyte(&vrs, &byte2)) {
975 cfg->vpd.vpd_w[off].keyword[1] = byte2;
976 if (vpd_nextbyte(&vrs, &byte2)) {
980 cfg->vpd.vpd_w[off].len = dflen = byte2;
981 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
982 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
983 sizeof(*cfg->vpd.vpd_w[off].value),
987 /* keep in sync w/ state 6's transistions */
988 if (dflen == 0 && remain == 0)
996 case 6: /* VPD-W Keyword Value */
997 cfg->vpd.vpd_w[off].value[i++] = byte;
1000 /* keep in sync w/ state 5's transistions */
1002 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1003 if (dflen == 0 && remain == 0) {
1004 cfg->vpd.vpd_wcnt = off;
1005 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1006 off * sizeof(*cfg->vpd.vpd_w),
1007 M_DEVBUF, M_WAITOK | M_ZERO);
1009 } else if (dflen == 0)
1014 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1015 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1022 if (cksumvalid == 0 || state < -1) {
1023 /* read-only data bad, clean up */
1024 if (cfg->vpd.vpd_ros != NULL) {
1025 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1026 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1027 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1028 cfg->vpd.vpd_ros = NULL;
1032 /* I/O error, clean up */
1033 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1034 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1035 if (cfg->vpd.vpd_ident != NULL) {
1036 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1037 cfg->vpd.vpd_ident = NULL;
1039 if (cfg->vpd.vpd_w != NULL) {
1040 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1041 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1042 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1043 cfg->vpd.vpd_w = NULL;
1046 cfg->vpd.vpd_cached = 1;
1052 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1054 struct pci_devinfo *dinfo = device_get_ivars(child);
1055 pcicfgregs *cfg = &dinfo->cfg;
1057 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1058 pci_read_vpd(device_get_parent(dev), cfg);
1060 *identptr = cfg->vpd.vpd_ident;
1062 if (*identptr == NULL)
1069 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1072 struct pci_devinfo *dinfo = device_get_ivars(child);
1073 pcicfgregs *cfg = &dinfo->cfg;
1076 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1077 pci_read_vpd(device_get_parent(dev), cfg);
1079 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1080 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1081 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1082 *vptr = cfg->vpd.vpd_ros[i].value;
1085 if (i != cfg->vpd.vpd_rocnt)
1093 * Return the offset in configuration space of the requested extended
1094 * capability entry or 0 if the specified capability was not found.
1097 pci_find_extcap_method(device_t dev, device_t child, int capability,
1100 struct pci_devinfo *dinfo = device_get_ivars(child);
1101 pcicfgregs *cfg = &dinfo->cfg;
1106 * Check the CAP_LIST bit of the PCI status register first.
1108 status = pci_read_config(child, PCIR_STATUS, 2);
1109 if (!(status & PCIM_STATUS_CAPPRESENT))
1113 * Determine the start pointer of the capabilities list.
1115 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1121 ptr = PCIR_CAP_PTR_2;
1125 return (ENXIO); /* no extended capabilities support */
1127 ptr = pci_read_config(child, ptr, 1);
1130 * Traverse the capabilities list.
1133 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1138 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1145 * Support for MSI-X message interrupts.
1148 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1150 struct pci_devinfo *dinfo = device_get_ivars(dev);
1151 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1154 KASSERT(msix->msix_table_len > index, ("bogus index"));
1155 offset = msix->msix_table_offset + index * 16;
1156 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1157 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1158 bus_write_4(msix->msix_table_res, offset + 8, data);
1160 /* Enable MSI -> HT mapping. */
1161 pci_ht_map_msi(dev, address);
1165 pci_mask_msix(device_t dev, u_int index)
1167 struct pci_devinfo *dinfo = device_get_ivars(dev);
1168 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1169 uint32_t offset, val;
1171 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1172 offset = msix->msix_table_offset + index * 16 + 12;
1173 val = bus_read_4(msix->msix_table_res, offset);
1174 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1175 val |= PCIM_MSIX_VCTRL_MASK;
1176 bus_write_4(msix->msix_table_res, offset, val);
1181 pci_unmask_msix(device_t dev, u_int index)
1183 struct pci_devinfo *dinfo = device_get_ivars(dev);
1184 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1185 uint32_t offset, val;
1187 KASSERT(msix->msix_table_len > index, ("bogus index"));
1188 offset = msix->msix_table_offset + index * 16 + 12;
1189 val = bus_read_4(msix->msix_table_res, offset);
1190 if (val & PCIM_MSIX_VCTRL_MASK) {
1191 val &= ~PCIM_MSIX_VCTRL_MASK;
1192 bus_write_4(msix->msix_table_res, offset, val);
1197 pci_pending_msix(device_t dev, u_int index)
1199 struct pci_devinfo *dinfo = device_get_ivars(dev);
1200 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1201 uint32_t offset, bit;
1203 KASSERT(msix->msix_table_len > index, ("bogus index"));
1204 offset = msix->msix_pba_offset + (index / 32) * 4;
1205 bit = 1 << index % 32;
1206 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1210 * Restore MSI-X registers and table during resume. If MSI-X is
1211 * enabled then walk the virtual table to restore the actual MSI-X
1215 pci_resume_msix(device_t dev)
1217 struct pci_devinfo *dinfo = device_get_ivars(dev);
1218 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1219 struct msix_table_entry *mte;
1220 struct msix_vector *mv;
1223 if (msix->msix_alloc > 0) {
1224 /* First, mask all vectors. */
1225 for (i = 0; i < msix->msix_msgnum; i++)
1226 pci_mask_msix(dev, i);
1228 /* Second, program any messages with at least one handler. */
1229 for (i = 0; i < msix->msix_table_len; i++) {
1230 mte = &msix->msix_table[i];
1231 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1233 mv = &msix->msix_vectors[mte->mte_vector - 1];
1234 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1235 pci_unmask_msix(dev, i);
1238 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1239 msix->msix_ctrl, 2);
1243 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1244 * returned in *count. After this function returns, each message will be
1245 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1248 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1250 struct pci_devinfo *dinfo = device_get_ivars(child);
1251 pcicfgregs *cfg = &dinfo->cfg;
1252 struct resource_list_entry *rle;
1253 int actual, error, i, irq, max;
1255 /* Don't let count == 0 get us into trouble. */
1259 /* If rid 0 is allocated, then fail. */
1260 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1261 if (rle != NULL && rle->res != NULL)
1264 /* Already have allocated messages? */
1265 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1268 /* If MSI is blacklisted for this system, fail. */
1269 if (pci_msi_blacklisted())
1272 /* MSI-X capability present? */
1273 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1276 /* Make sure the appropriate BARs are mapped. */
1277 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1278 cfg->msix.msix_table_bar);
1279 if (rle == NULL || rle->res == NULL ||
1280 !(rman_get_flags(rle->res) & RF_ACTIVE))
1282 cfg->msix.msix_table_res = rle->res;
1283 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1284 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1285 cfg->msix.msix_pba_bar);
1286 if (rle == NULL || rle->res == NULL ||
1287 !(rman_get_flags(rle->res) & RF_ACTIVE))
1290 cfg->msix.msix_pba_res = rle->res;
1293 device_printf(child,
1294 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1295 *count, cfg->msix.msix_msgnum);
1296 max = min(*count, cfg->msix.msix_msgnum);
1297 for (i = 0; i < max; i++) {
1298 /* Allocate a message. */
1299 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1302 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1308 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1310 device_printf(child, "using IRQ %lu for MSI-X\n",
1316 * Be fancy and try to print contiguous runs of
1317 * IRQ values as ranges. 'irq' is the previous IRQ.
1318 * 'run' is true if we are in a range.
1320 device_printf(child, "using IRQs %lu", rle->start);
1323 for (i = 1; i < actual; i++) {
1324 rle = resource_list_find(&dinfo->resources,
1325 SYS_RES_IRQ, i + 1);
1327 /* Still in a run? */
1328 if (rle->start == irq + 1) {
1334 /* Finish previous range. */
1336 kprintf("-%d", irq);
1340 /* Start new range. */
1341 kprintf(",%lu", rle->start);
1345 /* Unfinished range? */
1347 kprintf("-%d", irq);
1348 kprintf(" for MSI-X\n");
1352 /* Mask all vectors. */
1353 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1354 pci_mask_msix(child, i);
1356 /* Allocate and initialize vector data and virtual table. */
1357 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1358 M_DEVBUF, M_WAITOK | M_ZERO);
1359 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1360 M_DEVBUF, M_WAITOK | M_ZERO);
1361 for (i = 0; i < actual; i++) {
1362 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1363 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1364 cfg->msix.msix_table[i].mte_vector = i + 1;
1367 /* Update control register to enable MSI-X. */
1368 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1369 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1370 cfg->msix.msix_ctrl, 2);
1372 /* Update counts of alloc'd messages. */
1373 cfg->msix.msix_alloc = actual;
1374 cfg->msix.msix_table_len = actual;
1380 * By default, pci_alloc_msix() will assign the allocated IRQ
1381 * resources consecutively to the first N messages in the MSI-X table.
1382 * However, device drivers may want to use different layouts if they
1383 * either receive fewer messages than they asked for, or they wish to
1384 * populate the MSI-X table sparsely. This method allows the driver
1385 * to specify what layout it wants. It must be called after a
1386 * successful pci_alloc_msix() but before any of the associated
1387 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1389 * The 'vectors' array contains 'count' message vectors. The array
1390 * maps directly to the MSI-X table in that index 0 in the array
1391 * specifies the vector for the first message in the MSI-X table, etc.
1392 * The vector value in each array index can either be 0 to indicate
1393 * that no vector should be assigned to a message slot, or it can be a
1394 * number from 1 to N (where N is the count returned from a
1395 * succcessful call to pci_alloc_msix()) to indicate which message
1396 * vector (IRQ) to be used for the corresponding message.
1398 * On successful return, each message with a non-zero vector will have
1399 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1400 * 1. Additionally, if any of the IRQs allocated via the previous
1401 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1402 * will be kfreed back to the system automatically.
1404 * For example, suppose a driver has a MSI-X table with 6 messages and
1405 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1406 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1407 * C. After the call to pci_alloc_msix(), the device will be setup to
1408 * have an MSI-X table of ABC--- (where - means no vector assigned).
1409 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1410 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1411 * be kfreed back to the system. This device will also have valid
1412 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1414 * In any case, the SYS_RES_IRQ rid X will always map to the message
1415 * at MSI-X table index X - 1 and will only be valid if a vector is
1416 * assigned to that table entry.
1419 pci_remap_msix_method(device_t dev, device_t child, int count,
1420 const u_int *vectors)
1422 struct pci_devinfo *dinfo = device_get_ivars(child);
1423 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1424 struct resource_list_entry *rle;
1425 int i, irq, j, *used;
1428 * Have to have at least one message in the table but the
1429 * table can't be bigger than the actual MSI-X table in the
1432 if (count == 0 || count > msix->msix_msgnum)
1435 /* Sanity check the vectors. */
1436 for (i = 0; i < count; i++)
1437 if (vectors[i] > msix->msix_alloc)
1441 * Make sure there aren't any holes in the vectors to be used.
1442 * It's a big pain to support it, and it doesn't really make
1443 * sense anyway. Also, at least one vector must be used.
1445 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1447 for (i = 0; i < count; i++)
1448 if (vectors[i] != 0)
1449 used[vectors[i] - 1] = 1;
1450 for (i = 0; i < msix->msix_alloc - 1; i++)
1451 if (used[i] == 0 && used[i + 1] == 1) {
1452 kfree(used, M_DEVBUF);
1456 kfree(used, M_DEVBUF);
1460 /* Make sure none of the resources are allocated. */
1461 for (i = 0; i < msix->msix_table_len; i++) {
1462 if (msix->msix_table[i].mte_vector == 0)
1464 if (msix->msix_table[i].mte_handlers > 0)
1466 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1467 KASSERT(rle != NULL, ("missing resource"));
1468 if (rle->res != NULL)
1472 /* Free the existing resource list entries. */
1473 for (i = 0; i < msix->msix_table_len; i++) {
1474 if (msix->msix_table[i].mte_vector == 0)
1476 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1480 * Build the new virtual table keeping track of which vectors are
1483 kfree(msix->msix_table, M_DEVBUF);
1484 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1485 M_DEVBUF, M_WAITOK | M_ZERO);
1486 for (i = 0; i < count; i++)
1487 msix->msix_table[i].mte_vector = vectors[i];
1488 msix->msix_table_len = count;
1490 /* Free any unused IRQs and resize the vectors array if necessary. */
1491 j = msix->msix_alloc - 1;
1493 struct msix_vector *vec;
1495 while (used[j] == 0) {
1496 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1497 msix->msix_vectors[j].mv_irq);
1500 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1502 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1504 kfree(msix->msix_vectors, M_DEVBUF);
1505 msix->msix_vectors = vec;
1506 msix->msix_alloc = j + 1;
1508 kfree(used, M_DEVBUF);
1510 /* Map the IRQs onto the rids. */
1511 for (i = 0; i < count; i++) {
1512 if (vectors[i] == 0)
1514 irq = msix->msix_vectors[vectors[i]].mv_irq;
1515 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1520 device_printf(child, "Remapped MSI-X IRQs as: ");
1521 for (i = 0; i < count; i++) {
1524 if (vectors[i] == 0)
1528 msix->msix_vectors[vectors[i]].mv_irq);
1537 pci_release_msix(device_t dev, device_t child)
1539 struct pci_devinfo *dinfo = device_get_ivars(child);
1540 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1541 struct resource_list_entry *rle;
1544 /* Do we have any messages to release? */
1545 if (msix->msix_alloc == 0)
1548 /* Make sure none of the resources are allocated. */
1549 for (i = 0; i < msix->msix_table_len; i++) {
1550 if (msix->msix_table[i].mte_vector == 0)
1552 if (msix->msix_table[i].mte_handlers > 0)
1554 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1555 KASSERT(rle != NULL, ("missing resource"));
1556 if (rle->res != NULL)
1560 /* Update control register to disable MSI-X. */
1561 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1562 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1563 msix->msix_ctrl, 2);
1565 /* Free the resource list entries. */
1566 for (i = 0; i < msix->msix_table_len; i++) {
1567 if (msix->msix_table[i].mte_vector == 0)
1569 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1571 kfree(msix->msix_table, M_DEVBUF);
1572 msix->msix_table_len = 0;
1574 /* Release the IRQs. */
1575 for (i = 0; i < msix->msix_alloc; i++)
1576 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1577 msix->msix_vectors[i].mv_irq);
1578 kfree(msix->msix_vectors, M_DEVBUF);
1579 msix->msix_alloc = 0;
1584 * Return the max supported MSI-X messages this device supports.
1585 * Basically, assuming the MD code can alloc messages, this function
1586 * should return the maximum value that pci_alloc_msix() can return.
1587 * Thus, it is subject to the tunables, etc.
1590 pci_msix_count_method(device_t dev, device_t child)
1592 struct pci_devinfo *dinfo = device_get_ivars(child);
1593 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1595 if (pci_do_msix && msix->msix_location != 0)
1596 return (msix->msix_msgnum);
1601 * HyperTransport MSI mapping control
1604 pci_ht_map_msi(device_t dev, uint64_t addr)
1606 struct pci_devinfo *dinfo = device_get_ivars(dev);
1607 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1612 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1613 ht->ht_msiaddr >> 20 == addr >> 20) {
1614 /* Enable MSI -> HT mapping. */
1615 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1616 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1620 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1621 /* Disable MSI -> HT mapping. */
1622 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1623 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1629 * Support for MSI message signalled interrupts.
1632 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1634 struct pci_devinfo *dinfo = device_get_ivars(dev);
1635 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1637 /* Write data and address values. */
1638 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1639 address & 0xffffffff, 4);
1640 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1641 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1643 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1646 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1649 /* Enable MSI in the control register. */
1650 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1651 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1654 /* Enable MSI -> HT mapping. */
1655 pci_ht_map_msi(dev, address);
1659 pci_disable_msi(device_t dev)
1661 struct pci_devinfo *dinfo = device_get_ivars(dev);
1662 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1664 /* Disable MSI -> HT mapping. */
1665 pci_ht_map_msi(dev, 0);
1667 /* Disable MSI in the control register. */
1668 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1669 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1674 * Restore MSI registers during resume. If MSI is enabled then
1675 * restore the data and address registers in addition to the control
1679 pci_resume_msi(device_t dev)
1681 struct pci_devinfo *dinfo = device_get_ivars(dev);
1682 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1686 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1687 address = msi->msi_addr;
1688 data = msi->msi_data;
1689 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1690 address & 0xffffffff, 4);
1691 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1692 pci_write_config(dev, msi->msi_location +
1693 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1694 pci_write_config(dev, msi->msi_location +
1695 PCIR_MSI_DATA_64BIT, data, 2);
1697 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1700 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1705 pci_remap_msi_irq(device_t dev, u_int irq)
1707 struct pci_devinfo *dinfo = device_get_ivars(dev);
1708 pcicfgregs *cfg = &dinfo->cfg;
1709 struct resource_list_entry *rle;
1710 struct msix_table_entry *mte;
1711 struct msix_vector *mv;
1717 bus = device_get_parent(dev);
1720 * Handle MSI first. We try to find this IRQ among our list
1721 * of MSI IRQs. If we find it, we request updated address and
1722 * data registers and apply the results.
1724 if (cfg->msi.msi_alloc > 0) {
1726 /* If we don't have any active handlers, nothing to do. */
1727 if (cfg->msi.msi_handlers == 0)
1729 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1730 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1732 if (rle->start == irq) {
1733 error = PCIB_MAP_MSI(device_get_parent(bus),
1734 dev, irq, &addr, &data);
1737 pci_disable_msi(dev);
1738 dinfo->cfg.msi.msi_addr = addr;
1739 dinfo->cfg.msi.msi_data = data;
1740 pci_enable_msi(dev, addr, data);
1748 * For MSI-X, we check to see if we have this IRQ. If we do,
1749 * we request the updated mapping info. If that works, we go
1750 * through all the slots that use this IRQ and update them.
1752 if (cfg->msix.msix_alloc > 0) {
1753 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1754 mv = &cfg->msix.msix_vectors[i];
1755 if (mv->mv_irq == irq) {
1756 error = PCIB_MAP_MSI(device_get_parent(bus),
1757 dev, irq, &addr, &data);
1760 mv->mv_address = addr;
1762 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1763 mte = &cfg->msix.msix_table[j];
1764 if (mte->mte_vector != i + 1)
1766 if (mte->mte_handlers == 0)
1768 pci_mask_msix(dev, j);
1769 pci_enable_msix(dev, j, addr, data);
1770 pci_unmask_msix(dev, j);
1781 * Returns true if the specified device is blacklisted because MSI
1785 pci_msi_device_blacklisted(device_t dev)
1787 struct pci_quirk *q;
1789 if (!pci_honor_msi_blacklist)
1792 for (q = &pci_quirks[0]; q->devid; q++) {
1793 if (q->devid == pci_get_devid(dev) &&
1794 q->type == PCI_QUIRK_DISABLE_MSI)
1801 * Determine if MSI is blacklisted globally on this sytem. Currently,
1802 * we just check for blacklisted chipsets as represented by the
1803 * host-PCI bridge at device 0:0:0. In the future, it may become
1804 * necessary to check other system attributes, such as the kenv values
1805 * that give the motherboard manufacturer and model number.
1808 pci_msi_blacklisted(void)
1812 if (!pci_honor_msi_blacklist)
1815 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1816 if (!(pcie_chipset || pcix_chipset))
1819 dev = pci_find_bsf(0, 0, 0);
1821 return (pci_msi_device_blacklisted(dev));
1826 * Attempt to allocate *count MSI messages. The actual number allocated is
1827 * returned in *count. After this function returns, each message will be
1828 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1831 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1833 struct pci_devinfo *dinfo = device_get_ivars(child);
1834 pcicfgregs *cfg = &dinfo->cfg;
1835 struct resource_list_entry *rle;
1836 int actual, error, i, irqs[32];
1839 /* Don't let count == 0 get us into trouble. */
1843 /* If rid 0 is allocated, then fail. */
1844 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1845 if (rle != NULL && rle->res != NULL)
1848 /* Already have allocated messages? */
1849 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1852 /* If MSI is blacklisted for this system, fail. */
1853 if (pci_msi_blacklisted())
1856 /* MSI capability present? */
1857 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1861 device_printf(child,
1862 "attempting to allocate %d MSI vectors (%d supported)\n",
1863 *count, cfg->msi.msi_msgnum);
1865 /* Don't ask for more than the device supports. */
1866 actual = min(*count, cfg->msi.msi_msgnum);
1868 /* Don't ask for more than 32 messages. */
1869 actual = min(actual, 32);
1871 /* MSI requires power of 2 number of messages. */
1872 if (!powerof2(actual))
1876 /* Try to allocate N messages. */
1877 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1878 cfg->msi.msi_msgnum, irqs);
1889 * We now have N actual messages mapped onto SYS_RES_IRQ
1890 * resources in the irqs[] array, so add new resources
1891 * starting at rid 1.
1893 for (i = 0; i < actual; i++)
1894 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1895 irqs[i], irqs[i], 1);
1899 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1904 * Be fancy and try to print contiguous runs
1905 * of IRQ values as ranges. 'run' is true if
1906 * we are in a range.
1908 device_printf(child, "using IRQs %d", irqs[0]);
1910 for (i = 1; i < actual; i++) {
1912 /* Still in a run? */
1913 if (irqs[i] == irqs[i - 1] + 1) {
1918 /* Finish previous range. */
1920 kprintf("-%d", irqs[i - 1]);
1924 /* Start new range. */
1925 kprintf(",%d", irqs[i]);
1928 /* Unfinished range? */
1930 kprintf("-%d", irqs[actual - 1]);
1931 kprintf(" for MSI\n");
1935 /* Update control register with actual count. */
1936 ctrl = cfg->msi.msi_ctrl;
1937 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1938 ctrl |= (ffs(actual) - 1) << 4;
1939 cfg->msi.msi_ctrl = ctrl;
1940 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1942 /* Update counts of alloc'd messages. */
1943 cfg->msi.msi_alloc = actual;
1944 cfg->msi.msi_handlers = 0;
1949 /* Release the MSI messages associated with this device. */
1951 pci_release_msi_method(device_t dev, device_t child)
1953 struct pci_devinfo *dinfo = device_get_ivars(child);
1954 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1955 struct resource_list_entry *rle;
1956 int error, i, irqs[32];
1958 /* Try MSI-X first. */
1959 error = pci_release_msix(dev, child);
1960 if (error != ENODEV)
1963 /* Do we have any messages to release? */
1964 if (msi->msi_alloc == 0)
1966 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
1968 /* Make sure none of the resources are allocated. */
1969 if (msi->msi_handlers > 0)
1971 for (i = 0; i < msi->msi_alloc; i++) {
1972 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1973 KASSERT(rle != NULL, ("missing MSI resource"));
1974 if (rle->res != NULL)
1976 irqs[i] = rle->start;
1979 /* Update control register with 0 count. */
1980 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
1981 ("%s: MSI still enabled", __func__));
1982 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
1983 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
1986 /* Release the messages. */
1987 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
1988 for (i = 0; i < msi->msi_alloc; i++)
1989 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1991 /* Update alloc count. */
1999 * Return the max supported MSI messages this device supports.
2000 * Basically, assuming the MD code can alloc messages, this function
2001 * should return the maximum value that pci_alloc_msi() can return.
2002 * Thus, it is subject to the tunables, etc.
2005 pci_msi_count_method(device_t dev, device_t child)
2007 struct pci_devinfo *dinfo = device_get_ivars(child);
2008 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2010 if (pci_do_msi && msi->msi_location != 0)
2011 return (msi->msi_msgnum);
2015 /* kfree pcicfgregs structure and all depending data structures */
2018 pci_freecfg(struct pci_devinfo *dinfo)
2020 struct devlist *devlist_head;
2023 devlist_head = &pci_devq;
2025 if (dinfo->cfg.vpd.vpd_reg) {
2026 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2027 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2028 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2029 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2030 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2031 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2032 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2034 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2035 kfree(dinfo, M_DEVBUF);
2037 /* increment the generation count */
2040 /* we're losing one device */
2046 * PCI power manangement
2049 pci_set_powerstate_method(device_t dev, device_t child, int state)
2051 struct pci_devinfo *dinfo = device_get_ivars(child);
2052 pcicfgregs *cfg = &dinfo->cfg;
2054 int result, oldstate, highest, delay;
2056 if (cfg->pp.pp_cap == 0)
2057 return (EOPNOTSUPP);
2060 * Optimize a no state change request away. While it would be OK to
2061 * write to the hardware in theory, some devices have shown odd
2062 * behavior when going from D3 -> D3.
2064 oldstate = pci_get_powerstate(child);
2065 if (oldstate == state)
2069 * The PCI power management specification states that after a state
2070 * transition between PCI power states, system software must
2071 * guarantee a minimal delay before the function accesses the device.
2072 * Compute the worst case delay that we need to guarantee before we
2073 * access the device. Many devices will be responsive much more
2074 * quickly than this delay, but there are some that don't respond
2075 * instantly to state changes. Transitions to/from D3 state require
2076 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2077 * is done below with DELAY rather than a sleeper function because
2078 * this function can be called from contexts where we cannot sleep.
2080 highest = (oldstate > state) ? oldstate : state;
2081 if (highest == PCI_POWERSTATE_D3)
2083 else if (highest == PCI_POWERSTATE_D2)
2087 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2088 & ~PCIM_PSTAT_DMASK;
2091 case PCI_POWERSTATE_D0:
2092 status |= PCIM_PSTAT_D0;
2094 case PCI_POWERSTATE_D1:
2095 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2096 return (EOPNOTSUPP);
2097 status |= PCIM_PSTAT_D1;
2099 case PCI_POWERSTATE_D2:
2100 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2101 return (EOPNOTSUPP);
2102 status |= PCIM_PSTAT_D2;
2104 case PCI_POWERSTATE_D3:
2105 status |= PCIM_PSTAT_D3;
2113 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2114 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2115 dinfo->cfg.func, oldstate, state);
2117 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2124 pci_get_powerstate_method(device_t dev, device_t child)
2126 struct pci_devinfo *dinfo = device_get_ivars(child);
2127 pcicfgregs *cfg = &dinfo->cfg;
2131 if (cfg->pp.pp_cap != 0) {
2132 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2133 switch (status & PCIM_PSTAT_DMASK) {
2135 result = PCI_POWERSTATE_D0;
2138 result = PCI_POWERSTATE_D1;
2141 result = PCI_POWERSTATE_D2;
2144 result = PCI_POWERSTATE_D3;
2147 result = PCI_POWERSTATE_UNKNOWN;
2151 /* No support, device is always at D0 */
2152 result = PCI_POWERSTATE_D0;
2158 * Some convenience functions for PCI device drivers.
2161 static __inline void
2162 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2166 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2168 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2171 static __inline void
2172 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2176 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2178 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2182 pci_enable_busmaster_method(device_t dev, device_t child)
2184 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2189 pci_disable_busmaster_method(device_t dev, device_t child)
2191 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2196 pci_enable_io_method(device_t dev, device_t child, int space)
2206 case SYS_RES_IOPORT:
2207 bit = PCIM_CMD_PORTEN;
2210 case SYS_RES_MEMORY:
2211 bit = PCIM_CMD_MEMEN;
2217 pci_set_command_bit(dev, child, bit);
2218 /* Some devices seem to need a brief stall here, what do to? */
2219 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2222 device_printf(child, "failed to enable %s mapping!\n", error);
2227 pci_disable_io_method(device_t dev, device_t child, int space)
2237 case SYS_RES_IOPORT:
2238 bit = PCIM_CMD_PORTEN;
2241 case SYS_RES_MEMORY:
2242 bit = PCIM_CMD_MEMEN;
2248 pci_clear_command_bit(dev, child, bit);
2249 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2250 if (command & bit) {
2251 device_printf(child, "failed to disable %s mapping!\n", error);
2258 * New style pci driver. Parent device is either a pci-host-bridge or a
2259 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2263 pci_print_verbose(struct pci_devinfo *dinfo)
2267 pcicfgregs *cfg = &dinfo->cfg;
2269 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2270 cfg->vendor, cfg->device, cfg->revid);
2271 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2272 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2273 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2274 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2276 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2277 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2278 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2279 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2280 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2281 if (cfg->intpin > 0)
2282 kprintf("\tintpin=%c, irq=%d\n",
2283 cfg->intpin +'a' -1, cfg->intline);
2284 if (cfg->pp.pp_cap) {
2287 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2288 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2289 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2290 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2291 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2292 status & PCIM_PSTAT_DMASK);
2294 if (cfg->msi.msi_location) {
2297 ctrl = cfg->msi.msi_ctrl;
2298 kprintf("\tMSI supports %d message%s%s%s\n",
2299 cfg->msi.msi_msgnum,
2300 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2301 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2302 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2304 if (cfg->msix.msix_location) {
2305 kprintf("\tMSI-X supports %d message%s ",
2306 cfg->msix.msix_msgnum,
2307 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2308 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2309 kprintf("in map 0x%x\n",
2310 cfg->msix.msix_table_bar);
2312 kprintf("in maps 0x%x and 0x%x\n",
2313 cfg->msix.msix_table_bar,
2314 cfg->msix.msix_pba_bar);
2320 pci_porten(device_t pcib, int b, int s, int f)
2322 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2323 & PCIM_CMD_PORTEN) != 0;
2327 pci_memen(device_t pcib, int b, int s, int f)
2329 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2330 & PCIM_CMD_MEMEN) != 0;
2334 * Add a resource based on a pci map register. Return 1 if the map
2335 * register is a 32bit map register or 2 if it is a 64bit register.
2338 pci_add_map(device_t pcib, device_t bus, device_t dev,
2339 int b, int s, int f, int reg, struct resource_list *rl, int force,
2344 pci_addr_t start, end, count;
2351 struct resource *res;
2353 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2354 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2355 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2356 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2358 if (PCI_BAR_MEM(map)) {
2359 type = SYS_RES_MEMORY;
2360 if (map & PCIM_BAR_MEM_PREFETCH)
2363 type = SYS_RES_IOPORT;
2364 ln2size = pci_mapsize(testval);
2365 ln2range = pci_maprange(testval);
2366 base = pci_mapbase(map);
2367 barlen = ln2range == 64 ? 2 : 1;
2370 * For I/O registers, if bottom bit is set, and the next bit up
2371 * isn't clear, we know we have a BAR that doesn't conform to the
2372 * spec, so ignore it. Also, sanity check the size of the data
2373 * areas to the type of memory involved. Memory must be at least
2374 * 16 bytes in size, while I/O ranges must be at least 4.
2376 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2378 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2379 (type == SYS_RES_IOPORT && ln2size < 2))
2383 /* Read the other half of a 64bit map register */
2384 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2386 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2387 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2388 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2389 kprintf(", port disabled\n");
2390 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2391 kprintf(", memory disabled\n");
2393 kprintf(", enabled\n");
2397 * If base is 0, then we have problems. It is best to ignore
2398 * such entries for the moment. These will be allocated later if
2399 * the driver specifically requests them. However, some
2400 * removable busses look better when all resources are allocated,
2401 * so allow '0' to be overriden.
2403 * Similarly treat maps whose values is the same as the test value
2404 * read back. These maps have had all f's written to them by the
2405 * BIOS in an attempt to disable the resources.
2407 if (!force && (base == 0 || map == testval))
2409 if ((u_long)base != base) {
2411 "pci%d:%d:%d:%d bar %#x too many address bits",
2412 pci_get_domain(dev), b, s, f, reg);
2417 * This code theoretically does the right thing, but has
2418 * undesirable side effects in some cases where peripherals
2419 * respond oddly to having these bits enabled. Let the user
2420 * be able to turn them off (since pci_enable_io_modes is 1 by
2423 if (pci_enable_io_modes) {
2424 /* Turn on resources that have been left off by a lazy BIOS */
2425 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2426 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2427 cmd |= PCIM_CMD_PORTEN;
2428 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2430 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2431 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2432 cmd |= PCIM_CMD_MEMEN;
2433 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2436 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2438 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2442 count = 1 << ln2size;
2443 if (base == 0 || base == pci_mapbase(testval)) {
2444 start = 0; /* Let the parent decide. */
2448 end = base + (1 << ln2size) - 1;
2450 resource_list_add(rl, type, reg, start, end, count);
2453 * Try to allocate the resource for this BAR from our parent
2454 * so that this resource range is already reserved. The
2455 * driver for this device will later inherit this resource in
2456 * pci_alloc_resource().
2458 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2459 prefetch ? RF_PREFETCHABLE : 0);
2462 * If the allocation fails, clear the BAR and delete
2463 * the resource list entry to force
2464 * pci_alloc_resource() to allocate resources from the
2467 resource_list_delete(rl, type, reg);
2470 start = rman_get_start(res);
2471 pci_write_config(dev, reg, start, 4);
2473 pci_write_config(dev, reg + 4, start >> 32, 4);
2478 * For ATA devices we need to decide early what addressing mode to use.
2479 * Legacy demands that the primary and secondary ATA ports sits on the
2480 * same addresses that old ISA hardware did. This dictates that we use
2481 * those addresses and ignore the BAR's if we cannot set PCI native
2485 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2486 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2488 int rid, type, progif;
2490 /* if this device supports PCI native addressing use it */
2491 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2492 if ((progif & 0x8a) == 0x8a) {
2493 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2494 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2495 kprintf("Trying ATA native PCI addressing mode\n");
2496 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2500 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2501 type = SYS_RES_IOPORT;
2502 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2503 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2504 prefetchmask & (1 << 0));
2505 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2506 prefetchmask & (1 << 1));
2509 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2510 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2513 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2514 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2517 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2518 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2519 prefetchmask & (1 << 2));
2520 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2521 prefetchmask & (1 << 3));
2524 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2525 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2528 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2529 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2532 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2533 prefetchmask & (1 << 4));
2534 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2535 prefetchmask & (1 << 5));
2539 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2541 struct pci_devinfo *dinfo = device_get_ivars(dev);
2542 pcicfgregs *cfg = &dinfo->cfg;
2543 char tunable_name[64];
2546 /* Has to have an intpin to have an interrupt. */
2547 if (cfg->intpin == 0)
2550 /* Let the user override the IRQ with a tunable. */
2551 irq = PCI_INVALID_IRQ;
2552 ksnprintf(tunable_name, sizeof(tunable_name),
2553 "hw.pci%d.%d.%d.INT%c.irq",
2554 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2555 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2556 irq = PCI_INVALID_IRQ;
2559 * If we didn't get an IRQ via the tunable, then we either use the
2560 * IRQ value in the intline register or we ask the bus to route an
2561 * interrupt for us. If force_route is true, then we only use the
2562 * value in the intline register if the bus was unable to assign an
2565 if (!PCI_INTERRUPT_VALID(irq)) {
2566 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2567 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2568 if (!PCI_INTERRUPT_VALID(irq))
2572 /* If after all that we don't have an IRQ, just bail. */
2573 if (!PCI_INTERRUPT_VALID(irq))
2576 /* Update the config register if it changed. */
2577 if (irq != cfg->intline) {
2579 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2582 /* Add this IRQ as rid 0 interrupt resource. */
2583 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2587 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2589 struct pci_devinfo *dinfo = device_get_ivars(dev);
2590 pcicfgregs *cfg = &dinfo->cfg;
2591 struct resource_list *rl = &dinfo->resources;
2592 struct pci_quirk *q;
2599 /* ATA devices needs special map treatment */
2600 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2601 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2602 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2603 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2604 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2605 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2607 for (i = 0; i < cfg->nummaps;)
2608 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2609 rl, force, prefetchmask & (1 << i));
2612 * Add additional, quirked resources.
2614 for (q = &pci_quirks[0]; q->devid; q++) {
2615 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2616 && q->type == PCI_QUIRK_MAP_REG)
2617 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2621 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2622 #ifdef __PCI_REROUTE_INTERRUPT
2624 * Try to re-route interrupts. Sometimes the BIOS or
2625 * firmware may leave bogus values in these registers.
2626 * If the re-route fails, then just stick with what we
2629 pci_assign_interrupt(bus, dev, 1);
2631 pci_assign_interrupt(bus, dev, 0);
2637 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2639 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2640 device_t pcib = device_get_parent(dev);
2641 struct pci_devinfo *dinfo;
2643 int s, f, pcifunchigh;
2646 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2647 ("dinfo_size too small"));
2648 maxslots = PCIB_MAXSLOTS(pcib);
2649 for (s = 0; s <= maxslots; s++) {
2653 hdrtype = REG(PCIR_HDRTYPE, 1);
2654 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2656 if (hdrtype & PCIM_MFDEV)
2657 pcifunchigh = PCI_FUNCMAX;
2658 for (f = 0; f <= pcifunchigh; f++) {
2659 dinfo = pci_read_device(pcib, domain, busno, s, f,
2661 if (dinfo != NULL) {
2662 pci_add_child(dev, dinfo);
2670 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2674 pcib = device_get_parent(bus);
2675 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2676 device_set_ivars(dinfo->cfg.dev, dinfo);
2677 resource_list_init(&dinfo->resources);
2678 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2679 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2680 pci_print_verbose(dinfo);
2681 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2685 pci_probe(device_t dev)
2687 device_set_desc(dev, "PCI bus");
2689 /* Allow other subclasses to override this driver. */
2694 pci_attach(device_t dev)
2699 * Since there can be multiple independantly numbered PCI
2700 * busses on systems with multiple PCI domains, we can't use
2701 * the unit number to decide which bus we are probing. We ask
2702 * the parent pcib what our domain and bus numbers are.
2704 domain = pcib_get_domain(dev);
2705 busno = pcib_get_bus(dev);
2707 device_printf(dev, "domain=%d, physical bus=%d\n",
2710 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2712 return (bus_generic_attach(dev));
2716 pci_suspend(device_t dev)
2718 int dstate, error, i, numdevs;
2719 device_t acpi_dev, child, *devlist;
2720 struct pci_devinfo *dinfo;
2723 * Save the PCI configuration space for each child and set the
2724 * device in the appropriate power state for this sleep state.
2727 if (pci_do_power_resume)
2728 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2729 device_get_children(dev, &devlist, &numdevs);
2730 for (i = 0; i < numdevs; i++) {
2732 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2733 pci_cfg_save(child, dinfo, 0);
2736 /* Suspend devices before potentially powering them down. */
2737 error = bus_generic_suspend(dev);
2739 kfree(devlist, M_TEMP);
2744 * Always set the device to D3. If ACPI suggests a different
2745 * power state, use it instead. If ACPI is not present, the
2746 * firmware is responsible for managing device power. Skip
2747 * children who aren't attached since they are powered down
2748 * separately. Only manage type 0 devices for now.
2750 for (i = 0; acpi_dev && i < numdevs; i++) {
2752 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2753 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2754 dstate = PCI_POWERSTATE_D3;
2755 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2756 pci_set_powerstate(child, dstate);
2759 kfree(devlist, M_TEMP);
2764 pci_resume(device_t dev)
2767 device_t acpi_dev, child, *devlist;
2768 struct pci_devinfo *dinfo;
2771 * Set each child to D0 and restore its PCI configuration space.
2774 if (pci_do_power_resume)
2775 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2776 device_get_children(dev, &devlist, &numdevs);
2777 for (i = 0; i < numdevs; i++) {
2779 * Notify ACPI we're going to D0 but ignore the result. If
2780 * ACPI is not present, the firmware is responsible for
2781 * managing device power. Only manage type 0 devices for now.
2784 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2785 if (acpi_dev && device_is_attached(child) &&
2786 dinfo->cfg.hdrtype == 0) {
2787 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2788 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2791 /* Now the device is powered up, restore its config space. */
2792 pci_cfg_restore(child, dinfo);
2794 kfree(devlist, M_TEMP);
2795 return (bus_generic_resume(dev));
2799 pci_load_vendor_data(void)
2801 caddr_t vendordata, info;
2803 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2804 info = preload_search_info(vendordata, MODINFO_ADDR);
2805 pci_vendordata = *(char **)info;
2806 info = preload_search_info(vendordata, MODINFO_SIZE);
2807 pci_vendordata_size = *(size_t *)info;
2808 /* terminate the database */
2809 pci_vendordata[pci_vendordata_size] = '\n';
2814 pci_driver_added(device_t dev, driver_t *driver)
2819 struct pci_devinfo *dinfo;
2823 device_printf(dev, "driver added\n");
2824 DEVICE_IDENTIFY(driver, dev);
2825 device_get_children(dev, &devlist, &numdevs);
2826 for (i = 0; i < numdevs; i++) {
2828 if (device_get_state(child) != DS_NOTPRESENT)
2830 dinfo = device_get_ivars(child);
2831 pci_print_verbose(dinfo);
2833 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2834 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2836 pci_cfg_restore(child, dinfo);
2837 if (device_probe_and_attach(child) != 0)
2838 pci_cfg_save(child, dinfo, 1);
2840 kfree(devlist, M_TEMP);
2844 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2845 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
2848 struct pci_devinfo *dinfo;
2849 struct msix_table_entry *mte;
2850 struct msix_vector *mv;
2856 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
2857 arg, &cookie, serializer);
2861 /* If this is not a direct child, just bail out. */
2862 if (device_get_parent(child) != dev) {
2867 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2869 rid = rman_get_rid(irq);
2871 /* Make sure that INTx is enabled */
2872 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2875 * Check to see if the interrupt is MSI or MSI-X.
2876 * Ask our parent to map the MSI and give
2877 * us the address and data register values.
2878 * If we fail for some reason, teardown the
2879 * interrupt handler.
2881 dinfo = device_get_ivars(child);
2882 if (dinfo->cfg.msi.msi_alloc > 0) {
2883 if (dinfo->cfg.msi.msi_addr == 0) {
2884 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
2885 ("MSI has handlers, but vectors not mapped"));
2886 error = PCIB_MAP_MSI(device_get_parent(dev),
2887 child, rman_get_start(irq), &addr, &data);
2890 dinfo->cfg.msi.msi_addr = addr;
2891 dinfo->cfg.msi.msi_data = data;
2892 pci_enable_msi(child, addr, data);
2894 dinfo->cfg.msi.msi_handlers++;
2896 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2897 ("No MSI or MSI-X interrupts allocated"));
2898 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2899 ("MSI-X index too high"));
2900 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2901 KASSERT(mte->mte_vector != 0, ("no message vector"));
2902 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
2903 KASSERT(mv->mv_irq == rman_get_start(irq),
2905 if (mv->mv_address == 0) {
2906 KASSERT(mte->mte_handlers == 0,
2907 ("MSI-X table entry has handlers, but vector not mapped"));
2908 error = PCIB_MAP_MSI(device_get_parent(dev),
2909 child, rman_get_start(irq), &addr, &data);
2912 mv->mv_address = addr;
2915 if (mte->mte_handlers == 0) {
2916 pci_enable_msix(child, rid - 1, mv->mv_address,
2918 pci_unmask_msix(child, rid - 1);
2920 mte->mte_handlers++;
2923 /* Make sure that INTx is disabled if we are using MSI/MSIX */
2924 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2927 (void)bus_generic_teardown_intr(dev, child, irq,
2938 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
2942 struct msix_table_entry *mte;
2943 struct resource_list_entry *rle;
2944 struct pci_devinfo *dinfo;
2948 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
2951 /* If this isn't a direct child, just bail out */
2952 if (device_get_parent(child) != dev)
2953 return(bus_generic_teardown_intr(dev, child, irq, cookie));
2955 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2957 rid = rman_get_rid(irq);
2960 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2963 * Check to see if the interrupt is MSI or MSI-X. If so,
2964 * decrement the appropriate handlers count and mask the
2965 * MSI-X message, or disable MSI messages if the count
2968 dinfo = device_get_ivars(child);
2969 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
2970 if (rle->res != irq)
2972 if (dinfo->cfg.msi.msi_alloc > 0) {
2973 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
2974 ("MSI-X index too high"));
2975 if (dinfo->cfg.msi.msi_handlers == 0)
2977 dinfo->cfg.msi.msi_handlers--;
2978 if (dinfo->cfg.msi.msi_handlers == 0)
2979 pci_disable_msi(child);
2981 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2982 ("No MSI or MSI-X interrupts allocated"));
2983 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2984 ("MSI-X index too high"));
2985 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2986 if (mte->mte_handlers == 0)
2988 mte->mte_handlers--;
2989 if (mte->mte_handlers == 0)
2990 pci_mask_msix(child, rid - 1);
2993 error = bus_generic_teardown_intr(dev, child, irq, cookie);
2996 ("%s: generic teardown failed for MSI/MSI-X", __func__));
2998 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3003 pci_print_child(device_t dev, device_t child)
3005 struct pci_devinfo *dinfo;
3006 struct resource_list *rl;
3009 dinfo = device_get_ivars(child);
3010 rl = &dinfo->resources;
3012 retval += bus_print_child_header(dev, child);
3014 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3015 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3016 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3017 if (device_get_flags(dev))
3018 retval += kprintf(" flags %#x", device_get_flags(dev));
3020 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3021 pci_get_function(child));
3023 retval += bus_print_child_footer(dev, child);
3033 } pci_nomatch_tab[] = {
3034 {PCIC_OLD, -1, "old"},
3035 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3036 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3037 {PCIC_STORAGE, -1, "mass storage"},
3038 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3039 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3040 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3041 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3042 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3043 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3044 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3045 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3046 {PCIC_NETWORK, -1, "network"},
3047 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3048 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3049 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3050 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3051 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3052 {PCIC_DISPLAY, -1, "display"},
3053 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3054 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3055 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3056 {PCIC_MULTIMEDIA, -1, "multimedia"},
3057 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3058 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3059 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3060 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3061 {PCIC_MEMORY, -1, "memory"},
3062 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3063 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3064 {PCIC_BRIDGE, -1, "bridge"},
3065 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3066 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3067 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3068 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3069 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3070 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3071 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3072 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3073 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3074 {PCIC_SIMPLECOMM, -1, "simple comms"},
3075 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3076 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3077 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3078 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3079 {PCIC_BASEPERIPH, -1, "base peripheral"},
3080 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3081 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3082 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3083 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3084 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3085 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3086 {PCIC_INPUTDEV, -1, "input device"},
3087 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3088 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3089 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3090 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3091 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3092 {PCIC_DOCKING, -1, "docking station"},
3093 {PCIC_PROCESSOR, -1, "processor"},
3094 {PCIC_SERIALBUS, -1, "serial bus"},
3095 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3096 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3097 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3098 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3099 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3100 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3101 {PCIC_WIRELESS, -1, "wireless controller"},
3102 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3103 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3104 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3105 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3106 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3107 {PCIC_SATCOM, -1, "satellite communication"},
3108 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3109 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3110 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3111 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3112 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3113 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3114 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3115 {PCIC_DASP, -1, "dasp"},
3116 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3121 pci_probe_nomatch(device_t dev, device_t child)
3124 char *cp, *scp, *device;
3127 * Look for a listing for this device in a loaded device database.
3129 if ((device = pci_describe_device(child)) != NULL) {
3130 device_printf(dev, "<%s>", device);
3131 kfree(device, M_DEVBUF);
3134 * Scan the class/subclass descriptions for a general
3139 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3140 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3141 if (pci_nomatch_tab[i].subclass == -1) {
3142 cp = pci_nomatch_tab[i].desc;
3143 } else if (pci_nomatch_tab[i].subclass ==
3144 pci_get_subclass(child)) {
3145 scp = pci_nomatch_tab[i].desc;
3149 device_printf(dev, "<%s%s%s>",
3151 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3154 kprintf(" at device %d.%d (no driver attached)\n",
3155 pci_get_slot(child), pci_get_function(child));
3156 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3161 * Parse the PCI device database, if loaded, and return a pointer to a
3162 * description of the device.
3164 * The database is flat text formatted as follows:
3166 * Any line not in a valid format is ignored.
3167 * Lines are terminated with newline '\n' characters.
3169 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3172 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3173 * - devices cannot be listed without a corresponding VENDOR line.
3174 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3175 * another TAB, then the device name.
3179 * Assuming (ptr) points to the beginning of a line in the database,
3180 * return the vendor or device and description of the next entry.
3181 * The value of (vendor) or (device) inappropriate for the entry type
3182 * is set to -1. Returns nonzero at the end of the database.
3184 * Note that this is slightly unrobust in the face of corrupt data;
3185 * we attempt to safeguard against this by spamming the end of the
3186 * database with a newline when we initialise.
3189 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3198 left = pci_vendordata_size - (cp - pci_vendordata);
3206 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3210 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3213 /* skip to next line */
3214 while (*cp != '\n' && left > 0) {
3223 /* skip to next line */
3224 while (*cp != '\n' && left > 0) {
3228 if (*cp == '\n' && left > 0)
3235 pci_describe_device(device_t dev)
3238 char *desc, *vp, *dp, *line;
3240 desc = vp = dp = NULL;
3243 * If we have no vendor data, we can't do anything.
3245 if (pci_vendordata == NULL)
3249 * Scan the vendor data looking for this device
3251 line = pci_vendordata;
3252 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3255 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3257 if (vendor == pci_get_vendor(dev))
3260 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3263 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3271 if (device == pci_get_device(dev))
3275 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3276 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3278 ksprintf(desc, "%s, %s", vp, dp);
3281 kfree(vp, M_DEVBUF);
3283 kfree(dp, M_DEVBUF);
3288 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3290 struct pci_devinfo *dinfo;
3293 dinfo = device_get_ivars(child);
3297 case PCI_IVAR_ETHADDR:
3299 * The generic accessor doesn't deal with failure, so
3300 * we set the return value, then return an error.
3302 *((uint8_t **) result) = NULL;
3304 case PCI_IVAR_SUBVENDOR:
3305 *result = cfg->subvendor;
3307 case PCI_IVAR_SUBDEVICE:
3308 *result = cfg->subdevice;
3310 case PCI_IVAR_VENDOR:
3311 *result = cfg->vendor;
3313 case PCI_IVAR_DEVICE:
3314 *result = cfg->device;
3316 case PCI_IVAR_DEVID:
3317 *result = (cfg->device << 16) | cfg->vendor;
3319 case PCI_IVAR_CLASS:
3320 *result = cfg->baseclass;
3322 case PCI_IVAR_SUBCLASS:
3323 *result = cfg->subclass;
3325 case PCI_IVAR_PROGIF:
3326 *result = cfg->progif;
3328 case PCI_IVAR_REVID:
3329 *result = cfg->revid;
3331 case PCI_IVAR_INTPIN:
3332 *result = cfg->intpin;
3335 *result = cfg->intline;
3337 case PCI_IVAR_DOMAIN:
3338 *result = cfg->domain;
3344 *result = cfg->slot;
3346 case PCI_IVAR_FUNCTION:
3347 *result = cfg->func;
3349 case PCI_IVAR_CMDREG:
3350 *result = cfg->cmdreg;
3352 case PCI_IVAR_CACHELNSZ:
3353 *result = cfg->cachelnsz;
3355 case PCI_IVAR_MINGNT:
3356 *result = cfg->mingnt;
3358 case PCI_IVAR_MAXLAT:
3359 *result = cfg->maxlat;
3361 case PCI_IVAR_LATTIMER:
3362 *result = cfg->lattimer;
3371 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3373 struct pci_devinfo *dinfo;
3375 dinfo = device_get_ivars(child);
3378 case PCI_IVAR_INTPIN:
3379 dinfo->cfg.intpin = value;
3381 case PCI_IVAR_ETHADDR:
3382 case PCI_IVAR_SUBVENDOR:
3383 case PCI_IVAR_SUBDEVICE:
3384 case PCI_IVAR_VENDOR:
3385 case PCI_IVAR_DEVICE:
3386 case PCI_IVAR_DEVID:
3387 case PCI_IVAR_CLASS:
3388 case PCI_IVAR_SUBCLASS:
3389 case PCI_IVAR_PROGIF:
3390 case PCI_IVAR_REVID:
3392 case PCI_IVAR_DOMAIN:
3395 case PCI_IVAR_FUNCTION:
3396 return (EINVAL); /* disallow for now */
3403 #include "opt_ddb.h"
3405 #include <ddb/ddb.h>
3406 #include <sys/cons.h>
3409 * List resources based on pci map registers, used for within ddb
3412 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3414 struct pci_devinfo *dinfo;
3415 struct devlist *devlist_head;
3418 int i, error, none_count;
3421 /* get the head of the device queue */
3422 devlist_head = &pci_devq;
3425 * Go through the list of devices and print out devices
3427 for (error = 0, i = 0,
3428 dinfo = STAILQ_FIRST(devlist_head);
3429 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3430 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3432 /* Populate pd_name and pd_unit */
3435 name = device_get_name(dinfo->cfg.dev);
3438 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3439 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3440 (name && *name) ? name : "none",
3441 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3443 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3444 p->pc_sel.pc_func, (p->pc_class << 16) |
3445 (p->pc_subclass << 8) | p->pc_progif,
3446 (p->pc_subdevice << 16) | p->pc_subvendor,
3447 (p->pc_device << 16) | p->pc_vendor,
3448 p->pc_revid, p->pc_hdr);
3454 static struct resource *
3455 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3456 u_long start, u_long end, u_long count, u_int flags)
3458 struct pci_devinfo *dinfo = device_get_ivars(child);
3459 struct resource_list *rl = &dinfo->resources;
3460 struct resource_list_entry *rle;
3461 struct resource *res;
3462 pci_addr_t map, testval;
3466 * Weed out the bogons, and figure out how large the BAR/map
3467 * is. Bars that read back 0 here are bogus and unimplemented.
3468 * Note: atapci in legacy mode are special and handled elsewhere
3469 * in the code. If you have a atapci device in legacy mode and
3470 * it fails here, that other code is broken.
3473 map = pci_read_config(child, *rid, 4);
3474 pci_write_config(child, *rid, 0xffffffff, 4);
3475 testval = pci_read_config(child, *rid, 4);
3476 if (pci_maprange(testval) == 64)
3477 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3478 if (pci_mapbase(testval) == 0)
3482 * Restore the original value of the BAR. We may have reprogrammed
3483 * the BAR of the low-level console device and when booting verbose,
3484 * we need the console device addressable.
3486 pci_write_config(child, *rid, map, 4);
3488 if (PCI_BAR_MEM(testval)) {
3489 if (type != SYS_RES_MEMORY) {
3492 "child %s requested type %d for rid %#x,"
3493 " but the BAR says it is an memio\n",
3494 device_get_nameunit(child), type, *rid);
3498 if (type != SYS_RES_IOPORT) {
3501 "child %s requested type %d for rid %#x,"
3502 " but the BAR says it is an ioport\n",
3503 device_get_nameunit(child), type, *rid);
3508 * For real BARs, we need to override the size that
3509 * the driver requests, because that's what the BAR
3510 * actually uses and we would otherwise have a
3511 * situation where we might allocate the excess to
3512 * another driver, which won't work.
3514 mapsize = pci_mapsize(testval);
3515 count = 1UL << mapsize;
3516 if (RF_ALIGNMENT(flags) < mapsize)
3517 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3518 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3519 flags |= RF_PREFETCHABLE;
3522 * Allocate enough resource, and then write back the
3523 * appropriate bar for that resource.
3525 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3526 start, end, count, flags);
3528 device_printf(child,
3529 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3530 count, *rid, type, start, end);
3533 resource_list_add(rl, type, *rid, start, end, count);
3534 rle = resource_list_find(rl, type, *rid);
3536 panic("pci_alloc_map: unexpectedly can't find resource.");
3538 rle->start = rman_get_start(res);
3539 rle->end = rman_get_end(res);
3542 device_printf(child,
3543 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3544 count, *rid, type, rman_get_start(res));
3545 map = rman_get_start(res);
3547 pci_write_config(child, *rid, map, 4);
3548 if (pci_maprange(testval) == 64)
3549 pci_write_config(child, *rid + 4, map >> 32, 4);
3555 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3556 u_long start, u_long end, u_long count, u_int flags)
3558 struct pci_devinfo *dinfo = device_get_ivars(child);
3559 struct resource_list *rl = &dinfo->resources;
3560 struct resource_list_entry *rle;
3561 pcicfgregs *cfg = &dinfo->cfg;
3562 //kprintf("%s on %s: requesting resource\n", device_get_desc(child), device_get_desc(dev));
3564 * Perform lazy resource allocation
3566 if (device_get_parent(child) == dev) {
3570 * Can't alloc legacy interrupt once MSI messages
3571 * have been allocated.
3574 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3575 cfg->msix.msix_alloc > 0))
3579 * If the child device doesn't have an
3580 * interrupt routed and is deserving of an
3581 * interrupt, try to assign it one.
3583 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3585 pci_assign_interrupt(dev, child, 0);
3587 case SYS_RES_IOPORT:
3588 case SYS_RES_MEMORY:
3589 if (*rid < PCIR_BAR(cfg->nummaps)) {
3591 * Enable the I/O mode. We should
3592 * also be assigning resources too
3593 * when none are present. The
3594 * resource_list_alloc kind of sorta does
3597 if (PCI_ENABLE_IO(dev, child, type))
3600 rle = resource_list_find(rl, type, *rid);
3602 return (pci_alloc_map(dev, child, type, rid,
3603 start, end, count, flags));
3607 * If we've already allocated the resource, then
3608 * return it now. But first we may need to activate
3609 * it, since we don't allocate the resource as active
3610 * above. Normally this would be done down in the
3611 * nexus, but since we short-circuit that path we have
3612 * to do its job here. Not sure if we should kfree the
3613 * resource if it fails to activate.
3615 rle = resource_list_find(rl, type, *rid);
3616 if (rle != NULL && rle->res != NULL) {
3618 device_printf(child,
3619 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3620 rman_get_size(rle->res), *rid, type,
3621 rman_get_start(rle->res));
3622 if ((flags & RF_ACTIVE) &&
3623 bus_generic_activate_resource(dev, child, type,
3624 *rid, rle->res) != 0)
3629 return (resource_list_alloc(rl, dev, child, type, rid,
3630 start, end, count, flags));
3634 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3636 struct pci_devinfo *dinfo;
3637 struct resource_list *rl;
3638 struct resource_list_entry *rle;
3640 if (device_get_parent(child) != dev)
3643 dinfo = device_get_ivars(child);
3644 rl = &dinfo->resources;
3645 rle = resource_list_find(rl, type, rid);
3648 if (rman_get_device(rle->res) != dev ||
3649 rman_get_flags(rle->res) & RF_ACTIVE) {
3650 device_printf(dev, "delete_resource: "
3651 "Resource still owned by child, oops. "
3652 "(type=%d, rid=%d, addr=%lx)\n",
3653 rle->type, rle->rid,
3654 rman_get_start(rle->res));
3657 bus_release_resource(dev, type, rid, rle->res);
3659 resource_list_delete(rl, type, rid);
3662 * Why do we turn off the PCI configuration BAR when we delete a
3665 pci_write_config(child, rid, 0, 4);
3666 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3669 struct resource_list *
3670 pci_get_resource_list (device_t dev, device_t child)
3672 struct pci_devinfo *dinfo = device_get_ivars(child);
3677 return (&dinfo->resources);
3681 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3683 struct pci_devinfo *dinfo = device_get_ivars(child);
3684 pcicfgregs *cfg = &dinfo->cfg;
3686 return (PCIB_READ_CONFIG(device_get_parent(dev),
3687 cfg->bus, cfg->slot, cfg->func, reg, width));
3691 pci_write_config_method(device_t dev, device_t child, int reg,
3692 uint32_t val, int width)
3694 struct pci_devinfo *dinfo = device_get_ivars(child);
3695 pcicfgregs *cfg = &dinfo->cfg;
3697 PCIB_WRITE_CONFIG(device_get_parent(dev),
3698 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3702 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3706 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3707 pci_get_function(child));
3712 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3715 struct pci_devinfo *dinfo;
3718 dinfo = device_get_ivars(child);
3720 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3721 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3722 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3728 pci_assign_interrupt_method(device_t dev, device_t child)
3730 struct pci_devinfo *dinfo = device_get_ivars(child);
3731 pcicfgregs *cfg = &dinfo->cfg;
3733 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3738 pci_modevent(module_t mod, int what, void *arg)
3740 static struct cdev *pci_cdev;
3741 extern struct dev_ops pcic_ops;
3745 STAILQ_INIT(&pci_devq);
3747 dev_ops_add(&pcic_ops, -1, 0);
3748 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3750 pci_load_vendor_data();
3754 destroy_dev(pci_cdev);
3762 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3767 * Only do header type 0 devices. Type 1 devices are bridges,
3768 * which we know need special treatment. Type 2 devices are
3769 * cardbus bridges which also require special treatment.
3770 * Other types are unknown, and we err on the side of safety
3773 if (dinfo->cfg.hdrtype != 0)
3777 * Restore the device to full power mode. We must do this
3778 * before we restore the registers because moving from D3 to
3779 * D0 will cause the chip's BARs and some other registers to
3780 * be reset to some unknown power on reset values. Cut down
3781 * the noise on boot by doing nothing if we are already in
3784 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3785 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3787 for (i = 0; i < dinfo->cfg.nummaps; i++)
3788 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3789 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3790 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3791 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3792 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3793 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3794 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3795 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3796 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3797 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3798 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3800 /* Restore MSI and MSI-X configurations if they are present. */
3801 if (dinfo->cfg.msi.msi_location != 0)
3802 pci_resume_msi(dev);
3803 if (dinfo->cfg.msix.msix_location != 0)
3804 pci_resume_msix(dev);
3808 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3815 * Only do header type 0 devices. Type 1 devices are bridges, which
3816 * we know need special treatment. Type 2 devices are cardbus bridges
3817 * which also require special treatment. Other types are unknown, and
3818 * we err on the side of safety by ignoring them. Powering down
3819 * bridges should not be undertaken lightly.
3821 if (dinfo->cfg.hdrtype != 0)
3823 for (i = 0; i < dinfo->cfg.nummaps; i++)
3824 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3825 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3828 * Some drivers apparently write to these registers w/o updating our
3829 * cached copy. No harm happens if we update the copy, so do so here
3830 * so we can restore them. The COMMAND register is modified by the
3831 * bus w/o updating the cache. This should represent the normally
3832 * writable portion of the 'defined' part of type 0 headers. In
3833 * theory we also need to save/restore the PCI capability structures
3834 * we know about, but apart from power we don't know any that are
3837 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3838 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3839 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3840 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3841 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3842 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3843 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3844 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3845 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3846 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3847 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3848 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
3849 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
3850 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
3851 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
3854 * don't set the state for display devices, base peripherals and
3855 * memory devices since bad things happen when they are powered down.
3856 * We should (a) have drivers that can easily detach and (b) use
3857 * generic drivers for these devices so that some device actually
3858 * attaches. We need to make sure that when we implement (a) we don't
3859 * power the device down on a reattach.
3861 cls = pci_get_class(dev);
3864 switch (pci_do_power_nodriver)
3866 case 0: /* NO powerdown at all */
3868 case 1: /* Conservative about what to power down */
3869 if (cls == PCIC_STORAGE)
3872 case 2: /* Agressive about what to power down */
3873 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
3874 cls == PCIC_BASEPERIPH)
3877 case 3: /* Power down everything */
3881 * PCI spec says we can only go into D3 state from D0 state.
3882 * Transition from D[12] into D0 before going to D3 state.
3884 ps = pci_get_powerstate(dev);
3885 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
3886 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3887 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
3888 pci_set_powerstate(dev, PCI_POWERSTATE_D3);