sys/platform/pc32/apic/apic_vector.s

   1 /*
   2  *      from: vector.s, 386BSD 0.1 unknown origin
   3  * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.47.2.5 2001/09/01 22:33:38 tegge Exp $
   4  * $DragonFly: src/sys/platform/pc32/apic/apic_vector.s,v 1.39 2008/08/02 01:14:43 dillon Exp $
   5  */
   6
   7 #include "use_npx.h"
   8 #include "opt_auto_eoi.h"
   9
  10 #include <machine/asmacros.h>
  11 #include <machine/lock.h>
  12 #include <machine/psl.h>
  13 #include <machine/trap.h>
  14
  15 #include <machine_base/icu/icu.h>
  16 #include <bus/isa/isa.h>
  17
  18 #include "assym.s"
  19
  20 #include "apicreg.h"
  21 #include "apic_ipl.h"
  22 #include <machine/smp.h>
  23 #include <machine_base/isa/intr_machdep.h>
  24
  25 /* convert an absolute IRQ# into a bitmask */
  26 #define IRQ_LBIT(irq_num)       (1 << (irq_num))
  27
  28 /* make an index into the IO APIC from the IRQ# */
  29 #define REDTBL_IDX(irq_num)     (0x10 + ((irq_num) * 2))
  30
  31 #ifdef SMP
  32 #define MPLOCKED     lock ;
  33 #else
  34 #define MPLOCKED
  35 #endif
  36
  37 /*
  38  * Push an interrupt frame in a format acceptable to doreti, reload
  39  * the segment registers for the kernel.
  40  */
  41 #define PUSH_FRAME                                                      \
  42         pushl   $0 ;            /* dummy error code */                  \
  43         pushl   $0 ;            /* dummy trap type */                   \
  44         pushl   $0 ;            /* dummy xflags type */                 \
  45         pushal ;                                                        \
  46         pushl   %ds ;           /* save data and extra segments ... */  \
  47         pushl   %es ;                                                   \
  48         pushl   %fs ;                                                   \
  49         pushl   %gs ;                                                   \
  50         cld ;                                                           \
  51         mov     $KDSEL,%ax ;                                            \
  52         mov     %ax,%ds ;                                               \
  53         mov     %ax,%es ;                                               \
  54         mov     %ax,%gs ;                                               \
  55         mov     $KPSEL,%ax ;                                            \
  56         mov     %ax,%fs ;                                               \
  57
  58 #define PUSH_DUMMY                                                      \
  59         pushfl ;                /* phys int frame / flags */            \
  60         pushl %cs ;             /* phys int frame / cs */               \
  61         pushl   12(%esp) ;      /* original caller eip */               \
  62         pushl   $0 ;            /* dummy error code */                  \
  63         pushl   $0 ;            /* dummy trap type */                   \
  64         pushl   $0 ;            /* dummy xflags type */                 \
  65         subl    $13*4,%esp ;    /* pushal + 4 seg regs (dummy) + CPL */ \
  66
  67 /*
  68  * Warning: POP_FRAME can only be used if there is no chance of a
  69  * segment register being changed (e.g. by procfs), which is why syscalls
  70  * have to use doreti.
  71  */
  72 #define POP_FRAME                                                       \
  73         popl    %gs ;                                                   \
  74         popl    %fs ;                                                   \
  75         popl    %es ;                                                   \
  76         popl    %ds ;                                                   \
  77         popal ;                                                         \
  78         addl    $3*4,%esp ;     /* dummy xflags, trap & error codes */  \
  79
  80 #define POP_DUMMY                                                       \
  81         addl    $19*4,%esp ;                                            \
  82
  83 #define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
  84 #define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
  85
  86 #define MASK_IRQ(irq_num)                                               \
  87         APIC_IMASK_LOCK ;                       /* into critical reg */ \
  88         testl   $IRQ_LBIT(irq_num), apic_imen ;                         \
  89         jne     7f ;                    /* masked, don't mask */        \
  90         orl     $IRQ_LBIT(irq_num), apic_imen ; /* set the mask bit */  \
  91         movl    IOAPICADDR(irq_num), %ecx ;     /* ioapic addr */       \
  92         movl    REDIRIDX(irq_num), %eax ;       /* get the index */     \
  93         movl    %eax, (%ecx) ;                  /* write the index */   \
  94         orl     $IOART_INTMASK,IOAPIC_WINDOW(%ecx) ;/* set the mask */  \
  95 7: ;                                            /* already masked */    \
  96         APIC_IMASK_UNLOCK ;                                             \
  97
  98 /*
  99  * Test to see whether we are handling an edge or level triggered INT.
 100  *  Level-triggered INTs must still be masked as we don't clear the source,
 101  *  and the EOI cycle would cause redundant INTs to occur.
 102  */
 103 #define MASK_LEVEL_IRQ(irq_num)                                         \
 104         testl   $IRQ_LBIT(irq_num), apic_pin_trigger ;                  \
 105         jz      9f ;                            /* edge, don't mask */  \
 106         MASK_IRQ(irq_num) ;                                             \
 107 9: ;                                                                    \
 108
 109 /*
 110  * Test to see if the source is currntly masked, clear if so.
 111  */
 112 #define UNMASK_IRQ(irq_num)                                     \
 113         cmpl    $0,%eax ;                                               \
 114         jnz     8f ;                                                    \
 115         APIC_IMASK_LOCK ;                       /* into critical reg */ \
 116         testl   $IRQ_LBIT(irq_num), apic_imen ;                         \
 117         je      7f ;                    /* bit clear, not masked */     \
 118         andl    $~IRQ_LBIT(irq_num), apic_imen ;/* clear mask bit */    \
 119         movl    IOAPICADDR(irq_num),%ecx ;      /* ioapic addr */       \
 120         movl    REDIRIDX(irq_num), %eax ;       /* get the index */     \
 121         movl    %eax,(%ecx) ;                   /* write the index */   \
 122         andl    $~IOART_INTMASK,IOAPIC_WINDOW(%ecx) ;/* clear the mask */ \
 123 7: ;                                                                    \
 124         APIC_IMASK_UNLOCK ;                                             \
 125 8: ;                                                                    \
 126
 127 #ifdef APIC_IO
 128
 129 /*
 130  * Fast interrupt call handlers run in the following sequence:
 131  *
 132  *      - Push the trap frame required by doreti
 133  *      - Mask the interrupt and reenable its source
 134  *      - If we cannot take the interrupt set its fpending bit and
 135  *        doreti.  Note that we cannot mess with mp_lock at all
 136  *        if we entered from a critical section!
 137  *      - If we can take the interrupt clear its fpending bit,
 138  *        call the handler, then unmask and doreti.
 139  *
 140  * YYY can cache gd base opitner instead of using hidden %fs prefixes.
 141  */
 142
 143 #define FAST_INTR(irq_num, vec_name)                                    \
 144         .text ;                                                         \
 145         SUPERALIGN_TEXT ;                                               \
 146 IDTVEC(vec_name) ;                                                      \
 147         PUSH_FRAME ;                                                    \
 148         FAKE_MCOUNT(15*4(%esp)) ;                                       \
 149         MASK_LEVEL_IRQ(irq_num) ;                                       \
 150         movl    $0, lapic_eoi ;                                         \
 151         movl    PCPU(curthread),%ebx ;                                  \
 152         movl    $0,%eax ;       /* CURRENT CPL IN FRAME (REMOVED) */    \
 153         pushl   %eax ;                                                  \
 154         testl   $-1,TD_NEST_COUNT(%ebx) ;                               \
 155         jne     1f ;                                                    \
 156         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 157         jl      2f ;                                                    \
 158 1: ;                                                                    \
 159         /* in critical section, make interrupt pending */               \
 160         /* set the pending bit and return, leave interrupt masked */    \
 161         orl     $IRQ_LBIT(irq_num),PCPU(fpending) ;                     \
 162         orl     $RQF_INTPEND,PCPU(reqflags) ;                           \
 163         jmp     5f ;                                                    \
 164 2: ;                                                                    \
 165         /* clear pending bit, run handler */                            \
 166         andl    $~IRQ_LBIT(irq_num),PCPU(fpending) ;                    \
 167         pushl   $irq_num ;                                              \
 168         pushl   %esp ;                   /* pass frame by reference */  \
 169         call    ithread_fast_handler ;   /* returns 0 to unmask */      \
 170         addl    $8, %esp ;                                              \
 171         UNMASK_IRQ(irq_num) ;                                           \
 172 5: ;                                                                    \
 173         MEXITCOUNT ;                                                    \
 174         jmp     doreti ;                                                \
 175
 176 /*
 177  * Slow interrupt call handlers run in the following sequence:
 178  *
 179  *      - Push the trap frame required by doreti.
 180  *      - Mask the interrupt and reenable its source.
 181  *      - If we cannot take the interrupt set its ipending bit and
 182  *        doreti.  In addition to checking for a critical section
 183  *        and cpl mask we also check to see if the thread is still
 184  *        running.  Note that we cannot mess with mp_lock at all
 185  *        if we entered from a critical section!
 186  *      - If we can take the interrupt clear its ipending bit
 187  *        and schedule the thread.  Leave interrupts masked and doreti.
 188  *
 189  *      Note that calls to sched_ithd() are made with interrupts enabled
 190  *      and outside a critical section.  YYY sched_ithd may preempt us
 191  *      synchronously (fix interrupt stacking).
 192  *
 193  *      YYY can cache gd base pointer instead of using hidden %fs
 194  *      prefixes.
 195  */
 196
 197 #define SLOW_INTR(irq_num, vec_name, maybe_extra_ipending)              \
 198         .text ;                                                         \
 199         SUPERALIGN_TEXT ;                                               \
 200 IDTVEC(vec_name) ;                                                      \
 201         PUSH_FRAME ;                                                    \
 202         maybe_extra_ipending ;                                          \
 203 ;                                                                       \
 204         MASK_LEVEL_IRQ(irq_num) ;                                       \
 205         incl    PCPU(cnt) + V_INTR ;                                    \
 206         movl    $0, lapic_eoi ;                                         \
 207         movl    PCPU(curthread),%ebx ;                                  \
 208         movl    $0,%eax ;       /* CURRENT CPL IN FRAME (REMOVED) */    \
 209         pushl   %eax ;          /* cpl do restore */                    \
 210         testl   $-1,TD_NEST_COUNT(%ebx) ;                               \
 211         jne     1f ;                                                    \
 212         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 213         jl      2f ;                                                    \
 214 1: ;                                                                    \
 215         /* set the pending bit and return, leave the interrupt masked */ \
 216         orl     $IRQ_LBIT(irq_num), PCPU(ipending) ;                    \
 217         orl     $RQF_INTPEND,PCPU(reqflags) ;                           \
 218         jmp     5f ;                                                    \
 219 2: ;                                                                    \
 220         /* set running bit, clear pending bit, run handler */           \
 221         andl    $~IRQ_LBIT(irq_num), PCPU(ipending) ;                   \
 222         incl    TD_NEST_COUNT(%ebx) ;                                   \
 223         sti ;                                                           \
 224         pushl   $irq_num ;                                              \
 225         call    sched_ithd ;                                            \
 226         addl    $4,%esp ;                                               \
 227         cli ;                                                           \
 228         decl    TD_NEST_COUNT(%ebx) ;                                   \
 229 5: ;                                                                    \
 230         MEXITCOUNT ;                                                    \
 231         jmp     doreti ;                                                \
 232
 233 /*
 234  * Wrong interrupt call handlers.  We program these into APIC vectors
 235  * that should otherwise never occur.  For example, we program the SLOW
 236  * vector for irq N with this when we program the FAST vector with the
 237  * real interrupt.
 238  *
 239  * XXX for now all we can do is EOI it.  We can't call do_wrongintr
 240  * (yet) because we could be in a critical section.
 241  */
 242 #define WRONGINTR(irq_num,vec_name)                                     \
 243         .text ;                                                         \
 244         SUPERALIGN_TEXT  ;                                              \
 245 IDTVEC(vec_name) ;                                                      \
 246         PUSH_FRAME ;                                                    \
 247         movl    $0, lapic_eoi ; /* End Of Interrupt to APIC */          \
 248         /*pushl $irq_num ;*/                                            \
 249         /*call  do_wrongintr ;*/                                        \
 250         /*addl  $4,%esp ;*/                                             \
 251         POP_FRAME ;                                                     \
 252         iret  ;                                                         \
 253
 254 #endif
 255
 256 /*
 257  * Handle "spurious INTerrupts".
 258  * Notes:
 259  *  This is different than the "spurious INTerrupt" generated by an
 260  *   8259 PIC for missing INTs.  See the APIC documentation for details.
 261  *  This routine should NOT do an 'EOI' cycle.
 262  */
 263         .text
 264         SUPERALIGN_TEXT
 265         .globl Xspuriousint
 266 Xspuriousint:
 267
 268         /* No EOI cycle used here */
 269
 270         iret
 271
 272
 273 /*
 274  * Handle TLB shootdowns.
 275  */
 276         .text
 277         SUPERALIGN_TEXT
 278         .globl  Xinvltlb
 279 Xinvltlb:
 280         pushl   %eax
 281
 282         movl    %cr3, %eax              /* invalidate the TLB */
 283         movl    %eax, %cr3
 284
 285         ss                              /* stack segment, avoid %ds load */
 286         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 287
 288         popl    %eax
 289         iret
 290
 291
 292 /*
 293  * Executed by a CPU when it receives an Xcpustop IPI from another CPU,
 294  *
 295  *  - Signals its receipt.
 296  *  - Waits for permission to restart.
 297  *  - Processing pending IPIQ events while waiting.
 298  *  - Signals its restart.
 299  */
 300
 301         .text
 302         SUPERALIGN_TEXT
 303         .globl Xcpustop
 304 Xcpustop:
 305         pushl   %ebp
 306         movl    %esp, %ebp
 307         pushl   %eax
 308         pushl   %ecx
 309         pushl   %edx
 310         pushl   %ds                     /* save current data segment */
 311         pushl   %fs
 312
 313         movl    $KDSEL, %eax
 314         mov     %ax, %ds                /* use KERNEL data segment */
 315         movl    $KPSEL, %eax
 316         mov     %ax, %fs
 317
 318         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 319
 320         movl    PCPU(cpuid), %eax
 321         imull   $PCB_SIZE, %eax
 322         leal    CNAME(stoppcbs)(%eax), %eax
 323         pushl   %eax
 324         call    CNAME(savectx)          /* Save process context */
 325         addl    $4, %esp
 326
 327
 328         movl    PCPU(cpuid), %eax
 329
 330         /*
 331          * Indicate that we have stopped and loop waiting for permission
 332          * to start again.  We must still process IPI events while in a
 333          * stopped state.
 334          */
 335         MPLOCKED
 336         btsl    %eax, stopped_cpus      /* stopped_cpus |= (1<<id) */
 337 1:
 338         andl    $~RQF_IPIQ,PCPU(reqflags)
 339         pushl   %eax
 340         call    lwkt_smp_stopped
 341         popl    %eax
 342         btl     %eax, started_cpus      /* while (!(started_cpus & (1<<id))) */
 343         jnc     1b
 344
 345         MPLOCKED
 346         btrl    %eax, started_cpus      /* started_cpus &= ~(1<<id) */
 347         MPLOCKED
 348         btrl    %eax, stopped_cpus      /* stopped_cpus &= ~(1<<id) */
 349
 350         test    %eax, %eax
 351         jnz     2f
 352
 353         movl    CNAME(cpustop_restartfunc), %eax
 354         test    %eax, %eax
 355         jz      2f
 356         movl    $0, CNAME(cpustop_restartfunc)  /* One-shot */
 357
 358         call    *%eax
 359 2:
 360         popl    %fs
 361         popl    %ds                     /* restore previous data segment */
 362         popl    %edx
 363         popl    %ecx
 364         popl    %eax
 365         movl    %ebp, %esp
 366         popl    %ebp
 367         iret
 368
 369         /*
 370          * For now just have one ipiq IPI, but what we really want is
 371          * to have one for each source cpu to the APICs don't get stalled
 372          * backlogging the requests.
 373          */
 374         .text
 375         SUPERALIGN_TEXT
 376         .globl Xipiq
 377 Xipiq:
 378         PUSH_FRAME
 379         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 380         FAKE_MCOUNT(15*4(%esp))
 381
 382         incl    PCPU(cnt) + V_IPI
 383         movl    PCPU(curthread),%ebx
 384         cmpl    $TDPRI_CRIT,TD_PRI(%ebx)
 385         jge     1f
 386         subl    $8,%esp                 /* make same as interrupt frame */
 387         pushl   %esp                    /* pass frame by reference */
 388         incl    PCPU(intr_nesting_level)
 389         addl    $TDPRI_CRIT,TD_PRI(%ebx)
 390         call    lwkt_process_ipiq_frame
 391         subl    $TDPRI_CRIT,TD_PRI(%ebx)
 392         decl    PCPU(intr_nesting_level)
 393         addl    $12,%esp
 394         pushl   $0                      /* CPL for frame (REMOVED) */
 395         MEXITCOUNT
 396         jmp     doreti
 397 1:
 398         orl     $RQF_IPIQ,PCPU(reqflags)
 399         MEXITCOUNT
 400         POP_FRAME
 401         iret
 402
 403         .text
 404         SUPERALIGN_TEXT
 405         .globl Xtimer
 406 Xtimer:
 407         PUSH_FRAME
 408         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 409         FAKE_MCOUNT(15*4(%esp))
 410
 411         incl    PCPU(cnt) + V_TIMER
 412         movl    PCPU(curthread),%ebx
 413         cmpl    $TDPRI_CRIT,TD_PRI(%ebx)
 414         jge     1f
 415         testl   $-1,TD_NEST_COUNT(%ebx)
 416         jne     1f
 417         subl    $8,%esp                 /* make same as interrupt frame */
 418         pushl   %esp                    /* pass frame by reference */
 419         incl    PCPU(intr_nesting_level)
 420         addl    $TDPRI_CRIT,TD_PRI(%ebx)
 421         call    lapic_timer_process_frame
 422         subl    $TDPRI_CRIT,TD_PRI(%ebx)
 423         decl    PCPU(intr_nesting_level)
 424         addl    $12,%esp
 425         pushl   $0                      /* CPL for frame (REMOVED) */
 426         MEXITCOUNT
 427         jmp     doreti
 428 1:
 429         orl     $RQF_TIMER,PCPU(reqflags)
 430         MEXITCOUNT
 431         POP_FRAME
 432         iret
 433
 434 #ifdef APIC_IO
 435
 436 MCOUNT_LABEL(bintr)
 437         FAST_INTR(0,apic_fastintr0)
 438         FAST_INTR(1,apic_fastintr1)
 439         FAST_INTR(2,apic_fastintr2)
 440         FAST_INTR(3,apic_fastintr3)
 441         FAST_INTR(4,apic_fastintr4)
 442         FAST_INTR(5,apic_fastintr5)
 443         FAST_INTR(6,apic_fastintr6)
 444         FAST_INTR(7,apic_fastintr7)
 445         FAST_INTR(8,apic_fastintr8)
 446         FAST_INTR(9,apic_fastintr9)
 447         FAST_INTR(10,apic_fastintr10)
 448         FAST_INTR(11,apic_fastintr11)
 449         FAST_INTR(12,apic_fastintr12)
 450         FAST_INTR(13,apic_fastintr13)
 451         FAST_INTR(14,apic_fastintr14)
 452         FAST_INTR(15,apic_fastintr15)
 453         FAST_INTR(16,apic_fastintr16)
 454         FAST_INTR(17,apic_fastintr17)
 455         FAST_INTR(18,apic_fastintr18)
 456         FAST_INTR(19,apic_fastintr19)
 457         FAST_INTR(20,apic_fastintr20)
 458         FAST_INTR(21,apic_fastintr21)
 459         FAST_INTR(22,apic_fastintr22)
 460         FAST_INTR(23,apic_fastintr23)
 461
 462         /* YYY what is this garbage? */
 463
 464         SLOW_INTR(0,apic_slowintr0,)
 465         SLOW_INTR(1,apic_slowintr1,)
 466         SLOW_INTR(2,apic_slowintr2,)
 467         SLOW_INTR(3,apic_slowintr3,)
 468         SLOW_INTR(4,apic_slowintr4,)
 469         SLOW_INTR(5,apic_slowintr5,)
 470         SLOW_INTR(6,apic_slowintr6,)
 471         SLOW_INTR(7,apic_slowintr7,)
 472         SLOW_INTR(8,apic_slowintr8,)
 473         SLOW_INTR(9,apic_slowintr9,)
 474         SLOW_INTR(10,apic_slowintr10,)
 475         SLOW_INTR(11,apic_slowintr11,)
 476         SLOW_INTR(12,apic_slowintr12,)
 477         SLOW_INTR(13,apic_slowintr13,)
 478         SLOW_INTR(14,apic_slowintr14,)
 479         SLOW_INTR(15,apic_slowintr15,)
 480         SLOW_INTR(16,apic_slowintr16,)
 481         SLOW_INTR(17,apic_slowintr17,)
 482         SLOW_INTR(18,apic_slowintr18,)
 483         SLOW_INTR(19,apic_slowintr19,)
 484         SLOW_INTR(20,apic_slowintr20,)
 485         SLOW_INTR(21,apic_slowintr21,)
 486         SLOW_INTR(22,apic_slowintr22,)
 487         SLOW_INTR(23,apic_slowintr23,)
 488
 489         WRONGINTR(0,apic_wrongintr0)
 490         WRONGINTR(1,apic_wrongintr1)
 491         WRONGINTR(2,apic_wrongintr2)
 492         WRONGINTR(3,apic_wrongintr3)
 493         WRONGINTR(4,apic_wrongintr4)
 494         WRONGINTR(5,apic_wrongintr5)
 495         WRONGINTR(6,apic_wrongintr6)
 496         WRONGINTR(7,apic_wrongintr7)
 497         WRONGINTR(8,apic_wrongintr8)
 498         WRONGINTR(9,apic_wrongintr9)
 499         WRONGINTR(10,apic_wrongintr10)
 500         WRONGINTR(11,apic_wrongintr11)
 501         WRONGINTR(12,apic_wrongintr12)
 502         WRONGINTR(13,apic_wrongintr13)
 503         WRONGINTR(14,apic_wrongintr14)
 504         WRONGINTR(15,apic_wrongintr15)
 505         WRONGINTR(16,apic_wrongintr16)
 506         WRONGINTR(17,apic_wrongintr17)
 507         WRONGINTR(18,apic_wrongintr18)
 508         WRONGINTR(19,apic_wrongintr19)
 509         WRONGINTR(20,apic_wrongintr20)
 510         WRONGINTR(21,apic_wrongintr21)
 511         WRONGINTR(22,apic_wrongintr22)
 512         WRONGINTR(23,apic_wrongintr23)
 513 MCOUNT_LABEL(eintr)
 514
 515 #endif
 516
 517         .data
 518
 519 /* variables used by stop_cpus()/restart_cpus()/Xcpustop */
 520         .globl stopped_cpus, started_cpus
 521 stopped_cpus:
 522         .long   0
 523 started_cpus:
 524         .long   0
 525
 526         .globl CNAME(cpustop_restartfunc)
 527 CNAME(cpustop_restartfunc):
 528         .long 0
 529
 530         .globl  apic_pin_trigger
 531 apic_pin_trigger:
 532         .long   0
 533
 534         .text
 535