2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/ioapic_abi.h>
60 #include <machine_base/apic/lapic.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
69 #include <machine/md_var.h> /* setidt() */
70 #include <machine_base/icu/icu.h> /* IPIs */
71 #include <machine/intr_machdep.h> /* IPIs */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
83 * this code MUST be enabled here and in mpboot.s.
84 * it follows the very early stages of AP boot by placing values in CMOS ram.
85 * it NORMALLY will never be needed and thus the primitive method for enabling.
88 #if defined(CHECK_POINTS)
89 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
90 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
92 #define CHECK_INIT(D); \
93 CHECK_WRITE(0x34, (D)); \
94 CHECK_WRITE(0x35, (D)); \
95 CHECK_WRITE(0x36, (D)); \
96 CHECK_WRITE(0x37, (D)); \
97 CHECK_WRITE(0x38, (D)); \
98 CHECK_WRITE(0x39, (D));
100 #define CHECK_PRINT(S); \
101 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
110 #else /* CHECK_POINTS */
112 #define CHECK_INIT(D)
113 #define CHECK_PRINT(S)
115 #endif /* CHECK_POINTS */
118 * Values to send to the POST hardware.
120 #define MP_BOOTADDRESS_POST 0x10
121 #define MP_PROBE_POST 0x11
122 #define MPTABLE_PASS1_POST 0x12
124 #define MP_START_POST 0x13
125 #define MP_ENABLE_POST 0x14
126 #define MPTABLE_PASS2_POST 0x15
128 #define START_ALL_APS_POST 0x16
129 #define INSTALL_AP_TRAMP_POST 0x17
130 #define START_AP_POST 0x18
132 #define MP_ANNOUNCE_POST 0x19
134 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
135 int current_postcode;
137 /** XXX FIXME: what system files declare these??? */
138 extern struct region_descriptor r_gdt, r_idt;
140 int mp_naps; /* # of Applications processors */
144 extern int64_t tsc_offsets[];
146 #ifdef SMP /* APIC-IO */
147 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
150 /* AP uses this during bootstrap. Do not staticize. */
154 /* Hotwire a 0->4MB V==P mapping */
155 extern pt_entry_t *KPTphys;
158 * SMP page table page. Setup by locore to point to a page table
159 * page from which we allocate per-cpu privatespace areas io_apics,
162 extern pt_entry_t *SMPpt;
164 struct pcb stoppcbs[MAXCPU];
167 * Local data and functions.
170 static u_int boot_address;
171 static int mp_finish;
172 static int mp_finish_lapic;
174 static void mp_enable(u_int boot_addr);
176 static int start_all_aps(u_int boot_addr);
177 static void install_ap_tramp(u_int boot_addr);
178 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
179 static int smitest(void);
181 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
182 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
183 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
184 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
190 * Calculate usable address in base memory for AP trampoline code.
193 mp_bootaddress(u_int basemem)
195 POSTCODE(MP_BOOTADDRESS_POST);
197 base_memory = basemem;
199 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
200 if ((base_memory - boot_address) < bootMP_size)
201 boot_address -= 4096; /* not enough, lower by 4k */
207 * Startup the SMP processors.
212 POSTCODE(MP_START_POST);
213 mp_enable(boot_address);
218 * Print various information about the SMP system hardware and setup.
225 POSTCODE(MP_ANNOUNCE_POST);
227 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
228 kprintf(" cpu0 (BSP): apic id: %2d\n", CPU_TO_ID(0));
229 for (x = 1; x <= mp_naps; ++x)
230 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPU_TO_ID(x));
233 kprintf(" Warning: APIC I/O disabled\n");
237 * AP cpu's call this to sync up protected mode.
239 * WARNING! We must ensure that the cpu is sufficiently initialized to
240 * be able to use to the FP for our optimized bzero/bcopy code before
241 * we enter more mainstream C code.
243 * WARNING! %fs is not set up on entry. This routine sets up %fs.
249 int x, myid = bootAP;
251 struct mdglobaldata *md;
252 struct privatespace *ps;
254 ps = &CPU_prvspace[myid];
256 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
257 gdt_segs[GPROC0_SEL].ssd_base =
258 (int) &ps->mdglobaldata.gd_common_tss;
259 ps->mdglobaldata.mi.gd_prvspace = ps;
261 for (x = 0; x < NGDT; x++) {
262 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
265 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
266 r_gdt.rd_base = (int) &gdt[myid * NGDT];
267 lgdt(&r_gdt); /* does magic intra-segment return */
272 mdcpu->gd_currentldt = _default_ldt;
274 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
275 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
277 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
279 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
280 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
281 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
282 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
283 md->gd_common_tssd = *md->gd_tss_gdt;
287 * Set to a known state:
288 * Set by mpboot.s: CR0_PG, CR0_PE
289 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
292 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
294 pmap_set_opt(); /* PSE/4MB pages, etc */
296 /* set up CPU registers and state */
299 /* set up FPU state on the AP */
300 npxinit(__INITIAL_NPXCW__);
302 /* set up SSE registers */
306 /*******************************************************************
307 * local functions and data
311 * start the SMP system
314 mp_enable(u_int boot_addr)
316 POSTCODE(MP_ENABLE_POST);
320 /* Initialize BSP's local APIC */
323 /* start each Application Processor */
324 start_all_aps(boot_addr);
330 MachIntrABI.finalize();
334 mp_set_cpuids(int cpu_id, int apic_id)
336 CPU_TO_ID(cpu_id) = apic_id;
337 ID_TO_CPU(apic_id) = cpu_id;
341 * start each AP in our list
344 start_all_aps(u_int boot_addr)
352 u_long mpbioswarmvec;
353 struct mdglobaldata *gd;
354 struct privatespace *ps;
358 POSTCODE(START_ALL_APS_POST);
360 /* install the AP 1st level boot code */
361 install_ap_tramp(boot_addr);
364 /* save the current value of the warm-start vector */
365 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
366 outb(CMOS_REG, BIOS_RESET);
367 mpbiosreason = inb(CMOS_DATA);
369 /* setup a vector to our boot code */
370 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
371 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
372 outb(CMOS_REG, BIOS_RESET);
373 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
376 * If we have a TSC we can figure out the SMI interrupt rate.
377 * The SMI does not necessarily use a constant rate. Spend
378 * up to 250ms trying to figure it out.
381 if (cpu_feature & CPUID_TSC) {
382 set_apic_timer(275000);
383 smilast = read_apic_timer();
384 for (x = 0; x < 20 && read_apic_timer(); ++x) {
385 smicount = smitest();
386 if (smibest == 0 || smilast - smicount < smibest)
387 smibest = smilast - smicount;
390 if (smibest > 250000)
393 smibest = smibest * (int64_t)1000000 /
394 get_apic_timer_frequency();
398 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
399 1000000 / smibest, smibest);
402 /* set up temporary P==V mapping for AP boot */
403 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
404 kptbase = (uintptr_t)(void *)KPTphys;
405 for (x = 0; x < NKPT; x++) {
406 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
407 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
412 for (x = 1; x <= mp_naps; ++x) {
414 /* This is a bit verbose, it will go away soon. */
416 /* first page of AP's private space */
417 pg = x * i386_btop(sizeof(struct privatespace));
419 /* allocate new private data page(s) */
420 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
421 MDGLOBALDATA_BASEALLOC_SIZE);
422 /* wire it into the private page table page */
423 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
424 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
425 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
427 pg += MDGLOBALDATA_BASEALLOC_PAGES;
429 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
430 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
431 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
432 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
434 /* allocate and set up an idle stack data page */
435 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
436 for (i = 0; i < UPAGES; i++) {
437 SMPpt[pg + 4 + i] = (pt_entry_t)
438 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
441 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
442 bzero(gd, sizeof(*gd));
443 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
445 /* prime data page for it to use */
446 mi_gdinit(&gd->mi, x);
448 gd->gd_CMAP1 = &SMPpt[pg + 0];
449 gd->gd_CMAP2 = &SMPpt[pg + 1];
450 gd->gd_CMAP3 = &SMPpt[pg + 2];
451 gd->gd_PMAP1 = &SMPpt[pg + 3];
452 gd->gd_CADDR1 = ps->CPAGE1;
453 gd->gd_CADDR2 = ps->CPAGE2;
454 gd->gd_CADDR3 = ps->CPAGE3;
455 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
458 * Per-cpu pmap for get_ptbase().
460 gd->gd_GDADDR1= (unsigned *)
461 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
462 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
464 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
465 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
468 * Setup the AP boot stack
470 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
473 /* attempt to start the Application Processor */
474 CHECK_INIT(99); /* setup checkpoints */
475 if (!start_ap(gd, boot_addr, smibest)) {
476 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
477 CHECK_PRINT("trace"); /* show checkpoints */
478 /* better panic as the AP may be running loose */
479 kprintf("panic y/n? [y] ");
483 CHECK_PRINT("trace"); /* show checkpoints */
486 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
489 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
490 for (shift = 0; (1 << shift) <= ncpus; ++shift)
493 ncpus2_shift = shift;
495 ncpus2_mask = ncpus2 - 1;
497 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
498 if ((1 << shift) < ncpus)
500 ncpus_fit = 1 << shift;
501 ncpus_fit_mask = ncpus_fit - 1;
503 /* build our map of 'other' CPUs */
504 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
505 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
506 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
508 /* restore the warmstart vector */
509 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
510 outb(CMOS_REG, BIOS_RESET);
511 outb(CMOS_DATA, mpbiosreason);
514 * NOTE! The idlestack for the BSP was setup by locore. Finish
515 * up, clean out the P==V mapping we did earlier.
517 for (x = 0; x < NKPT; x++)
522 * Wait all APs to finish initializing LAPIC
526 kprintf("SMP: Waiting APs LAPIC initialization\n");
527 if (cpu_feature & CPUID_TSC)
528 tsc0_offset = rdtsc();
531 while (smp_lapic_mask != smp_startup_mask) {
533 if (cpu_feature & CPUID_TSC)
534 tsc0_offset = rdtsc();
536 while (try_mplock() == 0)
539 /* number of APs actually started */
544 * load the 1st level AP boot code into base memory.
547 /* targets for relocation */
548 extern void bigJump(void);
549 extern void bootCodeSeg(void);
550 extern void bootDataSeg(void);
551 extern void MPentry(void);
553 extern u_int mp_gdtbase;
556 install_ap_tramp(u_int boot_addr)
559 int size = *(int *) ((u_long) & bootMP_size);
560 u_char *src = (u_char *) ((u_long) bootMP);
561 u_char *dst = (u_char *) boot_addr + KERNBASE;
562 u_int boot_base = (u_int) bootMP;
567 POSTCODE(INSTALL_AP_TRAMP_POST);
569 for (x = 0; x < size; ++x)
573 * modify addresses in code we just moved to basemem. unfortunately we
574 * need fairly detailed info about mpboot.s for this to work. changes
575 * to mpboot.s might require changes here.
578 /* boot code is located in KERNEL space */
579 dst = (u_char *) boot_addr + KERNBASE;
581 /* modify the lgdt arg */
582 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
583 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
585 /* modify the ljmp target for MPentry() */
586 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
587 *dst32 = ((u_int) MPentry - KERNBASE);
589 /* modify the target for boot code segment */
590 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
591 dst8 = (u_int8_t *) (dst16 + 1);
592 *dst16 = (u_int) boot_addr & 0xffff;
593 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
595 /* modify the target for boot data segment */
596 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
597 dst8 = (u_int8_t *) (dst16 + 1);
598 *dst16 = (u_int) boot_addr & 0xffff;
599 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
604 * This function starts the AP (application processor) identified
605 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
606 * to accomplish this. This is necessary because of the nuances
607 * of the different hardware we might encounter. It ain't pretty,
608 * but it seems to work.
610 * NOTE: eventually an AP gets to ap_init(), which is called just
611 * before the AP goes into the LWKT scheduler's idle loop.
614 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
618 u_long icr_lo, icr_hi;
620 POSTCODE(START_AP_POST);
622 /* get the PHYSICAL APIC ID# */
623 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
625 /* calculate the vector */
626 vector = (boot_addr >> 12) & 0xff;
628 /* We don't want anything interfering */
631 /* Make sure the target cpu sees everything */
635 * Try to detect when a SMI has occurred, wait up to 200ms.
637 * If a SMI occurs during an AP reset but before we issue
638 * the STARTUP command, the AP may brick. To work around
639 * this problem we hold off doing the AP startup until
640 * after we have detected the SMI. Hopefully another SMI
641 * will not occur before we finish the AP startup.
643 * Retries don't seem to help. SMIs have a window of opportunity
644 * and if USB->legacy keyboard emulation is enabled in the BIOS
645 * the interrupt rate can be quite high.
647 * NOTE: Don't worry about the L1 cache load, it might bloat
648 * ldelta a little but ndelta will be so huge when the SMI
649 * occurs the detection logic will still work fine.
652 set_apic_timer(200000);
657 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
658 * and running the target CPU. OR this INIT IPI might be latched (P5
659 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
662 * see apic/apicreg.h for icr bit definitions.
664 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
668 * Setup the address for the target AP. We can setup
669 * icr_hi once and then just trigger operations with
672 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
673 icr_hi |= (physical_cpu << 24);
674 icr_lo = lapic->icr_lo & 0xfff00000;
675 lapic->icr_hi = icr_hi;
678 * Do an INIT IPI: assert RESET
680 * Use edge triggered mode to assert INIT
682 lapic->icr_lo = icr_lo | 0x0000c500;
683 while (lapic->icr_lo & APIC_DELSTAT_MASK)
687 * The spec calls for a 10ms delay but we may have to use a
688 * MUCH lower delay to avoid bricking an AP due to a fast SMI
689 * interrupt. We have other loops here too and dividing by 2
690 * doesn't seem to be enough even after subtracting 350us,
693 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
694 * interrupt was detected we use the full 10ms.
698 else if (smibest < 150 * 4 + 350)
700 else if ((smibest - 350) / 4 < 10000)
701 u_sleep((smibest - 350) / 4);
706 * Do an INIT IPI: deassert RESET
708 * Use level triggered mode to deassert. It is unclear
709 * why we need to do this.
711 lapic->icr_lo = icr_lo | 0x00008500;
712 while (lapic->icr_lo & APIC_DELSTAT_MASK)
714 u_sleep(150); /* wait 150us */
717 * Next we do a STARTUP IPI: the previous INIT IPI might still be
718 * latched, (P5 bug) this 1st STARTUP would then terminate
719 * immediately, and the previously started INIT IPI would continue. OR
720 * the previous INIT IPI has already run. and this STARTUP IPI will
721 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
724 lapic->icr_lo = icr_lo | 0x00000600 | vector;
725 while (lapic->icr_lo & APIC_DELSTAT_MASK)
727 u_sleep(200); /* wait ~200uS */
730 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
731 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
732 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
733 * recognized after hardware RESET or INIT IPI.
735 lapic->icr_lo = icr_lo | 0x00000600 | vector;
736 while (lapic->icr_lo & APIC_DELSTAT_MASK)
739 /* Resume normal operation */
742 /* wait for it to start, see ap_init() */
743 set_apic_timer(5000000);/* == 5 seconds */
744 while (read_apic_timer()) {
745 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
746 return 1; /* return SUCCESS */
749 return 0; /* return FAILURE */
764 while (read_apic_timer()) {
766 for (count = 0; count < 100; ++count)
767 ntsc = rdtsc(); /* force loop to occur */
769 ndelta = ntsc - ltsc;
772 if (ndelta > ldelta * 2)
775 ldelta = ntsc - ltsc;
778 return(read_apic_timer());
782 * Lazy flush the TLB on all other CPU's. DEPRECATED.
784 * If for some reason we were unable to start all cpus we cannot safely
785 * use broadcast IPIs.
788 static cpumask_t smp_invltlb_req;
789 #define SMP_INVLTLB_DEBUG
795 struct mdglobaldata *md = mdcpu;
796 #ifdef SMP_INVLTLB_DEBUG
801 crit_enter_gd(&md->mi);
802 md->gd_invltlb_ret = 0;
803 ++md->mi.gd_cnt.v_smpinvltlb;
804 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
805 #ifdef SMP_INVLTLB_DEBUG
808 if (smp_startup_mask == smp_active_mask) {
809 all_but_self_ipi(XINVLTLB_OFFSET);
811 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
812 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
815 #ifdef SMP_INVLTLB_DEBUG
817 kprintf("smp_invltlb: ipi sent\n");
819 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
820 (smp_active_mask & ~md->mi.gd_cpumask)) {
823 #ifdef SMP_INVLTLB_DEBUG
825 if (++count == 400000000) {
827 kprintf("smp_invltlb: endless loop %08lx %08lx, "
828 "rflags %016lx retry",
829 (long)md->gd_invltlb_ret,
830 (long)smp_invltlb_req,
831 (long)read_eflags());
832 __asm __volatile ("sti");
837 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
841 kprintf("bcpu %d\n", bcpu);
842 xgd = globaldata_find(bcpu);
843 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
852 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
853 crit_exit_gd(&md->mi);
860 * Called from Xinvltlb assembly with interrupts disabled. We didn't
861 * bother to bump the critical section count or nested interrupt count
862 * so only do very low level operations here.
865 smp_invltlb_intr(void)
867 struct mdglobaldata *md = mdcpu;
868 struct mdglobaldata *omd;
872 mask = smp_invltlb_req;
876 cpu = BSFCPUMASK(mask);
877 mask &= ~CPUMASK(cpu);
878 omd = (struct mdglobaldata *)globaldata_find(cpu);
879 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
886 * When called the executing CPU will send an IPI to all other CPUs
887 * requesting that they halt execution.
889 * Usually (but not necessarily) called with 'other_cpus' as its arg.
891 * - Signals all CPUs in map to stop.
892 * - Waits for each to stop.
899 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
900 * from executing at same time.
903 stop_cpus(cpumask_t map)
905 map &= smp_active_mask;
907 /* send the Xcpustop IPI to all CPUs in map */
908 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
910 while ((stopped_cpus & map) != map)
918 * Called by a CPU to restart stopped CPUs.
920 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
922 * - Signals all CPUs in map to restart.
923 * - Waits for each to restart.
931 restart_cpus(cpumask_t map)
933 /* signal other cpus to restart */
934 started_cpus = map & smp_active_mask;
936 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
943 * This is called once the mpboot code has gotten us properly relocated
944 * and the MMU turned on, etc. ap_init() is actually the idle thread,
945 * and when it returns the scheduler will call the real cpu_idle() main
946 * loop for the idlethread. Interrupts are disabled on entry and should
947 * remain disabled at return.
955 * Adjust smp_startup_mask to signal the BSP that we have started
956 * up successfully. Note that we do not yet hold the BGL. The BSP
957 * is waiting for our signal.
959 * We can't set our bit in smp_active_mask yet because we are holding
960 * interrupts physically disabled and remote cpus could deadlock
961 * trying to send us an IPI.
963 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
967 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
968 * non-zero, then get the MP lock.
970 * Note: We are in a critical section.
972 * Note: we are the idle thread, we can only spin.
974 * Note: The load fence is memory volatile and prevents the compiler
975 * from improperly caching mp_finish_lapic, and the cpu from improperly
978 while (mp_finish_lapic == 0)
980 while (try_mplock() == 0)
983 if (cpu_feature & CPUID_TSC) {
985 * The BSP is constantly updating tsc0_offset, figure out
986 * the relative difference to synchronize ktrdump.
988 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
991 /* BSP may have changed PTD while we're waiting for the lock */
994 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
998 /* Build our map of 'other' CPUs. */
999 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1001 /* A quick check from sanity claus */
1002 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
1003 if (mycpu->gd_cpuid != apic_id) {
1004 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
1005 kprintf("SMP: apic_id = %d\n", apic_id);
1006 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1007 panic("cpuid mismatch! boom!!");
1010 /* Initialize AP's local APIC for irq's */
1013 /* LAPIC initialization is done */
1014 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1017 /* Let BSP move onto the next initialization stage */
1021 * Interlock for finalization. Wait until mp_finish is non-zero,
1022 * then get the MP lock.
1024 * Note: We are in a critical section.
1026 * Note: we are the idle thread, we can only spin.
1028 * Note: The load fence is memory volatile and prevents the compiler
1029 * from improperly caching mp_finish, and the cpu from improperly
1032 while (mp_finish == 0)
1034 while (try_mplock() == 0)
1037 /* BSP may have changed PTD while we're waiting for the lock */
1040 /* Set memory range attributes for this CPU to match the BSP */
1041 mem_range_AP_init();
1044 * Once we go active we must process any IPIQ messages that may
1045 * have been queued, because no actual IPI will occur until we
1046 * set our bit in the smp_active_mask. If we don't the IPI
1047 * message interlock could be left set which would also prevent
1050 * The idle loop doesn't expect the BGL to be held and while
1051 * lwkt_switch() normally cleans things up this is a special case
1052 * because we returning almost directly into the idle loop.
1054 * The idle thread is never placed on the runq, make sure
1055 * nothing we've done put it there.
1057 KKASSERT(get_mplock_count(curthread) == 1);
1058 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1061 * Enable interrupts here. idle_restore will also do it, but
1062 * doing it here lets us clean up any strays that got posted to
1063 * the CPU during the AP boot while we are still in a critical
1066 __asm __volatile("sti; pause; pause"::);
1067 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1069 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1070 lwkt_process_ipiq();
1073 * Releasing the mp lock lets the BSP finish up the SMP init
1076 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1080 * Get SMP fully working before we start initializing devices.
1088 kprintf("Finish MP startup\n");
1090 while (smp_active_mask != smp_startup_mask)
1092 while (try_mplock() == 0)
1095 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
1098 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1101 cpu_send_ipiq(int dcpu)
1103 if (CPUMASK(dcpu) & smp_active_mask)
1104 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1107 #if 0 /* single_apic_ipi_passive() not working yet */
1109 * Returns 0 on failure, 1 on success
1112 cpu_send_ipiq_passive(int dcpu)
1115 if (CPUMASK(dcpu) & smp_active_mask) {
1116 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1117 APIC_DELMODE_FIXED);