2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.23 2005/02/21 18:40:36 joerg Exp $
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
48 * Accton EN1217 (www.accton.com)
49 * Conexant LANfinity (www.conexant.com)
51 * Datasheets for the 21143 are available at developer.intel.com.
52 * Datasheets for the clone parts can be found at their respective sites.
53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
54 * The PNIC II is essentially a Macronix 98715A chip; the only difference
55 * worth noting is that its multicast hash table is only 128 bits wide
58 * Written by Bill Paul <wpaul@ee.columbia.edu>
59 * Electrical Engineering Department
60 * Columbia University, New York City
64 * The Intel 21143 is the successor to the DEC 21140. It is basically
65 * the same as the 21140 but with a few new features. The 21143 supports
66 * three kinds of media attachments:
68 * o MII port, for 10Mbps and 100Mbps support and NWAY
69 * autonegotiation provided by an external PHY.
70 * o SYM port, for symbol mode 100Mbps support.
74 * The 100Mbps SYM port and 10baseT port can be used together in
75 * combination with the internal NWAY support to create a 10/100
76 * autosensing configuration.
78 * Note that not all tulip workalikes are handled in this driver: we only
79 * deal with those which are relatively well behaved. The Winbond is
80 * handled separately due to its different register offsets and the
81 * special handling needed for its various bugs. The PNIC is handled
82 * here, but I'm not thrilled about it.
84 * All of the workalike chips use some form of MII transceiver support
85 * with the exception of the Macronix chips, which also have a SYM port.
86 * The ASIX AX88140A is also documented to have a SYM port, but all
87 * the cards I've seen use an MII transceiver, probably because the
88 * AX88140A doesn't support internal NWAY.
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
98 #include <sys/sysctl.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
107 #include <net/vlan/if_vlan_var.h>
111 #include <vm/vm.h> /* for vtophys */
112 #include <vm/pmap.h> /* for vtophys */
113 #include <machine/clock.h> /* for DELAY */
114 #include <machine/bus_pio.h>
115 #include <machine/bus_memio.h>
116 #include <machine/bus.h>
117 #include <machine/resource.h>
119 #include <sys/rman.h>
121 #include "../mii_layer/mii.h"
122 #include "../mii_layer/miivar.h"
124 #include <bus/pci/pcireg.h>
125 #include <bus/pci/pcivar.h>
127 #define DC_USEIOSPACE
132 #include "if_dcreg.h"
134 /* "controller miibus0" required. See GENERIC if you get errors here. */
135 #include "miibus_if.h"
138 * Various supported device vendors/types and their names.
140 static struct dc_type dc_devs[] = {
141 { DC_VENDORID_DEC, DC_DEVICEID_21143,
142 "Intel 21143 10/100BaseTX" },
143 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
144 "Davicom DM9009 10/100BaseTX" },
145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
146 "Davicom DM9100 10/100BaseTX" },
147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
148 "Davicom DM9102 10/100BaseTX" },
149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
150 "Davicom DM9102A 10/100BaseTX" },
151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
152 "ADMtek AL981 10/100BaseTX" },
153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
154 "ADMtek AN985 10/100BaseTX" },
155 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
156 "ASIX AX88140A 10/100BaseTX" },
157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
158 "ASIX AX88141 10/100BaseTX" },
159 { DC_VENDORID_MX, DC_DEVICEID_98713,
160 "Macronix 98713 10/100BaseTX" },
161 { DC_VENDORID_MX, DC_DEVICEID_98713,
162 "Macronix 98713A 10/100BaseTX" },
163 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
164 "Compex RL100-TX 10/100BaseTX" },
165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
166 "Compex RL100-TX 10/100BaseTX" },
167 { DC_VENDORID_MX, DC_DEVICEID_987x5,
168 "Macronix 98715/98715A 10/100BaseTX" },
169 { DC_VENDORID_MX, DC_DEVICEID_987x5,
170 "Macronix 98715AEC-C 10/100BaseTX" },
171 { DC_VENDORID_MX, DC_DEVICEID_987x5,
172 "Macronix 98725 10/100BaseTX" },
173 { DC_VENDORID_MX, DC_DEVICEID_98727,
174 "Macronix 98727/98732 10/100BaseTX" },
175 { DC_VENDORID_LO, DC_DEVICEID_82C115,
176 "LC82C115 PNIC II 10/100BaseTX" },
177 { DC_VENDORID_LO, DC_DEVICEID_82C168,
178 "82c168 PNIC 10/100BaseTX" },
179 { DC_VENDORID_LO, DC_DEVICEID_82C168,
180 "82c169 PNIC 10/100BaseTX" },
181 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
182 "Accton EN1217 10/100BaseTX" },
183 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
184 "Accton EN2242 MiniPCI 10/100BaseTX" },
185 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
186 "Conexant LANfinity MiniPCI 10/100BaseTX" },
187 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
188 "3Com OfficeConnect 10/100B" },
192 static int dc_probe (device_t);
193 static int dc_attach (device_t);
194 static int dc_detach (device_t);
195 static int dc_suspend (device_t);
196 static int dc_resume (device_t);
197 static void dc_acpi (device_t);
198 static struct dc_type *dc_devtype (device_t);
199 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
200 static int dc_encap (struct dc_softc *, struct mbuf *,
202 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
203 static int dc_rx_resync (struct dc_softc *);
204 static void dc_rxeof (struct dc_softc *);
205 static void dc_txeof (struct dc_softc *);
206 static void dc_tick (void *);
207 static void dc_tx_underrun (struct dc_softc *);
208 static void dc_intr (void *);
209 static void dc_start (struct ifnet *);
210 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
212 static void dc_init (void *);
213 static void dc_stop (struct dc_softc *);
214 static void dc_watchdog (struct ifnet *);
215 static void dc_shutdown (device_t);
216 static int dc_ifmedia_upd (struct ifnet *);
217 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
219 static void dc_delay (struct dc_softc *);
220 static void dc_eeprom_idle (struct dc_softc *);
221 static void dc_eeprom_putbyte (struct dc_softc *, int);
222 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
223 static void dc_eeprom_getword_pnic
224 (struct dc_softc *, int, u_int16_t *);
225 static void dc_eeprom_width (struct dc_softc *);
226 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
229 static void dc_mii_writebit (struct dc_softc *, int);
230 static int dc_mii_readbit (struct dc_softc *);
231 static void dc_mii_sync (struct dc_softc *);
232 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
233 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
234 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
235 static int dc_miibus_readreg (device_t, int, int);
236 static int dc_miibus_writereg (device_t, int, int, int);
237 static void dc_miibus_statchg (device_t);
238 static void dc_miibus_mediainit (device_t);
240 static void dc_setcfg (struct dc_softc *, int);
241 static u_int32_t dc_crc_le (struct dc_softc *, c_caddr_t);
242 static u_int32_t dc_crc_be (caddr_t);
243 static void dc_setfilt_21143 (struct dc_softc *);
244 static void dc_setfilt_asix (struct dc_softc *);
245 static void dc_setfilt_admtek (struct dc_softc *);
247 static void dc_setfilt (struct dc_softc *);
249 static void dc_reset (struct dc_softc *);
250 static int dc_list_rx_init (struct dc_softc *);
251 static int dc_list_tx_init (struct dc_softc *);
253 static void dc_read_srom (struct dc_softc *, int);
254 static void dc_parse_21143_srom (struct dc_softc *);
255 static void dc_decode_leaf_sia (struct dc_softc *,
256 struct dc_eblock_sia *);
257 static void dc_decode_leaf_mii (struct dc_softc *,
258 struct dc_eblock_mii *);
259 static void dc_decode_leaf_sym (struct dc_softc *,
260 struct dc_eblock_sym *);
261 static void dc_apply_fixup (struct dc_softc *, int);
264 #define DC_RES SYS_RES_IOPORT
265 #define DC_RID DC_PCI_CFBIO
267 #define DC_RES SYS_RES_MEMORY
268 #define DC_RID DC_PCI_CFBMA
271 static device_method_t dc_methods[] = {
272 /* Device interface */
273 DEVMETHOD(device_probe, dc_probe),
274 DEVMETHOD(device_attach, dc_attach),
275 DEVMETHOD(device_detach, dc_detach),
276 DEVMETHOD(device_suspend, dc_suspend),
277 DEVMETHOD(device_resume, dc_resume),
278 DEVMETHOD(device_shutdown, dc_shutdown),
281 DEVMETHOD(bus_print_child, bus_generic_print_child),
282 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
285 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
286 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
287 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
288 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
293 static driver_t dc_driver = {
296 sizeof(struct dc_softc)
299 static devclass_t dc_devclass;
302 static int dc_quick=1;
303 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
304 &dc_quick,0,"do not mdevget in dc driver");
307 DECLARE_DUMMY_MODULE(if_dc);
308 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
309 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
311 #define DC_SETBIT(sc, reg, x) \
312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
314 #define DC_CLRBIT(sc, reg, x) \
315 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
317 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
318 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
320 static void dc_delay(sc)
325 for (idx = (300 / 33) + 1; idx > 0; idx--)
326 CSR_READ_4(sc, DC_BUSCTL);
329 static void dc_eeprom_width(sc)
334 /* Force EEPROM to idle state. */
337 /* Enter EEPROM access mode. */
338 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
340 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
342 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
344 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
349 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
351 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
353 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
355 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
359 for (i = 1; i <= 12; i++) {
360 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
362 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
363 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
367 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
371 /* Turn off EEPROM access mode. */
379 /* Enter EEPROM access mode. */
380 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
382 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
384 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
386 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
389 /* Turn off EEPROM access mode. */
393 static void dc_eeprom_idle(sc)
398 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
400 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
407 for (i = 0; i < 25; i++) {
408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
410 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
418 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
424 * Send a read command and address to the EEPROM, check for ACK.
426 static void dc_eeprom_putbyte(sc, addr)
432 d = DC_EECMD_READ >> 6;
435 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
441 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
446 * Feed in each bit and strobe the clock.
448 for (i = sc->dc_romwidth; i--;) {
449 if (addr & (1 << i)) {
450 SIO_SET(DC_SIO_EE_DATAIN);
452 SIO_CLR(DC_SIO_EE_DATAIN);
455 SIO_SET(DC_SIO_EE_CLK);
457 SIO_CLR(DC_SIO_EE_CLK);
465 * Read a word of data stored in the EEPROM at address 'addr.'
466 * The PNIC 82c168/82c169 has its own non-standard way to read
469 static void dc_eeprom_getword_pnic(sc, addr, dest)
477 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
479 for (i = 0; i < DC_TIMEOUT; i++) {
481 r = CSR_READ_4(sc, DC_SIO);
482 if (!(r & DC_PN_SIOCTL_BUSY)) {
483 *dest = (u_int16_t)(r & 0xFFFF);
492 * Read a word of data stored in the EEPROM at address 'addr.'
494 static void dc_eeprom_getword(sc, addr, dest)
502 /* Force EEPROM to idle state. */
505 /* Enter EEPROM access mode. */
506 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
508 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
510 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
512 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
516 * Send address of word we want to read.
518 dc_eeprom_putbyte(sc, addr);
521 * Start reading bits from EEPROM.
523 for (i = 0x8000; i; i >>= 1) {
524 SIO_SET(DC_SIO_EE_CLK);
526 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
529 SIO_CLR(DC_SIO_EE_CLK);
533 /* Turn off EEPROM access mode. */
542 * Read a sequence of words from the EEPROM.
544 static void dc_read_eeprom(sc, dest, off, cnt, swap)
552 u_int16_t word = 0, *ptr;
554 for (i = 0; i < cnt; i++) {
556 dc_eeprom_getword_pnic(sc, off + i, &word);
558 dc_eeprom_getword(sc, off + i, &word);
559 ptr = (u_int16_t *)(dest + (i * 2));
570 * The following two routines are taken from the Macronix 98713
571 * Application Notes pp.19-21.
574 * Write a bit to the MII bus.
576 static void dc_mii_writebit(sc, bit)
581 CSR_WRITE_4(sc, DC_SIO,
582 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
584 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
586 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
587 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
593 * Read a bit from the MII bus.
595 static int dc_mii_readbit(sc)
598 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
599 CSR_READ_4(sc, DC_SIO);
600 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
601 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
602 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
609 * Sync the PHYs by setting data bit and strobing the clock 32 times.
611 static void dc_mii_sync(sc)
616 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
618 for (i = 0; i < 32; i++)
619 dc_mii_writebit(sc, 1);
625 * Clock a series of bits through the MII.
627 static void dc_mii_send(sc, bits, cnt)
634 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
635 dc_mii_writebit(sc, bits & i);
639 * Read an PHY register through the MII.
641 static int dc_mii_readreg(sc, frame)
643 struct dc_mii_frame *frame;
651 * Set up frame for RX.
653 frame->mii_stdelim = DC_MII_STARTDELIM;
654 frame->mii_opcode = DC_MII_READOP;
655 frame->mii_turnaround = 0;
664 * Send command/address info.
666 dc_mii_send(sc, frame->mii_stdelim, 2);
667 dc_mii_send(sc, frame->mii_opcode, 2);
668 dc_mii_send(sc, frame->mii_phyaddr, 5);
669 dc_mii_send(sc, frame->mii_regaddr, 5);
673 dc_mii_writebit(sc, 1);
674 dc_mii_writebit(sc, 0);
678 ack = dc_mii_readbit(sc);
681 * Now try reading data bits. If the ack failed, we still
682 * need to clock through 16 cycles to keep the PHY(s) in sync.
685 for(i = 0; i < 16; i++) {
691 for (i = 0x8000; i; i >>= 1) {
693 if (dc_mii_readbit(sc))
694 frame->mii_data |= i;
700 dc_mii_writebit(sc, 0);
701 dc_mii_writebit(sc, 0);
711 * Write to a PHY register through the MII.
713 static int dc_mii_writereg(sc, frame)
715 struct dc_mii_frame *frame;
722 * Set up frame for TX.
725 frame->mii_stdelim = DC_MII_STARTDELIM;
726 frame->mii_opcode = DC_MII_WRITEOP;
727 frame->mii_turnaround = DC_MII_TURNAROUND;
734 dc_mii_send(sc, frame->mii_stdelim, 2);
735 dc_mii_send(sc, frame->mii_opcode, 2);
736 dc_mii_send(sc, frame->mii_phyaddr, 5);
737 dc_mii_send(sc, frame->mii_regaddr, 5);
738 dc_mii_send(sc, frame->mii_turnaround, 2);
739 dc_mii_send(sc, frame->mii_data, 16);
742 dc_mii_writebit(sc, 0);
743 dc_mii_writebit(sc, 0);
750 static int dc_miibus_readreg(dev, phy, reg)
754 struct dc_mii_frame frame;
756 int i, rval, phy_reg = 0;
758 sc = device_get_softc(dev);
759 bzero((char *)&frame, sizeof(frame));
762 * Note: both the AL981 and AN985 have internal PHYs,
763 * however the AL981 provides direct access to the PHY
764 * registers while the AN985 uses a serial MII interface.
765 * The AN985's MII interface is also buggy in that you
766 * can read from any MII address (0 to 31), but only address 1
767 * behaves normally. To deal with both cases, we pretend
768 * that the PHY is at MII address 1.
770 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
774 * Note: the ukphy probes of the RS7112 report a PHY at
775 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
776 * so we only respond to correct one.
778 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
781 if (sc->dc_pmode != DC_PMODE_MII) {
782 if (phy == (MII_NPHY - 1)) {
786 * Fake something to make the probe
787 * code think there's a PHY here.
789 return(BMSR_MEDIAMASK);
793 return(DC_VENDORID_LO);
794 return(DC_VENDORID_DEC);
798 return(DC_DEVICEID_82C168);
799 return(DC_DEVICEID_21143);
809 if (DC_IS_PNIC(sc)) {
810 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
811 (phy << 23) | (reg << 18));
812 for (i = 0; i < DC_TIMEOUT; i++) {
814 rval = CSR_READ_4(sc, DC_PN_MII);
815 if (!(rval & DC_PN_MII_BUSY)) {
817 return(rval == 0xFFFF ? 0 : rval);
823 if (DC_IS_COMET(sc)) {
826 phy_reg = DC_AL_BMCR;
829 phy_reg = DC_AL_BMSR;
832 phy_reg = DC_AL_VENID;
835 phy_reg = DC_AL_DEVID;
838 phy_reg = DC_AL_ANAR;
841 phy_reg = DC_AL_LPAR;
844 phy_reg = DC_AL_ANER;
847 printf("dc%d: phy_read: bad phy register %x\n",
853 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
860 frame.mii_phyaddr = phy;
861 frame.mii_regaddr = reg;
862 if (sc->dc_type == DC_TYPE_98713) {
863 phy_reg = CSR_READ_4(sc, DC_NETCFG);
864 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
866 dc_mii_readreg(sc, &frame);
867 if (sc->dc_type == DC_TYPE_98713)
868 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
870 return(frame.mii_data);
873 static int dc_miibus_writereg(dev, phy, reg, data)
878 struct dc_mii_frame frame;
881 sc = device_get_softc(dev);
882 bzero((char *)&frame, sizeof(frame));
884 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
887 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
890 if (DC_IS_PNIC(sc)) {
891 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
892 (phy << 23) | (reg << 10) | data);
893 for (i = 0; i < DC_TIMEOUT; i++) {
894 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
900 if (DC_IS_COMET(sc)) {
903 phy_reg = DC_AL_BMCR;
906 phy_reg = DC_AL_BMSR;
909 phy_reg = DC_AL_VENID;
912 phy_reg = DC_AL_DEVID;
915 phy_reg = DC_AL_ANAR;
918 phy_reg = DC_AL_LPAR;
921 phy_reg = DC_AL_ANER;
924 printf("dc%d: phy_write: bad phy register %x\n",
930 CSR_WRITE_4(sc, phy_reg, data);
934 frame.mii_phyaddr = phy;
935 frame.mii_regaddr = reg;
936 frame.mii_data = data;
938 if (sc->dc_type == DC_TYPE_98713) {
939 phy_reg = CSR_READ_4(sc, DC_NETCFG);
940 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
942 dc_mii_writereg(sc, &frame);
943 if (sc->dc_type == DC_TYPE_98713)
944 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
949 static void dc_miibus_statchg(dev)
953 struct mii_data *mii;
956 sc = device_get_softc(dev);
957 if (DC_IS_ADMTEK(sc))
960 mii = device_get_softc(sc->dc_miibus);
961 ifm = &mii->mii_media;
962 if (DC_IS_DAVICOM(sc) &&
963 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
964 dc_setcfg(sc, ifm->ifm_media);
965 sc->dc_if_media = ifm->ifm_media;
967 dc_setcfg(sc, mii->mii_media_active);
968 sc->dc_if_media = mii->mii_media_active;
975 * Special support for DM9102A cards with HomePNA PHYs. Note:
976 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
977 * to be impossible to talk to the management interface of the DM9801
978 * PHY (its MDIO pin is not connected to anything). Consequently,
979 * the driver has to just 'know' about the additional mode and deal
980 * with it itself. *sigh*
982 static void dc_miibus_mediainit(dev)
986 struct mii_data *mii;
990 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
992 sc = device_get_softc(dev);
993 mii = device_get_softc(sc->dc_miibus);
994 ifm = &mii->mii_media;
996 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
997 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1002 #define DC_POLY 0xEDB88320
1003 #define DC_BITS_512 9
1004 #define DC_BITS_128 7
1005 #define DC_BITS_64 6
1007 static u_int32_t dc_crc_le(sc, addr)
1008 struct dc_softc *sc;
1011 u_int32_t idx, bit, data, crc;
1013 /* Compute CRC for the address value. */
1014 crc = 0xFFFFFFFF; /* initial value */
1016 for (idx = 0; idx < 6; idx++) {
1017 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1018 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1022 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1023 * chips is only 128 bits wide.
1025 if (sc->dc_flags & DC_128BIT_HASH)
1026 return (crc & ((1 << DC_BITS_128) - 1));
1028 /* The hash table on the MX98715BEC is only 64 bits wide. */
1029 if (sc->dc_flags & DC_64BIT_HASH)
1030 return (crc & ((1 << DC_BITS_64) - 1));
1032 return (crc & ((1 << DC_BITS_512) - 1));
1036 * Calculate CRC of a multicast group address, return the lower 6 bits.
1038 static u_int32_t dc_crc_be(addr)
1041 u_int32_t crc, carry;
1045 /* Compute CRC for the address value. */
1046 crc = 0xFFFFFFFF; /* initial value */
1048 for (i = 0; i < 6; i++) {
1050 for (j = 0; j < 8; j++) {
1051 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1055 crc = (crc ^ 0x04c11db6) | carry;
1059 /* return the filter bit position */
1060 return((crc >> 26) & 0x0000003F);
1064 * 21143-style RX filter setup routine. Filter programming is done by
1065 * downloading a special setup frame into the TX engine. 21143, Macronix,
1066 * PNIC, PNIC II and Davicom chips are programmed this way.
1068 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1069 * address (our node address) and a 512-bit hash filter for multicast
1070 * frames. We also sneak the broadcast address into the hash filter since
1073 void dc_setfilt_21143(sc)
1074 struct dc_softc *sc;
1076 struct dc_desc *sframe;
1078 struct ifmultiaddr *ifma;
1082 ifp = &sc->arpcom.ac_if;
1084 i = sc->dc_cdata.dc_tx_prod;
1085 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1086 sc->dc_cdata.dc_tx_cnt++;
1087 sframe = &sc->dc_ldata->dc_tx_list[i];
1088 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1089 bzero((char *)sp, DC_SFRAME_LEN);
1091 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1092 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1093 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1095 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1097 /* If we want promiscuous mode, set the allframes bit. */
1098 if (ifp->if_flags & IFF_PROMISC)
1099 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1101 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1103 if (ifp->if_flags & IFF_ALLMULTI)
1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1108 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1109 ifma = ifma->ifma_link.le_next) {
1110 if (ifma->ifma_addr->sa_family != AF_LINK)
1113 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1114 sp[h >> 4] |= 1 << (h & 0xF);
1117 if (ifp->if_flags & IFF_BROADCAST) {
1118 h = dc_crc_le(sc, ifp->if_broadcastaddr);
1119 sp[h >> 4] |= 1 << (h & 0xF);
1122 /* Set our MAC address */
1123 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1124 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1125 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1127 sframe->dc_status = DC_TXSTAT_OWN;
1128 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1131 * The PNIC takes an exceedingly long time to process its
1132 * setup frame; wait 10ms after posting the setup frame
1133 * before proceeding, just so it has time to swallow its
1143 void dc_setfilt_admtek(sc)
1144 struct dc_softc *sc;
1148 u_int32_t hashes[2] = { 0, 0 };
1149 struct ifmultiaddr *ifma;
1151 ifp = &sc->arpcom.ac_if;
1153 /* Init our MAC address */
1154 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1155 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1157 /* If we want promiscuous mode, set the allframes bit. */
1158 if (ifp->if_flags & IFF_PROMISC)
1159 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1161 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1163 if (ifp->if_flags & IFF_ALLMULTI)
1164 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1166 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1168 /* first, zot all the existing hash bits */
1169 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1170 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1173 * If we're already in promisc or allmulti mode, we
1174 * don't have to bother programming the multicast filter.
1176 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1179 /* now program new ones */
1180 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1181 ifma = ifma->ifma_link.le_next) {
1182 if (ifma->ifma_addr->sa_family != AF_LINK)
1184 if (DC_IS_CENTAUR(sc))
1185 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1187 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1189 hashes[0] |= (1 << h);
1191 hashes[1] |= (1 << (h - 32));
1194 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1195 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1200 void dc_setfilt_asix(sc)
1201 struct dc_softc *sc;
1205 u_int32_t hashes[2] = { 0, 0 };
1206 struct ifmultiaddr *ifma;
1208 ifp = &sc->arpcom.ac_if;
1210 /* Init our MAC address */
1211 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1212 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1213 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1214 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1215 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1216 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1218 /* If we want promiscuous mode, set the allframes bit. */
1219 if (ifp->if_flags & IFF_PROMISC)
1220 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1222 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1224 if (ifp->if_flags & IFF_ALLMULTI)
1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1227 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1230 * The ASIX chip has a special bit to enable reception
1231 * of broadcast frames.
1233 if (ifp->if_flags & IFF_BROADCAST)
1234 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1236 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1238 /* first, zot all the existing hash bits */
1239 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1240 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1245 * If we're already in promisc or allmulti mode, we
1246 * don't have to bother programming the multicast filter.
1248 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1251 /* now program new ones */
1252 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1253 ifma = ifma->ifma_link.le_next) {
1254 if (ifma->ifma_addr->sa_family != AF_LINK)
1256 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1258 hashes[0] |= (1 << h);
1260 hashes[1] |= (1 << (h - 32));
1263 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1264 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1271 static void dc_setfilt(sc)
1272 struct dc_softc *sc;
1274 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1275 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1276 dc_setfilt_21143(sc);
1279 dc_setfilt_asix(sc);
1281 if (DC_IS_ADMTEK(sc))
1282 dc_setfilt_admtek(sc);
1288 * In order to fiddle with the
1289 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1290 * first have to put the transmit and/or receive logic in the idle state.
1292 static void dc_setcfg(sc, media)
1293 struct dc_softc *sc;
1299 if (IFM_SUBTYPE(media) == IFM_NONE)
1302 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1304 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1306 for (i = 0; i < DC_TIMEOUT; i++) {
1307 isr = CSR_READ_4(sc, DC_ISR);
1308 if (isr & DC_ISR_TX_IDLE ||
1309 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1314 if (i == DC_TIMEOUT)
1315 printf("dc%d: failed to force tx and "
1316 "rx to idle state\n", sc->dc_unit);
1319 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1320 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1321 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1322 if (sc->dc_pmode == DC_PMODE_MII) {
1325 if (DC_IS_INTEL(sc)) {
1326 /* there's a write enable bit here that reads as 1 */
1327 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1328 watchdogreg &= ~DC_WDOG_CTLWREN;
1329 watchdogreg |= DC_WDOG_JABBERDIS;
1330 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1332 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1334 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1335 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1336 if (sc->dc_type == DC_TYPE_98713)
1337 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1338 DC_NETCFG_SCRAMBLER));
1339 if (!DC_IS_DAVICOM(sc))
1340 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1341 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1342 if (DC_IS_INTEL(sc))
1343 dc_apply_fixup(sc, IFM_AUTO);
1345 if (DC_IS_PNIC(sc)) {
1346 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1347 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1348 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1350 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1351 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1353 if (DC_IS_INTEL(sc))
1355 (media & IFM_GMASK) == IFM_FDX ?
1356 IFM_100_TX|IFM_FDX : IFM_100_TX);
1360 if (IFM_SUBTYPE(media) == IFM_10_T) {
1361 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1362 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1363 if (sc->dc_pmode == DC_PMODE_MII) {
1366 /* there's a write enable bit here that reads as 1 */
1367 if (DC_IS_INTEL(sc)) {
1368 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1369 watchdogreg &= ~DC_WDOG_CTLWREN;
1370 watchdogreg |= DC_WDOG_JABBERDIS;
1371 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1373 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1375 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1376 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1377 if (sc->dc_type == DC_TYPE_98713)
1378 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1379 if (!DC_IS_DAVICOM(sc))
1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1381 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1382 if (DC_IS_INTEL(sc))
1383 dc_apply_fixup(sc, IFM_AUTO);
1385 if (DC_IS_PNIC(sc)) {
1386 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1387 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1388 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1390 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1391 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1393 if (DC_IS_INTEL(sc)) {
1394 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1395 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1396 if ((media & IFM_GMASK) == IFM_FDX)
1397 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1399 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1400 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1401 DC_CLRBIT(sc, DC_10BTCTRL,
1402 DC_TCTL_AUTONEGENBL);
1404 (media & IFM_GMASK) == IFM_FDX ?
1405 IFM_10_T|IFM_FDX : IFM_10_T);
1412 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1413 * PHY and we want HomePNA mode, set the portsel bit to turn
1414 * on the external MII port.
1416 if (DC_IS_DAVICOM(sc)) {
1417 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1421 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1425 if ((media & IFM_GMASK) == IFM_FDX) {
1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1427 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1428 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1430 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1431 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1432 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1441 static void dc_reset(sc)
1442 struct dc_softc *sc;
1446 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1448 for (i = 0; i < DC_TIMEOUT; i++) {
1450 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1454 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) {
1456 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1460 if (i == DC_TIMEOUT)
1461 printf("dc%d: reset never completed!\n", sc->dc_unit);
1463 /* Wait a little while for the chip to get its brains in order. */
1466 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1467 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1468 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1471 * Bring the SIA out of reset. In some cases, it looks
1472 * like failing to unreset the SIA soon enough gets it
1473 * into a state where it will never come out of reset
1474 * until we reset the whole chip again.
1476 if (DC_IS_INTEL(sc)) {
1477 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1478 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1479 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1485 static struct dc_type *dc_devtype(dev)
1493 while(t->dc_name != NULL) {
1494 if ((pci_get_vendor(dev) == t->dc_vid) &&
1495 (pci_get_device(dev) == t->dc_did)) {
1496 /* Check the PCI revision */
1497 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1498 if (t->dc_did == DC_DEVICEID_98713 &&
1499 rev >= DC_REVISION_98713A)
1501 if (t->dc_did == DC_DEVICEID_98713_CP &&
1502 rev >= DC_REVISION_98713A)
1504 if (t->dc_did == DC_DEVICEID_987x5 &&
1505 rev >= DC_REVISION_98715AEC_C)
1507 if (t->dc_did == DC_DEVICEID_987x5 &&
1508 rev >= DC_REVISION_98725)
1510 if (t->dc_did == DC_DEVICEID_AX88140A &&
1511 rev >= DC_REVISION_88141)
1513 if (t->dc_did == DC_DEVICEID_82C168 &&
1514 rev >= DC_REVISION_82C169)
1516 if (t->dc_did == DC_DEVICEID_DM9102 &&
1517 rev >= DC_REVISION_DM9102A)
1528 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1529 * IDs against our list and return a device name if we find a match.
1530 * We do a little bit of extra work to identify the exact type of
1531 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1532 * but different revision IDs. The same is true for 98715/98715A
1533 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1534 * cases, the exact chip revision affects driver behavior.
1536 static int dc_probe(dev)
1541 t = dc_devtype(dev);
1544 device_set_desc(dev, t->dc_name);
1551 static void dc_acpi(dev)
1557 unit = device_get_unit(dev);
1559 /* Find the location of the capabilities block */
1560 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1562 r = pci_read_config(dev, cptr, 4) & 0xFF;
1565 r = pci_read_config(dev, cptr + 4, 4);
1566 if (r & DC_PSTATE_D3) {
1567 u_int32_t iobase, membase, irq;
1569 /* Save important PCI config data. */
1570 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1571 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1572 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1574 /* Reset the power state. */
1575 printf("dc%d: chip is in D%d power mode "
1576 "-- setting to D0\n", unit, r & DC_PSTATE_D3);
1578 pci_write_config(dev, cptr + 4, r, 4);
1580 /* Restore PCI config data. */
1581 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1582 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1583 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1589 static void dc_apply_fixup(sc, media)
1590 struct dc_softc *sc;
1593 struct dc_mediainfo *m;
1601 if (m->dc_media == media)
1609 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1610 reg = (p[0] | (p[1] << 8)) << 16;
1611 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1614 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1615 reg = (p[0] | (p[1] << 8)) << 16;
1616 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1622 static void dc_decode_leaf_sia(sc, l)
1623 struct dc_softc *sc;
1624 struct dc_eblock_sia *l;
1626 struct dc_mediainfo *m;
1628 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1629 if (l->dc_sia_code == DC_SIA_CODE_10BT)
1630 m->dc_media = IFM_10_T;
1632 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1633 m->dc_media = IFM_10_T|IFM_FDX;
1635 if (l->dc_sia_code == DC_SIA_CODE_10B2)
1636 m->dc_media = IFM_10_2;
1638 if (l->dc_sia_code == DC_SIA_CODE_10B5)
1639 m->dc_media = IFM_10_5;
1642 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1644 m->dc_next = sc->dc_mi;
1647 sc->dc_pmode = DC_PMODE_SIA;
1652 static void dc_decode_leaf_sym(sc, l)
1653 struct dc_softc *sc;
1654 struct dc_eblock_sym *l;
1656 struct dc_mediainfo *m;
1658 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1659 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1660 m->dc_media = IFM_100_TX;
1662 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1663 m->dc_media = IFM_100_TX|IFM_FDX;
1666 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1668 m->dc_next = sc->dc_mi;
1671 sc->dc_pmode = DC_PMODE_SYM;
1676 static void dc_decode_leaf_mii(sc, l)
1677 struct dc_softc *sc;
1678 struct dc_eblock_mii *l;
1681 struct dc_mediainfo *m;
1683 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1684 /* We abuse IFM_AUTO to represent MII. */
1685 m->dc_media = IFM_AUTO;
1686 m->dc_gp_len = l->dc_gpr_len;
1689 p += sizeof(struct dc_eblock_mii);
1691 p += 2 * l->dc_gpr_len;
1692 m->dc_reset_len = *p;
1694 m->dc_reset_ptr = p;
1696 m->dc_next = sc->dc_mi;
1702 static void dc_read_srom(sc, bits)
1703 struct dc_softc *sc;
1709 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT);
1710 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1713 static void dc_parse_21143_srom(sc)
1714 struct dc_softc *sc;
1716 struct dc_leaf_hdr *lhdr;
1717 struct dc_eblock_hdr *hdr;
1723 loff = sc->dc_srom[27];
1724 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1727 ptr += sizeof(struct dc_leaf_hdr) - 1;
1729 * Look if we got a MII media block.
1731 for (i = 0; i < lhdr->dc_mcnt; i++) {
1732 hdr = (struct dc_eblock_hdr *)ptr;
1733 if (hdr->dc_type == DC_EBLOCK_MII)
1736 ptr += (hdr->dc_len & 0x7F);
1741 * Do the same thing again. Only use SIA and SYM media
1742 * blocks if no MII media block is available.
1745 ptr += sizeof(struct dc_leaf_hdr) - 1;
1746 for (i = 0; i < lhdr->dc_mcnt; i++) {
1747 hdr = (struct dc_eblock_hdr *)ptr;
1748 switch(hdr->dc_type) {
1750 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1754 dc_decode_leaf_sia(sc,
1755 (struct dc_eblock_sia *)hdr);
1759 dc_decode_leaf_sym(sc,
1760 (struct dc_eblock_sym *)hdr);
1763 /* Don't care. Yet. */
1766 ptr += (hdr->dc_len & 0x7F);
1774 * Attach the interface. Allocate softc structures, do ifmedia
1775 * setup and ethernet/BPF attach.
1777 static int dc_attach(dev)
1781 u_char eaddr[ETHER_ADDR_LEN];
1783 struct dc_softc *sc;
1786 int unit, error = 0, rid, mac_offset;
1790 sc = device_get_softc(dev);
1791 unit = device_get_unit(dev);
1792 bzero(sc, sizeof(struct dc_softc));
1793 callout_init(&sc->dc_stat_timer);
1796 * Handle power management nonsense.
1801 * Map control/status registers.
1803 command = pci_read_config(dev, PCIR_COMMAND, 4);
1804 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1805 pci_write_config(dev, PCIR_COMMAND, command, 4);
1806 command = pci_read_config(dev, PCIR_COMMAND, 4);
1808 #ifdef DC_USEIOSPACE
1809 if (!(command & PCIM_CMD_PORTEN)) {
1810 printf("dc%d: failed to enable I/O ports!\n", unit);
1815 if (!(command & PCIM_CMD_MEMEN)) {
1816 printf("dc%d: failed to enable memory mapping!\n", unit);
1823 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
1824 0, ~0, 1, RF_ACTIVE);
1826 if (sc->dc_res == NULL) {
1827 printf("dc%d: couldn't map ports/memory\n", unit);
1832 sc->dc_btag = rman_get_bustag(sc->dc_res);
1833 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1835 /* Allocate interrupt */
1837 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1838 RF_SHAREABLE | RF_ACTIVE);
1840 if (sc->dc_irq == NULL) {
1841 printf("dc%d: couldn't map interrupt\n", unit);
1842 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1847 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
1848 dc_intr, sc, &sc->dc_intrhand);
1851 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
1852 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1853 printf("dc%d: couldn't set up irq\n", unit);
1857 /* Need this info to decide on a chip type. */
1858 sc->dc_info = dc_devtype(dev);
1859 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
1861 /* Get the eeprom width, but PNIC has diff eeprom */
1862 if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
1863 dc_eeprom_width(sc);
1865 switch(sc->dc_info->dc_did) {
1866 case DC_DEVICEID_21143:
1867 sc->dc_type = DC_TYPE_21143;
1868 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1869 sc->dc_flags |= DC_REDUCED_MII_POLL;
1870 /* Save EEPROM contents so we can parse them later. */
1871 dc_read_srom(sc, sc->dc_romwidth);
1873 case DC_DEVICEID_DM9009:
1874 case DC_DEVICEID_DM9100:
1875 case DC_DEVICEID_DM9102:
1876 sc->dc_type = DC_TYPE_DM9102;
1877 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1878 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1879 sc->dc_pmode = DC_PMODE_MII;
1880 /* Increase the latency timer value. */
1881 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1882 command &= 0xFFFF00FF;
1883 command |= 0x00008000;
1884 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1886 case DC_DEVICEID_AL981:
1887 sc->dc_type = DC_TYPE_AL981;
1888 sc->dc_flags |= DC_TX_USE_TX_INTR;
1889 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1890 sc->dc_pmode = DC_PMODE_MII;
1891 dc_read_srom(sc, sc->dc_romwidth);
1893 case DC_DEVICEID_AN985:
1894 case DC_DEVICEID_EN2242:
1895 case DC_DEVICEID_3CSOHOB:
1896 sc->dc_type = DC_TYPE_AN985;
1897 sc->dc_flags |= DC_64BIT_HASH;
1898 sc->dc_flags |= DC_TX_USE_TX_INTR;
1899 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1900 sc->dc_pmode = DC_PMODE_MII;
1901 dc_read_srom(sc, sc->dc_romwidth);
1903 case DC_DEVICEID_98713:
1904 case DC_DEVICEID_98713_CP:
1905 if (revision < DC_REVISION_98713A) {
1906 sc->dc_type = DC_TYPE_98713;
1908 if (revision >= DC_REVISION_98713A) {
1909 sc->dc_type = DC_TYPE_98713A;
1910 sc->dc_flags |= DC_21143_NWAY;
1912 sc->dc_flags |= DC_REDUCED_MII_POLL;
1913 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1915 case DC_DEVICEID_987x5:
1916 case DC_DEVICEID_EN1217:
1918 * Macronix MX98715AEC-C/D/E parts have only a
1919 * 128-bit hash table. We need to deal with these
1920 * in the same manner as the PNIC II so that we
1921 * get the right number of bits out of the
1924 if (revision >= DC_REVISION_98715AEC_C &&
1925 revision < DC_REVISION_98725)
1926 sc->dc_flags |= DC_128BIT_HASH;
1927 sc->dc_type = DC_TYPE_987x5;
1928 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1929 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1931 case DC_DEVICEID_98727:
1932 sc->dc_type = DC_TYPE_987x5;
1933 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1934 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1936 case DC_DEVICEID_82C115:
1937 sc->dc_type = DC_TYPE_PNICII;
1938 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1939 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1941 case DC_DEVICEID_82C168:
1942 sc->dc_type = DC_TYPE_PNIC;
1943 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1944 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1945 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1946 if (revision < DC_REVISION_82C169)
1947 sc->dc_pmode = DC_PMODE_SYM;
1949 case DC_DEVICEID_AX88140A:
1950 sc->dc_type = DC_TYPE_ASIX;
1951 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1952 sc->dc_flags |= DC_REDUCED_MII_POLL;
1953 sc->dc_pmode = DC_PMODE_MII;
1955 case DC_DEVICEID_RS7112:
1956 sc->dc_type = DC_TYPE_CONEXANT;
1957 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1958 sc->dc_flags |= DC_REDUCED_MII_POLL;
1959 sc->dc_pmode = DC_PMODE_MII;
1960 dc_read_srom(sc, sc->dc_romwidth);
1963 printf("dc%d: unknown device: %x\n", sc->dc_unit,
1964 sc->dc_info->dc_did);
1968 /* Save the cache line size. */
1969 if (DC_IS_DAVICOM(sc))
1970 sc->dc_cachesize = 0;
1972 sc->dc_cachesize = pci_read_config(dev,
1973 DC_PCI_CFLT, 4) & 0xFF;
1975 /* Reset the adapter. */
1978 /* Take 21143 out of snooze mode */
1979 if (DC_IS_INTEL(sc)) {
1980 command = pci_read_config(dev, DC_PCI_CFDD, 4);
1981 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
1982 pci_write_config(dev, DC_PCI_CFDD, command, 4);
1986 * Try to learn something about the supported media.
1987 * We know that ASIX and ADMtek and Davicom devices
1988 * will *always* be using MII media, so that's a no-brainer.
1989 * The tricky ones are the Macronix/PNIC II and the
1992 if (DC_IS_INTEL(sc))
1993 dc_parse_21143_srom(sc);
1994 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
1995 if (sc->dc_type == DC_TYPE_98713)
1996 sc->dc_pmode = DC_PMODE_MII;
1998 sc->dc_pmode = DC_PMODE_SYM;
1999 } else if (!sc->dc_pmode)
2000 sc->dc_pmode = DC_PMODE_MII;
2003 * Get station address from the EEPROM.
2005 switch(sc->dc_type) {
2007 case DC_TYPE_98713A:
2009 case DC_TYPE_PNICII:
2010 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2011 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2012 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2015 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2017 case DC_TYPE_DM9102:
2020 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2024 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2026 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2028 case DC_TYPE_CONEXANT:
2029 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2032 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2038 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2039 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
2041 if (sc->dc_ldata == NULL) {
2042 printf("dc%d: no memory for list buffers!\n", unit);
2043 if (sc->dc_pnic_rx_buf != NULL)
2044 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2045 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2046 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2047 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2052 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2054 ifp = &sc->arpcom.ac_if;
2056 if_initname(ifp, "dc", unit);
2057 ifp->if_mtu = ETHERMTU;
2058 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2059 ifp->if_ioctl = dc_ioctl;
2060 ifp->if_start = dc_start;
2061 ifp->if_watchdog = dc_watchdog;
2062 ifp->if_init = dc_init;
2063 ifp->if_baudrate = 10000000;
2064 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2065 ifq_set_ready(&ifp->if_snd);
2068 * Do MII setup. If this is a 21143, check for a PHY on the
2069 * MII bus after applying any necessary fixups to twiddle the
2070 * GPIO bits. If we don't end up finding a PHY, restore the
2071 * old selection (SIA only or SIA/SYM) and attach the dcphy
2074 if (DC_IS_INTEL(sc)) {
2075 dc_apply_fixup(sc, IFM_AUTO);
2077 sc->dc_pmode = DC_PMODE_MII;
2080 error = mii_phy_probe(dev, &sc->dc_miibus,
2081 dc_ifmedia_upd, dc_ifmedia_sts);
2083 if (error && DC_IS_INTEL(sc)) {
2085 if (sc->dc_pmode != DC_PMODE_SIA)
2086 sc->dc_pmode = DC_PMODE_SYM;
2087 sc->dc_flags |= DC_21143_NWAY;
2088 mii_phy_probe(dev, &sc->dc_miibus,
2089 dc_ifmedia_upd, dc_ifmedia_sts);
2091 * For non-MII cards, we need to have the 21143
2092 * drive the LEDs. Except there are some systems
2093 * like the NEC VersaPro NoteBook PC which have no
2094 * LEDs, and twiddling these bits has adverse effects
2095 * on them. (I.e. you suddenly can't get a link.)
2097 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2098 sc->dc_flags |= DC_TULIP_LEDS;
2103 printf("dc%d: MII without any PHY!\n", sc->dc_unit);
2104 contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2106 if (sc->dc_pnic_rx_buf != NULL)
2107 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2108 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2109 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2110 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2116 * Call MI attach routine.
2118 ether_ifattach(ifp, eaddr);
2120 if (DC_IS_ADMTEK(sc)) {
2122 * Set automatic TX underrun recovery for the ADMtek chips
2124 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2128 * Tell the upper layer(s) we support long frames.
2130 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2133 sc->dc_srm_media = 0;
2135 /* Remember the SRM console media setting */
2136 if (DC_IS_INTEL(sc)) {
2137 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2138 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2139 switch ((command >> 8) & 0xff) {
2141 sc->dc_srm_media = IFM_10_T;
2144 sc->dc_srm_media = IFM_10_T | IFM_FDX;
2147 sc->dc_srm_media = IFM_100_TX;
2150 sc->dc_srm_media = IFM_100_TX | IFM_FDX;
2153 if (sc->dc_srm_media)
2154 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER;
2165 static int dc_detach(dev)
2168 struct dc_softc *sc;
2171 struct dc_mediainfo *m;
2175 sc = device_get_softc(dev);
2176 ifp = &sc->arpcom.ac_if;
2179 ether_ifdetach(ifp);
2181 bus_generic_detach(dev);
2182 device_delete_child(dev, sc->dc_miibus);
2184 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2185 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2186 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2188 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2189 if (sc->dc_pnic_rx_buf != NULL)
2190 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2192 while(sc->dc_mi != NULL) {
2193 m = sc->dc_mi->dc_next;
2194 free(sc->dc_mi, M_DEVBUF);
2197 free(sc->dc_srom, M_DEVBUF);
2205 * Initialize the transmit descriptors.
2207 static int dc_list_tx_init(sc)
2208 struct dc_softc *sc;
2210 struct dc_chain_data *cd;
2211 struct dc_list_data *ld;
2216 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2217 if (i == (DC_TX_LIST_CNT - 1)) {
2218 ld->dc_tx_list[i].dc_next =
2219 vtophys(&ld->dc_tx_list[0]);
2221 ld->dc_tx_list[i].dc_next =
2222 vtophys(&ld->dc_tx_list[i + 1]);
2224 cd->dc_tx_chain[i] = NULL;
2225 ld->dc_tx_list[i].dc_data = 0;
2226 ld->dc_tx_list[i].dc_ctl = 0;
2229 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2236 * Initialize the RX descriptors and allocate mbufs for them. Note that
2237 * we arrange the descriptors in a closed ring, so that the last descriptor
2238 * points back to the first.
2240 static int dc_list_rx_init(sc)
2241 struct dc_softc *sc;
2243 struct dc_chain_data *cd;
2244 struct dc_list_data *ld;
2250 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2251 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2253 if (i == (DC_RX_LIST_CNT - 1)) {
2254 ld->dc_rx_list[i].dc_next =
2255 vtophys(&ld->dc_rx_list[0]);
2257 ld->dc_rx_list[i].dc_next =
2258 vtophys(&ld->dc_rx_list[i + 1]);
2268 * Initialize an RX descriptor and attach an MBUF cluster.
2270 static int dc_newbuf(sc, i, m)
2271 struct dc_softc *sc;
2275 struct mbuf *m_new = NULL;
2278 c = &sc->dc_ldata->dc_rx_list[i];
2281 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
2285 MCLGET(m_new, MB_DONTWAIT);
2286 if (!(m_new->m_flags & M_EXT)) {
2290 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2293 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2294 m_new->m_data = m_new->m_ext.ext_buf;
2297 m_adj(m_new, sizeof(u_int64_t));
2300 * If this is a PNIC chip, zero the buffer. This is part
2301 * of the workaround for the receive bug in the 82c168 and
2304 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2305 bzero((char *)mtod(m_new, char *), m_new->m_len);
2307 sc->dc_cdata.dc_rx_chain[i] = m_new;
2308 c->dc_data = vtophys(mtod(m_new, caddr_t));
2309 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2310 c->dc_status = DC_RXSTAT_OWN;
2317 * The PNIC chip has a terrible bug in it that manifests itself during
2318 * periods of heavy activity. The exact mode of failure if difficult to
2319 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2320 * will happen on slow machines. The bug is that sometimes instead of
2321 * uploading one complete frame during reception, it uploads what looks
2322 * like the entire contents of its FIFO memory. The frame we want is at
2323 * the end of the whole mess, but we never know exactly how much data has
2324 * been uploaded, so salvaging the frame is hard.
2326 * There is only one way to do it reliably, and it's disgusting.
2327 * Here's what we know:
2329 * - We know there will always be somewhere between one and three extra
2330 * descriptors uploaded.
2332 * - We know the desired received frame will always be at the end of the
2333 * total data upload.
2335 * - We know the size of the desired received frame because it will be
2336 * provided in the length field of the status word in the last descriptor.
2338 * Here's what we do:
2340 * - When we allocate buffers for the receive ring, we bzero() them.
2341 * This means that we know that the buffer contents should be all
2342 * zeros, except for data uploaded by the chip.
2344 * - We also force the PNIC chip to upload frames that include the
2345 * ethernet CRC at the end.
2347 * - We gather all of the bogus frame data into a single buffer.
2349 * - We then position a pointer at the end of this buffer and scan
2350 * backwards until we encounter the first non-zero byte of data.
2351 * This is the end of the received frame. We know we will encounter
2352 * some data at the end of the frame because the CRC will always be
2353 * there, so even if the sender transmits a packet of all zeros,
2354 * we won't be fooled.
2356 * - We know the size of the actual received frame, so we subtract
2357 * that value from the current pointer location. This brings us
2358 * to the start of the actual received packet.
2360 * - We copy this into an mbuf and pass it on, along with the actual
2363 * The performance hit is tremendous, but it beats dropping frames all
2367 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2368 static void dc_pnic_rx_bug_war(sc, idx)
2369 struct dc_softc *sc;
2372 struct dc_desc *cur_rx;
2373 struct dc_desc *c = NULL;
2374 struct mbuf *m = NULL;
2377 u_int32_t rxstat = 0;
2379 i = sc->dc_pnic_rx_bug_save;
2380 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2381 ptr = sc->dc_pnic_rx_buf;
2382 bzero(ptr, DC_RXLEN * 5);
2384 /* Copy all the bytes from the bogus buffers. */
2386 c = &sc->dc_ldata->dc_rx_list[i];
2387 rxstat = c->dc_status;
2388 m = sc->dc_cdata.dc_rx_chain[i];
2389 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2391 /* If this is the last buffer, break out. */
2392 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2394 dc_newbuf(sc, i, m);
2395 DC_INC(i, DC_RX_LIST_CNT);
2398 /* Find the length of the actual receive frame. */
2399 total_len = DC_RXBYTES(rxstat);
2401 /* Scan backwards until we hit a non-zero byte. */
2406 if ((uintptr_t)(ptr) & 0x3)
2409 /* Now find the start of the frame. */
2411 if (ptr < sc->dc_pnic_rx_buf)
2412 ptr = sc->dc_pnic_rx_buf;
2415 * Now copy the salvaged frame to the last mbuf and fake up
2416 * the status word to make it look like a successful
2419 dc_newbuf(sc, i, m);
2420 bcopy(ptr, mtod(m, char *), total_len);
2421 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2427 * This routine searches the RX ring for dirty descriptors in the
2428 * event that the rxeof routine falls out of sync with the chip's
2429 * current descriptor pointer. This may happen sometimes as a result
2430 * of a "no RX buffer available" condition that happens when the chip
2431 * consumes all of the RX buffers before the driver has a chance to
2432 * process the RX ring. This routine may need to be called more than
2433 * once to bring the driver back in sync with the chip, however we
2434 * should still be getting RX DONE interrupts to drive the search
2435 * for new packets in the RX ring, so we should catch up eventually.
2437 static int dc_rx_resync(sc)
2438 struct dc_softc *sc;
2441 struct dc_desc *cur_rx;
2443 pos = sc->dc_cdata.dc_rx_prod;
2445 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2446 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2447 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2449 DC_INC(pos, DC_RX_LIST_CNT);
2452 /* If the ring really is empty, then just return. */
2453 if (i == DC_RX_LIST_CNT)
2456 /* We've fallen behing the chip: catch it. */
2457 sc->dc_cdata.dc_rx_prod = pos;
2463 * A frame has been uploaded: pass the resulting mbuf chain up to
2464 * the higher level protocols.
2466 static void dc_rxeof(sc)
2467 struct dc_softc *sc;
2471 struct dc_desc *cur_rx;
2472 int i, total_len = 0;
2475 ifp = &sc->arpcom.ac_if;
2476 i = sc->dc_cdata.dc_rx_prod;
2478 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2480 #ifdef DEVICE_POLLING
2481 if (ifp->if_flags & IFF_POLLING) {
2482 if (sc->rxcycles <= 0)
2486 #endif /* DEVICE_POLLING */
2487 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2488 rxstat = cur_rx->dc_status;
2489 m = sc->dc_cdata.dc_rx_chain[i];
2490 total_len = DC_RXBYTES(rxstat);
2492 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2493 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2494 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2495 sc->dc_pnic_rx_bug_save = i;
2496 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2497 DC_INC(i, DC_RX_LIST_CNT);
2500 dc_pnic_rx_bug_war(sc, i);
2501 rxstat = cur_rx->dc_status;
2502 total_len = DC_RXBYTES(rxstat);
2506 sc->dc_cdata.dc_rx_chain[i] = NULL;
2509 * If an error occurs, update stats, clear the
2510 * status word and leave the mbuf cluster in place:
2511 * it should simply get re-used next time this descriptor
2512 * comes up in the ring. However, don't report long
2513 * frames as errors since they could be vlans
2515 if ((rxstat & DC_RXSTAT_RXERR)){
2516 if (!(rxstat & DC_RXSTAT_GIANT) ||
2517 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2518 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2519 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2521 if (rxstat & DC_RXSTAT_COLLSEEN)
2522 ifp->if_collisions++;
2523 dc_newbuf(sc, i, m);
2524 if (rxstat & DC_RXSTAT_CRCERR) {
2525 DC_INC(i, DC_RX_LIST_CNT);
2534 /* No errors; receive the packet. */
2535 total_len -= ETHER_CRC_LEN;
2539 * On the x86 we do not have alignment problems, so try to
2540 * allocate a new buffer for the receive ring, and pass up
2541 * the one where the packet is already, saving the expensive
2542 * copy done in m_devget().
2543 * If we are on an architecture with alignment problems, or
2544 * if the allocation fails, then use m_devget and leave the
2545 * existing buffer in the receive ring.
2547 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2548 m->m_pkthdr.rcvif = ifp;
2549 m->m_pkthdr.len = m->m_len = total_len;
2550 DC_INC(i, DC_RX_LIST_CNT);
2556 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2557 total_len + ETHER_ALIGN, 0, ifp, NULL);
2558 dc_newbuf(sc, i, m);
2559 DC_INC(i, DC_RX_LIST_CNT);
2564 m_adj(m0, ETHER_ALIGN);
2569 (*ifp->if_input)(ifp, m);
2572 sc->dc_cdata.dc_rx_prod = i;
2576 * A frame was downloaded to the chip. It's safe for us to clean up
2582 struct dc_softc *sc;
2584 struct dc_desc *cur_tx = NULL;
2588 ifp = &sc->arpcom.ac_if;
2591 * Go through our tx list and free mbufs for those
2592 * frames that have been transmitted.
2594 idx = sc->dc_cdata.dc_tx_cons;
2595 while(idx != sc->dc_cdata.dc_tx_prod) {
2598 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2599 txstat = cur_tx->dc_status;
2601 if (txstat & DC_TXSTAT_OWN)
2604 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2605 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2606 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2608 * Yes, the PNIC is so brain damaged
2609 * that it will sometimes generate a TX
2610 * underrun error while DMAing the RX
2611 * filter setup frame. If we detect this,
2612 * we have to send the setup frame again,
2613 * or else the filter won't be programmed
2616 if (DC_IS_PNIC(sc)) {
2617 if (txstat & DC_TXSTAT_ERRSUM)
2620 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2622 sc->dc_cdata.dc_tx_cnt--;
2623 DC_INC(idx, DC_TX_LIST_CNT);
2627 if (DC_IS_CONEXANT(sc)) {
2629 * For some reason Conexant chips like
2630 * setting the CARRLOST flag even when
2631 * the carrier is there. In CURRENT we
2632 * have the same problem for Xircom
2635 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2636 sc->dc_pmode == DC_PMODE_MII &&
2637 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2638 DC_TXSTAT_NOCARRIER)))
2639 txstat &= ~DC_TXSTAT_ERRSUM;
2641 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2642 sc->dc_pmode == DC_PMODE_MII &&
2643 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2644 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2645 txstat &= ~DC_TXSTAT_ERRSUM;
2648 if (txstat & DC_TXSTAT_ERRSUM) {
2650 if (txstat & DC_TXSTAT_EXCESSCOLL)
2651 ifp->if_collisions++;
2652 if (txstat & DC_TXSTAT_LATECOLL)
2653 ifp->if_collisions++;
2654 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2660 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2663 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2664 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2665 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2668 sc->dc_cdata.dc_tx_cnt--;
2669 DC_INC(idx, DC_TX_LIST_CNT);
2672 if (idx != sc->dc_cdata.dc_tx_cons) {
2673 /* some buffers have been freed */
2674 sc->dc_cdata.dc_tx_cons = idx;
2675 ifp->if_flags &= ~IFF_OACTIVE;
2677 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2682 static void dc_tick(xsc)
2685 struct dc_softc *sc;
2686 struct mii_data *mii;
2694 ifp = &sc->arpcom.ac_if;
2695 mii = device_get_softc(sc->dc_miibus);
2697 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2698 if (sc->dc_flags & DC_21143_NWAY) {
2699 r = CSR_READ_4(sc, DC_10BTSTAT);
2700 if (IFM_SUBTYPE(mii->mii_media_active) ==
2701 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2705 if (IFM_SUBTYPE(mii->mii_media_active) ==
2706 IFM_10_T && (r & DC_TSTAT_LS10)) {
2710 if (sc->dc_link == 0)
2713 r = CSR_READ_4(sc, DC_ISR);
2714 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2715 sc->dc_cdata.dc_tx_cnt == 0)
2717 if (!(mii->mii_media_status & IFM_ACTIVE))
2724 * When the init routine completes, we expect to be able to send
2725 * packets right away, and in fact the network code will send a
2726 * gratuitous ARP the moment the init routine marks the interface
2727 * as running. However, even though the MAC may have been initialized,
2728 * there may be a delay of a few seconds before the PHY completes
2729 * autonegotiation and the link is brought up. Any transmissions
2730 * made during that delay will be lost. Dealing with this is tricky:
2731 * we can't just pause in the init routine while waiting for the
2732 * PHY to come ready since that would bring the whole system to
2733 * a screeching halt for several seconds.
2735 * What we do here is prevent the TX start routine from sending
2736 * any packets until a link has been established. After the
2737 * interface has been initialized, the tick routine will poll
2738 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2739 * that time, packets will stay in the send queue, and once the
2740 * link comes up, they will be flushed out to the wire.
2744 if (mii->mii_media_status & IFM_ACTIVE &&
2745 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2747 if (!ifq_is_empty(&ifp->if_snd))
2752 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2753 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2755 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2763 * A transmit underrun has occurred. Back off the transmit threshold,
2764 * or switch to store and forward mode if we have to.
2766 static void dc_tx_underrun(sc)
2767 struct dc_softc *sc;
2772 if (DC_IS_DAVICOM(sc))
2775 if (DC_IS_INTEL(sc)) {
2777 * The real 21143 requires that the transmitter be idle
2778 * in order to change the transmit threshold or store
2779 * and forward state.
2781 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2783 for (i = 0; i < DC_TIMEOUT; i++) {
2784 isr = CSR_READ_4(sc, DC_ISR);
2785 if (isr & DC_ISR_TX_IDLE)
2789 if (i == DC_TIMEOUT) {
2790 printf("dc%d: failed to force tx to idle state\n",
2796 printf("dc%d: TX underrun -- ", sc->dc_unit);
2797 sc->dc_txthresh += DC_TXTHRESH_INC;
2798 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2799 printf("using store and forward mode\n");
2800 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2802 printf("increasing TX threshold\n");
2803 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2804 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2807 if (DC_IS_INTEL(sc))
2808 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2813 #ifdef DEVICE_POLLING
2814 static poll_handler_t dc_poll;
2817 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2819 struct dc_softc *sc = ifp->if_softc;
2821 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
2822 /* Re-enable interrupts. */
2823 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2826 sc->rxcycles = count;
2829 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2832 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2835 status = CSR_READ_4(sc, DC_ISR);
2836 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2837 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2841 /* ack what we have */
2842 CSR_WRITE_4(sc, DC_ISR, status);
2844 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2845 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2846 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2848 if (dc_rx_resync(sc))
2851 /* restart transmit unit if necessary */
2852 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2853 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2855 if (status & DC_ISR_TX_UNDERRUN)
2858 if (status & DC_ISR_BUS_ERR) {
2859 printf("dc_poll: dc%d bus error\n", sc->dc_unit);
2865 #endif /* DEVICE_POLLING */
2867 static void dc_intr(arg)
2870 struct dc_softc *sc;
2876 if (sc->suspended) {
2880 ifp = &sc->arpcom.ac_if;
2882 #ifdef DEVICE_POLLING
2883 if (ifp->if_flags & IFF_POLLING)
2885 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
2886 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2889 #endif /* DEVICE_POLLING */
2891 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2894 /* Suppress unwanted interrupts */
2895 if (!(ifp->if_flags & IFF_UP)) {
2896 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2901 /* Disable interrupts. */
2902 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2904 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
2906 CSR_WRITE_4(sc, DC_ISR, status);
2908 if (status & DC_ISR_RX_OK) {
2910 curpkts = ifp->if_ipackets;
2912 if (curpkts == ifp->if_ipackets) {
2913 while(dc_rx_resync(sc))
2918 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2921 if (status & DC_ISR_TX_IDLE) {
2923 if (sc->dc_cdata.dc_tx_cnt) {
2924 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2925 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2929 if (status & DC_ISR_TX_UNDERRUN)
2932 if ((status & DC_ISR_RX_WATDOGTIMEO)
2933 || (status & DC_ISR_RX_NOBUF)) {
2935 curpkts = ifp->if_ipackets;
2937 if (curpkts == ifp->if_ipackets) {
2938 while(dc_rx_resync(sc))
2943 if (status & DC_ISR_BUS_ERR) {
2949 /* Re-enable interrupts. */
2950 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2952 if (!ifq_is_empty(&ifp->if_snd))
2959 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2960 * pointers to the fragment pointers.
2962 static int dc_encap(sc, m_head, txidx)
2963 struct dc_softc *sc;
2964 struct mbuf *m_head;
2967 struct dc_desc *f = NULL;
2969 int frag, cur, cnt = 0;
2972 * Start packing the mbufs in this chain into
2973 * the fragment pointers. Stop when we run out
2974 * of fragments or hit the end of the mbuf chain.
2977 cur = frag = *txidx;
2979 for (m = m_head; m != NULL; m = m->m_next) {
2980 if (m->m_len != 0) {
2981 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2982 if (*txidx != sc->dc_cdata.dc_tx_prod &&
2983 frag == (DC_TX_LIST_CNT - 1))
2986 if ((DC_TX_LIST_CNT -
2987 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
2990 f = &sc->dc_ldata->dc_tx_list[frag];
2991 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
2994 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
2996 f->dc_status = DC_TXSTAT_OWN;
2997 f->dc_data = vtophys(mtod(m, vm_offset_t));
2999 DC_INC(frag, DC_TX_LIST_CNT);
3007 sc->dc_cdata.dc_tx_cnt += cnt;
3008 sc->dc_cdata.dc_tx_chain[cur] = m_head;
3009 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
3010 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3011 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
3012 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3013 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3014 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3015 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3016 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3023 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3024 * to the mbuf data regions directly in the transmit lists. We also save a
3025 * copy of the pointers since the transmit list fragment pointers are
3026 * physical addresses.
3029 static void dc_start(ifp)
3032 struct dc_softc *sc;
3033 struct mbuf *m_head = NULL, *m_new;
3034 int did_defrag, idx;
3041 if (ifp->if_flags & IFF_OACTIVE)
3044 idx = sc->dc_cdata.dc_tx_prod;
3046 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3048 m_head = ifq_poll(&ifp->if_snd);
3052 if (sc->dc_flags & DC_TX_COALESCE &&
3053 m_head->m_next != NULL) {
3055 * Check first if coalescing allows us to queue
3056 * the packet. We don't want to loose it if
3057 * the TX queue is full.
3059 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3060 idx != sc->dc_cdata.dc_tx_prod &&
3061 idx == (DC_TX_LIST_CNT - 1)) {
3062 ifp->if_flags |= IFF_OACTIVE;
3065 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
3066 ifp->if_flags |= IFF_OACTIVE;
3070 /* only coalesce if have >1 mbufs */
3071 m_new = m_defrag_nofree(m_head, MB_DONTWAIT);
3072 if (m_new == NULL) {
3073 ifp->if_flags |= IFF_OACTIVE;
3081 if (dc_encap(sc, m_head, &idx)) {
3084 m_new = ifq_dequeue(&ifp->if_snd);
3087 ifp->if_flags |= IFF_OACTIVE;
3091 m_new = ifq_dequeue(&ifp->if_snd);
3096 * If there's a BPF listener, bounce a copy of this frame
3099 BPF_MTAP(ifp, m_head);
3101 if (sc->dc_flags & DC_TX_ONE) {
3102 ifp->if_flags |= IFF_OACTIVE;
3108 sc->dc_cdata.dc_tx_prod = idx;
3109 if (!(sc->dc_flags & DC_TX_POLL))
3110 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3113 * Set a timeout in case the chip goes out to lunch.
3120 static void dc_init(xsc)
3123 struct dc_softc *sc = xsc;
3124 struct ifnet *ifp = &sc->arpcom.ac_if;
3125 struct mii_data *mii;
3130 mii = device_get_softc(sc->dc_miibus);
3133 * Cancel pending I/O and free all RX/TX buffers.
3139 * Set cache alignment and burst length.
3141 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3142 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3144 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3146 * Evenly share the bus between receive and transmit process.
3148 if (DC_IS_INTEL(sc))
3149 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3150 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3151 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3153 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3155 if (sc->dc_flags & DC_TX_POLL)
3156 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3157 switch(sc->dc_cachesize) {
3159 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3162 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3165 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3169 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3173 if (sc->dc_flags & DC_TX_STORENFWD)
3174 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3176 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3177 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3179 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3180 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3185 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3187 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3189 * The app notes for the 98713 and 98715A say that
3190 * in order to have the chips operate properly, a magic
3191 * number must be written to CSR16. Macronix does not
3192 * document the meaning of these bits so there's no way
3193 * to know exactly what they do. The 98713 has a magic
3194 * number all its own; the rest all use a different one.
3196 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3197 if (sc->dc_type == DC_TYPE_98713)
3198 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3200 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3203 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3204 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3206 /* Init circular RX list. */
3207 if (dc_list_rx_init(sc) == ENOBUFS) {
3208 printf("dc%d: initialization failed: no "
3209 "memory for rx buffers\n", sc->dc_unit);
3216 * Init tx descriptors.
3218 dc_list_tx_init(sc);
3221 * Load the address of the RX list.
3223 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3224 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3227 * Enable interrupts.
3229 #ifdef DEVICE_POLLING
3231 * ... but only if we are not polling, and make sure they are off in
3232 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3235 if (ifp->if_flags & IFF_POLLING)
3236 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3239 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3240 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3242 /* Enable transmitter. */
3243 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3246 * If this is an Intel 21143 and we're not using the
3247 * MII port, program the LED control pins so we get
3248 * link and activity indications.
3250 if (sc->dc_flags & DC_TULIP_LEDS) {
3251 CSR_WRITE_4(sc, DC_WATCHDOG,
3252 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3253 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3257 * Load the RX/multicast filter. We do this sort of late
3258 * because the filter programming scheme on the 21143 and
3259 * some clones requires DMAing a setup frame via the TX
3260 * engine, and we need the transmitter enabled for that.
3264 /* Enable receiver. */
3265 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3266 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3269 dc_setcfg(sc, sc->dc_if_media);
3271 ifp->if_flags |= IFF_RUNNING;
3272 ifp->if_flags &= ~IFF_OACTIVE;
3276 /* Don't start the ticker if this is a homePNA link. */
3277 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3280 if (sc->dc_flags & DC_21143_NWAY)
3281 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3283 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3287 if(sc->dc_srm_media) {
3290 ifr.ifr_media = sc->dc_srm_media;
3291 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3292 sc->dc_srm_media = 0;
3299 * Set media options.
3301 static int dc_ifmedia_upd(ifp)
3304 struct dc_softc *sc;
3305 struct mii_data *mii;
3306 struct ifmedia *ifm;
3309 mii = device_get_softc(sc->dc_miibus);
3311 ifm = &mii->mii_media;
3313 if (DC_IS_DAVICOM(sc) &&
3314 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3315 dc_setcfg(sc, ifm->ifm_media);
3323 * Report current media status.
3325 static void dc_ifmedia_sts(ifp, ifmr)
3327 struct ifmediareq *ifmr;
3329 struct dc_softc *sc;
3330 struct mii_data *mii;
3331 struct ifmedia *ifm;
3334 mii = device_get_softc(sc->dc_miibus);
3336 ifm = &mii->mii_media;
3337 if (DC_IS_DAVICOM(sc)) {
3338 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3339 ifmr->ifm_active = ifm->ifm_media;
3340 ifmr->ifm_status = 0;
3344 ifmr->ifm_active = mii->mii_media_active;
3345 ifmr->ifm_status = mii->mii_media_status;
3350 static int dc_ioctl(ifp, command, data, cr)
3356 struct dc_softc *sc = ifp->if_softc;
3357 struct ifreq *ifr = (struct ifreq *) data;
3358 struct mii_data *mii;
3367 error = ether_ioctl(ifp, command, data);
3370 if (ifp->if_flags & IFF_UP) {
3371 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3372 (IFF_PROMISC | IFF_ALLMULTI);
3373 if (ifp->if_flags & IFF_RUNNING) {
3377 sc->dc_txthresh = 0;
3381 if (ifp->if_flags & IFF_RUNNING)
3384 sc->dc_if_flags = ifp->if_flags;
3394 mii = device_get_softc(sc->dc_miibus);
3395 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3397 if (sc->dc_srm_media)
3398 sc->dc_srm_media = 0;
3411 static void dc_watchdog(ifp)
3414 struct dc_softc *sc;
3419 printf("dc%d: watchdog timeout\n", sc->dc_unit);
3425 if (!ifq_is_empty(&ifp->if_snd))
3432 * Stop the adapter and free any mbufs allocated to the
3435 static void dc_stop(sc)
3436 struct dc_softc *sc;
3441 ifp = &sc->arpcom.ac_if;
3444 callout_stop(&sc->dc_stat_timer);
3446 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3447 #ifdef DEVICE_POLLING
3448 ether_poll_deregister(ifp);
3451 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3452 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3453 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3454 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3458 * Free data in the RX lists.
3460 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3461 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3462 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3463 sc->dc_cdata.dc_rx_chain[i] = NULL;
3466 bzero((char *)&sc->dc_ldata->dc_rx_list,
3467 sizeof(sc->dc_ldata->dc_rx_list));
3470 * Free the TX list buffers.
3472 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3473 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3474 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3476 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3477 DC_TXCTL_LASTFRAG)) {
3478 sc->dc_cdata.dc_tx_chain[i] = NULL;
3481 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3482 sc->dc_cdata.dc_tx_chain[i] = NULL;
3486 bzero((char *)&sc->dc_ldata->dc_tx_list,
3487 sizeof(sc->dc_ldata->dc_tx_list));
3493 * Stop all chip I/O so that the kernel's probe routines don't
3494 * get confused by errant DMAs when rebooting.
3496 static void dc_shutdown(dev)
3499 struct dc_softc *sc;
3501 sc = device_get_softc(dev);
3509 * Device suspend routine. Stop the interface and save some PCI
3510 * settings in case the BIOS doesn't restore them properly on
3513 static int dc_suspend(dev)
3518 struct dc_softc *sc;
3522 sc = device_get_softc(dev);
3526 for (i = 0; i < 5; i++)
3527 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3528 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3529 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3530 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3531 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3540 * Device resume routine. Restore some PCI settings in case the BIOS
3541 * doesn't, re-enable busmastering, and restart the interface if
3544 static int dc_resume(dev)
3549 struct dc_softc *sc;
3554 sc = device_get_softc(dev);
3555 ifp = &sc->arpcom.ac_if;
3559 /* better way to do this? */
3560 for (i = 0; i < 5; i++)
3561 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3562 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3563 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3564 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3565 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3567 /* reenable busmastering */
3568 pci_enable_busmaster(dev);
3569 pci_enable_io(dev, DC_RES);
3571 /* reinitialize interface if necessary */
3572 if (ifp->if_flags & IFF_UP)
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