bnx: Regroup RX std and return rings into their own structs
[dragonfly.git] / sys / dev / netif / bnx / if_bnx.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 #include "opt_bnx.h"
37 #include "opt_ifpoll.h"
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/rman.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
52
53 #include <netinet/ip.h>
54 #include <netinet/tcp.h>
55
56 #include <net/bpf.h>
57 #include <net/ethernet.h>
58 #include <net/if.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_poll.h>
63 #include <net/if_types.h>
64 #include <net/ifq_var.h>
65 #include <net/vlan/if_vlan_var.h>
66 #include <net/vlan/if_vlan_ether.h>
67
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
70 #include <dev/netif/mii_layer/brgphyreg.h>
71
72 #include <bus/pci/pcidevs.h>
73 #include <bus/pci/pcireg.h>
74 #include <bus/pci/pcivar.h>
75
76 #include <dev/netif/bge/if_bgereg.h>
77 #include <dev/netif/bnx/if_bnxvar.h>
78
79 /* "device miibus" required.  See GENERIC if you get errors here. */
80 #include "miibus_if.h"
81
82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
83
84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
85
86 static const struct bnx_type {
87         uint16_t                bnx_vid;
88         uint16_t                bnx_did;
89         char                    *bnx_name;
90 } bnx_devs[] = {
91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
92                 "Broadcom BCM5717 Gigabit Ethernet" },
93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
94                 "Broadcom BCM5717C Gigabit Ethernet" },
95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
96                 "Broadcom BCM5718 Gigabit Ethernet" },
97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
98                 "Broadcom BCM5719 Gigabit Ethernet" },
99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
100                 "Broadcom BCM5720 Gigabit Ethernet" },
101
102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
103                 "Broadcom BCM5725 Gigabit Ethernet" },
104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
105                 "Broadcom BCM5727 Gigabit Ethernet" },
106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
107                 "Broadcom BCM5762 Gigabit Ethernet" },
108
109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
110                 "Broadcom BCM57761 Gigabit Ethernet" },
111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
112                 "Broadcom BCM57762 Gigabit Ethernet" },
113         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
114                 "Broadcom BCM57765 Gigabit Ethernet" },
115         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
116                 "Broadcom BCM57766 Gigabit Ethernet" },
117         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
118                 "Broadcom BCM57781 Gigabit Ethernet" },
119         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
120                 "Broadcom BCM57782 Gigabit Ethernet" },
121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
122                 "Broadcom BCM57785 Gigabit Ethernet" },
123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
124                 "Broadcom BCM57786 Gigabit Ethernet" },
125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
126                 "Broadcom BCM57791 Fast Ethernet" },
127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
128                 "Broadcom BCM57795 Fast Ethernet" },
129
130         { 0, 0, NULL }
131 };
132
133 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
134 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
135 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
136 #define BNX_IS_57765_FAMILY(sc)  \
137         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
138
139 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
140
141 static int      bnx_probe(device_t);
142 static int      bnx_attach(device_t);
143 static int      bnx_detach(device_t);
144 static void     bnx_shutdown(device_t);
145 static int      bnx_suspend(device_t);
146 static int      bnx_resume(device_t);
147 static int      bnx_miibus_readreg(device_t, int, int);
148 static int      bnx_miibus_writereg(device_t, int, int, int);
149 static void     bnx_miibus_statchg(device_t);
150
151 #ifdef IFPOLL_ENABLE
152 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
153 static void     bnx_npoll_compat(struct ifnet *, void *, int);
154 #endif
155 static void     bnx_intr_legacy(void *);
156 static void     bnx_msi(void *);
157 static void     bnx_msi_oneshot(void *);
158 static void     bnx_intr(struct bnx_softc *);
159 static void     bnx_enable_intr(struct bnx_softc *);
160 static void     bnx_disable_intr(struct bnx_softc *);
161 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
162 static void     bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int);
163
164 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
165 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
166 static void     bnx_init(void *);
167 static void     bnx_stop(struct bnx_softc *);
168 static void     bnx_watchdog(struct ifnet *);
169 static int      bnx_ifmedia_upd(struct ifnet *);
170 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
171 static void     bnx_tick(void *);
172
173 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
174 static void     bnx_free_jumbo_mem(struct bnx_softc *);
175 static struct bnx_jslot
176                 *bnx_jalloc(struct bnx_softc *);
177 static void     bnx_jfree(void *);
178 static void     bnx_jref(void *);
179 static int      bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int);
180 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
181 static void     bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int);
182 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
183 static int      bnx_init_rx_ring_std(struct bnx_rx_std_ring *);
184 static void     bnx_free_rx_ring_std(struct bnx_rx_std_ring *);
185 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
186 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
187 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
188 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
189 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
190 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
191 static int      bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *);
192 static void     bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *);
193 static int      bnx_dma_alloc(device_t);
194 static void     bnx_dma_free(struct bnx_softc *);
195 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
196                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
197 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
198 static struct mbuf *
199                 bnx_defrag_shortdma(struct mbuf *);
200 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
201                     uint32_t *, int *);
202 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
203                     uint16_t *, uint16_t *);
204
205 static void     bnx_reset(struct bnx_softc *);
206 static int      bnx_chipinit(struct bnx_softc *);
207 static int      bnx_blockinit(struct bnx_softc *);
208 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
209 static void     bnx_enable_msi(struct bnx_softc *sc);
210 static void     bnx_setmulti(struct bnx_softc *);
211 static void     bnx_setpromisc(struct bnx_softc *);
212 static void     bnx_stats_update_regs(struct bnx_softc *);
213 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
214
215 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
216 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
217 #ifdef notdef
218 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
219 #endif
220 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
221 static void     bnx_writembx(struct bnx_softc *, int, int);
222 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
223 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
224 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
225
226 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
227 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
228 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
229 static void     bnx_link_poll(struct bnx_softc *);
230
231 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
232 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
233 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
234 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
235
236 static void     bnx_coal_change(struct bnx_softc *);
237 static int      bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
238 static int      bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
239 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
240 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
241 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
242 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
243 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
244 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
245 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
246                     int, int, uint32_t);
247
248 static int      bnx_msi_enable = 1;
249 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
250
251 static device_method_t bnx_methods[] = {
252         /* Device interface */
253         DEVMETHOD(device_probe,         bnx_probe),
254         DEVMETHOD(device_attach,        bnx_attach),
255         DEVMETHOD(device_detach,        bnx_detach),
256         DEVMETHOD(device_shutdown,      bnx_shutdown),
257         DEVMETHOD(device_suspend,       bnx_suspend),
258         DEVMETHOD(device_resume,        bnx_resume),
259
260         /* bus interface */
261         DEVMETHOD(bus_print_child,      bus_generic_print_child),
262         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
263
264         /* MII interface */
265         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
266         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
267         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
268
269         DEVMETHOD_END
270 };
271
272 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
273 static devclass_t bnx_devclass;
274
275 DECLARE_DUMMY_MODULE(if_bnx);
276 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
277 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
278
279 static uint32_t
280 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
281 {
282         device_t dev = sc->bnx_dev;
283         uint32_t val;
284
285         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
286         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
287         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
288         return (val);
289 }
290
291 static void
292 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
293 {
294         device_t dev = sc->bnx_dev;
295
296         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
297         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
298         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
299 }
300
301 static void
302 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
303 {
304         CSR_WRITE_4(sc, off, val);
305 }
306
307 static void
308 bnx_writembx(struct bnx_softc *sc, int off, int val)
309 {
310         CSR_WRITE_4(sc, off, val);
311 }
312
313 /*
314  * Read a sequence of bytes from NVRAM.
315  */
316 static int
317 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
318 {
319         return (1);
320 }
321
322 /*
323  * Read a byte of data stored in the EEPROM at address 'addr.' The
324  * BCM570x supports both the traditional bitbang interface and an
325  * auto access interface for reading the EEPROM. We use the auto
326  * access method.
327  */
328 static uint8_t
329 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
330 {
331         int i;
332         uint32_t byte = 0;
333
334         /*
335          * Enable use of auto EEPROM access so we can avoid
336          * having to use the bitbang method.
337          */
338         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
339
340         /* Reset the EEPROM, load the clock period. */
341         CSR_WRITE_4(sc, BGE_EE_ADDR,
342             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
343         DELAY(20);
344
345         /* Issue the read EEPROM command. */
346         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
347
348         /* Wait for completion */
349         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
350                 DELAY(10);
351                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
352                         break;
353         }
354
355         if (i == BNX_TIMEOUT) {
356                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
357                 return(1);
358         }
359
360         /* Get result. */
361         byte = CSR_READ_4(sc, BGE_EE_DATA);
362
363         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
364
365         return(0);
366 }
367
368 /*
369  * Read a sequence of bytes from the EEPROM.
370  */
371 static int
372 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
373 {
374         size_t i;
375         int err;
376         uint8_t byte;
377
378         for (byte = 0, err = 0, i = 0; i < len; i++) {
379                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
380                 if (err)
381                         break;
382                 *(dest + i) = byte;
383         }
384
385         return(err ? 1 : 0);
386 }
387
388 static int
389 bnx_miibus_readreg(device_t dev, int phy, int reg)
390 {
391         struct bnx_softc *sc = device_get_softc(dev);
392         uint32_t val;
393         int i;
394
395         KASSERT(phy == sc->bnx_phyno,
396             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
397
398         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
399         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
400                 CSR_WRITE_4(sc, BGE_MI_MODE,
401                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
402                 DELAY(80);
403         }
404
405         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
406             BGE_MIPHY(phy) | BGE_MIREG(reg));
407
408         /* Poll for the PHY register access to complete. */
409         for (i = 0; i < BNX_TIMEOUT; i++) {
410                 DELAY(10);
411                 val = CSR_READ_4(sc, BGE_MI_COMM);
412                 if ((val & BGE_MICOMM_BUSY) == 0) {
413                         DELAY(5);
414                         val = CSR_READ_4(sc, BGE_MI_COMM);
415                         break;
416                 }
417         }
418         if (i == BNX_TIMEOUT) {
419                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
420                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
421                 val = 0;
422         }
423
424         /* Restore the autopoll bit if necessary. */
425         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
426                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
427                 DELAY(80);
428         }
429
430         if (val & BGE_MICOMM_READFAIL)
431                 return 0;
432
433         return (val & 0xFFFF);
434 }
435
436 static int
437 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
438 {
439         struct bnx_softc *sc = device_get_softc(dev);
440         int i;
441
442         KASSERT(phy == sc->bnx_phyno,
443             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
444
445         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
446         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
447                 CSR_WRITE_4(sc, BGE_MI_MODE,
448                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
449                 DELAY(80);
450         }
451
452         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
453             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
454
455         for (i = 0; i < BNX_TIMEOUT; i++) {
456                 DELAY(10);
457                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
458                         DELAY(5);
459                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
460                         break;
461                 }
462         }
463         if (i == BNX_TIMEOUT) {
464                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
465                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
466         }
467
468         /* Restore the autopoll bit if necessary. */
469         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
470                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
471                 DELAY(80);
472         }
473
474         return 0;
475 }
476
477 static void
478 bnx_miibus_statchg(device_t dev)
479 {
480         struct bnx_softc *sc;
481         struct mii_data *mii;
482
483         sc = device_get_softc(dev);
484         mii = device_get_softc(sc->bnx_miibus);
485
486         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
487             (IFM_ACTIVE | IFM_AVALID)) {
488                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
489                 case IFM_10_T:
490                 case IFM_100_TX:
491                         sc->bnx_link = 1;
492                         break;
493                 case IFM_1000_T:
494                 case IFM_1000_SX:
495                 case IFM_2500_SX:
496                         sc->bnx_link = 1;
497                         break;
498                 default:
499                         sc->bnx_link = 0;
500                         break;
501                 }
502         } else {
503                 sc->bnx_link = 0;
504         }
505         if (sc->bnx_link == 0)
506                 return;
507
508         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
509         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
510             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
511                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
512         } else {
513                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
514         }
515
516         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
517                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
518         } else {
519                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
520         }
521 }
522
523 /*
524  * Memory management for jumbo frames.
525  */
526 static int
527 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
528 {
529         struct ifnet *ifp = &sc->arpcom.ac_if;
530         struct bnx_jslot *entry;
531         uint8_t *ptr;
532         bus_addr_t paddr;
533         int i, error;
534
535         /*
536          * Create tag for jumbo mbufs.
537          * This is really a bit of a kludge. We allocate a special
538          * jumbo buffer pool which (thanks to the way our DMA
539          * memory allocation works) will consist of contiguous
540          * pages. This means that even though a jumbo buffer might
541          * be larger than a page size, we don't really need to
542          * map it into more than one DMA segment. However, the
543          * default mbuf tag will result in multi-segment mappings,
544          * so we have to create a special jumbo mbuf tag that
545          * lets us get away with mapping the jumbo buffers as
546          * a single segment. I think eventually the driver should
547          * be changed so that it uses ordinary mbufs and cluster
548          * buffers, i.e. jumbo frames can span multiple DMA
549          * descriptors. But that's a project for another day.
550          */
551
552         /*
553          * Create DMA stuffs for jumbo RX ring.
554          */
555         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
556                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
557                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
558                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
559                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
560         if (error) {
561                 if_printf(ifp, "could not create jumbo RX ring\n");
562                 return error;
563         }
564
565         /*
566          * Create DMA stuffs for jumbo buffer block.
567          */
568         error = bnx_dma_block_alloc(sc, BNX_JMEM,
569                                     &sc->bnx_cdata.bnx_jumbo_tag,
570                                     &sc->bnx_cdata.bnx_jumbo_map,
571                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
572                                     &paddr);
573         if (error) {
574                 if_printf(ifp, "could not create jumbo buffer\n");
575                 return error;
576         }
577
578         SLIST_INIT(&sc->bnx_jfree_listhead);
579
580         /*
581          * Now divide it up into 9K pieces and save the addresses
582          * in an array. Note that we play an evil trick here by using
583          * the first few bytes in the buffer to hold the the address
584          * of the softc structure for this interface. This is because
585          * bnx_jfree() needs it, but it is called by the mbuf management
586          * code which will not pass it to us explicitly.
587          */
588         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
589                 entry = &sc->bnx_cdata.bnx_jslots[i];
590                 entry->bnx_sc = sc;
591                 entry->bnx_buf = ptr;
592                 entry->bnx_paddr = paddr;
593                 entry->bnx_inuse = 0;
594                 entry->bnx_slot = i;
595                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
596
597                 ptr += BNX_JLEN;
598                 paddr += BNX_JLEN;
599         }
600         return 0;
601 }
602
603 static void
604 bnx_free_jumbo_mem(struct bnx_softc *sc)
605 {
606         /* Destroy jumbo RX ring. */
607         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
608                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
609                            sc->bnx_ldata.bnx_rx_jumbo_ring);
610
611         /* Destroy jumbo buffer block. */
612         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
613                            sc->bnx_cdata.bnx_jumbo_map,
614                            sc->bnx_ldata.bnx_jumbo_buf);
615 }
616
617 /*
618  * Allocate a jumbo buffer.
619  */
620 static struct bnx_jslot *
621 bnx_jalloc(struct bnx_softc *sc)
622 {
623         struct bnx_jslot *entry;
624
625         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
626         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
627         if (entry) {
628                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
629                 entry->bnx_inuse = 1;
630         } else {
631                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
632         }
633         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
634         return(entry);
635 }
636
637 /*
638  * Adjust usage count on a jumbo buffer.
639  */
640 static void
641 bnx_jref(void *arg)
642 {
643         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
644         struct bnx_softc *sc = entry->bnx_sc;
645
646         if (sc == NULL)
647                 panic("bnx_jref: can't find softc pointer!");
648
649         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
650                 panic("bnx_jref: asked to reference buffer "
651                     "that we don't manage!");
652         } else if (entry->bnx_inuse == 0) {
653                 panic("bnx_jref: buffer already free!");
654         } else {
655                 atomic_add_int(&entry->bnx_inuse, 1);
656         }
657 }
658
659 /*
660  * Release a jumbo buffer.
661  */
662 static void
663 bnx_jfree(void *arg)
664 {
665         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
666         struct bnx_softc *sc = entry->bnx_sc;
667
668         if (sc == NULL)
669                 panic("bnx_jfree: can't find softc pointer!");
670
671         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
672                 panic("bnx_jfree: asked to free buffer that we don't manage!");
673         } else if (entry->bnx_inuse == 0) {
674                 panic("bnx_jfree: buffer already free!");
675         } else {
676                 /*
677                  * Possible MP race to 0, use the serializer.  The atomic insn
678                  * is still needed for races against bnx_jref().
679                  */
680                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
681                 atomic_subtract_int(&entry->bnx_inuse, 1);
682                 if (entry->bnx_inuse == 0) {
683                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, 
684                                           entry, jslot_link);
685                 }
686                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
687         }
688 }
689
690
691 /*
692  * Intialize a standard receive ring descriptor.
693  */
694 static int
695 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init)
696 {
697         struct mbuf *m_new = NULL;
698         bus_dma_segment_t seg;
699         bus_dmamap_t map;
700         int error, nsegs;
701         struct bnx_rx_buf *rb;
702
703         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
704         if (m_new == NULL)
705                 return ENOBUFS;
706         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
707         m_adj(m_new, ETHER_ALIGN);
708
709         error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag,
710             ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
711         if (error) {
712                 m_freem(m_new);
713                 return error;
714         }
715
716         rb = &ret->bnx_std->bnx_rx_std_buf[i];
717
718         if (!init) {
719                 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap,
720                     BUS_DMASYNC_POSTREAD);
721                 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap);
722         }
723
724         map = ret->bnx_rx_tmpmap;
725         ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap;
726         rb->bnx_rx_dmamap = map;
727
728         rb->bnx_rx_mbuf = m_new;
729         rb->bnx_rx_paddr = seg.ds_addr;
730
731         bnx_setup_rxdesc_std(ret->bnx_std, i);
732         return 0;
733 }
734
735 static void
736 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i)
737 {
738         const struct bnx_rx_buf *rb;
739         struct bge_rx_bd *r;
740
741         rb = &std->bnx_rx_std_buf[i];
742         r = &std->bnx_rx_std_ring[i];
743
744         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rb->bnx_rx_paddr);
745         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rb->bnx_rx_paddr);
746         r->bge_len = rb->bnx_rx_mbuf->m_len;
747         r->bge_idx = i;
748         r->bge_flags = BGE_RXBDFLAG_END;
749 }
750
751 /*
752  * Initialize a jumbo receive ring descriptor. This allocates
753  * a jumbo buffer from the pool managed internally by the driver.
754  */
755 static int
756 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
757 {
758         struct mbuf *m_new = NULL;
759         struct bnx_jslot *buf;
760         bus_addr_t paddr;
761
762         /* Allocate the mbuf. */
763         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
764         if (m_new == NULL)
765                 return ENOBUFS;
766
767         /* Allocate the jumbo buffer */
768         buf = bnx_jalloc(sc);
769         if (buf == NULL) {
770                 m_freem(m_new);
771                 return ENOBUFS;
772         }
773
774         /* Attach the buffer to the mbuf. */
775         m_new->m_ext.ext_arg = buf;
776         m_new->m_ext.ext_buf = buf->bnx_buf;
777         m_new->m_ext.ext_free = bnx_jfree;
778         m_new->m_ext.ext_ref = bnx_jref;
779         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
780
781         m_new->m_flags |= M_EXT;
782
783         m_new->m_data = m_new->m_ext.ext_buf;
784         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
785
786         paddr = buf->bnx_paddr;
787         m_adj(m_new, ETHER_ALIGN);
788         paddr += ETHER_ALIGN;
789
790         /* Save necessary information */
791         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new;
792         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr;
793
794         /* Set up the descriptor. */
795         bnx_setup_rxdesc_jumbo(sc, i);
796         return 0;
797 }
798
799 static void
800 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
801 {
802         struct bge_rx_bd *r;
803         struct bnx_rx_buf *rc;
804
805         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
806         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
807
808         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr);
809         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr);
810         r->bge_len = rc->bnx_rx_mbuf->m_len;
811         r->bge_idx = i;
812         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
813 }
814
815 static int
816 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std)
817 {
818         int i, error;
819
820         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
821                 /* Use the first RX return ring's tmp RX mbuf DMA map */
822                 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1);
823                 if (error)
824                         return error;
825         }
826
827         std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1;
828         bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
829
830         return(0);
831 }
832
833 static void
834 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std)
835 {
836         int i;
837
838         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
839                 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i];
840
841                 if (rb->bnx_rx_mbuf != NULL) {
842                         bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap);
843                         m_freem(rb->bnx_rx_mbuf);
844                         rb->bnx_rx_mbuf = NULL;
845                 }
846                 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd));
847         }
848 }
849
850 static int
851 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
852 {
853         struct bge_rcb *rcb;
854         int i, error;
855
856         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
857                 error = bnx_newbuf_jumbo(sc, i, 1);
858                 if (error)
859                         return error;
860         }
861
862         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
863
864         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
865         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
866         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
867
868         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
869
870         return(0);
871 }
872
873 static void
874 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
875 {
876         int i;
877
878         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
879                 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
880
881                 if (rc->bnx_rx_mbuf != NULL) {
882                         m_freem(rc->bnx_rx_mbuf);
883                         rc->bnx_rx_mbuf = NULL;
884                 }
885                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
886                     sizeof(struct bge_rx_bd));
887         }
888 }
889
890 static void
891 bnx_free_tx_ring(struct bnx_tx_ring *txr)
892 {
893         int i;
894
895         for (i = 0; i < BGE_TX_RING_CNT; i++) {
896                 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
897
898                 if (buf->bnx_tx_mbuf != NULL) {
899                         bus_dmamap_unload(txr->bnx_tx_mtag,
900                             buf->bnx_tx_dmamap);
901                         m_freem(buf->bnx_tx_mbuf);
902                         buf->bnx_tx_mbuf = NULL;
903                 }
904                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
905         }
906         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
907 }
908
909 static int
910 bnx_init_tx_ring(struct bnx_tx_ring *txr)
911 {
912         txr->bnx_txcnt = 0;
913         txr->bnx_tx_saved_considx = 0;
914         txr->bnx_tx_prodidx = 0;
915
916         /* Initialize transmit producer index for host-memory send ring. */
917         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
918
919         return(0);
920 }
921
922 static void
923 bnx_setmulti(struct bnx_softc *sc)
924 {
925         struct ifnet *ifp;
926         struct ifmultiaddr *ifma;
927         uint32_t hashes[4] = { 0, 0, 0, 0 };
928         int h, i;
929
930         ifp = &sc->arpcom.ac_if;
931
932         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
933                 for (i = 0; i < 4; i++)
934                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
935                 return;
936         }
937
938         /* First, zot all the existing filters. */
939         for (i = 0; i < 4; i++)
940                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
941
942         /* Now program new ones. */
943         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
944                 if (ifma->ifma_addr->sa_family != AF_LINK)
945                         continue;
946                 h = ether_crc32_le(
947                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
948                     ETHER_ADDR_LEN) & 0x7f;
949                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
950         }
951
952         for (i = 0; i < 4; i++)
953                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
954 }
955
956 /*
957  * Do endian, PCI and DMA initialization. Also check the on-board ROM
958  * self-test results.
959  */
960 static int
961 bnx_chipinit(struct bnx_softc *sc)
962 {
963         uint32_t dma_rw_ctl, mode_ctl;
964         int i;
965
966         /* Set endian type before we access any non-PCI registers. */
967         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
968             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
969
970         /* Clear the MAC control register */
971         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
972
973         /*
974          * Clear the MAC statistics block in the NIC's
975          * internal memory.
976          */
977         for (i = BGE_STATS_BLOCK;
978             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
979                 BNX_MEMWIN_WRITE(sc, i, 0);
980
981         for (i = BGE_STATUS_BLOCK;
982             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
983                 BNX_MEMWIN_WRITE(sc, i, 0);
984
985         if (BNX_IS_57765_FAMILY(sc)) {
986                 uint32_t val;
987
988                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
989                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
990                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
991
992                         /* Access the lower 1K of PL PCI-E block registers. */
993                         CSR_WRITE_4(sc, BGE_MODE_CTL,
994                             val | BGE_MODECTL_PCIE_PL_SEL);
995
996                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
997                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
998                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
999
1000                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1001                 }
1002                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1003                         /* Fix transmit hangs */
1004                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1005                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1006                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1007
1008                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1009                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1010
1011                         /* Access the lower 1K of DL PCI-E block registers. */
1012                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1013                             val | BGE_MODECTL_PCIE_DL_SEL);
1014
1015                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1016                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1017                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1018                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1019
1020                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1021                 }
1022
1023                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1024                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1025                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1026                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1027         }
1028
1029         /*
1030          * Set up the PCI DMA control register.
1031          */
1032         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1033         /*
1034          * Disable 32bytes cache alignment for DMA write to host memory
1035          *
1036          * NOTE:
1037          * 64bytes cache alignment for DMA write to host memory is still
1038          * enabled.
1039          */
1040         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1041         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1042                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1043         /*
1044          * Enable HW workaround for controllers that misinterpret
1045          * a status tag update and leave interrupts permanently
1046          * disabled.
1047          */
1048         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1049             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1050             !BNX_IS_57765_FAMILY(sc))
1051                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1052         if (bootverbose) {
1053                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1054                     dma_rw_ctl);
1055         }
1056         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1057
1058         /*
1059          * Set up general mode register.
1060          */
1061         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1062             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1063         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1064
1065         /*
1066          * Disable memory write invalidate.  Apparently it is not supported
1067          * properly by these devices.  Also ensure that INTx isn't disabled,
1068          * as these chips need it even when using MSI.
1069          */
1070         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1071             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1072
1073         /* Set the timer prescaler (always 66Mhz) */
1074         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1075
1076         return(0);
1077 }
1078
1079 static int
1080 bnx_blockinit(struct bnx_softc *sc)
1081 {
1082         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
1083         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
1084         struct bge_rcb *rcb;
1085         bus_size_t vrcb;
1086         bge_hostaddr taddr;
1087         uint32_t val;
1088         int i, limit;
1089
1090         /*
1091          * Initialize the memory window pointer register so that
1092          * we can access the first 32K of internal NIC RAM. This will
1093          * allow us to set up the TX send ring RCBs and the RX return
1094          * ring RCBs, plus other things which live in NIC memory.
1095          */
1096         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1097
1098         /* Configure mbuf pool watermarks */
1099         if (BNX_IS_57765_PLUS(sc)) {
1100                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1101                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1102                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1103                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1104                 } else {
1105                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1106                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1107                 }
1108         } else {
1109                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1110                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1111                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1112         }
1113
1114         /* Configure DMA resource watermarks */
1115         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1116         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1117
1118         /* Enable buffer manager */
1119         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1120         /*
1121          * Change the arbitration algorithm of TXMBUF read request to
1122          * round-robin instead of priority based for BCM5719.  When
1123          * TXFIFO is almost empty, RDMA will hold its request until
1124          * TXFIFO is not almost empty.
1125          */
1126         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1127                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1128         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1129             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1130             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1131                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1132         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1133
1134         /* Poll for buffer manager start indication */
1135         for (i = 0; i < BNX_TIMEOUT; i++) {
1136                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1137                         break;
1138                 DELAY(10);
1139         }
1140
1141         if (i == BNX_TIMEOUT) {
1142                 if_printf(&sc->arpcom.ac_if,
1143                           "buffer manager failed to start\n");
1144                 return(ENXIO);
1145         }
1146
1147         /* Enable flow-through queues */
1148         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1149         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1150
1151         /* Wait until queue initialization is complete */
1152         for (i = 0; i < BNX_TIMEOUT; i++) {
1153                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1154                         break;
1155                 DELAY(10);
1156         }
1157
1158         if (i == BNX_TIMEOUT) {
1159                 if_printf(&sc->arpcom.ac_if,
1160                           "flow-through queue init failed\n");
1161                 return(ENXIO);
1162         }
1163
1164         /*
1165          * Summary of rings supported by the controller:
1166          *
1167          * Standard Receive Producer Ring
1168          * - This ring is used to feed receive buffers for "standard"
1169          *   sized frames (typically 1536 bytes) to the controller.
1170          *
1171          * Jumbo Receive Producer Ring
1172          * - This ring is used to feed receive buffers for jumbo sized
1173          *   frames (i.e. anything bigger than the "standard" frames)
1174          *   to the controller.
1175          *
1176          * Mini Receive Producer Ring
1177          * - This ring is used to feed receive buffers for "mini"
1178          *   sized frames to the controller.
1179          * - This feature required external memory for the controller
1180          *   but was never used in a production system.  Should always
1181          *   be disabled.
1182          *
1183          * Receive Return Ring
1184          * - After the controller has placed an incoming frame into a
1185          *   receive buffer that buffer is moved into a receive return
1186          *   ring.  The driver is then responsible to passing the
1187          *   buffer up to the stack.  Many versions of the controller
1188          *   support multiple RR rings.
1189          *
1190          * Send Ring
1191          * - This ring is used for outgoing frames.  Many versions of
1192          *   the controller support multiple send rings.
1193          */
1194
1195         /* Initialize the standard receive producer ring control block. */
1196         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1197         rcb->bge_hostaddr.bge_addr_lo =
1198             BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1199         rcb->bge_hostaddr.bge_addr_hi =
1200             BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1201         if (BNX_IS_57765_PLUS(sc)) {
1202                 /*
1203                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1204                  * Bits 15-2 : Maximum RX frame size
1205                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1206                  * Bit 0     : Reserved
1207                  */
1208                 rcb->bge_maxlen_flags =
1209                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1210         } else {
1211                 /*
1212                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1213                  * Bits 15-2 : Reserved (should be 0)
1214                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1215                  * Bit 0     : Reserved
1216                  */
1217                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1218         }
1219         if (BNX_IS_5717_PLUS(sc))
1220                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1221         else
1222                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1223         /* Write the standard receive producer ring control block. */
1224         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1225         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1226         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1227         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1228         /* Reset the standard receive producer ring producer index. */
1229         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1230
1231         /*
1232          * Initialize the jumbo RX producer ring control
1233          * block.  We set the 'ring disabled' bit in the
1234          * flags field until we're actually ready to start
1235          * using this ring (i.e. once we set the MTU
1236          * high enough to require it).
1237          */
1238         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1239                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1240                 /* Get the jumbo receive producer ring RCB parameters. */
1241                 rcb->bge_hostaddr.bge_addr_lo =
1242                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1243                 rcb->bge_hostaddr.bge_addr_hi =
1244                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1245                 rcb->bge_maxlen_flags =
1246                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1247                     BGE_RCB_FLAG_RING_DISABLED);
1248                 if (BNX_IS_5717_PLUS(sc))
1249                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1250                 else
1251                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1252                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1253                     rcb->bge_hostaddr.bge_addr_hi);
1254                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1255                     rcb->bge_hostaddr.bge_addr_lo);
1256                 /* Program the jumbo receive producer ring RCB parameters. */
1257                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1258                     rcb->bge_maxlen_flags);
1259                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1260                 /* Reset the jumbo receive producer ring producer index. */
1261                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1262         }
1263
1264         /*
1265          * The BD ring replenish thresholds control how often the
1266          * hardware fetches new BD's from the producer rings in host
1267          * memory.  Setting the value too low on a busy system can
1268          * starve the hardware and recue the throughpout.
1269          *
1270          * Set the BD ring replentish thresholds. The recommended
1271          * values are 1/8th the number of descriptors allocated to
1272          * each ring.
1273          */
1274         val = 8;
1275         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1276         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1277                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1278                     BGE_JUMBO_RX_RING_CNT/8);
1279         }
1280         if (BNX_IS_57765_PLUS(sc)) {
1281                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1282                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1283         }
1284
1285         /*
1286          * Disable all send rings by setting the 'ring disabled' bit
1287          * in the flags field of all the TX send ring control blocks,
1288          * located in NIC memory.
1289          */
1290         if (BNX_IS_5717_PLUS(sc))
1291                 limit = 4;
1292         else if (BNX_IS_57765_FAMILY(sc) ||
1293             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1294                 limit = 2;
1295         else
1296                 limit = 1;
1297         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1298         for (i = 0; i < limit; i++) {
1299                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1300                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1301                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1302                 vrcb += sizeof(struct bge_rcb);
1303         }
1304
1305         /* Configure send ring RCB 0 (we use only the first ring) */
1306         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1307         BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1308         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1309         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1310         if (BNX_IS_5717_PLUS(sc)) {
1311                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1312         } else {
1313                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1314                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1315         }
1316         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1317             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1318
1319         /*
1320          * Disable all receive return rings by setting the
1321          * 'ring disabled' bit in the flags field of all the receive
1322          * return ring control blocks, located in NIC memory.
1323          */
1324         if (BNX_IS_5717_PLUS(sc)) {
1325                 /* Should be 17, use 16 until we get an SRAM map. */
1326                 limit = 16;
1327         } else if (BNX_IS_57765_FAMILY(sc) ||
1328             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1329                 limit = 4;
1330         } else {
1331                 limit = 1;
1332         }
1333         /* Disable all receive return rings. */
1334         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1335         for (i = 0; i < limit; i++) {
1336                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1337                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1338                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1339                     BGE_RCB_FLAG_RING_DISABLED);
1340                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1341                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1342                     (i * (sizeof(uint64_t))), 0);
1343                 vrcb += sizeof(struct bge_rcb);
1344         }
1345
1346         /*
1347          * Set up receive return ring 0.  Note that the NIC address
1348          * for RX return rings is 0x0.  The return rings live entirely
1349          * within the host, so the nicaddr field in the RCB isn't used.
1350          */
1351         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1352         BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr);
1353         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1354         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1355         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1356         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1357             BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1358
1359         /* Set random backoff seed for TX */
1360         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1361             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1362             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1363             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1364             BGE_TX_BACKOFF_SEED_MASK);
1365
1366         /* Set inter-packet gap */
1367         val = 0x2620;
1368         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1369             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1370                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1371                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1372         }
1373         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1374
1375         /*
1376          * Specify which ring to use for packets that don't match
1377          * any RX rules.
1378          */
1379         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1380
1381         /*
1382          * Configure number of RX lists. One interrupt distribution
1383          * list, sixteen active lists, one bad frames class.
1384          */
1385         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1386
1387         /* Inialize RX list placement stats mask. */
1388         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1389         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1390
1391         /* Disable host coalescing until we get it set up */
1392         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1393
1394         /* Poll to make sure it's shut down. */
1395         for (i = 0; i < BNX_TIMEOUT; i++) {
1396                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1397                         break;
1398                 DELAY(10);
1399         }
1400
1401         if (i == BNX_TIMEOUT) {
1402                 if_printf(&sc->arpcom.ac_if,
1403                           "host coalescing engine failed to idle\n");
1404                 return(ENXIO);
1405         }
1406
1407         /* Set up host coalescing defaults */
1408         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1409         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1410         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1411         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1412         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1413         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1414
1415         /* Set up address of status block */
1416         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1417         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1418             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1419         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1420             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1421
1422         /* Set up status block partail update size. */
1423         val = BGE_STATBLKSZ_32BYTE;
1424 #if 0
1425         /*
1426          * Does not seem to have visible effect in both
1427          * bulk data (1472B UDP datagram) and tiny data
1428          * (18B UDP datagram) TX tests.
1429          */
1430         val |= BGE_HCCMODE_CLRTICK_TX;
1431 #endif
1432         /* Turn on host coalescing state machine */
1433         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1434
1435         /* Turn on RX BD completion state machine and enable attentions */
1436         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1437             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1438
1439         /* Turn on RX list placement state machine */
1440         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1441
1442         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1443             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1444             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1445             BGE_MACMODE_FRMHDR_DMA_ENB;
1446
1447         if (sc->bnx_flags & BNX_FLAG_TBI)
1448                 val |= BGE_PORTMODE_TBI;
1449         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1450                 val |= BGE_PORTMODE_GMII;
1451         else
1452                 val |= BGE_PORTMODE_MII;
1453
1454         /* Turn on DMA, clear stats */
1455         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1456
1457         /* Set misc. local control, enable interrupts on attentions */
1458         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1459
1460 #ifdef notdef
1461         /* Assert GPIO pins for PHY reset */
1462         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1463             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1464         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1465             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1466 #endif
1467
1468         /* Turn on write DMA state machine */
1469         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1470         /* Enable host coalescing bug fix. */
1471         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1472         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1473                 /* Request larger DMA burst size to get better performance. */
1474                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1475         }
1476         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1477         DELAY(40);
1478
1479         if (BNX_IS_57765_PLUS(sc)) {
1480                 uint32_t dmactl, dmactl_reg;
1481
1482                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1483                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1484                 else
1485                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1486
1487                 dmactl = CSR_READ_4(sc, dmactl_reg);
1488                 /*
1489                  * Adjust tx margin to prevent TX data corruption and
1490                  * fix internal FIFO overflow.
1491                  */
1492                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1493                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1494                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1495                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1496                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1497                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1498                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1499                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1500                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1501                 }
1502                 /*
1503                  * Enable fix for read DMA FIFO overruns.
1504                  * The fix is to limit the number of RX BDs
1505                  * the hardware would fetch at a fime.
1506                  */
1507                 CSR_WRITE_4(sc, dmactl_reg,
1508                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1509         }
1510
1511         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1512                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1513                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1514                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1515                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1516         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1517             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1518                 uint32_t ctrl_reg;
1519
1520                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1521                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1522                 else
1523                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1524
1525                 /*
1526                  * Allow 4KB burst length reads for non-LSO frames.
1527                  * Enable 512B burst length reads for buffer descriptors.
1528                  */
1529                 CSR_WRITE_4(sc, ctrl_reg,
1530                     CSR_READ_4(sc, ctrl_reg) |
1531                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1532                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1533         }
1534
1535         /* Turn on read DMA state machine */
1536         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1537         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1538                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1539         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1540             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1541             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1542                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1543                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1544                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1545         }
1546         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1547             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1548                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1549                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1550                 /*
1551                  * Allow multiple outstanding read requests from
1552                  * non-LSO read DMA engine.
1553                  */
1554                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1555         }
1556         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1557                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1558         if (sc->bnx_flags & BNX_FLAG_TSO)
1559                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1560         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1561         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1562         DELAY(40);
1563
1564         /* Turn on RX data completion state machine */
1565         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1566
1567         /* Turn on RX BD initiator state machine */
1568         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1569
1570         /* Turn on RX data and RX BD initiator state machine */
1571         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1572
1573         /* Turn on send BD completion state machine */
1574         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1575
1576         /* Turn on send data completion state machine */
1577         val = BGE_SDCMODE_ENABLE;
1578         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1579                 val |= BGE_SDCMODE_CDELAY; 
1580         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1581
1582         /* Turn on send data initiator state machine */
1583         if (sc->bnx_flags & BNX_FLAG_TSO) {
1584                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1585                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1586         } else {
1587                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1588         }
1589
1590         /* Turn on send BD initiator state machine */
1591         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1592
1593         /* Turn on send BD selector state machine */
1594         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1595
1596         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1597         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1598             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1599
1600         /* ack/clear link change events */
1601         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1602             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1603             BGE_MACSTAT_LINK_CHANGED);
1604         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1605
1606         /*
1607          * Enable attention when the link has changed state for
1608          * devices that use auto polling.
1609          */
1610         if (sc->bnx_flags & BNX_FLAG_TBI) {
1611                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1612         } else {
1613                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1614                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1615                         DELAY(80);
1616                 }
1617         }
1618
1619         /*
1620          * Clear any pending link state attention.
1621          * Otherwise some link state change events may be lost until attention
1622          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1623          * It's not necessary on newer BCM chips - perhaps enabling link
1624          * state change attentions implies clearing pending attention.
1625          */
1626         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1627             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1628             BGE_MACSTAT_LINK_CHANGED);
1629
1630         /* Enable link state change attentions. */
1631         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1632
1633         return(0);
1634 }
1635
1636 /*
1637  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1638  * against our list and return its name if we find a match. Note
1639  * that since the Broadcom controller contains VPD support, we
1640  * can get the device name string from the controller itself instead
1641  * of the compiled-in string. This is a little slow, but it guarantees
1642  * we'll always announce the right product name.
1643  */
1644 static int
1645 bnx_probe(device_t dev)
1646 {
1647         const struct bnx_type *t;
1648         uint16_t product, vendor;
1649
1650         if (!pci_is_pcie(dev))
1651                 return ENXIO;
1652
1653         product = pci_get_device(dev);
1654         vendor = pci_get_vendor(dev);
1655
1656         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1657                 if (vendor == t->bnx_vid && product == t->bnx_did)
1658                         break;
1659         }
1660         if (t->bnx_name == NULL)
1661                 return ENXIO;
1662
1663         device_set_desc(dev, t->bnx_name);
1664         return 0;
1665 }
1666
1667 static int
1668 bnx_attach(device_t dev)
1669 {
1670         struct ifnet *ifp;
1671         struct bnx_softc *sc;
1672         uint32_t hwcfg = 0;
1673         int error = 0, rid, capmask;
1674         uint8_t ether_addr[ETHER_ADDR_LEN];
1675         uint16_t product;
1676         driver_intr_t *intr_func;
1677         uintptr_t mii_priv = 0;
1678         u_int intr_flags;
1679 #ifdef BNX_TSO_DEBUG
1680         char desc[32];
1681         int i;
1682 #endif
1683
1684         sc = device_get_softc(dev);
1685         sc->bnx_dev = dev;
1686         callout_init_mp(&sc->bnx_stat_timer);
1687         callout_init_mp(&sc->bnx_intr_timer);
1688         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1689
1690         product = pci_get_device(dev);
1691
1692 #ifndef BURN_BRIDGES
1693         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1694                 uint32_t irq, mem;
1695
1696                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1697                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1698
1699                 device_printf(dev, "chip is in D%d power mode "
1700                     "-- setting to D0\n", pci_get_powerstate(dev));
1701
1702                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1703
1704                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1705                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1706         }
1707 #endif  /* !BURN_BRIDGE */
1708
1709         /*
1710          * Map control/status registers.
1711          */
1712         pci_enable_busmaster(dev);
1713
1714         rid = BGE_PCI_BAR0;
1715         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1716             RF_ACTIVE);
1717
1718         if (sc->bnx_res == NULL) {
1719                 device_printf(dev, "couldn't map memory\n");
1720                 return ENXIO;
1721         }
1722
1723         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1724         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1725
1726         /* Save various chip information */
1727         sc->bnx_chipid =
1728             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1729             BGE_PCIMISCCTL_ASICREV_SHIFT;
1730         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1731                 /* All chips having dedicated ASICREV register have CPMU */
1732                 sc->bnx_flags |= BNX_FLAG_CPMU;
1733
1734                 switch (product) {
1735                 case PCI_PRODUCT_BROADCOM_BCM5717:
1736                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1737                 case PCI_PRODUCT_BROADCOM_BCM5718:
1738                 case PCI_PRODUCT_BROADCOM_BCM5719:
1739                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1740                 case PCI_PRODUCT_BROADCOM_BCM5725:
1741                 case PCI_PRODUCT_BROADCOM_BCM5727:
1742                 case PCI_PRODUCT_BROADCOM_BCM5762:
1743                         sc->bnx_chipid = pci_read_config(dev,
1744                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1745                         break;
1746
1747                 case PCI_PRODUCT_BROADCOM_BCM57761:
1748                 case PCI_PRODUCT_BROADCOM_BCM57762:
1749                 case PCI_PRODUCT_BROADCOM_BCM57765:
1750                 case PCI_PRODUCT_BROADCOM_BCM57766:
1751                 case PCI_PRODUCT_BROADCOM_BCM57781:
1752                 case PCI_PRODUCT_BROADCOM_BCM57782:
1753                 case PCI_PRODUCT_BROADCOM_BCM57785:
1754                 case PCI_PRODUCT_BROADCOM_BCM57786:
1755                 case PCI_PRODUCT_BROADCOM_BCM57791:
1756                 case PCI_PRODUCT_BROADCOM_BCM57795:
1757                         sc->bnx_chipid = pci_read_config(dev,
1758                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1759                         break;
1760
1761                 default:
1762                         sc->bnx_chipid = pci_read_config(dev,
1763                             BGE_PCI_PRODID_ASICREV, 4);
1764                         break;
1765                 }
1766         }
1767         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1768                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1769
1770         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1771         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1772
1773         switch (sc->bnx_asicrev) {
1774         case BGE_ASICREV_BCM5717:
1775         case BGE_ASICREV_BCM5719:
1776         case BGE_ASICREV_BCM5720:
1777                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1778                 break;
1779
1780         case BGE_ASICREV_BCM5762:
1781                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1782                 break;
1783
1784         case BGE_ASICREV_BCM57765:
1785         case BGE_ASICREV_BCM57766:
1786                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1787                 break;
1788         }
1789
1790         sc->bnx_flags |= BNX_FLAG_TSO;
1791         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1792             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1793                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1794
1795         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1796             BNX_IS_57765_FAMILY(sc)) {
1797                 /*
1798                  * All BCM57785 and BCM5718 families chips have a bug that
1799                  * under certain situation interrupt will not be enabled
1800                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1801                  *
1802                  * While BCM5719 and BCM5720 have a hardware workaround
1803                  * which could fix the above bug.
1804                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1805                  * bnx_chipinit().
1806                  *
1807                  * For the rest of the chips in these two families, we will
1808                  * have to poll the status block at high rate (10ms currently)
1809                  * to check whether the interrupt is hosed or not.
1810                  * See bnx_intr_check() for details.
1811                  */
1812                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1813         }
1814
1815         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1816         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1817             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1818                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1819         else
1820                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1821         device_printf(dev, "CHIP ID 0x%08x; "
1822                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1823                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1824
1825         /*
1826          * Set various PHY quirk flags.
1827          */
1828
1829         capmask = MII_CAPMASK_DEFAULT;
1830         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1831             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1832                 /* 10/100 only */
1833                 capmask &= ~BMSR_EXTSTAT;
1834         }
1835
1836         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1837         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1838                 mii_priv |= BRGPHY_FLAG_5762_A0;
1839
1840         /* Initialize if_name earlier, so if_printf could be used */
1841         ifp = &sc->arpcom.ac_if;
1842         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1843
1844         /* Try to reset the chip. */
1845         bnx_reset(sc);
1846
1847         if (bnx_chipinit(sc)) {
1848                 device_printf(dev, "chip initialization failed\n");
1849                 error = ENXIO;
1850                 goto fail;
1851         }
1852
1853         /*
1854          * Get station address
1855          */
1856         error = bnx_get_eaddr(sc, ether_addr);
1857         if (error) {
1858                 device_printf(dev, "failed to read station address\n");
1859                 goto fail;
1860         }
1861
1862         /* XXX */
1863         sc->bnx_tx_ringcnt = 1;
1864         sc->bnx_rx_retcnt = 1;
1865
1866         error = bnx_dma_alloc(dev);
1867         if (error)
1868                 goto fail;
1869
1870         /*
1871          * Allocate interrupt
1872          */
1873         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1874             &intr_flags);
1875
1876         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1877             intr_flags);
1878         if (sc->bnx_irq == NULL) {
1879                 device_printf(dev, "couldn't map interrupt\n");
1880                 error = ENXIO;
1881                 goto fail;
1882         }
1883
1884         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1885                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1886                 bnx_enable_msi(sc);
1887         }
1888
1889         /* Set default tuneable values. */
1890         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1891         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1892         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1893         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1894         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1895         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1896
1897         /* Set up ifnet structure */
1898         ifp->if_softc = sc;
1899         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1900         ifp->if_ioctl = bnx_ioctl;
1901         ifp->if_start = bnx_start;
1902 #ifdef IFPOLL_ENABLE
1903         ifp->if_npoll = bnx_npoll;
1904 #endif
1905         ifp->if_watchdog = bnx_watchdog;
1906         ifp->if_init = bnx_init;
1907         ifp->if_mtu = ETHERMTU;
1908         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1909         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1910         ifq_set_ready(&ifp->if_snd);
1911
1912         ifp->if_capabilities |= IFCAP_HWCSUM;
1913         ifp->if_hwassist = BNX_CSUM_FEATURES;
1914         if (sc->bnx_flags & BNX_FLAG_TSO) {
1915                 ifp->if_capabilities |= IFCAP_TSO;
1916                 ifp->if_hwassist |= CSUM_TSO;
1917         }
1918         ifp->if_capenable = ifp->if_capabilities;
1919
1920         /*
1921          * Figure out what sort of media we have by checking the
1922          * hardware config word in the first 32k of NIC internal memory,
1923          * or fall back to examining the EEPROM if necessary.
1924          * Note: on some BCM5700 cards, this value appears to be unset.
1925          * If that's the case, we have to rely on identifying the NIC
1926          * by its PCI subsystem ID, as we do below for the SysKonnect
1927          * SK-9D41.
1928          */
1929         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1930                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1931         } else {
1932                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1933                                     sizeof(hwcfg))) {
1934                         device_printf(dev, "failed to read EEPROM\n");
1935                         error = ENXIO;
1936                         goto fail;
1937                 }
1938                 hwcfg = ntohl(hwcfg);
1939         }
1940
1941         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1942         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1943             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1944                 sc->bnx_flags |= BNX_FLAG_TBI;
1945
1946         /* Setup MI MODE */
1947         if (sc->bnx_flags & BNX_FLAG_CPMU)
1948                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1949         else
1950                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1951
1952         /* Setup link status update stuffs */
1953         if (sc->bnx_flags & BNX_FLAG_TBI) {
1954                 sc->bnx_link_upd = bnx_tbi_link_upd;
1955                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1956         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1957                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1958                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1959         } else {
1960                 sc->bnx_link_upd = bnx_copper_link_upd;
1961                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1962         }
1963
1964         /* Set default PHY address */
1965         sc->bnx_phyno = 1;
1966
1967         /*
1968          * PHY address mapping for various devices.
1969          *
1970          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1971          * ---------+-------+-------+-------+-------+
1972          * BCM57XX  |   1   |   X   |   X   |   X   |
1973          * BCM5704  |   1   |   X   |   1   |   X   |
1974          * BCM5717  |   1   |   8   |   2   |   9   |
1975          * BCM5719  |   1   |   8   |   2   |   9   |
1976          * BCM5720  |   1   |   8   |   2   |   9   |
1977          *
1978          * Other addresses may respond but they are not
1979          * IEEE compliant PHYs and should be ignored.
1980          */
1981         if (BNX_IS_5717_PLUS(sc)) {
1982                 int f;
1983
1984                 f = pci_get_function(dev);
1985                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
1986                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
1987                             BGE_SGDIGSTS_IS_SERDES)
1988                                 sc->bnx_phyno = f + 8;
1989                         else
1990                                 sc->bnx_phyno = f + 1;
1991                 } else {
1992                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
1993                             BGE_CPMU_PHY_STRAP_IS_SERDES)
1994                                 sc->bnx_phyno = f + 8;
1995                         else
1996                                 sc->bnx_phyno = f + 1;
1997                 }
1998         }
1999
2000         if (sc->bnx_flags & BNX_FLAG_TBI) {
2001                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2002                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2003                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2004                 ifmedia_add(&sc->bnx_ifmedia,
2005                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2006                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2007                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2008                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2009         } else {
2010                 struct mii_probe_args mii_args;
2011
2012                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2013                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2014                 mii_args.mii_capmask = capmask;
2015                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2016                 mii_args.mii_priv = mii_priv;
2017
2018                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2019                 if (error) {
2020                         device_printf(dev, "MII without any PHY!\n");
2021                         goto fail;
2022                 }
2023         }
2024
2025         /*
2026          * Create sysctl nodes.
2027          */
2028         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2029         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2030                                               SYSCTL_STATIC_CHILDREN(_hw),
2031                                               OID_AUTO,
2032                                               device_get_nameunit(dev),
2033                                               CTLFLAG_RD, 0, "");
2034         if (sc->bnx_sysctl_tree == NULL) {
2035                 device_printf(dev, "can't add sysctl node\n");
2036                 error = ENXIO;
2037                 goto fail;
2038         }
2039
2040         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2041                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2042                         OID_AUTO, "rx_coal_ticks",
2043                         CTLTYPE_INT | CTLFLAG_RW,
2044                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2045                         "Receive coalescing ticks (usec).");
2046         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2047                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2048                         OID_AUTO, "tx_coal_ticks",
2049                         CTLTYPE_INT | CTLFLAG_RW,
2050                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2051                         "Transmit coalescing ticks (usec).");
2052         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2053                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2054                         OID_AUTO, "rx_coal_bds",
2055                         CTLTYPE_INT | CTLFLAG_RW,
2056                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2057                         "Receive max coalesced BD count.");
2058         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2059                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2060                         OID_AUTO, "tx_coal_bds",
2061                         CTLTYPE_INT | CTLFLAG_RW,
2062                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2063                         "Transmit max coalesced BD count.");
2064         /*
2065          * A common design characteristic for many Broadcom
2066          * client controllers is that they only support a
2067          * single outstanding DMA read operation on the PCIe
2068          * bus. This means that it will take twice as long to
2069          * fetch a TX frame that is split into header and
2070          * payload buffers as it does to fetch a single,
2071          * contiguous TX frame (2 reads vs. 1 read). For these
2072          * controllers, coalescing buffers to reduce the number
2073          * of memory reads is effective way to get maximum
2074          * performance(about 940Mbps).  Without collapsing TX
2075          * buffers the maximum TCP bulk transfer performance
2076          * is about 850Mbps. However forcing coalescing mbufs
2077          * consumes a lot of CPU cycles, so leave it off by
2078          * default.
2079          */
2080         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2081             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2082             "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2083             sc, 0, bnx_sysctl_force_defrag, "I",
2084             "Force defragment on TX path");
2085
2086         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2087             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2088             "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2089             sc, 0, bnx_sysctl_tx_wreg, "I",
2090             "# of segments before writing to hardware register");
2091
2092         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2093             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2094             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2095             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2096             "Receive max coalesced BD count during interrupt.");
2097         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2098             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2099             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2100             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2101             "Transmit max coalesced BD count during interrupt.");
2102
2103 #ifdef BNX_TSO_DEBUG
2104         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2105                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2106                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2107                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2108                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2109         }
2110 #endif
2111
2112         /*
2113          * Call MI attach routine.
2114          */
2115         ether_ifattach(ifp, ether_addr, NULL);
2116
2117         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2118
2119 #ifdef IFPOLL_ENABLE
2120         ifpoll_compat_setup(&sc->bnx_npoll,
2121             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2122             device_get_unit(dev), ifp->if_serializer);
2123 #endif
2124
2125         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2126                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2127                         intr_func = bnx_msi_oneshot;
2128                         if (bootverbose)
2129                                 device_printf(dev, "oneshot MSI\n");
2130                 } else {
2131                         intr_func = bnx_msi;
2132                 }
2133         } else {
2134                 intr_func = bnx_intr_legacy;
2135         }
2136         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2137             &sc->bnx_intrhand, ifp->if_serializer);
2138         if (error) {
2139                 ether_ifdetach(ifp);
2140                 device_printf(dev, "couldn't set up irq\n");
2141                 goto fail;
2142         }
2143
2144         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2145         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2146
2147         return(0);
2148 fail:
2149         bnx_detach(dev);
2150         return(error);
2151 }
2152
2153 static int
2154 bnx_detach(device_t dev)
2155 {
2156         struct bnx_softc *sc = device_get_softc(dev);
2157
2158         if (device_is_attached(dev)) {
2159                 struct ifnet *ifp = &sc->arpcom.ac_if;
2160
2161                 lwkt_serialize_enter(ifp->if_serializer);
2162                 bnx_stop(sc);
2163                 bnx_reset(sc);
2164                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2165                 lwkt_serialize_exit(ifp->if_serializer);
2166
2167                 ether_ifdetach(ifp);
2168         }
2169
2170         if (sc->bnx_flags & BNX_FLAG_TBI)
2171                 ifmedia_removeall(&sc->bnx_ifmedia);
2172         if (sc->bnx_miibus)
2173                 device_delete_child(dev, sc->bnx_miibus);
2174         bus_generic_detach(dev);
2175
2176         if (sc->bnx_irq != NULL) {
2177                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2178                     sc->bnx_irq);
2179         }
2180         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2181                 pci_release_msi(dev);
2182
2183         if (sc->bnx_res != NULL) {
2184                 bus_release_resource(dev, SYS_RES_MEMORY,
2185                     BGE_PCI_BAR0, sc->bnx_res);
2186         }
2187
2188         if (sc->bnx_sysctl_tree != NULL)
2189                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2190
2191         bnx_dma_free(sc);
2192
2193         return 0;
2194 }
2195
2196 static void
2197 bnx_reset(struct bnx_softc *sc)
2198 {
2199         device_t dev;
2200         uint32_t cachesize, command, pcistate, reset;
2201         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2202         int i, val = 0;
2203         uint16_t devctl;
2204
2205         dev = sc->bnx_dev;
2206
2207         write_op = bnx_writemem_direct;
2208
2209         /* Save some important PCI state. */
2210         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2211         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2212         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2213
2214         pci_write_config(dev, BGE_PCI_MISC_CTL,
2215             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2216             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2217             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2218
2219         /* Disable fastboot on controllers that support it. */
2220         if (bootverbose)
2221                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2222         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2223
2224         /*
2225          * Write the magic number to SRAM at offset 0xB50.
2226          * When firmware finishes its initialization it will
2227          * write ~BGE_MAGIC_NUMBER to the same location.
2228          */
2229         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2230
2231         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2232
2233         /* XXX: Broadcom Linux driver. */
2234         /* Force PCI-E 1.0a mode */
2235         if (!BNX_IS_57765_PLUS(sc) &&
2236             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2237             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2238              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2239                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2240                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2241         }
2242         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2243                 /* Prevent PCIE link training during global reset */
2244                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2245                 reset |= (1<<29);
2246         }
2247
2248         /* 
2249          * Set GPHY Power Down Override to leave GPHY
2250          * powered up in D0 uninitialized.
2251          */
2252         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2253                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2254
2255         /* Issue global reset */
2256         write_op(sc, BGE_MISC_CFG, reset);
2257
2258         DELAY(1000);
2259
2260         /* XXX: Broadcom Linux driver. */
2261         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2262                 uint32_t v;
2263
2264                 DELAY(500000); /* wait for link training to complete */
2265                 v = pci_read_config(dev, 0xc4, 4);
2266                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2267         }
2268
2269         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2270
2271         /* Disable no snoop and disable relaxed ordering. */
2272         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2273
2274         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2275         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2276                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2277                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2278         }
2279
2280         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2281             devctl, 2);
2282
2283         /* Clear error status. */
2284         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2285             PCIEM_DEVSTS_CORR_ERR |
2286             PCIEM_DEVSTS_NFATAL_ERR |
2287             PCIEM_DEVSTS_FATAL_ERR |
2288             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2289
2290         /* Reset some of the PCI state that got zapped by reset */
2291         pci_write_config(dev, BGE_PCI_MISC_CTL,
2292             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2293             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2294             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2295         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2296         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2297         write_op(sc, BGE_MISC_CFG, (65 << 1));
2298
2299         /* Enable memory arbiter */
2300         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2301
2302         /*
2303          * Poll until we see the 1's complement of the magic number.
2304          * This indicates that the firmware initialization is complete.
2305          */
2306         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2307                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2308                 if (val == ~BGE_MAGIC_NUMBER)
2309                         break;
2310                 DELAY(10);
2311         }
2312         if (i == BNX_FIRMWARE_TIMEOUT) {
2313                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2314                           "timed out, found 0x%08x\n", val);
2315         }
2316
2317         /* BCM57765 A0 needs additional time before accessing. */
2318         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2319                 DELAY(10 * 1000);
2320
2321         /*
2322          * XXX Wait for the value of the PCISTATE register to
2323          * return to its original pre-reset state. This is a
2324          * fairly good indicator of reset completion. If we don't
2325          * wait for the reset to fully complete, trying to read
2326          * from the device's non-PCI registers may yield garbage
2327          * results.
2328          */
2329         for (i = 0; i < BNX_TIMEOUT; i++) {
2330                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2331                         break;
2332                 DELAY(10);
2333         }
2334
2335         /* Fix up byte swapping */
2336         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2337
2338         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2339
2340         /*
2341          * The 5704 in TBI mode apparently needs some special
2342          * adjustment to insure the SERDES drive level is set
2343          * to 1.2V.
2344          */
2345         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2346             (sc->bnx_flags & BNX_FLAG_TBI)) {
2347                 uint32_t serdescfg;
2348
2349                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2350                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2351                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2352         }
2353
2354         CSR_WRITE_4(sc, BGE_MI_MODE,
2355             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2356         DELAY(80);
2357
2358         /* XXX: Broadcom Linux driver. */
2359         if (!BNX_IS_57765_PLUS(sc)) {
2360                 uint32_t v;
2361
2362                 /* Enable Data FIFO protection. */
2363                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2364                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2365         }
2366
2367         DELAY(10000);
2368
2369         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2370                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2371                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2372         }
2373 }
2374
2375 /*
2376  * Frame reception handling. This is called if there's a frame
2377  * on the receive return list.
2378  *
2379  * Note: we have to be able to handle two possibilities here:
2380  * 1) the frame is from the jumbo recieve ring
2381  * 2) the frame is from the standard receive ring
2382  */
2383
2384 static void
2385 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count)
2386 {
2387         struct bnx_softc *sc = ret->bnx_sc;
2388         struct bnx_rx_std_ring *std = ret->bnx_std;
2389         struct ifnet *ifp = &sc->arpcom.ac_if;
2390         int stdcnt = 0, jumbocnt = 0;
2391
2392         while (ret->bnx_rx_saved_considx != rx_prod && count != 0) {
2393                 struct bge_rx_bd        *cur_rx;
2394                 uint32_t                rxidx;
2395                 struct mbuf             *m = NULL;
2396                 uint16_t                vlan_tag = 0;
2397                 int                     have_tag = 0;
2398
2399                 --count;
2400
2401                 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx];
2402
2403                 rxidx = cur_rx->bge_idx;
2404                 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2405
2406                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2407                         have_tag = 1;
2408                         vlan_tag = cur_rx->bge_vlan_tag;
2409                 }
2410
2411                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2412                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2413                         jumbocnt++;
2414
2415                         if (rxidx != sc->bnx_jumbo) {
2416                                 IFNET_STAT_INC(ifp, ierrors, 1);
2417                                 if_printf(ifp, "sw jumbo index(%d) "
2418                                     "and hw jumbo index(%d) mismatch, drop!\n",
2419                                     sc->bnx_jumbo, rxidx);
2420                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2421                                 continue;
2422                         }
2423
2424                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_rx_mbuf;
2425                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2426                                 IFNET_STAT_INC(ifp, ierrors, 1);
2427                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2428                                 continue;
2429                         }
2430                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2431                                 IFNET_STAT_INC(ifp, ierrors, 1);
2432                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2433                                 continue;
2434                         }
2435                 } else {
2436                         BNX_INC(std->bnx_rx_std, BGE_STD_RX_RING_CNT);
2437                         stdcnt++;
2438
2439                         if (rxidx != std->bnx_rx_std) {
2440                                 IFNET_STAT_INC(ifp, ierrors, 1);
2441                                 if_printf(ifp, "sw std index(%d) "
2442                                     "and hw std index(%d) mismatch, drop!\n",
2443                                     std->bnx_rx_std, rxidx);
2444                                 bnx_setup_rxdesc_std(std, rxidx);
2445                                 continue;
2446                         }
2447
2448                         m = std->bnx_rx_std_buf[rxidx].bnx_rx_mbuf;
2449                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2450                                 IFNET_STAT_INC(ifp, ierrors, 1);
2451                                 bnx_setup_rxdesc_std(std, std->bnx_rx_std);
2452                                 continue;
2453                         }
2454                         if (bnx_newbuf_std(ret, std->bnx_rx_std, 0)) {
2455                                 IFNET_STAT_INC(ifp, ierrors, 1);
2456                                 bnx_setup_rxdesc_std(std, std->bnx_rx_std);
2457                                 continue;
2458                         }
2459                 }
2460
2461                 IFNET_STAT_INC(ifp, ipackets, 1);
2462                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2463                 m->m_pkthdr.rcvif = ifp;
2464
2465                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2466                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2467                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2468                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2469                                 if ((cur_rx->bge_error_flag &
2470                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2471                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2472                         }
2473                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2474                                 m->m_pkthdr.csum_data =
2475                                     cur_rx->bge_tcp_udp_csum;
2476                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2477                                     CSUM_PSEUDO_HDR;
2478                         }
2479                 }
2480
2481                 /*
2482                  * If we received a packet with a vlan tag, pass it
2483                  * to vlan_input() instead of ether_input().
2484                  */
2485                 if (have_tag) {
2486                         m->m_flags |= M_VLANTAG;
2487                         m->m_pkthdr.ether_vlantag = vlan_tag;
2488                 }
2489                 ifp->if_input(ifp, m);
2490         }
2491
2492         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, ret->bnx_rx_saved_considx);
2493         if (stdcnt)
2494                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
2495         if (jumbocnt)
2496                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2497 }
2498
2499 static void
2500 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2501 {
2502         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2503
2504         /*
2505          * Go through our tx ring and free mbufs for those
2506          * frames that have been sent.
2507          */
2508         while (txr->bnx_tx_saved_considx != tx_cons) {
2509                 struct bnx_tx_buf *buf;
2510                 uint32_t idx = 0;
2511
2512                 idx = txr->bnx_tx_saved_considx;
2513                 buf = &txr->bnx_tx_buf[idx];
2514                 if (buf->bnx_tx_mbuf != NULL) {
2515                         IFNET_STAT_INC(ifp, opackets, 1);
2516                         bus_dmamap_unload(txr->bnx_tx_mtag,
2517                             buf->bnx_tx_dmamap);
2518                         m_freem(buf->bnx_tx_mbuf);
2519                         buf->bnx_tx_mbuf = NULL;
2520                 }
2521                 txr->bnx_txcnt--;
2522                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2523         }
2524
2525         if ((BGE_TX_RING_CNT - txr->bnx_txcnt) >=
2526             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2527                 ifq_clr_oactive(&ifp->if_snd);
2528
2529         if (txr->bnx_txcnt == 0)
2530                 ifp->if_timer = 0;
2531
2532         if (!ifq_is_empty(&ifp->if_snd))
2533                 if_devstart(ifp);
2534 }
2535
2536 #ifdef IFPOLL_ENABLE
2537
2538 static void
2539 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2540 {
2541         struct bnx_softc *sc = ifp->if_softc;
2542
2543         ASSERT_SERIALIZED(ifp->if_serializer);
2544
2545         if (info != NULL) {
2546                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2547
2548                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2549                 info->ifpi_rx[cpuid].arg = NULL;
2550                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2551
2552                 if (ifp->if_flags & IFF_RUNNING)
2553                         bnx_disable_intr(sc);
2554                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2555         } else {
2556                 if (ifp->if_flags & IFF_RUNNING)
2557                         bnx_enable_intr(sc);
2558                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2559         }
2560 }
2561
2562 static void
2563 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2564 {
2565         struct bnx_softc *sc = ifp->if_softc;
2566         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2567         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; /* XXX */
2568         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2569         uint16_t rx_prod, tx_cons;
2570
2571         ASSERT_SERIALIZED(ifp->if_serializer);
2572
2573         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2574                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2575                 /*
2576                  * Process link state changes.
2577                  */
2578                 bnx_link_poll(sc);
2579         }
2580
2581         sc->bnx_status_tag = sblk->bge_status_tag;
2582
2583         /*
2584          * Use a load fence to ensure that status_tag is saved
2585          * before rx_prod and tx_cons.
2586          */
2587         cpu_lfence();
2588
2589         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2590         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2591
2592         if (ret->bnx_rx_saved_considx != rx_prod)
2593                 bnx_rxeof(ret, rx_prod, cycle);
2594
2595         if (txr->bnx_tx_saved_considx != tx_cons)
2596                 bnx_txeof(txr, tx_cons);
2597
2598         if (sc->bnx_coal_chg)
2599                 bnx_coal_change(sc);
2600 }
2601
2602 #endif  /* IFPOLL_ENABLE */
2603
2604 static void
2605 bnx_intr_legacy(void *xsc)
2606 {
2607         struct bnx_softc *sc = xsc;
2608         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2609
2610         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2611                 uint32_t val;
2612
2613                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2614                 if (val & BGE_PCISTAT_INTR_NOTACT)
2615                         return;
2616         }
2617
2618         /*
2619          * NOTE:
2620          * Interrupt will have to be disabled if tagged status
2621          * is used, else interrupt will always be asserted on
2622          * certain chips (at least on BCM5750 AX/BX).
2623          */
2624         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2625
2626         bnx_intr(sc);
2627 }
2628
2629 static void
2630 bnx_msi(void *xsc)
2631 {
2632         struct bnx_softc *sc = xsc;
2633
2634         /* Disable interrupt first */
2635         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2636         bnx_intr(sc);
2637 }
2638
2639 static void
2640 bnx_msi_oneshot(void *xsc)
2641 {
2642         bnx_intr(xsc);
2643 }
2644
2645 static void
2646 bnx_intr(struct bnx_softc *sc)
2647 {
2648         struct ifnet *ifp = &sc->arpcom.ac_if;
2649         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2650         uint16_t rx_prod, tx_cons;
2651         uint32_t status;
2652
2653         sc->bnx_status_tag = sblk->bge_status_tag;
2654         /*
2655          * Use a load fence to ensure that status_tag is saved 
2656          * before rx_prod, tx_cons and status.
2657          */
2658         cpu_lfence();
2659
2660         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2661         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2662         status = sblk->bge_status;
2663
2664         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2665                 bnx_link_poll(sc);
2666
2667         if (ifp->if_flags & IFF_RUNNING) {
2668                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2669                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; /* XXX */
2670
2671                 if (ret->bnx_rx_saved_considx != rx_prod)
2672                         bnx_rxeof(ret, rx_prod, -1);
2673
2674                 if (txr->bnx_tx_saved_considx != tx_cons)
2675                         bnx_txeof(txr, tx_cons);
2676         }
2677
2678         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2679
2680         if (sc->bnx_coal_chg)
2681                 bnx_coal_change(sc);
2682 }
2683
2684 static void
2685 bnx_tick(void *xsc)
2686 {
2687         struct bnx_softc *sc = xsc;
2688         struct ifnet *ifp = &sc->arpcom.ac_if;
2689
2690         lwkt_serialize_enter(ifp->if_serializer);
2691
2692         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2693
2694         bnx_stats_update_regs(sc);
2695
2696         if (sc->bnx_flags & BNX_FLAG_TBI) {
2697                 /*
2698                  * Since in TBI mode auto-polling can't be used we should poll
2699                  * link status manually. Here we register pending link event
2700                  * and trigger interrupt.
2701                  */
2702                 sc->bnx_link_evt++;
2703                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2704         } else if (!sc->bnx_link) {
2705                 mii_tick(device_get_softc(sc->bnx_miibus));
2706         }
2707
2708         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2709
2710         lwkt_serialize_exit(ifp->if_serializer);
2711 }
2712
2713 static void
2714 bnx_stats_update_regs(struct bnx_softc *sc)
2715 {
2716         struct ifnet *ifp = &sc->arpcom.ac_if;
2717         struct bge_mac_stats_regs stats;
2718         uint32_t *s;
2719         int i;
2720
2721         s = (uint32_t *)&stats;
2722         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2723                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2724                 s++;
2725         }
2726
2727         IFNET_STAT_SET(ifp, collisions,
2728            (stats.dot3StatsSingleCollisionFrames +
2729            stats.dot3StatsMultipleCollisionFrames +
2730            stats.dot3StatsExcessiveCollisions +
2731            stats.dot3StatsLateCollisions));
2732 }
2733
2734 /*
2735  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2736  * pointers to descriptors.
2737  */
2738 static int
2739 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
2740     int *segs_used)
2741 {
2742         struct bge_tx_bd *d = NULL;
2743         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2744         bus_dma_segment_t segs[BNX_NSEG_NEW];
2745         bus_dmamap_t map;
2746         int error, maxsegs, nsegs, idx, i;
2747         struct mbuf *m_head = *m_head0, *m_new;
2748
2749         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2750 #ifdef BNX_TSO_DEBUG
2751                 int tso_nsegs;
2752 #endif
2753
2754                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
2755                 if (error)
2756                         return error;
2757                 m_head = *m_head0;
2758
2759 #ifdef BNX_TSO_DEBUG
2760                 tso_nsegs = (m_head->m_pkthdr.len /
2761                     m_head->m_pkthdr.tso_segsz) - 1;
2762                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2763                         tso_nsegs = BNX_TSO_NSTATS - 1;
2764                 else if (tso_nsegs < 0)
2765                         tso_nsegs = 0;
2766                 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
2767 #endif
2768         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2769                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2770                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2771                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2772                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2773                 if (m_head->m_flags & M_LASTFRAG)
2774                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2775                 else if (m_head->m_flags & M_FRAG)
2776                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2777         }
2778         if (m_head->m_flags & M_VLANTAG) {
2779                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2780                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2781         }
2782
2783         idx = *txidx;
2784         map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
2785
2786         maxsegs = (BGE_TX_RING_CNT - txr->bnx_txcnt) - BNX_NSEG_RSVD;
2787         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2788                 ("not enough segments %d", maxsegs));
2789
2790         if (maxsegs > BNX_NSEG_NEW)
2791                 maxsegs = BNX_NSEG_NEW;
2792
2793         /*
2794          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2795          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2796          * but when such padded frames employ the bge IP/TCP checksum
2797          * offload, the hardware checksum assist gives incorrect results
2798          * (possibly from incorporating its own padding into the UDP/TCP
2799          * checksum; who knows).  If we pad such runts with zeros, the
2800          * onboard checksum comes out correct.
2801          */
2802         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2803             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2804                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2805                 if (error)
2806                         goto back;
2807         }
2808
2809         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
2810             m_head->m_next != NULL) {
2811                 m_new = bnx_defrag_shortdma(m_head);
2812                 if (m_new == NULL) {
2813                         error = ENOBUFS;
2814                         goto back;
2815                 }
2816                 *m_head0 = m_head = m_new;
2817         }
2818         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2819             (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
2820             m_head->m_next != NULL) {
2821                 /*
2822                  * Forcefully defragment mbuf chain to overcome hardware
2823                  * limitation which only support a single outstanding
2824                  * DMA read operation.  If it fails, keep moving on using
2825                  * the original mbuf chain.
2826                  */
2827                 m_new = m_defrag(m_head, MB_DONTWAIT);
2828                 if (m_new != NULL)
2829                         *m_head0 = m_head = m_new;
2830         }
2831
2832         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
2833             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2834         if (error)
2835                 goto back;
2836         *segs_used += nsegs;
2837
2838         m_head = *m_head0;
2839         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2840
2841         for (i = 0; ; i++) {
2842                 d = &txr->bnx_tx_ring[idx];
2843
2844                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2845                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2846                 d->bge_len = segs[i].ds_len;
2847                 d->bge_flags = csum_flags;
2848                 d->bge_vlan_tag = vlan_tag;
2849                 d->bge_mss = mss;
2850
2851                 if (i == nsegs - 1)
2852                         break;
2853                 BNX_INC(idx, BGE_TX_RING_CNT);
2854         }
2855         /* Mark the last segment as end of packet... */
2856         d->bge_flags |= BGE_TXBDFLAG_END;
2857
2858         /*
2859          * Insure that the map for this transmission is placed at
2860          * the array index of the last descriptor in this chain.
2861          */
2862         txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
2863         txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
2864         txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
2865         txr->bnx_txcnt += nsegs;
2866
2867         BNX_INC(idx, BGE_TX_RING_CNT);
2868         *txidx = idx;
2869 back:
2870         if (error) {
2871                 m_freem(*m_head0);
2872                 *m_head0 = NULL;
2873         }
2874         return error;
2875 }
2876
2877 /*
2878  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2879  * to the mbuf data regions directly in the transmit descriptors.
2880  */
2881 static void
2882 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2883 {
2884         struct bnx_softc *sc = ifp->if_softc;
2885         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2886         struct mbuf *m_head = NULL;
2887         uint32_t prodidx;
2888         int nsegs = 0;
2889
2890         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2891
2892         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2893                 return;
2894
2895         prodidx = txr->bnx_tx_prodidx;
2896
2897         while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
2898                 /*
2899                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2900                  * descriptors of the end of the ring.  Also make
2901                  * sure there are BGE_NSEG_SPARE descriptors for
2902                  * jumbo buffers' or TSO segments' defragmentation.
2903                  */
2904                 if ((BGE_TX_RING_CNT - txr->bnx_txcnt) <
2905                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2906                         ifq_set_oactive(&ifp->if_snd);
2907                         break;
2908                 }
2909
2910                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2911                 if (m_head == NULL)
2912                         break;
2913
2914                 /*
2915                  * Pack the data into the transmit ring. If we
2916                  * don't have room, set the OACTIVE flag and wait
2917                  * for the NIC to drain the ring.
2918                  */
2919                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
2920                         ifq_set_oactive(&ifp->if_snd);
2921                         IFNET_STAT_INC(ifp, oerrors, 1);
2922                         break;
2923                 }
2924
2925                 if (nsegs >= txr->bnx_tx_wreg) {
2926                         /* Transmit */
2927                         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
2928                         nsegs = 0;
2929                 }
2930
2931                 ETHER_BPF_MTAP(ifp, m_head);
2932
2933                 /*
2934                  * Set a timeout in case the chip goes out to lunch.
2935                  */
2936                 ifp->if_timer = 5;
2937         }
2938
2939         if (nsegs > 0) {
2940                 /* Transmit */
2941                 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
2942         }
2943         txr->bnx_tx_prodidx = prodidx;
2944 }
2945
2946 static void
2947 bnx_init(void *xsc)
2948 {
2949         struct bnx_softc *sc = xsc;
2950         struct ifnet *ifp = &sc->arpcom.ac_if;
2951         uint16_t *m;
2952         uint32_t mode;
2953         int i;
2954
2955         ASSERT_SERIALIZED(ifp->if_serializer);
2956
2957         /* Cancel pending I/O and flush buffers. */
2958         bnx_stop(sc);
2959         bnx_reset(sc);
2960         bnx_chipinit(sc);
2961
2962         /*
2963          * Init the various state machines, ring
2964          * control blocks and firmware.
2965          */
2966         if (bnx_blockinit(sc)) {
2967                 if_printf(ifp, "initialization failure\n");
2968                 bnx_stop(sc);
2969                 return;
2970         }
2971
2972         /* Specify MTU. */
2973         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2974             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2975
2976         /* Load our MAC address. */
2977         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2978         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2979         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2980
2981         /* Enable or disable promiscuous mode as needed. */
2982         bnx_setpromisc(sc);
2983
2984         /* Program multicast filter. */
2985         bnx_setmulti(sc);
2986
2987         /* Init RX ring. */
2988         if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) {
2989                 if_printf(ifp, "RX ring initialization failed\n");
2990                 bnx_stop(sc);
2991                 return;
2992         }
2993
2994         /* Init jumbo RX ring. */
2995         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2996                 if (bnx_init_rx_ring_jumbo(sc)) {
2997                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
2998                         bnx_stop(sc);
2999                         return;
3000                 }
3001         }
3002
3003         /* Init our RX return ring index */
3004         for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3005                 sc->bnx_rx_ret_ring[i].bnx_rx_saved_considx = 0;
3006
3007         /* Init TX ring. */
3008         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3009                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3010
3011         /* Enable TX MAC state machine lockup fix. */
3012         mode = CSR_READ_4(sc, BGE_TX_MODE);
3013         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3014         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3015             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3016                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3017                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3018                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3019         }
3020         /* Turn on transmitter */
3021         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3022
3023         /* Turn on receiver */
3024         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3025
3026         /*
3027          * Set the number of good frames to receive after RX MBUF
3028          * Low Watermark has been reached.  After the RX MAC receives
3029          * this number of frames, it will drop subsequent incoming
3030          * frames until the MBUF High Watermark is reached.
3031          */
3032         if (BNX_IS_57765_FAMILY(sc))
3033                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3034         else
3035                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3036
3037         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3038                 if (bootverbose) {
3039                         if_printf(ifp, "MSI_MODE: %#x\n",
3040                             CSR_READ_4(sc, BGE_MSI_MODE));
3041                 }
3042         }
3043
3044         /* Tell firmware we're alive. */
3045         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3046
3047         /* Enable host interrupts if polling(4) is not enabled. */
3048         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3049 #ifdef IFPOLL_ENABLE
3050         if (ifp->if_flags & IFF_NPOLLING)
3051                 bnx_disable_intr(sc);
3052         else
3053 #endif
3054         bnx_enable_intr(sc);
3055
3056         bnx_ifmedia_upd(ifp);
3057
3058         ifp->if_flags |= IFF_RUNNING;
3059         ifq_clr_oactive(&ifp->if_snd);
3060
3061         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3062             sc->bnx_stat_cpuid);
3063 }
3064
3065 /*
3066  * Set media options.
3067  */
3068 static int
3069 bnx_ifmedia_upd(struct ifnet *ifp)
3070 {
3071         struct bnx_softc *sc = ifp->if_softc;
3072
3073         /* If this is a 1000baseX NIC, enable the TBI port. */
3074         if (sc->bnx_flags & BNX_FLAG_TBI) {
3075                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3076
3077                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3078                         return(EINVAL);
3079
3080                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3081                 case IFM_AUTO:
3082                         break;
3083
3084                 case IFM_1000_SX:
3085                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3086                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3087                                     BGE_MACMODE_HALF_DUPLEX);
3088                         } else {
3089                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3090                                     BGE_MACMODE_HALF_DUPLEX);
3091                         }
3092                         break;
3093                 default:
3094                         return(EINVAL);
3095                 }
3096         } else {
3097                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3098
3099                 sc->bnx_link_evt++;
3100                 sc->bnx_link = 0;
3101                 if (mii->mii_instance) {
3102                         struct mii_softc *miisc;
3103
3104                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3105                                 mii_phy_reset(miisc);
3106                 }
3107                 mii_mediachg(mii);
3108
3109                 /*
3110                  * Force an interrupt so that we will call bnx_link_upd
3111                  * if needed and clear any pending link state attention.
3112                  * Without this we are not getting any further interrupts
3113                  * for link state changes and thus will not UP the link and
3114                  * not be able to send in bnx_start.  The only way to get
3115                  * things working was to receive a packet and get an RX
3116                  * intr.
3117                  *
3118                  * bnx_tick should help for fiber cards and we might not
3119                  * need to do this here if BNX_FLAG_TBI is set but as
3120                  * we poll for fiber anyway it should not harm.
3121                  */
3122                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3123         }
3124         return(0);
3125 }
3126
3127 /*
3128  * Report current media status.
3129  */
3130 static void
3131 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3132 {
3133         struct bnx_softc *sc = ifp->if_softc;
3134
3135         if (sc->bnx_flags & BNX_FLAG_TBI) {
3136                 ifmr->ifm_status = IFM_AVALID;
3137                 ifmr->ifm_active = IFM_ETHER;
3138                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3139                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3140                         ifmr->ifm_status |= IFM_ACTIVE;
3141                 } else {
3142                         ifmr->ifm_active |= IFM_NONE;
3143                         return;
3144                 }
3145
3146                 ifmr->ifm_active |= IFM_1000_SX;
3147                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3148                         ifmr->ifm_active |= IFM_HDX;    
3149                 else
3150                         ifmr->ifm_active |= IFM_FDX;
3151         } else {
3152                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3153
3154                 mii_pollstat(mii);
3155                 ifmr->ifm_active = mii->mii_media_active;
3156                 ifmr->ifm_status = mii->mii_media_status;
3157         }
3158 }
3159
3160 static int
3161 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3162 {
3163         struct bnx_softc *sc = ifp->if_softc;
3164         struct ifreq *ifr = (struct ifreq *)data;
3165         int mask, error = 0;
3166
3167         ASSERT_SERIALIZED(ifp->if_serializer);
3168
3169         switch (command) {
3170         case SIOCSIFMTU:
3171                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3172                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3173                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3174                         error = EINVAL;
3175                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3176                         ifp->if_mtu = ifr->ifr_mtu;
3177                         if (ifp->if_flags & IFF_RUNNING)
3178                                 bnx_init(sc);
3179                 }
3180                 break;
3181         case SIOCSIFFLAGS:
3182                 if (ifp->if_flags & IFF_UP) {
3183                         if (ifp->if_flags & IFF_RUNNING) {
3184                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3185
3186                                 /*
3187                                  * If only the state of the PROMISC flag
3188                                  * changed, then just use the 'set promisc
3189                                  * mode' command instead of reinitializing
3190                                  * the entire NIC. Doing a full re-init
3191                                  * means reloading the firmware and waiting
3192                                  * for it to start up, which may take a
3193                                  * second or two.  Similarly for ALLMULTI.
3194                                  */
3195                                 if (mask & IFF_PROMISC)
3196                                         bnx_setpromisc(sc);
3197                                 if (mask & IFF_ALLMULTI)
3198                                         bnx_setmulti(sc);
3199                         } else {
3200                                 bnx_init(sc);
3201                         }
3202                 } else if (ifp->if_flags & IFF_RUNNING) {
3203                         bnx_stop(sc);
3204                 }
3205                 sc->bnx_if_flags = ifp->if_flags;
3206                 break;
3207         case SIOCADDMULTI:
3208         case SIOCDELMULTI:
3209                 if (ifp->if_flags & IFF_RUNNING)
3210                         bnx_setmulti(sc);
3211                 break;
3212         case SIOCSIFMEDIA:
3213         case SIOCGIFMEDIA:
3214                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3215                         error = ifmedia_ioctl(ifp, ifr,
3216                             &sc->bnx_ifmedia, command);
3217                 } else {
3218                         struct mii_data *mii;
3219
3220                         mii = device_get_softc(sc->bnx_miibus);
3221                         error = ifmedia_ioctl(ifp, ifr,
3222                                               &mii->mii_media, command);
3223                 }
3224                 break;
3225         case SIOCSIFCAP:
3226                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3227                 if (mask & IFCAP_HWCSUM) {
3228                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3229                         if (ifp->if_capenable & IFCAP_TXCSUM)
3230                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3231                         else
3232                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3233                 }
3234                 if (mask & IFCAP_TSO) {
3235                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3236                         if (ifp->if_capenable & IFCAP_TSO)
3237                                 ifp->if_hwassist |= CSUM_TSO;
3238                         else
3239                                 ifp->if_hwassist &= ~CSUM_TSO;
3240                 }
3241                 break;
3242         default:
3243                 error = ether_ioctl(ifp, command, data);
3244                 break;
3245         }
3246         return error;
3247 }
3248
3249 static void
3250 bnx_watchdog(struct ifnet *ifp)
3251 {
3252         struct bnx_softc *sc = ifp->if_softc;
3253
3254         if_printf(ifp, "watchdog timeout -- resetting\n");
3255
3256         bnx_init(sc);
3257
3258         IFNET_STAT_INC(ifp, oerrors, 1);
3259
3260         if (!ifq_is_empty(&ifp->if_snd))
3261                 if_devstart(ifp);
3262 }
3263
3264 /*
3265  * Stop the adapter and free any mbufs allocated to the
3266  * RX and TX lists.
3267  */
3268 static void
3269 bnx_stop(struct bnx_softc *sc)
3270 {
3271         struct ifnet *ifp = &sc->arpcom.ac_if;
3272         int i;
3273
3274         ASSERT_SERIALIZED(ifp->if_serializer);
3275
3276         callout_stop(&sc->bnx_stat_timer);
3277
3278         /*
3279          * Disable all of the receiver blocks
3280          */
3281         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3282         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3283         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3284         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3285         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3286         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3287
3288         /*
3289          * Disable all of the transmit blocks
3290          */
3291         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3292         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3293         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3294         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3295         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3296         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3297
3298         /*
3299          * Shut down all of the memory managers and related
3300          * state machines.
3301          */
3302         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3303         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3304         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3305         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3306
3307         /* Disable host interrupts. */
3308         bnx_disable_intr(sc);
3309
3310         /*
3311          * Tell firmware we're shutting down.
3312          */
3313         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3314
3315         /* Free the RX lists. */
3316         bnx_free_rx_ring_std(&sc->bnx_rx_std_ring);
3317
3318         /* Free jumbo RX list. */
3319         if (BNX_IS_JUMBO_CAPABLE(sc))
3320                 bnx_free_rx_ring_jumbo(sc);
3321
3322         /* Free TX buffers. */
3323         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3324                 bnx_free_tx_ring(&sc->bnx_tx_ring[i]);
3325
3326         sc->bnx_status_tag = 0;
3327         sc->bnx_link = 0;
3328         sc->bnx_coal_chg = 0;
3329
3330         ifp->if_flags &= ~IFF_RUNNING;
3331         ifq_clr_oactive(&ifp->if_snd);
3332         ifp->if_timer = 0;
3333 }
3334
3335 /*
3336  * Stop all chip I/O so that the kernel's probe routines don't
3337  * get confused by errant DMAs when rebooting.
3338  */
3339 static void
3340 bnx_shutdown(device_t dev)
3341 {
3342         struct bnx_softc *sc = device_get_softc(dev);
3343         struct ifnet *ifp = &sc->arpcom.ac_if;
3344
3345         lwkt_serialize_enter(ifp->if_serializer);
3346         bnx_stop(sc);
3347         bnx_reset(sc);
3348         lwkt_serialize_exit(ifp->if_serializer);
3349 }
3350
3351 static int
3352 bnx_suspend(device_t dev)
3353 {
3354         struct bnx_softc *sc = device_get_softc(dev);
3355         struct ifnet *ifp = &sc->arpcom.ac_if;
3356
3357         lwkt_serialize_enter(ifp->if_serializer);
3358         bnx_stop(sc);
3359         lwkt_serialize_exit(ifp->if_serializer);
3360
3361         return 0;
3362 }
3363
3364 static int
3365 bnx_resume(device_t dev)
3366 {
3367         struct bnx_softc *sc = device_get_softc(dev);
3368         struct ifnet *ifp = &sc->arpcom.ac_if;
3369
3370         lwkt_serialize_enter(ifp->if_serializer);
3371
3372         if (ifp->if_flags & IFF_UP) {
3373                 bnx_init(sc);
3374
3375                 if (!ifq_is_empty(&ifp->if_snd))
3376                         if_devstart(ifp);
3377         }
3378
3379         lwkt_serialize_exit(ifp->if_serializer);
3380
3381         return 0;
3382 }
3383
3384 static void
3385 bnx_setpromisc(struct bnx_softc *sc)
3386 {
3387         struct ifnet *ifp = &sc->arpcom.ac_if;
3388
3389         if (ifp->if_flags & IFF_PROMISC)
3390                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3391         else
3392                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3393 }
3394
3395 static void
3396 bnx_dma_free(struct bnx_softc *sc)
3397 {
3398         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3399         int i;
3400
3401         /* Destroy RX return rings */
3402         if (sc->bnx_rx_ret_ring != NULL) {
3403                 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3404                         bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]);
3405                 kfree(sc->bnx_rx_ret_ring, M_DEVBUF);
3406         }
3407
3408         /* Destroy RX mbuf DMA stuffs. */
3409         if (std->bnx_rx_mtag != NULL) {
3410                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3411                         KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL);
3412                         bus_dmamap_destroy(std->bnx_rx_mtag,
3413                             std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3414                 }
3415                 bus_dma_tag_destroy(std->bnx_rx_mtag);
3416         }
3417
3418         /* Destroy standard RX ring */
3419         bnx_dma_block_free(std->bnx_rx_std_ring_tag,
3420             std->bnx_rx_std_ring_map, std->bnx_rx_std_ring);
3421
3422         /* Destroy TX rings */
3423         if (sc->bnx_tx_ring != NULL) {
3424                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3425                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3426                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3427         }
3428
3429         if (BNX_IS_JUMBO_CAPABLE(sc))
3430                 bnx_free_jumbo_mem(sc);
3431
3432         /* Destroy status block */
3433         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3434             sc->bnx_cdata.bnx_status_map,
3435             sc->bnx_ldata.bnx_status_block);
3436
3437         /* Destroy the parent tag */
3438         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3439                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3440 }
3441
3442 static int
3443 bnx_dma_alloc(device_t dev)
3444 {
3445         struct bnx_softc *sc = device_get_softc(dev);
3446         struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3447         int i, error, mbx;
3448
3449         /*
3450          * Allocate the parent bus DMA tag appropriate for PCI.
3451          *
3452          * All of the NetExtreme/NetLink controllers have 4GB boundary
3453          * DMA bug.
3454          * Whenever an address crosses a multiple of the 4GB boundary
3455          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3456          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3457          * state machine will lockup and cause the device to hang.
3458          */
3459         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3460             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3461             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3462             0, &sc->bnx_cdata.bnx_parent_tag);
3463         if (error) {
3464                 device_printf(dev, "could not create parent DMA tag\n");
3465                 return error;
3466         }
3467
3468         /*
3469          * Create DMA stuffs for status block.
3470          */
3471         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3472             &sc->bnx_cdata.bnx_status_tag,
3473             &sc->bnx_cdata.bnx_status_map,
3474             (void *)&sc->bnx_ldata.bnx_status_block,
3475             &sc->bnx_ldata.bnx_status_block_paddr);
3476         if (error) {
3477                 device_printf(dev, "could not create status block\n");
3478                 return error;
3479         }
3480
3481         /*
3482          * Create DMA tag and maps for RX mbufs.
3483          */
3484         std->bnx_sc = sc;
3485         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3486             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3487             NULL, NULL, MCLBYTES, 1, MCLBYTES,
3488             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag);
3489         if (error) {
3490                 device_printf(dev, "could not create RX mbuf DMA tag\n");
3491                 return error;
3492         }
3493
3494         for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) {
3495                 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK,
3496                     &std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3497                 if (error) {
3498                         int j;
3499
3500                         for (j = 0; j < i; ++j) {
3501                                 bus_dmamap_destroy(std->bnx_rx_mtag,
3502                                     std->bnx_rx_std_buf[j].bnx_rx_dmamap);
3503                         }
3504                         bus_dma_tag_destroy(std->bnx_rx_mtag);
3505                         std->bnx_rx_mtag = NULL;
3506
3507                         device_printf(dev,
3508                             "could not create %dth RX mbuf DMA map\n", i);
3509                         return error;
3510                 }
3511         }
3512
3513         /*
3514          * Create DMA stuffs for standard RX ring.
3515          */
3516         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3517             &std->bnx_rx_std_ring_tag,
3518             &std->bnx_rx_std_ring_map,
3519             (void *)&std->bnx_rx_std_ring,
3520             &std->bnx_rx_std_ring_paddr);
3521         if (error) {
3522                 device_printf(dev, "could not create std RX ring\n");
3523                 return error;
3524         }
3525
3526         /*
3527          * Create RX return rings
3528          */
3529         sc->bnx_rx_ret_ring = kmalloc_cachealign(
3530             sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, M_DEVBUF,
3531             M_WAITOK | M_ZERO);
3532         for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3533                 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3534
3535                 ret->bnx_sc = sc;
3536                 ret->bnx_std = std;
3537                 error = bnx_create_rx_ret_ring(ret);
3538                 if (error) {
3539                         device_printf(dev,
3540                             "could not create %dth RX ret ring\n", i);
3541                         return error;
3542                 }
3543         }
3544
3545         /*
3546          * Create TX rings
3547          */
3548         mbx = BGE_MBX_TX_HOST_PROD0_LO;
3549         sc->bnx_tx_ring = kmalloc_cachealign(
3550             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
3551             M_WAITOK | M_ZERO);
3552         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3553                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3554
3555                 txr->bnx_sc = sc;
3556                 txr->bnx_tx_mbx = mbx;
3557
3558                 if (mbx & 0x4)
3559                         mbx -= 0x4;
3560                 else
3561                         mbx += 0xc;
3562
3563                 error = bnx_create_tx_ring(txr);
3564                 if (error) {
3565                         device_printf(dev,
3566                             "could not create %dth TX ring\n", i);
3567                         return error;
3568                 }
3569         }
3570
3571         /*
3572          * Create jumbo buffer pool.
3573          */
3574         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3575                 error = bnx_alloc_jumbo_mem(sc);
3576                 if (error) {
3577                         device_printf(dev,
3578                             "could not create jumbo buffer pool\n");
3579                         return error;
3580                 }
3581         }
3582
3583         return 0;
3584 }
3585
3586 static int
3587 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3588                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3589 {
3590         bus_dmamem_t dmem;
3591         int error;
3592
3593         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3594                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3595                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3596         if (error)
3597                 return error;
3598
3599         *tag = dmem.dmem_tag;
3600         *map = dmem.dmem_map;
3601         *addr = dmem.dmem_addr;
3602         *paddr = dmem.dmem_busaddr;
3603
3604         return 0;
3605 }
3606
3607 static void
3608 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3609 {
3610         if (tag != NULL) {
3611                 bus_dmamap_unload(tag, map);
3612                 bus_dmamem_free(tag, addr, map);
3613                 bus_dma_tag_destroy(tag);
3614         }
3615 }
3616
3617 static void
3618 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3619 {
3620         struct ifnet *ifp = &sc->arpcom.ac_if;
3621
3622 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3623
3624         /*
3625          * Sometimes PCS encoding errors are detected in
3626          * TBI mode (on fiber NICs), and for some reason
3627          * the chip will signal them as link changes.
3628          * If we get a link change event, but the 'PCS
3629          * encoding error' bit in the MAC status register
3630          * is set, don't bother doing a link check.
3631          * This avoids spurious "gigabit link up" messages
3632          * that sometimes appear on fiber NICs during
3633          * periods of heavy traffic.
3634          */
3635         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3636                 if (!sc->bnx_link) {
3637                         sc->bnx_link++;
3638                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3639                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3640                                     BGE_MACMODE_TBI_SEND_CFGS);
3641                         }
3642                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3643
3644                         if (bootverbose)
3645                                 if_printf(ifp, "link UP\n");
3646
3647                         ifp->if_link_state = LINK_STATE_UP;
3648                         if_link_state_change(ifp);
3649                 }
3650         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3651                 if (sc->bnx_link) {
3652                         sc->bnx_link = 0;
3653
3654                         if (bootverbose)
3655                                 if_printf(ifp, "link DOWN\n");
3656
3657                         ifp->if_link_state = LINK_STATE_DOWN;
3658                         if_link_state_change(ifp);
3659                 }
3660         }
3661
3662 #undef PCS_ENCODE_ERR
3663
3664         /* Clear the attention. */
3665         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3666             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3667             BGE_MACSTAT_LINK_CHANGED);
3668 }
3669
3670 static void
3671 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3672 {
3673         struct ifnet *ifp = &sc->arpcom.ac_if;
3674         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3675
3676         mii_pollstat(mii);
3677         bnx_miibus_statchg(sc->bnx_dev);
3678
3679         if (bootverbose) {
3680                 if (sc->bnx_link)
3681                         if_printf(ifp, "link UP\n");
3682                 else
3683                         if_printf(ifp, "link DOWN\n");
3684         }
3685
3686         /* Clear the attention. */
3687         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3688             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3689             BGE_MACSTAT_LINK_CHANGED);
3690 }
3691
3692 static void
3693 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3694 {
3695         struct ifnet *ifp = &sc->arpcom.ac_if;
3696         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3697
3698         mii_pollstat(mii);
3699
3700         if (!sc->bnx_link &&
3701             (mii->mii_media_status & IFM_ACTIVE) &&
3702             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3703                 sc->bnx_link++;
3704                 if (bootverbose)
3705                         if_printf(ifp, "link UP\n");
3706         } else if (sc->bnx_link &&
3707             (!(mii->mii_media_status & IFM_ACTIVE) ||
3708             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3709                 sc->bnx_link = 0;
3710                 if (bootverbose)
3711                         if_printf(ifp, "link DOWN\n");
3712         }
3713
3714         /* Clear the attention. */
3715         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3716             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3717             BGE_MACSTAT_LINK_CHANGED);
3718 }
3719
3720 static int
3721 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3722 {
3723         struct bnx_softc *sc = arg1;
3724
3725         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3726             &sc->bnx_rx_coal_ticks,
3727             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3728             BNX_RX_COAL_TICKS_CHG);
3729 }
3730
3731 static int
3732 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3733 {
3734         struct bnx_softc *sc = arg1;
3735
3736         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3737             &sc->bnx_tx_coal_ticks,
3738             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3739             BNX_TX_COAL_TICKS_CHG);
3740 }
3741
3742 static int
3743 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3744 {
3745         struct bnx_softc *sc = arg1;
3746
3747         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3748             &sc->bnx_rx_coal_bds,
3749             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3750             BNX_RX_COAL_BDS_CHG);
3751 }
3752
3753 static int
3754 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3755 {
3756         struct bnx_softc *sc = arg1;
3757
3758         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3759             &sc->bnx_tx_coal_bds,
3760             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3761             BNX_TX_COAL_BDS_CHG);
3762 }
3763
3764 static int
3765 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3766 {
3767         struct bnx_softc *sc = arg1;
3768
3769         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3770             &sc->bnx_rx_coal_bds_int,
3771             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3772             BNX_RX_COAL_BDS_INT_CHG);
3773 }
3774
3775 static int
3776 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3777 {
3778         struct bnx_softc *sc = arg1;
3779
3780         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3781             &sc->bnx_tx_coal_bds_int,
3782             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3783             BNX_TX_COAL_BDS_INT_CHG);
3784 }
3785
3786 static int
3787 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3788     int coal_min, int coal_max, uint32_t coal_chg_mask)
3789 {
3790         struct bnx_softc *sc = arg1;
3791         struct ifnet *ifp = &sc->arpcom.ac_if;
3792         int error = 0, v;
3793
3794         lwkt_serialize_enter(ifp->if_serializer);
3795
3796         v = *coal;
3797         error = sysctl_handle_int(oidp, &v, 0, req);
3798         if (!error && req->newptr != NULL) {
3799                 if (v < coal_min || v > coal_max) {
3800                         error = EINVAL;
3801                 } else {
3802                         *coal = v;
3803                         sc->bnx_coal_chg |= coal_chg_mask;
3804                 }
3805         }
3806
3807         lwkt_serialize_exit(ifp->if_serializer);
3808         return error;
3809 }
3810
3811 static void
3812 bnx_coal_change(struct bnx_softc *sc)
3813 {
3814         struct ifnet *ifp = &sc->arpcom.ac_if;
3815
3816         ASSERT_SERIALIZED(ifp->if_serializer);
3817
3818         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3819                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3820                             sc->bnx_rx_coal_ticks);
3821                 DELAY(10);
3822                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3823
3824                 if (bootverbose) {
3825                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3826                                   sc->bnx_rx_coal_ticks);
3827                 }
3828         }
3829
3830         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3831                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3832                             sc->bnx_tx_coal_ticks);
3833                 DELAY(10);
3834                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3835
3836                 if (bootverbose) {
3837                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3838                                   sc->bnx_tx_coal_ticks);
3839                 }
3840         }
3841
3842         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3843                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3844                             sc->bnx_rx_coal_bds);
3845                 DELAY(10);
3846                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3847
3848                 if (bootverbose) {
3849                         if_printf(ifp, "rx_coal_bds -> %u\n",
3850                                   sc->bnx_rx_coal_bds);
3851                 }
3852         }
3853
3854         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3855                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3856                             sc->bnx_tx_coal_bds);
3857                 DELAY(10);
3858                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3859
3860                 if (bootverbose) {
3861                         if_printf(ifp, "tx_coal_bds -> %u\n",
3862                                   sc->bnx_tx_coal_bds);
3863                 }
3864         }
3865
3866         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3867                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3868                     sc->bnx_rx_coal_bds_int);
3869                 DELAY(10);
3870                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3871
3872                 if (bootverbose) {
3873                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3874                             sc->bnx_rx_coal_bds_int);
3875                 }
3876         }
3877
3878         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3879                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3880                     sc->bnx_tx_coal_bds_int);
3881                 DELAY(10);
3882                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3883
3884                 if (bootverbose) {
3885                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3886                             sc->bnx_tx_coal_bds_int);
3887                 }
3888         }
3889
3890         sc->bnx_coal_chg = 0;
3891 }
3892
3893 static void
3894 bnx_intr_check(void *xsc)
3895 {
3896         struct bnx_softc *sc = xsc;
3897         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
3898         struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0]; /* XXX */
3899         struct ifnet *ifp = &sc->arpcom.ac_if;
3900         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
3901
3902         lwkt_serialize_enter(ifp->if_serializer);
3903
3904         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
3905
3906         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
3907                 lwkt_serialize_exit(ifp->if_serializer);
3908                 return;
3909         }
3910
3911         if (sblk->bge_idx[0].bge_rx_prod_idx != ret->bnx_rx_saved_considx ||
3912             sblk->bge_idx[0].bge_tx_cons_idx != txr->bnx_tx_saved_considx) {
3913                 if (sc->bnx_rx_check_considx == ret->bnx_rx_saved_considx &&
3914                     sc->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
3915                         if (!sc->bnx_intr_maylose) {
3916                                 sc->bnx_intr_maylose = TRUE;
3917                                 goto done;
3918                         }
3919                         if (bootverbose)
3920                                 if_printf(ifp, "lost interrupt\n");
3921                         bnx_msi(sc);
3922                 }
3923         }
3924         sc->bnx_intr_maylose = FALSE;
3925         sc->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
3926         sc->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
3927
3928 done:
3929         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3930             bnx_intr_check, sc);
3931         lwkt_serialize_exit(ifp->if_serializer);
3932 }
3933
3934 static void
3935 bnx_enable_intr(struct bnx_softc *sc)
3936 {
3937         struct ifnet *ifp = &sc->arpcom.ac_if;
3938
3939         lwkt_serialize_handler_enable(ifp->if_serializer);
3940
3941         /*
3942          * Enable interrupt.
3943          */
3944         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3945         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3946                 /* XXX Linux driver */
3947                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3948         }
3949
3950         /*
3951          * Unmask the interrupt when we stop polling.
3952          */
3953         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3954             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3955
3956         /*
3957          * Trigger another interrupt, since above writing
3958          * to interrupt mailbox0 may acknowledge pending
3959          * interrupt.
3960          */
3961         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3962
3963         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
3964                 sc->bnx_intr_maylose = FALSE;
3965                 sc->bnx_rx_check_considx = 0;
3966                 sc->bnx_tx_check_considx = 0;
3967
3968                 if (bootverbose)
3969                         if_printf(ifp, "status tag bug workaround\n");
3970
3971                 /* 10ms check interval */
3972                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3973                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
3974         }
3975 }
3976
3977 static void
3978 bnx_disable_intr(struct bnx_softc *sc)
3979 {
3980         struct ifnet *ifp = &sc->arpcom.ac_if;
3981
3982         /*
3983          * Mask the interrupt when we start polling.
3984          */
3985         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3986             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3987
3988         /*
3989          * Acknowledge possible asserted interrupt.
3990          */
3991         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3992
3993         callout_stop(&sc->bnx_intr_timer);
3994         sc->bnx_intr_maylose = FALSE;
3995         sc->bnx_rx_check_considx = 0;
3996         sc->bnx_tx_check_considx = 0;
3997
3998         sc->bnx_npoll.ifpc_stcount = 0;
3999
4000         lwkt_serialize_handler_disable(ifp->if_serializer);
4001 }
4002
4003 static int
4004 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4005 {
4006         uint32_t mac_addr;
4007         int ret = 1;
4008
4009         mac_addr = bnx_readmem_ind(sc, 0x0c14);
4010         if ((mac_addr >> 16) == 0x484b) {
4011                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4012                 ether_addr[1] = (uint8_t)mac_addr;
4013                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4014                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4015                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4016                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4017                 ether_addr[5] = (uint8_t)mac_addr;
4018                 ret = 0;
4019         }
4020         return ret;
4021 }
4022
4023 static int
4024 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4025 {
4026         int mac_offset = BGE_EE_MAC_OFFSET;
4027
4028         if (BNX_IS_5717_PLUS(sc)) {
4029                 int f;
4030
4031                 f = pci_get_function(sc->bnx_dev);
4032                 if (f & 1)
4033 &nb