2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
166 vm_size_t mp_cth_mapsz;
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int need_hyperthreading_fixup;
222 static u_int logical_cpus;
223 u_int logical_cpus_mask;
225 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226 int current_postcode;
228 /** XXX FIXME: what system files declare these??? */
229 extern struct region_descriptor r_gdt, r_idt;
231 int bsp_apic_ready = 0; /* flags useability of BSP apic */
232 int mp_naps; /* # of Applications processors */
233 int mp_nbusses; /* # of busses */
235 int mp_napics; /* # of IO APICs */
237 vm_offset_t cpu_apic_address;
239 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
240 u_int32_t *io_apic_versions;
244 u_int32_t cpu_apic_versions[MAXCPU];
246 extern int64_t tsc_offsets[];
248 extern u_long ebda_addr;
251 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
255 * APIC ID logical/physical mapping structures.
256 * We oversize these to simplify boot-time config.
258 int cpu_num_to_apic_id[NAPICID];
260 int io_num_to_apic_id[NAPICID];
262 int apic_id_to_logical[NAPICID];
264 /* AP uses this during bootstrap. Do not staticize. */
269 * SMP page table page. Setup by locore to point to a page table
270 * page from which we allocate per-cpu privatespace areas io_apics,
274 #define IO_MAPPING_START_INDEX \
275 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277 extern pt_entry_t *SMPpt;
279 struct pcb stoppcbs[MAXCPU];
281 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
284 * Local data and functions.
287 static u_int boot_address;
288 static u_int base_memory;
289 static int mp_finish;
291 static long search_for_sig(u_int32_t target, int count);
292 static void mp_enable(u_int boot_addr);
294 static int mptable_probe(void);
295 static void mptable_hyperthread_fixup(u_int id_mask);
296 static void mptable_pass1(struct mptable_pos *);
297 static int mptable_pass2(struct mptable_pos *);
298 static void default_mp_table(int type);
299 static void fix_mp_table(void);
300 static void mptable_map(struct mptable_pos *, vm_paddr_t);
301 static void mptable_unmap(struct mptable_pos *);
303 static void setup_apic_irq_mapping(void);
304 static int apic_int_is_bus_type(int intr, int bus_type);
306 static int start_all_aps(u_int boot_addr);
308 static void install_ap_tramp(u_int boot_addr);
310 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
311 static int smitest(void);
313 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
314 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
315 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
316 static u_int bootMP_size;
319 * Calculate usable address in base memory for AP trampoline code.
322 mp_bootaddress(u_int basemem)
324 POSTCODE(MP_BOOTADDRESS_POST);
326 base_memory = basemem;
328 bootMP_size = mptramp_end - mptramp_start;
329 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
330 if (((basemem * 1024) - boot_address) < bootMP_size)
331 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
332 /* 3 levels of page table pages */
333 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
335 return mptramp_pagetables;
340 * Look for an Intel MP spec table (ie, SMP capable hardware).
349 * Make sure our SMPpt[] page table is big enough to hold all the
352 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
354 POSTCODE(MP_PROBE_POST);
356 /* see if EBDA exists */
357 if (ebda_addr != 0) {
358 /* search first 1K of EBDA */
359 target = (u_int32_t)ebda_addr;
360 if ((x = search_for_sig(target, 1024 / 4)) > 0)
363 /* last 1K of base memory, effective 'top of base' passed in */
364 target = (u_int32_t)(base_memory - 0x400);
365 if ((x = search_for_sig(target, 1024 / 4)) > 0)
369 /* search the BIOS */
370 target = (u_int32_t)BIOS_BASE;
371 if ((x = search_for_sig(target, BIOS_COUNT)) > 0)
380 * Startup the SMP processors.
385 POSTCODE(MP_START_POST);
386 mp_enable(boot_address);
391 * Print various information about the SMP system hardware and setup.
398 POSTCODE(MP_ANNOUNCE_POST);
400 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
401 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
402 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
403 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
404 for (x = 1; x <= mp_naps; ++x) {
405 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
406 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
407 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
411 for (x = 0; x < mp_napics; ++x) {
412 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
413 kprintf(", version: 0x%08x", io_apic_versions[x]);
414 kprintf(", at 0x%08lx\n", io_apic_address[x]);
417 kprintf(" Warning: APIC I/O disabled\n");
422 * AP cpu's call this to sync up protected mode.
424 * WARNING! %gs is not set up on entry. This routine sets up %gs.
430 int x, myid = bootAP;
432 struct mdglobaldata *md;
433 struct privatespace *ps;
435 ps = &CPU_prvspace[myid];
437 gdt_segs[GPROC0_SEL].ssd_base =
438 (long) &ps->mdglobaldata.gd_common_tss;
439 ps->mdglobaldata.mi.gd_prvspace = ps;
441 /* We fill the 32-bit segment descriptors */
442 for (x = 0; x < NGDT; x++) {
443 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
444 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
446 /* And now a 64-bit one */
447 ssdtosyssd(&gdt_segs[GPROC0_SEL],
448 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
450 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
451 r_gdt.rd_base = (long) &gdt[myid * NGDT];
452 lgdt(&r_gdt); /* does magic intra-segment return */
454 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
455 wrmsr(MSR_FSBASE, 0); /* User value */
456 wrmsr(MSR_GSBASE, (u_int64_t)ps);
457 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
463 mdcpu->gd_currentldt = _default_ldt;
466 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
467 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
469 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
471 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
473 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
475 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
476 md->gd_common_tssd = *md->gd_tss_gdt;
478 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
483 * Set to a known state:
484 * Set by mpboot.s: CR0_PG, CR0_PE
485 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
488 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
491 /* Set up the fast syscall stuff */
492 msr = rdmsr(MSR_EFER) | EFER_SCE;
493 wrmsr(MSR_EFER, msr);
494 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
495 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
496 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
497 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
498 wrmsr(MSR_STAR, msr);
499 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
501 pmap_set_opt(); /* PSE/4MB pages, etc */
503 /* Initialize the PAT MSR. */
507 /* set up CPU registers and state */
510 /* set up SSE/NX registers */
513 /* set up FPU state on the AP */
514 npxinit(__INITIAL_NPXCW__);
516 /* disable the APIC, just to be SURE */
517 lapic->svr &= ~APIC_SVR_ENABLE;
519 /* data returned to BSP */
520 cpu_apic_versions[0] = lapic->version;
523 /*******************************************************************
524 * local functions and data
528 * start the SMP system
531 mp_enable(u_int boot_addr)
538 vm_paddr_t mpfps_paddr;
539 struct mptable_pos mpt;
541 POSTCODE(MP_ENABLE_POST);
543 mpfps_paddr = mptable_probe();
544 if (mpfps_paddr == 0)
545 panic("mp_enable: mptable_probe failed\n");
547 mptable_map(&mpt, mpfps_paddr);
550 * We can safely map physical memory into SMPpt after
551 * mptable_pass1() completes.
555 if (cpu_apic_address == 0)
556 panic("mp_enable: no local apic!\n");
558 /* examine the MP table for needed info, uses physical addresses */
559 x = mptable_pass2(&mpt);
563 /* can't process default configs till the CPU APIC is pmapped */
567 /* post scan cleanup */
572 setup_apic_irq_mapping();
574 /* fill the LOGICAL io_apic_versions table */
575 for (apic = 0; apic < mp_napics; ++apic) {
576 ux = io_apic_read(apic, IOAPIC_VER);
577 io_apic_versions[apic] = ux;
578 io_apic_set_id(apic, IO_TO_ID(apic));
581 /* program each IO APIC in the system */
582 for (apic = 0; apic < mp_napics; ++apic)
583 if (io_apic_setup(apic) < 0)
584 panic("IO APIC setup failure");
589 * These are required for SMP operation
592 /* install a 'Spurious INTerrupt' vector */
593 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
594 SDT_SYSIGT, SEL_KPL, 0);
596 /* install an inter-CPU IPI for TLB invalidation */
597 setidt(XINVLTLB_OFFSET, Xinvltlb,
598 SDT_SYSIGT, SEL_KPL, 0);
600 /* install an inter-CPU IPI for IPIQ messaging */
601 setidt(XIPIQ_OFFSET, Xipiq,
602 SDT_SYSIGT, SEL_KPL, 0);
604 /* install a timer vector */
605 setidt(XTIMER_OFFSET, Xtimer,
606 SDT_SYSIGT, SEL_KPL, 0);
608 /* install an inter-CPU IPI for CPU stop/restart */
609 setidt(XCPUSTOP_OFFSET, Xcpustop,
610 SDT_SYSIGT, SEL_KPL, 0);
612 /* start each Application Processor */
613 start_all_aps(boot_addr);
618 * look for the MP spec signature
621 /* string defined by the Intel MP Spec as identifying the MP table */
622 #define MP_SIG 0x5f504d5f /* _MP_ */
623 #define NEXT(X) ((X) += 4)
625 search_for_sig(u_int32_t target, int count)
631 KKASSERT(target != 0);
633 map_size = count * sizeof(u_int32_t);
634 addr = pmap_mapdev((vm_paddr_t)target, map_size);
637 for (x = 0; x < count; NEXT(x)) {
638 if (addr[x] == MP_SIG) {
639 /* make array index a byte index */
640 ret = target + (x * sizeof(u_int32_t));
645 pmap_unmapdev((vm_offset_t)addr, map_size);
650 static basetable_entry basetable_entry_types[] =
652 {0, 20, "Processor"},
659 typedef struct BUSDATA {
661 enum busTypes bus_type;
664 typedef struct INTDATA {
674 typedef struct BUSTYPENAME {
679 static bus_type_name bus_type_table[] =
685 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"},
699 {UNKNOWN_BUSTYPE, "---"}
701 /* from MP spec v1.4, table 5-1 */
702 static int default_data[7][5] =
704 /* nbus, id0, type0, id1, type1 */
705 {1, 0, ISA, 255, 255},
706 {1, 0, EISA, 255, 255},
707 {1, 0, EISA, 255, 255},
708 {1, 0, MCA, 255, 255},
710 {2, 0, EISA, 1, PCI},
716 static bus_datum *bus_data;
719 /* the IO INT data, one entry per possible APIC INTerrupt */
720 static io_int *io_apic_ints;
724 static int processor_entry (proc_entry_ptr entry, int cpu);
725 static int bus_entry (bus_entry_ptr entry, int bus);
727 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
728 static int int_entry (int_entry_ptr entry, int intr);
730 static int lookup_bus_type (char *name);
734 * 1st pass on motherboard's Intel MP specification table.
737 * cpu_apic_address (common to all CPUs)
743 * need_hyperthreading_fixup
747 mptable_pass1(struct mptable_pos *mpt)
760 POSTCODE(MPTABLE_PASS1_POST);
763 KKASSERT(fps != NULL);
766 /* clear various tables */
767 for (x = 0; x < NAPICID; ++x) {
768 io_apic_address[x] = ~0; /* IO APIC address table */
772 /* init everything to empty */
781 /* check for use of 'default' configuration */
782 if (fps->mpfb1 != 0) {
783 /* use default addresses */
784 cpu_apic_address = DEFAULT_APIC_BASE;
786 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
789 /* fill in with defaults */
790 mp_naps = 2; /* includes BSP */
791 mp_nbusses = default_data[fps->mpfb1 - 1][0];
800 panic("MP Configuration Table Header MISSING!");
802 cpu_apic_address = (vm_offset_t) cth->apic_address;
804 /* walk the table, recording info of interest */
805 totalSize = cth->base_table_length - sizeof(struct MPCTH);
806 position = (u_char *) cth + sizeof(struct MPCTH);
807 count = cth->entry_count;
810 switch (type = *(u_char *) position) {
811 case 0: /* processor_entry */
812 if (((proc_entry_ptr)position)->cpu_flags
813 & PROCENTRY_FLAG_EN) {
816 ((proc_entry_ptr)position)->apic_id;
819 case 1: /* bus_entry */
822 case 2: /* io_apic_entry */
824 if (((io_apic_entry_ptr)position)->apic_flags
825 & IOAPICENTRY_FLAG_EN)
826 io_apic_address[mp_napics++] =
827 (vm_offset_t)((io_apic_entry_ptr)
828 position)->apic_address;
831 case 3: /* int_entry */
836 case 4: /* int_entry */
839 panic("mpfps Base Table HOSED!");
843 totalSize -= basetable_entry_types[type].length;
844 position = (uint8_t *)position +
845 basetable_entry_types[type].length;
849 /* qualify the numbers */
850 if (mp_naps > MAXCPU) {
851 kprintf("Warning: only using %d of %d available CPUs!\n",
856 /* See if we need to fixup HT logical CPUs. */
857 mptable_hyperthread_fixup(id_mask);
859 --mp_naps; /* subtract the BSP */
864 * 2nd pass on motherboard's Intel MP specification table.
868 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
869 * CPU_TO_ID(N), logical CPU to APIC ID table
870 * IO_TO_ID(N), logical IO to APIC ID table
875 mptable_pass2(struct mptable_pos *mpt)
877 struct PROCENTRY proc;
885 int apic, bus, cpu, intr;
888 POSTCODE(MPTABLE_PASS2_POST);
891 KKASSERT(fps != NULL);
893 /* Initialize fake proc entry for use with HT fixup. */
894 bzero(&proc, sizeof(proc));
896 proc.cpu_flags = PROCENTRY_FLAG_EN;
899 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
901 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
902 M_DEVBUF, M_WAITOK | M_ZERO);
903 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
906 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
910 for (i = 0; i < mp_napics; i++) {
911 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
915 /* clear various tables */
916 for (x = 0; x < NAPICID; ++x) {
917 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
919 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
920 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
924 /* clear bus data table */
925 for (x = 0; x < mp_nbusses; ++x)
926 bus_data[x].bus_id = 0xff;
929 /* clear IO APIC INT table */
930 for (x = 0; x < (nintrs + 1); ++x) {
931 io_apic_ints[x].int_type = 0xff;
932 io_apic_ints[x].int_vector = 0xff;
936 /* record whether PIC or virtual-wire mode */
937 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
939 /* check for use of 'default' configuration */
941 return fps->mpfb1; /* return default configuration type */
945 panic("MP Configuration Table Header MISSING!");
947 /* walk the table, recording info of interest */
948 totalSize = cth->base_table_length - sizeof(struct MPCTH);
949 position = (u_char *) cth + sizeof(struct MPCTH);
950 count = cth->entry_count;
951 apic = bus = intr = 0;
952 cpu = 1; /* pre-count the BSP */
955 switch (type = *(u_char *) position) {
957 if (processor_entry(position, cpu))
960 if (need_hyperthreading_fixup) {
962 * Create fake mptable processor entries
963 * and feed them to processor_entry() to
964 * enumerate the logical CPUs.
966 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
967 for (i = 1; i < logical_cpus; i++) {
969 processor_entry(&proc, cpu);
970 logical_cpus_mask |= (1 << cpu);
976 if (bus_entry(position, bus))
981 if (io_apic_entry(position, apic))
987 if (int_entry(position, intr))
992 /* int_entry(position); */
995 panic("mpfps Base Table HOSED!");
999 totalSize -= basetable_entry_types[type].length;
1000 position = (uint8_t *)position + basetable_entry_types[type].length;
1003 if (CPU_TO_ID(0) < 0)
1004 panic("NO BSP found!");
1006 /* report fact that its NOT a default configuration */
1012 * Check if we should perform a hyperthreading "fix-up" to
1013 * enumerate any logical CPU's that aren't already listed
1016 * XXX: We assume that all of the physical CPUs in the
1017 * system have the same number of logical CPUs.
1019 * XXX: We assume that APIC ID's are allocated such that
1020 * the APIC ID's for a physical processor are aligned
1021 * with the number of logical CPU's in the processor.
1024 mptable_hyperthread_fixup(u_int id_mask)
1028 /* Nothing to do if there is no HTT support. */
1029 if ((cpu_feature & CPUID_HTT) == 0)
1031 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1032 if (logical_cpus <= 1)
1036 * For each APIC ID of a CPU that is set in the mask,
1037 * scan the other candidate APIC ID's for this
1038 * physical processor. If any of those ID's are
1039 * already in the table, then kill the fixup.
1041 for (id = 0; id <= MAXCPU; id++) {
1042 if ((id_mask & 1 << id) == 0)
1044 /* First, make sure we are on a logical_cpus boundary. */
1045 if (id % logical_cpus != 0)
1047 for (i = id + 1; i < id + logical_cpus; i++)
1048 if ((id_mask & 1 << i) != 0)
1053 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1054 * mp_naps right now.
1056 need_hyperthreading_fixup = 1;
1057 mp_naps *= logical_cpus;
1061 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1065 vm_size_t cth_mapsz = 0;
1067 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1068 if (fps->pap != 0) {
1070 * Map configuration table header to get
1071 * the base table size
1073 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1074 cth_mapsz = cth->base_table_length;
1075 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1078 * Map the base table
1080 cth = pmap_mapdev(fps->pap, cth_mapsz);
1085 mpt->mp_cth_mapsz = cth_mapsz;
1089 mptable_unmap(struct mptable_pos *mpt)
1091 if (mpt->mp_cth != NULL) {
1092 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1094 mpt->mp_cth_mapsz = 0;
1096 if (mpt->mp_fps != NULL) {
1097 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1105 assign_apic_irq(int apic, int intpin, int irq)
1109 if (int_to_apicintpin[irq].ioapic != -1)
1110 panic("assign_apic_irq: inconsistent table");
1112 int_to_apicintpin[irq].ioapic = apic;
1113 int_to_apicintpin[irq].int_pin = intpin;
1114 int_to_apicintpin[irq].apic_address = ioapic[apic];
1115 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1117 for (x = 0; x < nintrs; x++) {
1118 if ((io_apic_ints[x].int_type == 0 ||
1119 io_apic_ints[x].int_type == 3) &&
1120 io_apic_ints[x].int_vector == 0xff &&
1121 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1122 io_apic_ints[x].dst_apic_int == intpin)
1123 io_apic_ints[x].int_vector = irq;
1128 revoke_apic_irq(int irq)
1134 if (int_to_apicintpin[irq].ioapic == -1)
1135 panic("revoke_apic_irq: inconsistent table");
1137 oldapic = int_to_apicintpin[irq].ioapic;
1138 oldintpin = int_to_apicintpin[irq].int_pin;
1140 int_to_apicintpin[irq].ioapic = -1;
1141 int_to_apicintpin[irq].int_pin = 0;
1142 int_to_apicintpin[irq].apic_address = NULL;
1143 int_to_apicintpin[irq].redirindex = 0;
1145 for (x = 0; x < nintrs; x++) {
1146 if ((io_apic_ints[x].int_type == 0 ||
1147 io_apic_ints[x].int_type == 3) &&
1148 io_apic_ints[x].int_vector != 0xff &&
1149 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1150 io_apic_ints[x].dst_apic_int == oldintpin)
1151 io_apic_ints[x].int_vector = 0xff;
1159 allocate_apic_irq(int intr)
1165 if (io_apic_ints[intr].int_vector != 0xff)
1166 return; /* Interrupt handler already assigned */
1168 if (io_apic_ints[intr].int_type != 0 &&
1169 (io_apic_ints[intr].int_type != 3 ||
1170 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1171 io_apic_ints[intr].dst_apic_int == 0)))
1172 return; /* Not INT or ExtInt on != (0, 0) */
1175 while (irq < APIC_INTMAPSIZE &&
1176 int_to_apicintpin[irq].ioapic != -1)
1179 if (irq >= APIC_INTMAPSIZE)
1180 return; /* No free interrupt handlers */
1182 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1183 intpin = io_apic_ints[intr].dst_apic_int;
1185 assign_apic_irq(apic, intpin, irq);
1190 swap_apic_id(int apic, int oldid, int newid)
1197 return; /* Nothing to do */
1199 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1200 apic, oldid, newid);
1202 /* Swap physical APIC IDs in interrupt entries */
1203 for (x = 0; x < nintrs; x++) {
1204 if (io_apic_ints[x].dst_apic_id == oldid)
1205 io_apic_ints[x].dst_apic_id = newid;
1206 else if (io_apic_ints[x].dst_apic_id == newid)
1207 io_apic_ints[x].dst_apic_id = oldid;
1210 /* Swap physical APIC IDs in IO_TO_ID mappings */
1211 for (oapic = 0; oapic < mp_napics; oapic++)
1212 if (IO_TO_ID(oapic) == newid)
1215 if (oapic < mp_napics) {
1216 kprintf("Changing APIC ID for IO APIC #%d from "
1217 "%d to %d in MP table\n",
1218 oapic, newid, oldid);
1219 IO_TO_ID(oapic) = oldid;
1221 IO_TO_ID(apic) = newid;
1226 fix_id_to_io_mapping(void)
1230 for (x = 0; x < NAPICID; x++)
1233 for (x = 0; x <= mp_naps; x++)
1234 if (CPU_TO_ID(x) < NAPICID)
1235 ID_TO_IO(CPU_TO_ID(x)) = x;
1237 for (x = 0; x < mp_napics; x++)
1238 if (IO_TO_ID(x) < NAPICID)
1239 ID_TO_IO(IO_TO_ID(x)) = x;
1244 first_free_apic_id(void)
1248 for (freeid = 0; freeid < NAPICID; freeid++) {
1249 for (x = 0; x <= mp_naps; x++)
1250 if (CPU_TO_ID(x) == freeid)
1254 for (x = 0; x < mp_napics; x++)
1255 if (IO_TO_ID(x) == freeid)
1266 io_apic_id_acceptable(int apic, int id)
1268 int cpu; /* Logical CPU number */
1269 int oapic; /* Logical IO APIC number for other IO APIC */
1272 return 0; /* Out of range */
1274 for (cpu = 0; cpu <= mp_naps; cpu++)
1275 if (CPU_TO_ID(cpu) == id)
1276 return 0; /* Conflict with CPU */
1278 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1279 if (IO_TO_ID(oapic) == id)
1280 return 0; /* Conflict with other APIC */
1282 return 1; /* ID is acceptable for IO APIC */
1287 io_apic_find_int_entry(int apic, int pin)
1291 /* search each of the possible INTerrupt sources */
1292 for (x = 0; x < nintrs; ++x) {
1293 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1294 (pin == io_apic_ints[x].dst_apic_int))
1295 return (&io_apic_ints[x]);
1303 * parse an Intel MP specification table
1311 int apic; /* IO APIC unit number */
1312 int freeid; /* Free physical APIC ID */
1313 int physid; /* Current physical IO APIC ID */
1316 int bus_0 = 0; /* Stop GCC warning */
1317 int bus_pci = 0; /* Stop GCC warning */
1321 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1322 * did it wrong. The MP spec says that when more than 1 PCI bus
1323 * exists the BIOS must begin with bus entries for the PCI bus and use
1324 * actual PCI bus numbering. This implies that when only 1 PCI bus
1325 * exists the BIOS can choose to ignore this ordering, and indeed many
1326 * MP motherboards do ignore it. This causes a problem when the PCI
1327 * sub-system makes requests of the MP sub-system based on PCI bus
1328 * numbers. So here we look for the situation and renumber the
1329 * busses and associated INTs in an effort to "make it right".
1332 /* find bus 0, PCI bus, count the number of PCI busses */
1333 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1334 if (bus_data[x].bus_id == 0) {
1337 if (bus_data[x].bus_type == PCI) {
1343 * bus_0 == slot of bus with ID of 0
1344 * bus_pci == slot of last PCI bus encountered
1347 /* check the 1 PCI bus case for sanity */
1348 /* if it is number 0 all is well */
1349 if (num_pci_bus == 1 &&
1350 bus_data[bus_pci].bus_id != 0) {
1352 /* mis-numbered, swap with whichever bus uses slot 0 */
1354 /* swap the bus entry types */
1355 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1356 bus_data[bus_0].bus_type = PCI;
1359 /* swap each relavant INTerrupt entry */
1360 id = bus_data[bus_pci].bus_id;
1361 for (x = 0; x < nintrs; ++x) {
1362 if (io_apic_ints[x].src_bus_id == id) {
1363 io_apic_ints[x].src_bus_id = 0;
1365 else if (io_apic_ints[x].src_bus_id == 0) {
1366 io_apic_ints[x].src_bus_id = id;
1373 /* Assign IO APIC IDs.
1375 * First try the existing ID. If a conflict is detected, try
1376 * the ID in the MP table. If a conflict is still detected, find
1379 * We cannot use the ID_TO_IO table before all conflicts has been
1380 * resolved and the table has been corrected.
1382 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1384 /* First try to use the value set by the BIOS */
1385 physid = io_apic_get_id(apic);
1386 if (io_apic_id_acceptable(apic, physid)) {
1387 if (IO_TO_ID(apic) != physid)
1388 swap_apic_id(apic, IO_TO_ID(apic), physid);
1392 /* Then check if the value in the MP table is acceptable */
1393 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1396 /* Last resort, find a free APIC ID and use it */
1397 freeid = first_free_apic_id();
1398 if (freeid >= NAPICID)
1399 panic("No free physical APIC IDs found");
1401 if (io_apic_id_acceptable(apic, freeid)) {
1402 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1405 panic("Free physical APIC ID not usable");
1407 fix_id_to_io_mapping();
1411 /* detect and fix broken Compaq MP table */
1412 if (apic_int_type(0, 0) == -1) {
1413 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1414 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1415 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1416 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1417 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1418 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1420 } else if (apic_int_type(0, 0) == 0) {
1421 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1422 for (x = 0; x < nintrs; ++x)
1423 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1424 (0 == io_apic_ints[x].dst_apic_int)) {
1425 io_apic_ints[x].int_type = 3;
1426 io_apic_ints[x].int_vector = 0xff;
1432 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1433 * controllers universally come in pairs. If IRQ 14 is specified
1434 * as an ISA interrupt, then IRQ 15 had better be too.
1436 * [ Shuttle XPC / AMD Athlon X2 ]
1437 * The MPTable is missing an entry for IRQ 15. Note that the
1438 * ACPI table has an entry for both 14 and 15.
1440 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1441 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1442 io14 = io_apic_find_int_entry(0, 14);
1443 io_apic_ints[nintrs] = *io14;
1444 io_apic_ints[nintrs].src_bus_irq = 15;
1445 io_apic_ints[nintrs].dst_apic_int = 15;
1453 /* Assign low level interrupt handlers */
1455 setup_apic_irq_mapping(void)
1461 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1462 int_to_apicintpin[x].ioapic = -1;
1463 int_to_apicintpin[x].int_pin = 0;
1464 int_to_apicintpin[x].apic_address = NULL;
1465 int_to_apicintpin[x].redirindex = 0;
1468 /* First assign ISA/EISA interrupts */
1469 for (x = 0; x < nintrs; x++) {
1470 int_vector = io_apic_ints[x].src_bus_irq;
1471 if (int_vector < APIC_INTMAPSIZE &&
1472 io_apic_ints[x].int_vector == 0xff &&
1473 int_to_apicintpin[int_vector].ioapic == -1 &&
1474 (apic_int_is_bus_type(x, ISA) ||
1475 apic_int_is_bus_type(x, EISA)) &&
1476 io_apic_ints[x].int_type == 0) {
1477 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1478 io_apic_ints[x].dst_apic_int,
1483 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1484 for (x = 0; x < nintrs; x++) {
1485 if (io_apic_ints[x].dst_apic_int == 0 &&
1486 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1487 io_apic_ints[x].int_vector == 0xff &&
1488 int_to_apicintpin[0].ioapic == -1 &&
1489 io_apic_ints[x].int_type == 3) {
1490 assign_apic_irq(0, 0, 0);
1495 /* Assign PCI interrupts */
1496 for (x = 0; x < nintrs; ++x) {
1497 if (io_apic_ints[x].int_type == 0 &&
1498 io_apic_ints[x].int_vector == 0xff &&
1499 apic_int_is_bus_type(x, PCI))
1500 allocate_apic_irq(x);
1507 processor_entry(proc_entry_ptr entry, int cpu)
1511 /* check for usability */
1512 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1515 if(entry->apic_id >= NAPICID)
1516 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1517 /* check for BSP flag */
1518 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1519 CPU_TO_ID(0) = entry->apic_id;
1520 ID_TO_CPU(entry->apic_id) = 0;
1521 return 0; /* its already been counted */
1524 /* add another AP to list, if less than max number of CPUs */
1525 else if (cpu < MAXCPU) {
1526 CPU_TO_ID(cpu) = entry->apic_id;
1527 ID_TO_CPU(entry->apic_id) = cpu;
1536 bus_entry(bus_entry_ptr entry, int bus)
1541 /* encode the name into an index */
1542 for (x = 0; x < 6; ++x) {
1543 if ((c = entry->bus_type[x]) == ' ')
1549 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1550 panic("unknown bus type: '%s'", name);
1552 bus_data[bus].bus_id = entry->bus_id;
1553 bus_data[bus].bus_type = x;
1561 io_apic_entry(io_apic_entry_ptr entry, int apic)
1563 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1566 IO_TO_ID(apic) = entry->apic_id;
1567 if (entry->apic_id < NAPICID)
1568 ID_TO_IO(entry->apic_id) = apic;
1576 lookup_bus_type(char *name)
1580 for (x = 0; x < MAX_BUSTYPE; ++x)
1581 if (strcmp(bus_type_table[x].name, name) == 0)
1582 return bus_type_table[x].type;
1584 return UNKNOWN_BUSTYPE;
1590 int_entry(int_entry_ptr entry, int intr)
1594 io_apic_ints[intr].int_type = entry->int_type;
1595 io_apic_ints[intr].int_flags = entry->int_flags;
1596 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1597 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1598 if (entry->dst_apic_id == 255) {
1599 /* This signal goes to all IO APICS. Select an IO APIC
1600 with sufficient number of interrupt pins */
1601 for (apic = 0; apic < mp_napics; apic++)
1602 if (((io_apic_read(apic, IOAPIC_VER) &
1603 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1604 entry->dst_apic_int)
1606 if (apic < mp_napics)
1607 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1609 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1611 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1612 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1618 apic_int_is_bus_type(int intr, int bus_type)
1622 for (bus = 0; bus < mp_nbusses; ++bus)
1623 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1624 && ((int) bus_data[bus].bus_type == bus_type))
1631 * Given a traditional ISA INT mask, return an APIC mask.
1634 isa_apic_mask(u_int isa_mask)
1639 #if defined(SKIP_IRQ15_REDIRECT)
1640 if (isa_mask == (1 << 15)) {
1641 kprintf("skipping ISA IRQ15 redirect\n");
1644 #endif /* SKIP_IRQ15_REDIRECT */
1646 isa_irq = ffs(isa_mask); /* find its bit position */
1647 if (isa_irq == 0) /* doesn't exist */
1649 --isa_irq; /* make it zero based */
1651 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1655 return (1 << apic_pin); /* convert pin# to a mask */
1659 * Determine which APIC pin an ISA/EISA INT is attached to.
1661 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1662 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1663 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1664 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1666 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1668 isa_apic_irq(int isa_irq)
1672 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1673 if (INTTYPE(intr) == 0) { /* standard INT */
1674 if (SRCBUSIRQ(intr) == isa_irq) {
1675 if (apic_int_is_bus_type(intr, ISA) ||
1676 apic_int_is_bus_type(intr, EISA)) {
1677 if (INTIRQ(intr) == 0xff)
1678 return -1; /* unassigned */
1679 return INTIRQ(intr); /* found */
1684 return -1; /* NOT found */
1689 * Determine which APIC pin a PCI INT is attached to.
1691 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1692 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1693 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1695 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1699 --pciInt; /* zero based */
1701 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1702 if ((INTTYPE(intr) == 0) /* standard INT */
1703 && (SRCBUSID(intr) == pciBus)
1704 && (SRCBUSDEVICE(intr) == pciDevice)
1705 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1706 if (apic_int_is_bus_type(intr, PCI)) {
1707 if (INTIRQ(intr) == 0xff) {
1708 kprintf("IOAPIC: pci_apic_irq() "
1710 return -1; /* unassigned */
1712 return INTIRQ(intr); /* exact match */
1717 return -1; /* NOT found */
1721 next_apic_irq(int irq)
1728 for (intr = 0; intr < nintrs; intr++) {
1729 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1731 bus = SRCBUSID(intr);
1732 bustype = apic_bus_type(bus);
1733 if (bustype != ISA &&
1739 if (intr >= nintrs) {
1742 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1743 if (INTTYPE(ointr) != 0)
1745 if (bus != SRCBUSID(ointr))
1747 if (bustype == PCI) {
1748 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1750 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1753 if (bustype == ISA || bustype == EISA) {
1754 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1757 if (INTPIN(intr) == INTPIN(ointr))
1761 if (ointr >= nintrs) {
1764 return INTIRQ(ointr);
1779 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1782 * Exactly what this means is unclear at this point. It is a solution
1783 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1784 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1785 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1789 undirect_isa_irq(int rirq)
1793 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1794 /** FIXME: tickle the MB redirector chip */
1798 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1805 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1808 undirect_pci_irq(int rirq)
1812 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1814 /** FIXME: tickle the MB redirector chip */
1818 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1826 * given a bus ID, return:
1827 * the bus type if found
1831 apic_bus_type(int id)
1835 for (x = 0; x < mp_nbusses; ++x)
1836 if (bus_data[x].bus_id == id)
1837 return bus_data[x].bus_type;
1845 * given a LOGICAL APIC# and pin#, return:
1846 * the associated src bus ID if found
1850 apic_src_bus_id(int apic, int pin)
1854 /* search each of the possible INTerrupt sources */
1855 for (x = 0; x < nintrs; ++x)
1856 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1857 (pin == io_apic_ints[x].dst_apic_int))
1858 return (io_apic_ints[x].src_bus_id);
1860 return -1; /* NOT found */
1864 * given a LOGICAL APIC# and pin#, return:
1865 * the associated src bus IRQ if found
1869 apic_src_bus_irq(int apic, int pin)
1873 for (x = 0; x < nintrs; x++)
1874 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1875 (pin == io_apic_ints[x].dst_apic_int))
1876 return (io_apic_ints[x].src_bus_irq);
1878 return -1; /* NOT found */
1883 * given a LOGICAL APIC# and pin#, return:
1884 * the associated INTerrupt type if found
1888 apic_int_type(int apic, int pin)
1892 /* search each of the possible INTerrupt sources */
1893 for (x = 0; x < nintrs; ++x) {
1894 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1895 (pin == io_apic_ints[x].dst_apic_int))
1896 return (io_apic_ints[x].int_type);
1898 return -1; /* NOT found */
1902 * Return the IRQ associated with an APIC pin
1905 apic_irq(int apic, int pin)
1910 for (x = 0; x < nintrs; ++x) {
1911 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1912 (pin == io_apic_ints[x].dst_apic_int)) {
1913 res = io_apic_ints[x].int_vector;
1916 if (apic != int_to_apicintpin[res].ioapic)
1917 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1918 if (pin != int_to_apicintpin[res].int_pin)
1919 panic("apic_irq inconsistent table (2)");
1928 * given a LOGICAL APIC# and pin#, return:
1929 * the associated trigger mode if found
1933 apic_trigger(int apic, int pin)
1937 /* search each of the possible INTerrupt sources */
1938 for (x = 0; x < nintrs; ++x)
1939 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1940 (pin == io_apic_ints[x].dst_apic_int))
1941 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1943 return -1; /* NOT found */
1948 * given a LOGICAL APIC# and pin#, return:
1949 * the associated 'active' level if found
1953 apic_polarity(int apic, int pin)
1957 /* search each of the possible INTerrupt sources */
1958 for (x = 0; x < nintrs; ++x)
1959 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1960 (pin == io_apic_ints[x].dst_apic_int))
1961 return (io_apic_ints[x].int_flags & 0x03);
1963 return -1; /* NOT found */
1969 * set data according to MP defaults
1970 * FIXME: probably not complete yet...
1973 default_mp_table(int type)
1975 int ap_cpu_id, boot_cpu_id;
1976 #if defined(APIC_IO)
1979 #endif /* APIC_IO */
1982 kprintf(" MP default config type: %d\n", type);
1985 kprintf(" bus: ISA, APIC: 82489DX\n");
1988 kprintf(" bus: EISA, APIC: 82489DX\n");
1991 kprintf(" bus: EISA, APIC: 82489DX\n");
1994 kprintf(" bus: MCA, APIC: 82489DX\n");
1997 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2000 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2003 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2006 kprintf(" future type\n");
2012 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
2013 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2016 CPU_TO_ID(0) = boot_cpu_id;
2017 ID_TO_CPU(boot_cpu_id) = 0;
2019 /* one and only AP */
2020 CPU_TO_ID(1) = ap_cpu_id;
2021 ID_TO_CPU(ap_cpu_id) = 1;
2023 #if defined(APIC_IO)
2024 /* one and only IO APIC */
2025 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2028 * sanity check, refer to MP spec section 3.6.6, last paragraph
2029 * necessary as some hardware isn't properly setting up the IO APIC
2031 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2032 if (io_apic_id != 2) {
2034 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2035 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2036 io_apic_set_id(0, 2);
2039 IO_TO_ID(0) = io_apic_id;
2040 ID_TO_IO(io_apic_id) = 0;
2041 #endif /* APIC_IO */
2043 /* fill out bus entries */
2052 bus_data[0].bus_id = default_data[type - 1][1];
2053 bus_data[0].bus_type = default_data[type - 1][2];
2054 bus_data[1].bus_id = default_data[type - 1][3];
2055 bus_data[1].bus_type = default_data[type - 1][4];
2058 /* case 4: case 7: MCA NOT supported */
2059 default: /* illegal/reserved */
2060 panic("BAD default MP config: %d", type);
2064 #if defined(APIC_IO)
2065 /* general cases from MP v1.4, table 5-2 */
2066 for (pin = 0; pin < 16; ++pin) {
2067 io_apic_ints[pin].int_type = 0;
2068 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2069 io_apic_ints[pin].src_bus_id = 0;
2070 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2071 io_apic_ints[pin].dst_apic_id = io_apic_id;
2072 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2075 /* special cases from MP v1.4, table 5-2 */
2077 io_apic_ints[2].int_type = 0xff; /* N/C */
2078 io_apic_ints[13].int_type = 0xff; /* N/C */
2079 #if !defined(APIC_MIXED_MODE)
2081 panic("sorry, can't support type 2 default yet");
2082 #endif /* APIC_MIXED_MODE */
2085 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2088 io_apic_ints[0].int_type = 0xff; /* N/C */
2090 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2091 #endif /* APIC_IO */
2095 * Map a physical memory address representing I/O into KVA. The I/O
2096 * block is assumed not to cross a page boundary.
2099 permanent_io_mapping(vm_paddr_t pa)
2101 KKASSERT(pa < 0x100000000LL);
2103 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2107 * start each AP in our list
2110 start_all_aps(u_int boot_addr)
2112 vm_offset_t va = boot_address + KERNBASE;
2113 u_int64_t *pt4, *pt3, *pt2;
2119 u_char mpbiosreason;
2120 u_long mpbioswarmvec;
2121 struct mdglobaldata *gd;
2122 struct privatespace *ps;
2124 POSTCODE(START_ALL_APS_POST);
2126 /* Initialize BSP's local APIC */
2127 apic_initialize(TRUE);
2130 /* install the AP 1st level boot code */
2131 pmap_kenter(va, boot_address);
2132 cpu_invlpg((void *)va); /* JG XXX */
2133 bcopy(mptramp_start, (void *)va, bootMP_size);
2135 /* Locate the page tables, they'll be below the trampoline */
2136 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2137 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2138 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2140 /* Create the initial 1GB replicated page tables */
2141 for (i = 0; i < 512; i++) {
2142 /* Each slot of the level 4 pages points to the same level 3 page */
2143 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2144 pt4[i] |= PG_V | PG_RW | PG_U;
2146 /* Each slot of the level 3 pages points to the same level 2 page */
2147 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2148 pt3[i] |= PG_V | PG_RW | PG_U;
2150 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2151 pt2[i] = i * (2 * 1024 * 1024);
2152 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2155 /* save the current value of the warm-start vector */
2156 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2157 outb(CMOS_REG, BIOS_RESET);
2158 mpbiosreason = inb(CMOS_DATA);
2160 /* setup a vector to our boot code */
2161 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2162 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2163 outb(CMOS_REG, BIOS_RESET);
2164 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2167 * If we have a TSC we can figure out the SMI interrupt rate.
2168 * The SMI does not necessarily use a constant rate. Spend
2169 * up to 250ms trying to figure it out.
2172 if (cpu_feature & CPUID_TSC) {
2173 set_apic_timer(275000);
2174 smilast = read_apic_timer();
2175 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2176 smicount = smitest();
2177 if (smibest == 0 || smilast - smicount < smibest)
2178 smibest = smilast - smicount;
2181 if (smibest > 250000)
2184 smibest = smibest * (int64_t)1000000 /
2185 get_apic_timer_frequency();
2189 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2190 1000000 / smibest, smibest);
2193 for (x = 1; x <= mp_naps; ++x) {
2195 /* This is a bit verbose, it will go away soon. */
2197 /* first page of AP's private space */
2198 pg = x * x86_64_btop(sizeof(struct privatespace));
2200 /* allocate new private data page(s) */
2201 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2202 MDGLOBALDATA_BASEALLOC_SIZE);
2204 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2205 bzero(gd, sizeof(*gd));
2206 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2208 /* prime data page for it to use */
2209 mi_gdinit(&gd->mi, x);
2211 gd->gd_CMAP1 = &SMPpt[pg + 0];
2212 gd->gd_CMAP2 = &SMPpt[pg + 1];
2213 gd->gd_CMAP3 = &SMPpt[pg + 2];
2214 gd->gd_PMAP1 = &SMPpt[pg + 3];
2215 gd->gd_CADDR1 = ps->CPAGE1;
2216 gd->gd_CADDR2 = ps->CPAGE2;
2217 gd->gd_CADDR3 = ps->CPAGE3;
2218 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2219 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2220 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2222 /* setup a vector to our boot code */
2223 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2224 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2225 outb(CMOS_REG, BIOS_RESET);
2226 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2229 * Setup the AP boot stack
2231 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2234 /* attempt to start the Application Processor */
2235 CHECK_INIT(99); /* setup checkpoints */
2236 if (!start_ap(gd, boot_addr, smibest)) {
2237 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2238 CHECK_PRINT("trace"); /* show checkpoints */
2239 /* better panic as the AP may be running loose */
2240 kprintf("panic y/n? [y] ");
2241 if (cngetc() != 'n')
2244 CHECK_PRINT("trace"); /* show checkpoints */
2246 /* record its version info */
2247 cpu_apic_versions[x] = cpu_apic_versions[0];
2250 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2253 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2254 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2257 ncpus2_shift = shift;
2258 ncpus2 = 1 << shift;
2259 ncpus2_mask = ncpus2 - 1;
2261 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2262 if ((1 << shift) < ncpus)
2264 ncpus_fit = 1 << shift;
2265 ncpus_fit_mask = ncpus_fit - 1;
2267 /* build our map of 'other' CPUs */
2268 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2269 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2270 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2272 /* fill in our (BSP) APIC version */
2273 cpu_apic_versions[0] = lapic->version;
2275 /* restore the warmstart vector */
2276 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2277 outb(CMOS_REG, BIOS_RESET);
2278 outb(CMOS_DATA, mpbiosreason);
2281 * NOTE! The idlestack for the BSP was setup by locore. Finish
2282 * up, clean out the P==V mapping we did earlier.
2286 /* number of APs actually started */
2292 * load the 1st level AP boot code into base memory.
2295 /* targets for relocation */
2296 extern void bigJump(void);
2297 extern void bootCodeSeg(void);
2298 extern void bootDataSeg(void);
2299 extern void MPentry(void);
2300 extern u_int MP_GDT;
2301 extern u_int mp_gdtbase;
2306 install_ap_tramp(u_int boot_addr)
2309 int size = *(int *) ((u_long) & bootMP_size);
2310 u_char *src = (u_char *) ((u_long) bootMP);
2311 u_char *dst = (u_char *) boot_addr + KERNBASE;
2312 u_int boot_base = (u_int) bootMP;
2317 POSTCODE(INSTALL_AP_TRAMP_POST);
2319 for (x = 0; x < size; ++x)
2323 * modify addresses in code we just moved to basemem. unfortunately we
2324 * need fairly detailed info about mpboot.s for this to work. changes
2325 * to mpboot.s might require changes here.
2328 /* boot code is located in KERNEL space */
2329 dst = (u_char *) boot_addr + KERNBASE;
2331 /* modify the lgdt arg */
2332 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2333 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2335 /* modify the ljmp target for MPentry() */
2336 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2337 *dst32 = ((u_int) MPentry - KERNBASE);
2339 /* modify the target for boot code segment */
2340 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2341 dst8 = (u_int8_t *) (dst16 + 1);
2342 *dst16 = (u_int) boot_addr & 0xffff;
2343 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2345 /* modify the target for boot data segment */
2346 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2347 dst8 = (u_int8_t *) (dst16 + 1);
2348 *dst16 = (u_int) boot_addr & 0xffff;
2349 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2355 * This function starts the AP (application processor) identified
2356 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2357 * to accomplish this. This is necessary because of the nuances
2358 * of the different hardware we might encounter. It ain't pretty,
2359 * but it seems to work.
2361 * NOTE: eventually an AP gets to ap_init(), which is called just
2362 * before the AP goes into the LWKT scheduler's idle loop.
2365 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2369 u_long icr_lo, icr_hi;
2371 POSTCODE(START_AP_POST);
2373 /* get the PHYSICAL APIC ID# */
2374 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2376 /* calculate the vector */
2377 vector = (boot_addr >> 12) & 0xff;
2379 /* We don't want anything interfering */
2382 /* Make sure the target cpu sees everything */
2386 * Try to detect when a SMI has occurred, wait up to 200ms.
2388 * If a SMI occurs during an AP reset but before we issue
2389 * the STARTUP command, the AP may brick. To work around
2390 * this problem we hold off doing the AP startup until
2391 * after we have detected the SMI. Hopefully another SMI
2392 * will not occur before we finish the AP startup.
2394 * Retries don't seem to help. SMIs have a window of opportunity
2395 * and if USB->legacy keyboard emulation is enabled in the BIOS
2396 * the interrupt rate can be quite high.
2398 * NOTE: Don't worry about the L1 cache load, it might bloat
2399 * ldelta a little but ndelta will be so huge when the SMI
2400 * occurs the detection logic will still work fine.
2403 set_apic_timer(200000);
2408 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2409 * and running the target CPU. OR this INIT IPI might be latched (P5
2410 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2413 * see apic/apicreg.h for icr bit definitions.
2415 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2419 * Setup the address for the target AP. We can setup
2420 * icr_hi once and then just trigger operations with
2423 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2424 icr_hi |= (physical_cpu << 24);
2425 icr_lo = lapic->icr_lo & 0xfff00000;
2426 lapic->icr_hi = icr_hi;
2429 * Do an INIT IPI: assert RESET
2431 * Use edge triggered mode to assert INIT
2433 lapic->icr_lo = icr_lo | 0x00004500;
2434 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2438 * The spec calls for a 10ms delay but we may have to use a
2439 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2440 * interrupt. We have other loops here too and dividing by 2
2441 * doesn't seem to be enough even after subtracting 350us,
2442 * so we divide by 4.
2444 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2445 * interrupt was detected we use the full 10ms.
2449 else if (smibest < 150 * 4 + 350)
2451 else if ((smibest - 350) / 4 < 10000)
2452 u_sleep((smibest - 350) / 4);
2457 * Do an INIT IPI: deassert RESET
2459 * Use level triggered mode to deassert. It is unclear
2460 * why we need to do this.
2462 lapic->icr_lo = icr_lo | 0x00008500;
2463 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2465 u_sleep(150); /* wait 150us */
2468 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2469 * latched, (P5 bug) this 1st STARTUP would then terminate
2470 * immediately, and the previously started INIT IPI would continue. OR
2471 * the previous INIT IPI has already run. and this STARTUP IPI will
2472 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2475 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2476 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2478 u_sleep(200); /* wait ~200uS */
2481 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2482 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2483 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2484 * recognized after hardware RESET or INIT IPI.
2486 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2487 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2490 /* Resume normal operation */
2493 /* wait for it to start, see ap_init() */
2494 set_apic_timer(5000000);/* == 5 seconds */
2495 while (read_apic_timer()) {
2496 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2497 return 1; /* return SUCCESS */
2500 return 0; /* return FAILURE */
2515 while (read_apic_timer()) {
2517 for (count = 0; count < 100; ++count)
2518 ntsc = rdtsc(); /* force loop to occur */
2520 ndelta = ntsc - ltsc;
2521 if (ldelta > ndelta)
2523 if (ndelta > ldelta * 2)
2526 ldelta = ntsc - ltsc;
2529 return(read_apic_timer());
2533 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2535 * If for some reason we were unable to start all cpus we cannot safely
2536 * use broadcast IPIs.
2542 if (smp_startup_mask == smp_active_mask) {
2543 all_but_self_ipi(XINVLTLB_OFFSET);
2545 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2546 APIC_DELMODE_FIXED);
2552 * When called the executing CPU will send an IPI to all other CPUs
2553 * requesting that they halt execution.
2555 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2557 * - Signals all CPUs in map to stop.
2558 * - Waits for each to stop.
2565 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2566 * from executing at same time.
2569 stop_cpus(u_int map)
2571 map &= smp_active_mask;
2573 /* send the Xcpustop IPI to all CPUs in map */
2574 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2576 while ((stopped_cpus & map) != map)
2584 * Called by a CPU to restart stopped CPUs.
2586 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2588 * - Signals all CPUs in map to restart.
2589 * - Waits for each to restart.
2597 restart_cpus(u_int map)
2599 /* signal other cpus to restart */
2600 started_cpus = map & smp_active_mask;
2602 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2609 * This is called once the mpboot code has gotten us properly relocated
2610 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2611 * and when it returns the scheduler will call the real cpu_idle() main
2612 * loop for the idlethread. Interrupts are disabled on entry and should
2613 * remain disabled at return.
2621 * Adjust smp_startup_mask to signal the BSP that we have started
2622 * up successfully. Note that we do not yet hold the BGL. The BSP
2623 * is waiting for our signal.
2625 * We can't set our bit in smp_active_mask yet because we are holding
2626 * interrupts physically disabled and remote cpus could deadlock
2627 * trying to send us an IPI.
2629 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2633 * Interlock for finalization. Wait until mp_finish is non-zero,
2634 * then get the MP lock.
2636 * Note: We are in a critical section.
2638 * Note: We have to synchronize td_mpcount to our desired MP state
2639 * before calling cpu_try_mplock().
2641 * Note: we are the idle thread, we can only spin.
2643 * Note: The load fence is memory volatile and prevents the compiler
2644 * from improperly caching mp_finish, and the cpu from improperly
2647 while (mp_finish == 0)
2649 ++curthread->td_mpcount;
2650 while (cpu_try_mplock() == 0)
2653 if (cpu_feature & CPUID_TSC) {
2655 * The BSP is constantly updating tsc0_offset, figure out the
2656 * relative difference to synchronize ktrdump.
2658 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2661 /* BSP may have changed PTD while we're waiting for the lock */
2664 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2668 /* Build our map of 'other' CPUs. */
2669 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2671 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2673 /* A quick check from sanity claus */
2674 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2675 if (mycpu->gd_cpuid != apic_id) {
2676 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2677 kprintf("SMP: apic_id = %d\n", apic_id);
2679 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2681 panic("cpuid mismatch! boom!!");
2684 /* Initialize AP's local APIC for irq's */
2685 apic_initialize(FALSE);
2687 /* Set memory range attributes for this CPU to match the BSP */
2688 mem_range_AP_init();
2691 * Once we go active we must process any IPIQ messages that may
2692 * have been queued, because no actual IPI will occur until we
2693 * set our bit in the smp_active_mask. If we don't the IPI
2694 * message interlock could be left set which would also prevent
2697 * The idle loop doesn't expect the BGL to be held and while
2698 * lwkt_switch() normally cleans things up this is a special case
2699 * because we returning almost directly into the idle loop.
2701 * The idle thread is never placed on the runq, make sure
2702 * nothing we've done put it there.
2704 KKASSERT(curthread->td_mpcount == 1);
2705 smp_active_mask |= 1 << mycpu->gd_cpuid;
2708 * Enable interrupts here. idle_restore will also do it, but
2709 * doing it here lets us clean up any strays that got posted to
2710 * the CPU during the AP boot while we are still in a critical
2713 __asm __volatile("sti; pause; pause"::);
2714 mdcpu->gd_fpending = 0;
2716 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2717 lwkt_process_ipiq();
2720 * Releasing the mp lock lets the BSP finish up the SMP init
2723 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2727 * Get SMP fully working before we start initializing devices.
2735 kprintf("Finish MP startup\n");
2736 if (cpu_feature & CPUID_TSC)
2737 tsc0_offset = rdtsc();
2740 while (smp_active_mask != smp_startup_mask) {
2742 if (cpu_feature & CPUID_TSC)
2743 tsc0_offset = rdtsc();
2745 while (try_mplock() == 0)
2748 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2751 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2754 cpu_send_ipiq(int dcpu)
2756 if ((1 << dcpu) & smp_active_mask)
2757 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2760 #if 0 /* single_apic_ipi_passive() not working yet */
2762 * Returns 0 on failure, 1 on success
2765 cpu_send_ipiq_passive(int dcpu)
2768 if ((1 << dcpu) & smp_active_mask) {
2769 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2770 APIC_DELMODE_FIXED);