sys/dev/netif/et/if_et.c

   1 /*
   2  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  */
  35
  36 #include <sys/param.h>
  37 #include <sys/bitops.h>
  38 #include <sys/endian.h>
  39 #include <sys/kernel.h>
  40 #include <sys/bus.h>
  41 #include <sys/interrupt.h>
  42 #include <sys/malloc.h>
  43 #include <sys/proc.h>
  44 #include <sys/rman.h>
  45 #include <sys/serialize.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49
  50 #include <net/ethernet.h>
  51 #include <net/if.h>
  52 #include <net/bpf.h>
  53 #include <net/if_arp.h>
  54 #include <net/if_dl.h>
  55 #include <net/if_media.h>
  56 #include <net/ifq_var.h>
  57 #include <net/vlan/if_vlan_var.h>
  58
  59 #include <dev/netif/mii_layer/miivar.h>
  60
  61 #include <bus/pci/pcireg.h>
  62 #include <bus/pci/pcivar.h>
  63 #include <bus/pci/pcidevs.h>
  64
  65 #include <dev/netif/et/if_etreg.h>
  66 #include <dev/netif/et/if_etvar.h>
  67
  68 #include "miibus_if.h"
  69
  70 static int      et_probe(device_t);
  71 static int      et_attach(device_t);
  72 static int      et_detach(device_t);
  73 static int      et_shutdown(device_t);
  74
  75 static int      et_miibus_readreg(device_t, int, int);
  76 static int      et_miibus_writereg(device_t, int, int, int);
  77 static void     et_miibus_statchg(device_t);
  78
  79 static void     et_init(void *);
  80 static int      et_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
  81 static void     et_start(struct ifnet *);
  82 static void     et_watchdog(struct ifnet *);
  83 static int      et_ifmedia_upd(struct ifnet *);
  84 static void     et_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  85
  86 static int      et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS);
  87 static int      et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS);
  88
  89 static void     et_intr(void *);
  90 static void     et_enable_intrs(struct et_softc *, uint32_t);
  91 static void     et_disable_intrs(struct et_softc *);
  92 static void     et_rxeof(struct et_softc *);
  93 static void     et_txeof(struct et_softc *, int);
  94
  95 static int      et_dma_alloc(device_t);
  96 static void     et_dma_free(device_t);
  97 static void     et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t);
  98 static int      et_dma_mbuf_create(device_t);
  99 static void     et_dma_mbuf_destroy(device_t, int, const int[]);
 100 static int      et_jumbo_mem_alloc(device_t);
 101 static void     et_jumbo_mem_free(device_t);
 102 static int      et_init_tx_ring(struct et_softc *);
 103 static int      et_init_rx_ring(struct et_softc *);
 104 static void     et_free_tx_ring(struct et_softc *);
 105 static void     et_free_rx_ring(struct et_softc *);
 106 static int      et_encap(struct et_softc *, struct mbuf **);
 107 static struct et_jslot *
 108                 et_jalloc(struct et_jumbo_data *);
 109 static void     et_jfree(void *);
 110 static void     et_jref(void *);
 111 static int      et_newbuf(struct et_rxbuf_data *, int, int, int);
 112 static int      et_newbuf_cluster(struct et_rxbuf_data *, int, int);
 113 static int      et_newbuf_hdr(struct et_rxbuf_data *, int, int);
 114 static int      et_newbuf_jumbo(struct et_rxbuf_data *, int, int);
 115
 116 static void     et_stop(struct et_softc *);
 117 static int      et_chip_init(struct et_softc *);
 118 static void     et_chip_attach(struct et_softc *);
 119 static void     et_init_mac(struct et_softc *);
 120 static void     et_init_rxmac(struct et_softc *);
 121 static void     et_init_txmac(struct et_softc *);
 122 static int      et_init_rxdma(struct et_softc *);
 123 static int      et_init_txdma(struct et_softc *);
 124 static int      et_start_rxdma(struct et_softc *);
 125 static int      et_start_txdma(struct et_softc *);
 126 static int      et_stop_rxdma(struct et_softc *);
 127 static int      et_stop_txdma(struct et_softc *);
 128 static int      et_enable_txrx(struct et_softc *, int);
 129 static void     et_reset(struct et_softc *);
 130 static int      et_bus_config(device_t);
 131 static void     et_get_eaddr(device_t, uint8_t[]);
 132 static void     et_setmulti(struct et_softc *);
 133 static void     et_tick(void *);
 134 static void     et_setmedia(struct et_softc *);
 135 static void     et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t);
 136
 137 static const struct et_dev {
 138         uint16_t        vid;
 139         uint16_t        did;
 140         const char      *desc;
 141 } et_devices[] = {
 142         { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310,
 143           "Agere ET1310 Gigabit Ethernet" },
 144         { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST,
 145           "Agere ET1310 Fast Ethernet" },
 146         { 0, 0, NULL }
 147 };
 148
 149 static device_method_t et_methods[] = {
 150         DEVMETHOD(device_probe,         et_probe),
 151         DEVMETHOD(device_attach,        et_attach),
 152         DEVMETHOD(device_detach,        et_detach),
 153         DEVMETHOD(device_shutdown,      et_shutdown),
 154 #if 0
 155         DEVMETHOD(device_suspend,       et_suspend),
 156         DEVMETHOD(device_resume,        et_resume),
 157 #endif
 158
 159         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 160         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 161
 162         DEVMETHOD(miibus_readreg,       et_miibus_readreg),
 163         DEVMETHOD(miibus_writereg,      et_miibus_writereg),
 164         DEVMETHOD(miibus_statchg,       et_miibus_statchg),
 165
 166         { 0, 0 }
 167 };
 168
 169 static driver_t et_driver = {
 170         "et",
 171         et_methods,
 172         sizeof(struct et_softc)
 173 };
 174
 175 static devclass_t et_devclass;
 176
 177 DECLARE_DUMMY_MODULE(if_et);
 178 MODULE_DEPEND(if_et, miibus, 1, 1, 1);
 179 DRIVER_MODULE(if_et, pci, et_driver, et_devclass, NULL, NULL);
 180 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, NULL, NULL);
 181
 182 static int      et_rx_intr_npkts = 129;
 183 static int      et_rx_intr_delay = 25;          /* x4 usec */
 184 static int      et_tx_intr_nsegs = 256;
 185 static uint32_t et_timer = 1000 * 1000 * 1000;  /* nanosec */
 186
 187 TUNABLE_INT("hw.et.timer", &et_timer);
 188 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts);
 189 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay);
 190 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs);
 191
 192 struct et_bsize {
 193         int             bufsize;
 194         int             jumbo;
 195         et_newbuf_t     newbuf;
 196 };
 197
 198 static const struct et_bsize    et_bufsize_std[ET_RX_NRING] = {
 199         { .bufsize = ET_RXDMA_CTRL_RING0_128,   .jumbo = 0,
 200           .newbuf = et_newbuf_hdr },
 201         { .bufsize = ET_RXDMA_CTRL_RING1_2048,  .jumbo = 0,
 202           .newbuf = et_newbuf_cluster },
 203 };
 204
 205 static const struct et_bsize    et_bufsize_jumbo[ET_RX_NRING] = {
 206         { .bufsize = ET_RXDMA_CTRL_RING0_128,   .jumbo = 0,
 207           .newbuf = et_newbuf_hdr },
 208         { .bufsize = ET_RXDMA_CTRL_RING1_16384, .jumbo = 1,
 209           .newbuf = et_newbuf_jumbo },
 210 };
 211
 212 static int
 213 et_probe(device_t dev)
 214 {
 215         const struct et_dev *d;
 216         uint16_t did, vid;
 217
 218         vid = pci_get_vendor(dev);
 219         did = pci_get_device(dev);
 220
 221         for (d = et_devices; d->desc != NULL; ++d) {
 222                 if (vid == d->vid && did == d->did) {
 223                         device_set_desc(dev, d->desc);
 224                         return 0;
 225                 }
 226         }
 227         return ENXIO;
 228 }
 229
 230 static int
 231 et_attach(device_t dev)
 232 {
 233         struct et_softc *sc = device_get_softc(dev);
 234         struct ifnet *ifp = &sc->arpcom.ac_if;
 235         uint8_t eaddr[ETHER_ADDR_LEN];
 236         int error;
 237
 238         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 239         callout_init(&sc->sc_tick);
 240
 241         /*
 242          * Initialize tunables
 243          */
 244         sc->sc_rx_intr_npkts = et_rx_intr_npkts;
 245         sc->sc_rx_intr_delay = et_rx_intr_delay;
 246         sc->sc_tx_intr_nsegs = et_tx_intr_nsegs;
 247         sc->sc_timer = et_timer;
 248
 249 #ifndef BURN_BRIDGES
 250         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 251                 uint32_t irq, mem;
 252
 253                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 254                 mem = pci_read_config(dev, ET_PCIR_BAR, 4);
 255
 256                 device_printf(dev, "chip is in D%d power mode "
 257                     "-- setting to D0\n", pci_get_powerstate(dev));
 258
 259                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 260
 261                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 262                 pci_write_config(dev, ET_PCIR_BAR, mem, 4);
 263         }
 264 #endif  /* !BURN_BRIDGE */
 265
 266         /* Enable bus mastering */
 267         pci_enable_busmaster(dev);
 268
 269         /*
 270          * Allocate IO memory
 271          */
 272         sc->sc_mem_rid = ET_PCIR_BAR;
 273         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 274                                                 &sc->sc_mem_rid, RF_ACTIVE);
 275         if (sc->sc_mem_res == NULL) {
 276                 device_printf(dev, "can't allocate IO memory\n");
 277                 return ENXIO;
 278         }
 279         sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
 280         sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
 281
 282         /*
 283          * Allocate IRQ
 284          */
 285         sc->sc_irq_rid = 0;
 286         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 287                                                 &sc->sc_irq_rid,
 288                                                 RF_SHAREABLE | RF_ACTIVE);
 289         if (sc->sc_irq_res == NULL) {
 290                 device_printf(dev, "can't allocate irq\n");
 291                 error = ENXIO;
 292                 goto fail;
 293         }
 294
 295         /*
 296          * Create sysctl tree
 297          */
 298         sysctl_ctx_init(&sc->sc_sysctl_ctx);
 299         sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
 300                                              SYSCTL_STATIC_CHILDREN(_hw),
 301                                              OID_AUTO,
 302                                              device_get_nameunit(dev),
 303                                              CTLFLAG_RD, 0, "");
 304         if (sc->sc_sysctl_tree == NULL) {
 305                 device_printf(dev, "can't add sysctl node\n");
 306                 error = ENXIO;
 307                 goto fail;
 308         }
 309
 310         SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
 311                         SYSCTL_CHILDREN(sc->sc_sysctl_tree),
 312                         OID_AUTO, "rx_intr_npkts", CTLTYPE_INT | CTLFLAG_RW,
 313                         sc, 0, et_sysctl_rx_intr_npkts, "I",
 314                         "RX IM, # packets per RX interrupt");
 315         SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
 316                         SYSCTL_CHILDREN(sc->sc_sysctl_tree),
 317                         OID_AUTO, "rx_intr_delay", CTLTYPE_INT | CTLFLAG_RW,
 318                         sc, 0, et_sysctl_rx_intr_delay, "I",
 319                         "RX IM, RX interrupt delay (x10 usec)");
 320         SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
 321                        SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
 322                        "tx_intr_nsegs", CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0,
 323                        "TX IM, # segments per TX interrupt");
 324         SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
 325                         SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
 326                         "timer", CTLFLAG_RW, &sc->sc_timer, 0,
 327                         "TX timer");
 328
 329         error = et_bus_config(dev);
 330         if (error)
 331                 goto fail;
 332
 333         et_get_eaddr(dev, eaddr);
 334
 335         CSR_WRITE_4(sc, ET_PM,
 336                     ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE);
 337
 338         et_reset(sc);
 339
 340         et_disable_intrs(sc);
 341
 342         error = et_dma_alloc(dev);
 343         if (error)
 344                 goto fail;
 345
 346         ifp->if_softc = sc;
 347         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 348         ifp->if_init = et_init;
 349         ifp->if_ioctl = et_ioctl;
 350         ifp->if_start = et_start;
 351         ifp->if_watchdog = et_watchdog;
 352         ifp->if_mtu = ETHERMTU;
 353         ifp->if_capabilities = IFCAP_VLAN_MTU;
 354         ifp->if_capenable = ifp->if_capabilities;
 355         ifq_set_maxlen(&ifp->if_snd, ET_TX_NDESC);
 356         ifq_set_ready(&ifp->if_snd);
 357
 358         et_chip_attach(sc);
 359
 360         error = mii_phy_probe(dev, &sc->sc_miibus,
 361                               et_ifmedia_upd, et_ifmedia_sts);
 362         if (error) {
 363                 device_printf(dev, "can't probe any PHY\n");
 364                 goto fail;
 365         }
 366
 367         ether_ifattach(ifp, eaddr, NULL);
 368
 369         error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, et_intr, sc,
 370                                &sc->sc_irq_handle, ifp->if_serializer);
 371         if (error) {
 372                 ether_ifdetach(ifp);
 373                 device_printf(dev, "can't setup intr\n");
 374                 goto fail;
 375         }
 376
 377         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
 378         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 379
 380         return 0;
 381 fail:
 382         et_detach(dev);
 383         return error;
 384 }
 385
 386 static int
 387 et_detach(device_t dev)
 388 {
 389         struct et_softc *sc = device_get_softc(dev);
 390
 391         if (device_is_attached(dev)) {
 392                 struct ifnet *ifp = &sc->arpcom.ac_if;
 393
 394                 lwkt_serialize_enter(ifp->if_serializer);
 395                 et_stop(sc);
 396                 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
 397                 lwkt_serialize_exit(ifp->if_serializer);
 398
 399                 ether_ifdetach(ifp);
 400         }
 401
 402         if (sc->sc_sysctl_tree != NULL)
 403                 sysctl_ctx_free(&sc->sc_sysctl_ctx);
 404
 405         if (sc->sc_miibus != NULL)
 406                 device_delete_child(dev, sc->sc_miibus);
 407         bus_generic_detach(dev);
 408
 409         if (sc->sc_irq_res != NULL) {
 410                 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
 411                                      sc->sc_irq_res);
 412         }
 413
 414         if (sc->sc_mem_res != NULL) {
 415                 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
 416                                      sc->sc_mem_res);
 417         }
 418
 419         et_dma_free(dev);
 420
 421         return 0;
 422 }
 423
 424 static int
 425 et_shutdown(device_t dev)
 426 {
 427         struct et_softc *sc = device_get_softc(dev);
 428         struct ifnet *ifp = &sc->arpcom.ac_if;
 429
 430         lwkt_serialize_enter(ifp->if_serializer);
 431         et_stop(sc);
 432         lwkt_serialize_exit(ifp->if_serializer);
 433         return 0;
 434 }
 435
 436 static int
 437 et_miibus_readreg(device_t dev, int phy, int reg)
 438 {
 439         struct et_softc *sc = device_get_softc(dev);
 440         uint32_t val;
 441         int i, ret;
 442
 443         /* Stop any pending operations */
 444         CSR_WRITE_4(sc, ET_MII_CMD, 0);
 445
 446         val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
 447               __SHIFTIN(reg, ET_MII_ADDR_REG);
 448         CSR_WRITE_4(sc, ET_MII_ADDR, val);
 449
 450         /* Start reading */
 451         CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ);
 452
 453 #define NRETRY  50
 454
 455         for (i = 0; i < NRETRY; ++i) {
 456                 val = CSR_READ_4(sc, ET_MII_IND);
 457                 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0)
 458                         break;
 459                 DELAY(50);
 460         }
 461         if (i == NRETRY) {
 462                 if_printf(&sc->arpcom.ac_if,
 463                           "read phy %d, reg %d timed out\n", phy, reg);
 464                 ret = 0;
 465                 goto back;
 466         }
 467
 468 #undef NRETRY
 469
 470         val = CSR_READ_4(sc, ET_MII_STAT);
 471         ret = __SHIFTOUT(val, ET_MII_STAT_VALUE);
 472
 473 back:
 474         /* Make sure that the current operation is stopped */
 475         CSR_WRITE_4(sc, ET_MII_CMD, 0);
 476         return ret;
 477 }
 478
 479 static int
 480 et_miibus_writereg(device_t dev, int phy, int reg, int val0)
 481 {
 482         struct et_softc *sc = device_get_softc(dev);
 483         uint32_t val;
 484         int i;
 485
 486         /* Stop any pending operations */
 487         CSR_WRITE_4(sc, ET_MII_CMD, 0);
 488
 489         val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
 490               __SHIFTIN(reg, ET_MII_ADDR_REG);
 491         CSR_WRITE_4(sc, ET_MII_ADDR, val);
 492
 493         /* Start writing */
 494         CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE));
 495
 496 #define NRETRY 100
 497
 498         for (i = 0; i < NRETRY; ++i) {
 499                 val = CSR_READ_4(sc, ET_MII_IND);
 500                 if ((val & ET_MII_IND_BUSY) == 0)
 501                         break;
 502                 DELAY(50);
 503         }
 504         if (i == NRETRY) {
 505                 if_printf(&sc->arpcom.ac_if,
 506                           "write phy %d, reg %d timed out\n", phy, reg);
 507                 et_miibus_readreg(dev, phy, reg);
 508         }
 509
 510 #undef NRETRY
 511
 512         /* Make sure that the current operation is stopped */
 513         CSR_WRITE_4(sc, ET_MII_CMD, 0);
 514         return 0;
 515 }
 516
 517 static void
 518 et_miibus_statchg(device_t dev)
 519 {
 520         et_setmedia(device_get_softc(dev));
 521 }
 522
 523 static int
 524 et_ifmedia_upd(struct ifnet *ifp)
 525 {
 526         struct et_softc *sc = ifp->if_softc;
 527         struct mii_data *mii = device_get_softc(sc->sc_miibus);
 528
 529         if (mii->mii_instance != 0) {
 530                 struct mii_softc *miisc;
 531
 532                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 533                         mii_phy_reset(miisc);
 534         }
 535         mii_mediachg(mii);
 536
 537         return 0;
 538 }
 539
 540 static void
 541 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 542 {
 543         struct et_softc *sc = ifp->if_softc;
 544         struct mii_data *mii = device_get_softc(sc->sc_miibus);
 545
 546         mii_pollstat(mii);
 547         ifmr->ifm_active = mii->mii_media_active;
 548         ifmr->ifm_status = mii->mii_media_status;
 549 }
 550
 551 static void
 552 et_stop(struct et_softc *sc)
 553 {
 554         struct ifnet *ifp = &sc->arpcom.ac_if;
 555
 556         ASSERT_SERIALIZED(ifp->if_serializer);
 557
 558         callout_stop(&sc->sc_tick);
 559
 560         et_stop_rxdma(sc);
 561         et_stop_txdma(sc);
 562
 563         et_disable_intrs(sc);
 564
 565         et_free_tx_ring(sc);
 566         et_free_rx_ring(sc);
 567
 568         et_reset(sc);
 569
 570         sc->sc_tx = 0;
 571         sc->sc_tx_intr = 0;
 572         sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED;
 573
 574         ifp->if_timer = 0;
 575         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 576 }
 577
 578 static int
 579 et_bus_config(device_t dev)
 580 {
 581         uint32_t val, max_plsz;
 582         uint16_t ack_latency, replay_timer;
 583
 584         /*
 585          * Test whether EEPROM is valid
 586          * NOTE: Read twice to get the correct value
 587          */
 588         pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1);
 589         val = pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1);
 590         if (val & ET_PCIM_EEPROM_STATUS_ERROR) {
 591                 device_printf(dev, "EEPROM status error 0x%02x\n", val);
 592                 return ENXIO;
 593         }
 594
 595         /* TODO: LED */
 596
 597         /*
 598          * Configure ACK latency and replay timer according to
 599          * max playload size
 600          */
 601         val = pci_read_config(dev, ET_PCIR_DEVICE_CAPS, 4);
 602         max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ;
 603
 604         switch (max_plsz) {
 605         case ET_PCIV_DEVICE_CAPS_PLSZ_128:
 606                 ack_latency = ET_PCIV_ACK_LATENCY_128;
 607                 replay_timer = ET_PCIV_REPLAY_TIMER_128;
 608                 break;
 609
 610         case ET_PCIV_DEVICE_CAPS_PLSZ_256:
 611                 ack_latency = ET_PCIV_ACK_LATENCY_256;
 612                 replay_timer = ET_PCIV_REPLAY_TIMER_256;
 613                 break;
 614
 615         default:
 616                 ack_latency = pci_read_config(dev, ET_PCIR_ACK_LATENCY, 2);
 617                 replay_timer = pci_read_config(dev, ET_PCIR_REPLAY_TIMER, 2);
 618                 device_printf(dev, "ack latency %u, replay timer %u\n",
 619                               ack_latency, replay_timer);
 620                 break;
 621         }
 622         if (ack_latency != 0) {
 623                 pci_write_config(dev, ET_PCIR_ACK_LATENCY, ack_latency, 2);
 624                 pci_write_config(dev, ET_PCIR_REPLAY_TIMER, replay_timer, 2);
 625         }
 626
 627         /*
 628          * Set L0s and L1 latency timer to 2us
 629          */
 630         val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2);
 631         pci_write_config(dev, ET_PCIR_L0S_L1_LATENCY, val, 1);
 632
 633         /*
 634          * Set max read request size to 2048 bytes
 635          */
 636         val = pci_read_config(dev, ET_PCIR_DEVICE_CTRL, 2);
 637         val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ;
 638         val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K;
 639         pci_write_config(dev, ET_PCIR_DEVICE_CTRL, val, 2);
 640
 641         return 0;
 642 }
 643
 644 static void
 645 et_get_eaddr(device_t dev, uint8_t eaddr[])
 646 {
 647         uint32_t val;
 648         int i;
 649
 650         val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4);
 651         for (i = 0; i < 4; ++i)
 652                 eaddr[i] = (val >> (8 * i)) & 0xff;
 653
 654         val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2);
 655         for (; i < ETHER_ADDR_LEN; ++i)
 656                 eaddr[i] = (val >> (8 * (i - 4))) & 0xff;
 657 }
 658
 659 static void
 660 et_reset(struct et_softc *sc)
 661 {
 662         CSR_WRITE_4(sc, ET_MAC_CFG1,
 663                     ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
 664                     ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
 665                     ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
 666
 667         CSR_WRITE_4(sc, ET_SWRST,
 668                     ET_SWRST_TXDMA | ET_SWRST_RXDMA |
 669                     ET_SWRST_TXMAC | ET_SWRST_RXMAC |
 670                     ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC);
 671
 672         CSR_WRITE_4(sc, ET_MAC_CFG1,
 673                     ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
 674                     ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC);
 675         CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
 676 }
 677
 678 static void
 679 et_disable_intrs(struct et_softc *sc)
 680 {
 681         CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
 682 }
 683
 684 static void
 685 et_enable_intrs(struct et_softc *sc, uint32_t intrs)
 686 {
 687         CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs);
 688 }
 689
 690 static int
 691 et_dma_alloc(device_t dev)
 692 {
 693         struct et_softc *sc = device_get_softc(dev);
 694         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
 695         struct et_txstatus_data *txsd = &sc->sc_tx_status;
 696         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
 697         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
 698         int i, error;
 699
 700         /*
 701          * Create top level DMA tag
 702          */
 703         error = bus_dma_tag_create(NULL, 1, 0,
 704                                    BUS_SPACE_MAXADDR,
 705                                    BUS_SPACE_MAXADDR,
 706                                    NULL, NULL,
 707                                    BUS_SPACE_MAXSIZE_32BIT,
 708                                    0,
 709                                    BUS_SPACE_MAXSIZE_32BIT,
 710                                    0, &sc->sc_dtag);
 711         if (error) {
 712                 device_printf(dev, "can't create DMA tag\n");
 713                 return error;
 714         }
 715
 716         /*
 717          * Create TX ring DMA stuffs
 718          */
 719         tx_ring->tr_desc = bus_dmamem_coherent_any(sc->sc_dtag,
 720                                 ET_ALIGN, ET_TX_RING_SIZE,
 721                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
 722                                 &tx_ring->tr_dtag, &tx_ring->tr_dmap,
 723                                 &tx_ring->tr_paddr);
 724         if (tx_ring->tr_desc == NULL) {
 725                 device_printf(dev, "can't create TX ring DMA stuffs\n");
 726                 return ENOMEM;
 727         }
 728
 729         /*
 730          * Create TX status DMA stuffs
 731          */
 732         txsd->txsd_status = bus_dmamem_coherent_any(sc->sc_dtag,
 733                                 ET_ALIGN, sizeof(uint32_t),
 734                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
 735                                 &txsd->txsd_dtag, &txsd->txsd_dmap,
 736                                 &txsd->txsd_paddr);
 737         if (txsd->txsd_status == NULL) {
 738                 device_printf(dev, "can't create TX status DMA stuffs\n");
 739                 return ENOMEM;
 740         }
 741
 742         /*
 743          * Create DMA stuffs for RX rings
 744          */
 745         for (i = 0; i < ET_RX_NRING; ++i) {
 746                 static const uint32_t rx_ring_posreg[ET_RX_NRING] =
 747                 { ET_RX_RING0_POS, ET_RX_RING1_POS };
 748
 749                 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
 750
 751                 rx_ring->rr_desc = bus_dmamem_coherent_any(sc->sc_dtag,
 752                                         ET_ALIGN, ET_RX_RING_SIZE,
 753                                         BUS_DMA_WAITOK | BUS_DMA_ZERO,
 754                                         &rx_ring->rr_dtag, &rx_ring->rr_dmap,
 755                                         &rx_ring->rr_paddr);
 756                 if (rx_ring->rr_desc == NULL) {
 757                         device_printf(dev, "can't create DMA stuffs for "
 758                                       "the %d RX ring\n", i);
 759                         return ENOMEM;
 760                 }
 761                 rx_ring->rr_posreg = rx_ring_posreg[i];
 762         }
 763
 764         /*
 765          * Create RX stat ring DMA stuffs
 766          */
 767         rxst_ring->rsr_stat = bus_dmamem_coherent_any(sc->sc_dtag,
 768                                 ET_ALIGN, ET_RXSTAT_RING_SIZE,
 769                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
 770                                 &rxst_ring->rsr_dtag, &rxst_ring->rsr_dmap,
 771                                 &rxst_ring->rsr_paddr);
 772         if (rxst_ring->rsr_stat == NULL) {
 773                 device_printf(dev, "can't create RX stat ring DMA stuffs\n");
 774                 return ENOMEM;
 775         }
 776
 777         /*
 778          * Create RX status DMA stuffs
 779          */
 780         rxsd->rxsd_status = bus_dmamem_coherent_any(sc->sc_dtag,
 781                                 ET_ALIGN, sizeof(struct et_rxstatus),
 782                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
 783                                 &rxsd->rxsd_dtag, &rxsd->rxsd_dmap,
 784                                 &rxsd->rxsd_paddr);
 785         if (rxsd->rxsd_status == NULL) {
 786                 device_printf(dev, "can't create RX status DMA stuffs\n");
 787                 return ENOMEM;
 788         }
 789
 790         /*
 791          * Create mbuf DMA stuffs
 792          */
 793         error = et_dma_mbuf_create(dev);
 794         if (error)
 795                 return error;
 796
 797         /*
 798          * Create jumbo buffer DMA stuffs
 799          * NOTE: Allow it to fail
 800          */
 801         if (et_jumbo_mem_alloc(dev) == 0)
 802                 sc->sc_flags |= ET_FLAG_JUMBO;
 803
 804         return 0;
 805 }
 806
 807 static void
 808 et_dma_free(device_t dev)
 809 {
 810         struct et_softc *sc = device_get_softc(dev);
 811         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
 812         struct et_txstatus_data *txsd = &sc->sc_tx_status;
 813         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
 814         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
 815         int i, rx_done[ET_RX_NRING];
 816
 817         /*
 818          * Destroy TX ring DMA stuffs
 819          */
 820         et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc,
 821                            tx_ring->tr_dmap);
 822
 823         /*
 824          * Destroy TX status DMA stuffs
 825          */
 826         et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status,
 827                            txsd->txsd_dmap);
 828
 829         /*
 830          * Destroy DMA stuffs for RX rings
 831          */
 832         for (i = 0; i < ET_RX_NRING; ++i) {
 833                 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
 834
 835                 et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc,
 836                                    rx_ring->rr_dmap);
 837         }
 838
 839         /*
 840          * Destroy RX stat ring DMA stuffs
 841          */
 842         et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat,
 843                            rxst_ring->rsr_dmap);
 844
 845         /*
 846          * Destroy RX status DMA stuffs
 847          */
 848         et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status,
 849                            rxsd->rxsd_dmap);
 850
 851         /*
 852          * Destroy mbuf DMA stuffs
 853          */
 854         for (i = 0; i < ET_RX_NRING; ++i)
 855                 rx_done[i] = ET_RX_NDESC;
 856         et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done);
 857
 858         /*
 859          * Destroy jumbo buffer DMA stuffs
 860          */
 861         if (sc->sc_flags & ET_FLAG_JUMBO)
 862                 et_jumbo_mem_free(dev);
 863
 864         /*
 865          * Destroy top level DMA tag
 866          */
 867         if (sc->sc_dtag != NULL)
 868                 bus_dma_tag_destroy(sc->sc_dtag);
 869 }
 870
 871 static int
 872 et_dma_mbuf_create(device_t dev)
 873 {
 874         struct et_softc *sc = device_get_softc(dev);
 875         struct et_txbuf_data *tbd = &sc->sc_tx_data;
 876         int i, error, rx_done[ET_RX_NRING];
 877
 878         /*
 879          * Create RX mbuf DMA tag
 880          */
 881         error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
 882                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
 883                                    NULL, NULL,
 884                                    MCLBYTES, 1, MCLBYTES,
 885                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
 886                                    &sc->sc_rxbuf_dtag);
 887         if (error) {
 888                 device_printf(dev, "can't create RX mbuf DMA tag\n");
 889                 return error;
 890         }
 891
 892         /*
 893          * Create spare DMA map for RX mbufs
 894          */
 895         error = bus_dmamap_create(sc->sc_rxbuf_dtag, BUS_DMA_WAITOK,
 896                                   &sc->sc_rxbuf_tmp_dmap);
 897         if (error) {
 898                 device_printf(dev, "can't create spare mbuf DMA map\n");
 899                 bus_dma_tag_destroy(sc->sc_rxbuf_dtag);
 900                 sc->sc_rxbuf_dtag = NULL;
 901                 return error;
 902         }
 903
 904         /*
 905          * Create DMA maps for RX mbufs
 906          */
 907         bzero(rx_done, sizeof(rx_done));
 908         for (i = 0; i < ET_RX_NRING; ++i) {
 909                 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
 910                 int j;
 911
 912                 for (j = 0; j < ET_RX_NDESC; ++j) {
 913                         error = bus_dmamap_create(sc->sc_rxbuf_dtag,
 914                                                   BUS_DMA_WAITOK,
 915                                                   &rbd->rbd_buf[j].rb_dmap);
 916                         if (error) {
 917                                 device_printf(dev, "can't create %d RX mbuf "
 918                                               "for %d RX ring\n", j, i);
 919                                 rx_done[i] = j;
 920                                 et_dma_mbuf_destroy(dev, 0, rx_done);
 921                                 return error;
 922                         }
 923                 }
 924                 rx_done[i] = ET_RX_NDESC;
 925
 926                 rbd->rbd_softc = sc;
 927                 rbd->rbd_ring = &sc->sc_rx_ring[i];
 928         }
 929
 930         /*
 931          * Create TX mbuf DMA tag
 932          */
 933         error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
 934                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
 935                                    NULL, NULL,
 936                                    ET_JUMBO_FRAMELEN, ET_NSEG_MAX, MCLBYTES,
 937                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
 938                                    BUS_DMA_ONEBPAGE,
 939                                    &sc->sc_txbuf_dtag);
 940         if (error) {
 941                 device_printf(dev, "can't create TX mbuf DMA tag\n");
 942                 return error;
 943         }
 944
 945         /*
 946          * Create DMA maps for TX mbufs
 947          */
 948         for (i = 0; i < ET_TX_NDESC; ++i) {
 949                 error = bus_dmamap_create(sc->sc_txbuf_dtag,
 950                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
 951                                           &tbd->tbd_buf[i].tb_dmap);
 952                 if (error) {
 953                         device_printf(dev, "can't create %d TX mbuf "
 954                                       "DMA map\n", i);
 955                         et_dma_mbuf_destroy(dev, i, rx_done);
 956                         return error;
 957                 }
 958         }
 959
 960         return 0;
 961 }
 962
 963 static void
 964 et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[])
 965 {
 966         struct et_softc *sc = device_get_softc(dev);
 967         struct et_txbuf_data *tbd = &sc->sc_tx_data;
 968         int i;
 969
 970         /*
 971          * Destroy DMA tag and maps for RX mbufs
 972          */
 973         if (sc->sc_rxbuf_dtag) {
 974                 for (i = 0; i < ET_RX_NRING; ++i) {
 975                         struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
 976                         int j;
 977
 978                         for (j = 0; j < rx_done[i]; ++j) {
 979                                 struct et_rxbuf *rb = &rbd->rbd_buf[j];
 980
 981                                 KASSERT(rb->rb_mbuf == NULL,
 982                                         ("RX mbuf in %d RX ring is "
 983                                          "not freed yet\n", i));
 984                                 bus_dmamap_destroy(sc->sc_rxbuf_dtag,
 985                                                    rb->rb_dmap);
 986                         }
 987                 }
 988                 bus_dmamap_destroy(sc->sc_rxbuf_dtag, sc->sc_rxbuf_tmp_dmap);
 989                 bus_dma_tag_destroy(sc->sc_rxbuf_dtag);
 990                 sc->sc_rxbuf_dtag = NULL;
 991         }
 992
 993         /*
 994          * Destroy DMA tag and maps for TX mbufs
 995          */
 996         if (sc->sc_txbuf_dtag) {
 997                 for (i = 0; i < tx_done; ++i) {
 998                         struct et_txbuf *tb = &tbd->tbd_buf[i];
 999
1000                         KASSERT(tb->tb_mbuf == NULL,
1001                                 ("TX mbuf is not freed yet\n"));
1002                         bus_dmamap_destroy(sc->sc_txbuf_dtag, tb->tb_dmap);
1003                 }
1004                 bus_dma_tag_destroy(sc->sc_txbuf_dtag);
1005                 sc->sc_txbuf_dtag = NULL;
1006         }
1007 }
1008
1009 static void
1010 et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap)
1011 {
1012         if (dtag != NULL) {
1013                 bus_dmamap_unload(dtag, dmap);
1014                 bus_dmamem_free(dtag, addr, dmap);
1015                 bus_dma_tag_destroy(dtag);
1016         }
1017 }
1018
1019 static void
1020 et_chip_attach(struct et_softc *sc)
1021 {
1022         uint32_t val;
1023
1024         /*
1025          * Perform minimal initialization
1026          */
1027
1028         /* Disable loopback */
1029         CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1030
1031         /* Reset MAC */
1032         CSR_WRITE_4(sc, ET_MAC_CFG1,
1033                     ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1034                     ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1035                     ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1036
1037         /*
1038          * Setup half duplex mode
1039          */
1040         val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
1041               __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
1042               __SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
1043               ET_MAC_HDX_EXC_DEFER;
1044         CSR_WRITE_4(sc, ET_MAC_HDX, val);
1045
1046         /* Clear MAC control */
1047         CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1048
1049         /* Reset MII */
1050         CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1051
1052         /* Bring MAC out of reset state */
1053         CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1054
1055         /* Enable memory controllers */
1056         CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1057 }
1058
1059 static void
1060 et_intr(void *xsc)
1061 {
1062         struct et_softc *sc = xsc;
1063         struct ifnet *ifp = &sc->arpcom.ac_if;
1064         uint32_t intrs;
1065
1066         ASSERT_SERIALIZED(ifp->if_serializer);
1067
1068         if ((ifp->if_flags & IFF_RUNNING) == 0)
1069                 return;
1070
1071         et_disable_intrs(sc);
1072
1073         intrs = CSR_READ_4(sc, ET_INTR_STATUS);
1074         intrs &= ET_INTRS;
1075         if (intrs == 0) /* Not interested */
1076                 goto back;
1077
1078         if (intrs & ET_INTR_RXEOF)
1079                 et_rxeof(sc);
1080         if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER))
1081                 et_txeof(sc, 1);
1082         if (intrs & ET_INTR_TIMER)
1083                 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1084 back:
1085         et_enable_intrs(sc, ET_INTRS);
1086 }
1087
1088 static void
1089 et_init(void *xsc)
1090 {
1091         struct et_softc *sc = xsc;
1092         struct ifnet *ifp = &sc->arpcom.ac_if;
1093         const struct et_bsize *arr;
1094         int error, i;
1095
1096         ASSERT_SERIALIZED(ifp->if_serializer);
1097
1098         et_stop(sc);
1099
1100         arr = ET_FRAMELEN(ifp->if_mtu) < MCLBYTES ?
1101               et_bufsize_std : et_bufsize_jumbo;
1102         for (i = 0; i < ET_RX_NRING; ++i) {
1103                 sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize;
1104                 sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf;
1105                 sc->sc_rx_data[i].rbd_jumbo = arr[i].jumbo;
1106         }
1107
1108         error = et_init_tx_ring(sc);
1109         if (error)
1110                 goto back;
1111
1112         error = et_init_rx_ring(sc);
1113         if (error)
1114                 goto back;
1115
1116         error = et_chip_init(sc);
1117         if (error)
1118                 goto back;
1119
1120         error = et_enable_txrx(sc, 1);
1121         if (error)
1122                 goto back;
1123
1124         et_enable_intrs(sc, ET_INTRS);
1125
1126         callout_reset(&sc->sc_tick, hz, et_tick, sc);
1127
1128         CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1129
1130         ifp->if_flags |= IFF_RUNNING;
1131         ifp->if_flags &= ~IFF_OACTIVE;
1132 back:
1133         if (error)
1134                 et_stop(sc);
1135 }
1136
1137 static int
1138 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1139 {
1140         struct et_softc *sc = ifp->if_softc;
1141         struct mii_data *mii = device_get_softc(sc->sc_miibus);
1142         struct ifreq *ifr = (struct ifreq *)data;
1143         int error = 0, max_framelen;
1144
1145         ASSERT_SERIALIZED(ifp->if_serializer);
1146
1147         switch (cmd) {
1148         case SIOCSIFFLAGS:
1149                 if (ifp->if_flags & IFF_UP) {
1150                         if (ifp->if_flags & IFF_RUNNING) {
1151                                 if ((ifp->if_flags ^ sc->sc_if_flags) &
1152                                     (IFF_ALLMULTI | IFF_PROMISC))
1153                                         et_setmulti(sc);
1154                         } else {
1155                                 et_init(sc);
1156                         }
1157                 } else {
1158                         if (ifp->if_flags & IFF_RUNNING)
1159                                 et_stop(sc);
1160                 }
1161                 sc->sc_if_flags = ifp->if_flags;
1162                 break;
1163
1164         case SIOCSIFMEDIA:
1165         case SIOCGIFMEDIA:
1166                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1167                 break;
1168
1169         case SIOCADDMULTI:
1170         case SIOCDELMULTI:
1171                 if (ifp->if_flags & IFF_RUNNING)
1172                         et_setmulti(sc);
1173                 break;
1174
1175         case SIOCSIFMTU:
1176                 if (sc->sc_flags & ET_FLAG_JUMBO)
1177                         max_framelen = ET_JUMBO_FRAMELEN;
1178                 else
1179                         max_framelen = MCLBYTES - 1;
1180
1181                 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) {
1182                         error = EOPNOTSUPP;
1183                         break;
1184                 }
1185
1186                 ifp->if_mtu = ifr->ifr_mtu;
1187                 if (ifp->if_flags & IFF_RUNNING)
1188                         et_init(sc);
1189                 break;
1190
1191         default:
1192                 error = ether_ioctl(ifp, cmd, data);
1193                 break;
1194         }
1195         return error;
1196 }
1197
1198 static void
1199 et_start(struct ifnet *ifp)
1200 {
1201         struct et_softc *sc = ifp->if_softc;
1202         struct et_txbuf_data *tbd = &sc->sc_tx_data;
1203         int trans, oactive;
1204
1205         ASSERT_SERIALIZED(ifp->if_serializer);
1206
1207         if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) {
1208                 ifq_purge(&ifp->if_snd);
1209                 return;
1210         }
1211
1212         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1213                 return;
1214
1215         oactive = 0;
1216         trans = 0;
1217         for (;;) {
1218                 struct mbuf *m;
1219                 int error;
1220
1221                 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) {
1222                         if (oactive) {
1223                                 ifp->if_flags |= IFF_OACTIVE;
1224                                 break;
1225                         }
1226
1227                         et_txeof(sc, 0);
1228                         oactive = 1;
1229                         continue;
1230                 }
1231
1232                 m = ifq_dequeue(&ifp->if_snd, NULL);
1233                 if (m == NULL)
1234                         break;
1235
1236                 error = et_encap(sc, &m);
1237                 if (error) {
1238                         ifp->if_oerrors++;
1239                         KKASSERT(m == NULL);
1240
1241                         if (error == EFBIG) {
1242                                 /*
1243                                  * Excessive fragmented packets
1244                                  */
1245                                 if (oactive) {
1246                                         ifp->if_flags |= IFF_OACTIVE;
1247                                         break;
1248                                 }
1249                                 et_txeof(sc, 0);
1250                                 oactive = 1;
1251                         }
1252                         continue;
1253                 } else {
1254                         oactive = 0;
1255                 }
1256                 trans = 1;
1257
1258                 BPF_MTAP(ifp, m);
1259         }
1260
1261         if (trans)
1262                 ifp->if_timer = 5;
1263 }
1264
1265 static void
1266 et_watchdog(struct ifnet *ifp)
1267 {
1268         ASSERT_SERIALIZED(ifp->if_serializer);
1269
1270         if_printf(ifp, "watchdog timed out\n");
1271
1272         ifp->if_init(ifp->if_softc);
1273         if_devstart(ifp);
1274 }
1275
1276 static int
1277 et_stop_rxdma(struct et_softc *sc)
1278 {
1279         CSR_WRITE_4(sc, ET_RXDMA_CTRL,
1280                     ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE);
1281
1282         DELAY(5);
1283         if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {
1284                 if_printf(&sc->arpcom.ac_if, "can't stop RX DMA engine\n");
1285                 return ETIMEDOUT;
1286         }
1287         return 0;
1288 }
1289
1290 static int
1291 et_stop_txdma(struct et_softc *sc)
1292 {
1293         CSR_WRITE_4(sc, ET_TXDMA_CTRL,
1294                     ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT);
1295         return 0;
1296 }
1297
1298 static void
1299 et_free_tx_ring(struct et_softc *sc)
1300 {
1301         struct et_txbuf_data *tbd = &sc->sc_tx_data;
1302         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1303         int i;
1304
1305         for (i = 0; i < ET_TX_NDESC; ++i) {
1306                 struct et_txbuf *tb = &tbd->tbd_buf[i];
1307
1308                 if (tb->tb_mbuf != NULL) {
1309                         bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap);
1310                         m_freem(tb->tb_mbuf);
1311                         tb->tb_mbuf = NULL;
1312                 }
1313         }
1314         bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1315 }
1316
1317 static void
1318 et_free_rx_ring(struct et_softc *sc)
1319 {
1320         int n;
1321
1322         for (n = 0; n < ET_RX_NRING; ++n) {
1323                 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1324                 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n];
1325                 int i;
1326
1327                 for (i = 0; i < ET_RX_NDESC; ++i) {
1328                         struct et_rxbuf *rb = &rbd->rbd_buf[i];
1329
1330                         if (rb->rb_mbuf != NULL) {
1331                                 if (!rbd->rbd_jumbo) {
1332                                         bus_dmamap_unload(sc->sc_rxbuf_dtag,
1333                                                           rb->rb_dmap);
1334                                 }
1335                                 m_freem(rb->rb_mbuf);
1336                                 rb->rb_mbuf = NULL;
1337                         }
1338                 }
1339                 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE);
1340         }
1341 }
1342
1343 static void
1344 et_setmulti(struct et_softc *sc)
1345 {
1346         struct ifnet *ifp = &sc->arpcom.ac_if;
1347         uint32_t hash[4] = { 0, 0, 0, 0 };
1348         uint32_t rxmac_ctrl, pktfilt;
1349         struct ifmultiaddr *ifma;
1350         int i, count;
1351
1352         pktfilt = CSR_READ_4(sc, ET_PKTFILT);
1353         rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);
1354
1355         pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST);
1356         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1357                 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT;
1358                 goto back;
1359         }
1360
1361         count = 0;
1362         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1363                 uint32_t *hp, h;
1364
1365                 if (ifma->ifma_addr->sa_family != AF_LINK)
1366                         continue;
1367
1368                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1369                                    ifma->ifma_addr), ETHER_ADDR_LEN);
1370                 h = (h & 0x3f800000) >> 23;
1371
1372                 hp = &hash[0];
1373                 if (h >= 32 && h < 64) {
1374                         h -= 32;
1375                         hp = &hash[1];
1376                 } else if (h >= 64 && h < 96) {
1377                         h -= 64;
1378                         hp = &hash[2];
1379                 } else if (h >= 96) {
1380                         h -= 96;
1381                         hp = &hash[3];
1382                 }
1383                 *hp |= (1 << h);
1384
1385                 ++count;
1386         }
1387
1388         for (i = 0; i < 4; ++i)
1389                 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]);
1390
1391         if (count > 0)
1392                 pktfilt |= ET_PKTFILT_MCAST;
1393         rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT;
1394 back:
1395         CSR_WRITE_4(sc, ET_PKTFILT, pktfilt);
1396         CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl);
1397 }
1398
1399 static int
1400 et_chip_init(struct et_softc *sc)
1401 {
1402         struct ifnet *ifp = &sc->arpcom.ac_if;
1403         uint32_t rxq_end;
1404         int error, frame_len, rxmem_size;
1405
1406         /*
1407          * Split 16Kbytes internal memory between TX and RX
1408          * according to frame length.
1409          */
1410         frame_len = ET_FRAMELEN(ifp->if_mtu);
1411         if (frame_len < 2048) {
1412                 rxmem_size = ET_MEM_RXSIZE_DEFAULT;
1413         } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) {
1414                 rxmem_size = ET_MEM_SIZE / 2;
1415         } else {
1416                 rxmem_size = ET_MEM_SIZE -
1417                 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT);
1418         }
1419         rxq_end = ET_QUEUE_ADDR(rxmem_size);
1420
1421         CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START);
1422         CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end);
1423         CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1);
1424         CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END);
1425
1426         /* No loopback */
1427         CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1428
1429         /* Clear MSI configure */
1430         CSR_WRITE_4(sc, ET_MSI_CFG, 0);
1431
1432         /* Disable timer */
1433         CSR_WRITE_4(sc, ET_TIMER, 0);
1434
1435         /* Initialize MAC */
1436         et_init_mac(sc);
1437
1438         /* Enable memory controllers */
1439         CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1440
1441         /* Initialize RX MAC */
1442         et_init_rxmac(sc);
1443
1444         /* Initialize TX MAC */
1445         et_init_txmac(sc);
1446
1447         /* Initialize RX DMA engine */
1448         error = et_init_rxdma(sc);
1449         if (error)
1450                 return error;
1451
1452         /* Initialize TX DMA engine */
1453         error = et_init_txdma(sc);
1454         if (error)
1455                 return error;
1456
1457         return 0;
1458 }
1459
1460 static int
1461 et_init_tx_ring(struct et_softc *sc)
1462 {
1463         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1464         struct et_txstatus_data *txsd = &sc->sc_tx_status;
1465         struct et_txbuf_data *tbd = &sc->sc_tx_data;
1466
1467         bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1468
1469         tbd->tbd_start_index = 0;
1470         tbd->tbd_start_wrap = 0;
1471         tbd->tbd_used = 0;
1472
1473         bzero(txsd->txsd_status, sizeof(uint32_t));
1474
1475         return 0;
1476 }
1477
1478 static int
1479 et_init_rx_ring(struct et_softc *sc)
1480 {
1481         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1482         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1483         int n;
1484
1485         for (n = 0; n < ET_RX_NRING; ++n) {
1486                 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1487                 int i, error;
1488
1489                 for (i = 0; i < ET_RX_NDESC; ++i) {
1490                         error = rbd->rbd_newbuf(rbd, i, 1);
1491                         if (error) {
1492                                 if_printf(&sc->arpcom.ac_if, "%d ring %d buf, "
1493                                           "newbuf failed: %d\n", n, i, error);
1494                                 return error;
1495                         }
1496                 }
1497         }
1498
1499         bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus));
1500         bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE);
1501
1502         return 0;
1503 }
1504
1505 static int
1506 et_init_rxdma(struct et_softc *sc)
1507 {
1508         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1509         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1510         struct et_rxdesc_ring *rx_ring;
1511         int error;
1512
1513         error = et_stop_rxdma(sc);
1514         if (error) {
1515                 if_printf(&sc->arpcom.ac_if, "can't init RX DMA engine\n");
1516                 return error;
1517         }
1518
1519         /*
1520          * Install RX status
1521          */
1522         CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr));
1523         CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr));
1524
1525         /*
1526          * Install RX stat ring
1527          */
1528         CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr));
1529         CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr));
1530         CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1);
1531         CSR_WRITE_4(sc, ET_RXSTAT_POS, 0);
1532         CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1);
1533
1534         /* Match ET_RXSTAT_POS */
1535         rxst_ring->rsr_index = 0;
1536         rxst_ring->rsr_wrap = 0;
1537
1538         /*
1539          * Install the 2nd RX descriptor ring
1540          */
1541         rx_ring = &sc->sc_rx_ring[1];
1542         CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1543         CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1544         CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1);
1545         CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP);
1546         CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1547
1548         /* Match ET_RX_RING1_POS */
1549         rx_ring->rr_index = 0;
1550         rx_ring->rr_wrap = 1;
1551
1552         /*
1553          * Install the 1st RX descriptor ring
1554          */
1555         rx_ring = &sc->sc_rx_ring[0];
1556         CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1557         CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1558         CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1);
1559         CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP);
1560         CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1561
1562         /* Match ET_RX_RING0_POS */
1563         rx_ring->rr_index = 0;
1564         rx_ring->rr_wrap = 1;
1565
1566         /*
1567          * RX intr moderation
1568          */
1569         CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts);
1570         CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay);
1571
1572         return 0;
1573 }
1574
1575 static int
1576 et_init_txdma(struct et_softc *sc)
1577 {
1578         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1579         struct et_txstatus_data *txsd = &sc->sc_tx_status;
1580         int error;
1581
1582         error = et_stop_txdma(sc);
1583         if (error) {
1584                 if_printf(&sc->arpcom.ac_if, "can't init TX DMA engine\n");
1585                 return error;
1586         }
1587
1588         /*
1589          * Install TX descriptor ring
1590          */
1591         CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr));
1592         CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr));
1593         CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1);
1594
1595         /*
1596          * Install TX status
1597          */
1598         CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr));
1599         CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr));
1600
1601         CSR_WRITE_4(sc, ET_TX_READY_POS, 0);
1602
1603         /* Match ET_TX_READY_POS */
1604         tx_ring->tr_ready_index = 0;
1605         tx_ring->tr_ready_wrap = 0;
1606
1607         return 0;
1608 }
1609
1610 static void
1611 et_init_mac(struct et_softc *sc)
1612 {
1613         struct ifnet *ifp = &sc->arpcom.ac_if;
1614         const uint8_t *eaddr = IF_LLADDR(ifp);
1615         uint32_t val;
1616
1617         /* Reset MAC */
1618         CSR_WRITE_4(sc, ET_MAC_CFG1,
1619                     ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1620                     ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1621                     ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1622
1623         /*
1624          * Setup inter packet gap
1625          */
1626         val = __SHIFTIN(56, ET_IPG_NONB2B_1) |
1627               __SHIFTIN(88, ET_IPG_NONB2B_2) |
1628               __SHIFTIN(80, ET_IPG_MINIFG) |
1629               __SHIFTIN(96, ET_IPG_B2B);
1630         CSR_WRITE_4(sc, ET_IPG, val);
1631
1632         /*
1633          * Setup half duplex mode
1634          */
1635         val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
1636               __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
1637               __SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
1638               ET_MAC_HDX_EXC_DEFER;
1639         CSR_WRITE_4(sc, ET_MAC_HDX, val);
1640
1641         /* Clear MAC control */
1642         CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1643
1644         /* Reset MII */
1645         CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1646
1647         /*
1648          * Set MAC address
1649          */
1650         val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24);
1651         CSR_WRITE_4(sc, ET_MAC_ADDR1, val);
1652         val = (eaddr[0] << 16) | (eaddr[1] << 24);
1653         CSR_WRITE_4(sc, ET_MAC_ADDR2, val);
1654
1655         /* Set max frame length */
1656         CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu));
1657
1658         /* Bring MAC out of reset state */
1659         CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1660 }
1661
1662 static void
1663 et_init_rxmac(struct et_softc *sc)
1664 {
1665         struct ifnet *ifp = &sc->arpcom.ac_if;
1666         const uint8_t *eaddr = IF_LLADDR(ifp);
1667         uint32_t val;
1668         int i;
1669
1670         /* Disable RX MAC and WOL */
1671         CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE);
1672
1673         /*
1674          * Clear all WOL related registers
1675          */
1676         for (i = 0; i < 3; ++i)
1677                 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0);
1678         for (i = 0; i < 20; ++i)
1679                 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0);
1680
1681         /*
1682          * Set WOL source address.  XXX is this necessary?
1683          */
1684         val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5];
1685         CSR_WRITE_4(sc, ET_WOL_SA_LO, val);
1686         val = (eaddr[0] << 8) | eaddr[1];
1687         CSR_WRITE_4(sc, ET_WOL_SA_HI, val);
1688
1689         /* Clear packet filters */
1690         CSR_WRITE_4(sc, ET_PKTFILT, 0);
1691
1692         /* No ucast filtering */
1693         CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0);
1694         CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0);
1695         CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0);
1696
1697         if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) {
1698                 /*
1699                  * In order to transmit jumbo packets greater than
1700                  * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between
1701                  * RX MAC and RX DMA needs to be reduced in size to
1702                  * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen).  In
1703                  * order to implement this, we must use "cut through"
1704                  * mode in the RX MAC, which chops packets down into
1705                  * segments.  In this case we selected 256 bytes,
1706                  * since this is the size of the PCI-Express TLP's
1707                  * that the ET1310 uses.
1708                  */
1709                 val = __SHIFTIN(ET_RXMAC_SEGSZ(256), ET_RXMAC_MC_SEGSZ_MAX) |
1710                       ET_RXMAC_MC_SEGSZ_ENABLE;
1711         } else {
1712                 val = 0;
1713         }
1714         CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val);
1715
1716         CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0);
1717
1718         /* Initialize RX MAC management register */
1719         CSR_WRITE_4(sc, ET_RXMAC_MGT, 0);
1720
1721         CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0);
1722
1723         CSR_WRITE_4(sc, ET_RXMAC_MGT,
1724                     ET_RXMAC_MGT_PASS_ECRC |
1725                     ET_RXMAC_MGT_PASS_ELEN |
1726                     ET_RXMAC_MGT_PASS_ETRUNC |
1727                     ET_RXMAC_MGT_CHECK_PKT);
1728
1729         /*
1730          * Configure runt filtering (may not work on certain chip generation)
1731          */
1732         val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG;
1733         CSR_WRITE_4(sc, ET_PKTFILT, val);
1734
1735         /* Enable RX MAC but leave WOL disabled */
1736         CSR_WRITE_4(sc, ET_RXMAC_CTRL,
1737                     ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE);
1738
1739         /*
1740          * Setup multicast hash and allmulti/promisc mode
1741          */
1742         et_setmulti(sc);
1743 }
1744
1745 static void
1746 et_init_txmac(struct et_softc *sc)
1747 {
1748         /* Disable TX MAC and FC(?) */
1749         CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE);
1750
1751         /* No flow control yet */
1752         CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0);
1753
1754         /* Enable TX MAC but leave FC(?) diabled */
1755         CSR_WRITE_4(sc, ET_TXMAC_CTRL,
1756                     ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE);
1757 }
1758
1759 static int
1760 et_start_rxdma(struct et_softc *sc)
1761 {
1762         uint32_t val = 0;
1763
1764         val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize,
1765                          ET_RXDMA_CTRL_RING0_SIZE) |
1766                ET_RXDMA_CTRL_RING0_ENABLE;
1767         val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize,
1768                          ET_RXDMA_CTRL_RING1_SIZE) |
1769                ET_RXDMA_CTRL_RING1_ENABLE;
1770
1771         CSR_WRITE_4(sc, ET_RXDMA_CTRL, val);
1772
1773         DELAY(5);
1774
1775         if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {
1776                 if_printf(&sc->arpcom.ac_if, "can't start RX DMA engine\n");
1777                 return ETIMEDOUT;
1778         }
1779         return 0;
1780 }
1781
1782 static int
1783 et_start_txdma(struct et_softc *sc)
1784 {
1785         CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT);
1786         return 0;
1787 }
1788
1789 static int
1790 et_enable_txrx(struct et_softc *sc, int media_upd)
1791 {
1792         struct ifnet *ifp = &sc->arpcom.ac_if;
1793         uint32_t val;
1794         int i, error;
1795
1796         val = CSR_READ_4(sc, ET_MAC_CFG1);
1797         val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
1798         val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
1799                  ET_MAC_CFG1_LOOPBACK);
1800         CSR_WRITE_4(sc, ET_MAC_CFG1, val);
1801
1802         if (media_upd)
1803                 et_ifmedia_upd(ifp);
1804         else
1805                 et_setmedia(sc);
1806
1807 #define NRETRY  100
1808
1809         for (i = 0; i < NRETRY; ++i) {
1810                 val = CSR_READ_4(sc, ET_MAC_CFG1);
1811                 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
1812                     (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
1813                         break;
1814
1815                 DELAY(10);
1816         }
1817         if (i == NRETRY) {
1818                 if_printf(ifp, "can't enable RX/TX\n");
1819                 return 0;
1820         }
1821         sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
1822
1823 #undef NRETRY
1824
1825         /*
1826          * Start TX/RX DMA engine
1827          */
1828         error = et_start_rxdma(sc);
1829         if (error)
1830                 return error;
1831
1832         error = et_start_txdma(sc);
1833         if (error)
1834                 return error;
1835
1836         return 0;
1837 }
1838
1839 static void
1840 et_rxeof(struct et_softc *sc)
1841 {
1842         struct ifnet *ifp = &sc->arpcom.ac_if;
1843         struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1844         struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1845         uint32_t rxs_stat_ring;
1846         int rxst_wrap, rxst_index;
1847         struct mbuf_chain chain[MAXCPU];
1848
1849         if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
1850                 return;
1851
1852         rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring;
1853         rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0;
1854         rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX);
1855
1856         ether_input_chain_init(chain);
1857
1858         while (rxst_index != rxst_ring->rsr_index ||
1859                rxst_wrap != rxst_ring->rsr_wrap) {
1860                 struct et_rxbuf_data *rbd;
1861                 struct et_rxdesc_ring *rx_ring;
1862                 struct et_rxstat *st;
1863                 struct mbuf *m;
1864                 int buflen, buf_idx, ring_idx;
1865                 uint32_t rxstat_pos, rxring_pos;
1866
1867                 KKASSERT(rxst_ring->rsr_index < ET_RX_NSTAT);
1868                 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index];
1869
1870                 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN);
1871                 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX);
1872                 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX);
1873
1874                 if (++rxst_ring->rsr_index == ET_RX_NSTAT) {
1875                         rxst_ring->rsr_index = 0;
1876                         rxst_ring->rsr_wrap ^= 1;
1877                 }
1878                 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index,
1879                                        ET_RXSTAT_POS_INDEX);
1880                 if (rxst_ring->rsr_wrap)
1881                         rxstat_pos |= ET_RXSTAT_POS_WRAP;
1882                 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos);
1883
1884                 if (ring_idx >= ET_RX_NRING) {
1885                         ifp->if_ierrors++;
1886                         if_printf(ifp, "invalid ring index %d\n", ring_idx);
1887                         continue;
1888                 }
1889                 if (buf_idx >= ET_RX_NDESC) {
1890                         ifp->if_ierrors++;
1891                         if_printf(ifp, "invalid buf index %d\n", buf_idx);
1892                         continue;
1893                 }
1894
1895                 rbd = &sc->sc_rx_data[ring_idx];
1896                 m = rbd->rbd_buf[buf_idx].rb_mbuf;
1897
1898                 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) {
1899                         if (buflen < ETHER_CRC_LEN) {
1900                                 m_freem(m);
1901                                 ifp->if_ierrors++;
1902                         } else {
1903                                 m->m_pkthdr.len = m->m_len = buflen;
1904                                 m->m_pkthdr.rcvif = ifp;
1905
1906                                 m_adj(m, -ETHER_CRC_LEN);
1907
1908                                 ifp->if_ipackets++;
1909                                 ether_input_chain(ifp, m, NULL, chain);
1910                         }
1911                 } else {
1912                         ifp->if_ierrors++;
1913                 }
1914                 m = NULL;       /* Catch invalid reference */
1915
1916                 rx_ring = &sc->sc_rx_ring[ring_idx];
1917
1918                 if (buf_idx != rx_ring->rr_index) {
1919                         if_printf(ifp, "WARNING!! ring %d, "
1920                                   "buf_idx %d, rr_idx %d\n",
1921                                   ring_idx, buf_idx, rx_ring->rr_index);
1922                 }
1923
1924                 KKASSERT(rx_ring->rr_index < ET_RX_NDESC);
1925                 if (++rx_ring->rr_index == ET_RX_NDESC) {
1926                         rx_ring->rr_index = 0;
1927                         rx_ring->rr_wrap ^= 1;
1928                 }
1929                 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX);
1930                 if (rx_ring->rr_wrap)
1931                         rxring_pos |= ET_RX_RING_POS_WRAP;
1932                 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos);
1933         }
1934
1935         ether_input_dispatch(chain);
1936 }
1937
1938 static int
1939 et_encap(struct et_softc *sc, struct mbuf **m0)
1940 {
1941         bus_dma_segment_t segs[ET_NSEG_MAX];
1942         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1943         struct et_txbuf_data *tbd = &sc->sc_tx_data;
1944         struct et_txdesc *td;
1945         bus_dmamap_t map;
1946         int error, maxsegs, nsegs, first_idx, last_idx, i;
1947         uint32_t tx_ready_pos, last_td_ctrl2;
1948
1949         maxsegs = ET_TX_NDESC - tbd->tbd_used;
1950         if (maxsegs > ET_NSEG_MAX)
1951                 maxsegs = ET_NSEG_MAX;
1952         KASSERT(maxsegs >= ET_NSEG_SPARE,
1953                 ("not enough spare TX desc (%d)\n", maxsegs));
1954
1955         KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC);
1956         first_idx = tx_ring->tr_ready_index;
1957         map = tbd->tbd_buf[first_idx].tb_dmap;
1958
1959         error = bus_dmamap_load_mbuf_defrag(sc->sc_txbuf_dtag, map, m0,
1960                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1961         if (error)
1962                 goto back;
1963         bus_dmamap_sync(sc->sc_txbuf_dtag, map, BUS_DMASYNC_PREWRITE);
1964
1965         last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG;
1966         sc->sc_tx += nsegs;
1967         if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) {
1968                 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs;
1969                 last_td_ctrl2 |= ET_TDCTRL2_INTR;
1970         }
1971
1972         last_idx = -1;
1973         for (i = 0; i < nsegs; ++i) {
1974                 int idx;
1975
1976                 idx = (first_idx + i) % ET_TX_NDESC;
1977                 td = &tx_ring->tr_desc[idx];
1978                 td->td_addr_hi = ET_ADDR_HI(segs[i].ds_addr);
1979                 td->td_addr_lo = ET_ADDR_LO(segs[i].ds_addr);
1980                 td->td_ctrl1 = __SHIFTIN(segs[i].ds_len, ET_TDCTRL1_LEN);
1981
1982                 if (i == nsegs - 1) {   /* Last frag */
1983                         td->td_ctrl2 = last_td_ctrl2;
1984                         last_idx = idx;
1985                 }
1986
1987                 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC);
1988                 if (++tx_ring->tr_ready_index == ET_TX_NDESC) {
1989                         tx_ring->tr_ready_index = 0;
1990                         tx_ring->tr_ready_wrap ^= 1;
1991                 }
1992         }
1993         td = &tx_ring->tr_desc[first_idx];
1994         td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG;  /* First frag */
1995
1996         KKASSERT(last_idx >= 0);
1997         tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap;
1998         tbd->tbd_buf[last_idx].tb_dmap = map;
1999         tbd->tbd_buf[last_idx].tb_mbuf = *m0;
2000
2001         tbd->tbd_used += nsegs;
2002         KKASSERT(tbd->tbd_used <= ET_TX_NDESC);
2003
2004         tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index,
2005                        ET_TX_READY_POS_INDEX);
2006         if (tx_ring->tr_ready_wrap)
2007                 tx_ready_pos |= ET_TX_READY_POS_WRAP;
2008         CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos);
2009
2010         error = 0;
2011 back:
2012         if (error) {
2013                 m_freem(*m0);
2014                 *m0 = NULL;
2015         }
2016         return error;
2017 }
2018
2019 static void
2020 et_txeof(struct et_softc *sc, int start)
2021 {
2022         struct ifnet *ifp = &sc->arpcom.ac_if;
2023         struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
2024         struct et_txbuf_data *tbd = &sc->sc_tx_data;
2025         uint32_t tx_done;
2026         int end, wrap;
2027
2028         if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
2029                 return;
2030
2031         if (tbd->tbd_used == 0)
2032                 return;
2033
2034         tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);
2035         end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX);
2036         wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0;
2037
2038         while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) {
2039                 struct et_txbuf *tb;
2040
2041                 KKASSERT(tbd->tbd_start_index < ET_TX_NDESC);
2042                 tb = &tbd->tbd_buf[tbd->tbd_start_index];
2043
2044                 bzero(&tx_ring->tr_desc[tbd->tbd_start_index],
2045                       sizeof(struct et_txdesc));
2046
2047                 if (tb->tb_mbuf != NULL) {
2048                         bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap);
2049                         m_freem(tb->tb_mbuf);
2050                         tb->tb_mbuf = NULL;
2051                         ifp->if_opackets++;
2052                 }
2053
2054                 if (++tbd->tbd_start_index == ET_TX_NDESC) {
2055                         tbd->tbd_start_index = 0;
2056                         tbd->tbd_start_wrap ^= 1;
2057                 }
2058
2059                 KKASSERT(tbd->tbd_used > 0);
2060                 tbd->tbd_used--;
2061         }
2062
2063         if (tbd->tbd_used == 0)
2064                 ifp->if_timer = 0;
2065         if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC)
2066                 ifp->if_flags &= ~IFF_OACTIVE;
2067
2068         if (start)
2069                 if_devstart(ifp);
2070 }
2071
2072 static void
2073 et_tick(void *xsc)
2074 {
2075         struct et_softc *sc = xsc;
2076         struct ifnet *ifp = &sc->arpcom.ac_if;
2077         struct mii_data *mii = device_get_softc(sc->sc_miibus);
2078
2079         lwkt_serialize_enter(ifp->if_serializer);
2080
2081         mii_tick(mii);
2082         if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 &&
2083             (mii->mii_media_status & IFM_ACTIVE) &&
2084             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2085                 if_printf(ifp, "Link up, enable TX/RX\n");
2086                 if (et_enable_txrx(sc, 0) == 0)
2087                         if_devstart(ifp);
2088         }
2089         callout_reset(&sc->sc_tick, hz, et_tick, sc);
2090
2091         lwkt_serialize_exit(ifp->if_serializer);
2092 }
2093
2094 static int
2095 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init)
2096 {
2097         return et_newbuf(rbd, buf_idx, init, MCLBYTES);
2098 }
2099
2100 static int
2101 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init)
2102 {
2103         return et_newbuf(rbd, buf_idx, init, MHLEN);
2104 }
2105
2106 static int
2107 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0)
2108 {
2109         struct et_softc *sc = rbd->rbd_softc;
2110         struct et_rxbuf *rb;
2111         struct mbuf *m;
2112         bus_dma_segment_t seg;
2113         bus_dmamap_t dmap;
2114         int error, len, nseg;
2115
2116         KASSERT(!rbd->rbd_jumbo, ("calling %s with jumbo ring\n", __func__));
2117
2118         KKASSERT(buf_idx < ET_RX_NDESC);
2119         rb = &rbd->rbd_buf[buf_idx];
2120
2121         m = m_getl(len0, init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR, &len);
2122         if (m == NULL) {
2123                 error = ENOBUFS;
2124
2125                 if (init) {
2126                         if_printf(&sc->arpcom.ac_if,
2127                                   "m_getl failed, size %d\n", len0);
2128                         return error;
2129                 } else {
2130                         goto back;
2131                 }
2132         }
2133         m->m_len = m->m_pkthdr.len = len;
2134
2135         /*
2136          * Try load RX mbuf into temporary DMA tag
2137          */
2138         error = bus_dmamap_load_mbuf_segment(sc->sc_rxbuf_dtag,
2139                         sc->sc_rxbuf_tmp_dmap, m, &seg, 1, &nseg,
2140                         BUS_DMA_NOWAIT);
2141         if (error) {
2142                 m_freem(m);
2143                 if (init) {
2144                         if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2145                         return error;
2146                 } else {
2147                         goto back;
2148                 }
2149         }
2150
2151         if (!init) {
2152                 bus_dmamap_sync(sc->sc_rxbuf_dtag, rb->rb_dmap,
2153                                 BUS_DMASYNC_POSTREAD);
2154                 bus_dmamap_unload(sc->sc_rxbuf_dtag, rb->rb_dmap);
2155         }
2156         rb->rb_mbuf = m;
2157         rb->rb_paddr = seg.ds_addr;
2158
2159         /*
2160          * Swap RX buf's DMA map with the loaded temporary one
2161          */
2162         dmap = rb->rb_dmap;
2163         rb->rb_dmap = sc->sc_rxbuf_tmp_dmap;
2164         sc->sc_rxbuf_tmp_dmap = dmap;
2165
2166         error = 0;
2167 back:
2168         et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
2169         return error;
2170 }
2171
2172 static int
2173 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS)
2174 {
2175         struct et_softc *sc = arg1;
2176         struct ifnet *ifp = &sc->arpcom.ac_if;
2177         int error = 0, v;
2178
2179         lwkt_serialize_enter(ifp->if_serializer);
2180
2181         v = sc->sc_rx_intr_npkts;
2182         error = sysctl_handle_int(oidp, &v, 0, req);
2183         if (error || req->newptr == NULL)
2184                 goto back;
2185         if (v <= 0) {
2186                 error = EINVAL;
2187                 goto back;
2188         }
2189
2190         if (sc->sc_rx_intr_npkts != v) {
2191                 if (ifp->if_flags & IFF_RUNNING)
2192                         CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v);
2193                 sc->sc_rx_intr_npkts = v;
2194         }
2195 back:
2196         lwkt_serialize_exit(ifp->if_serializer);
2197         return error;
2198 }
2199
2200 static int
2201 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS)
2202 {
2203         struct et_softc *sc = arg1;
2204         struct ifnet *ifp = &sc->arpcom.ac_if;
2205         int error = 0, v;
2206
2207         lwkt_serialize_enter(ifp->if_serializer);
2208
2209         v = sc->sc_rx_intr_delay;
2210         error = sysctl_handle_int(oidp, &v, 0, req);
2211         if (error || req->newptr == NULL)
2212                 goto back;
2213         if (v <= 0) {
2214                 error = EINVAL;
2215                 goto back;
2216         }
2217
2218         if (sc->sc_rx_intr_delay != v) {
2219                 if (ifp->if_flags & IFF_RUNNING)
2220                         CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v);
2221                 sc->sc_rx_intr_delay = v;
2222         }
2223 back:
2224         lwkt_serialize_exit(ifp->if_serializer);
2225         return error;
2226 }
2227
2228 static void
2229 et_setmedia(struct et_softc *sc)
2230 {
2231         struct mii_data *mii = device_get_softc(sc->sc_miibus);
2232         uint32_t cfg2, ctrl;
2233
2234         cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
2235         cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
2236                   ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
2237         cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
2238                 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN);
2239
2240         ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
2241         ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
2242
2243         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
2244                 cfg2 |= ET_MAC_CFG2_MODE_GMII;
2245         } else {
2246                 cfg2 |= ET_MAC_CFG2_MODE_MII;
2247                 ctrl |= ET_MAC_CTRL_MODE_MII;
2248         }
2249
2250         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
2251                 cfg2 |= ET_MAC_CFG2_FDX;
2252         else
2253                 ctrl |= ET_MAC_CTRL_GHDX;
2254
2255         CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
2256         CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
2257 }
2258
2259 static int
2260 et_jumbo_mem_alloc(device_t dev)
2261 {
2262         struct et_softc *sc = device_get_softc(dev);
2263         struct et_jumbo_data *jd = &sc->sc_jumbo_data;
2264         bus_addr_t paddr;
2265         uint8_t *buf;
2266         int i;
2267
2268         jd->jd_buf = bus_dmamem_coherent_any(sc->sc_dtag,
2269                         ET_JUMBO_ALIGN, ET_JUMBO_MEM_SIZE, BUS_DMA_WAITOK,
2270                         &jd->jd_dtag, &jd->jd_dmap, &paddr);
2271         if (jd->jd_buf == NULL) {
2272                 device_printf(dev, "can't create jumbo DMA stuffs\n");
2273                 return ENOMEM;
2274         }
2275
2276         jd->jd_slots = kmalloc(sizeof(*jd->jd_slots) * ET_JSLOTS, M_DEVBUF,
2277                                M_WAITOK | M_ZERO);
2278         lwkt_serialize_init(&jd->jd_serializer);
2279         SLIST_INIT(&jd->jd_free_slots);
2280
2281         buf = jd->jd_buf;
2282         for (i = 0; i < ET_JSLOTS; ++i) {
2283                 struct et_jslot *jslot = &jd->jd_slots[i];
2284
2285                 jslot->jslot_data = jd;
2286                 jslot->jslot_buf = buf;
2287                 jslot->jslot_paddr = paddr;
2288                 jslot->jslot_inuse = 0;
2289                 jslot->jslot_index = i;
2290                 SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot, jslot_link);
2291
2292                 buf += ET_JLEN;
2293                 paddr += ET_JLEN;
2294         }
2295         return 0;
2296 }
2297
2298 static void
2299 et_jumbo_mem_free(device_t dev)
2300 {
2301         struct et_softc *sc = device_get_softc(dev);
2302         struct et_jumbo_data *jd = &sc->sc_jumbo_data;
2303
2304         KKASSERT(sc->sc_flags & ET_FLAG_JUMBO);
2305
2306         kfree(jd->jd_slots, M_DEVBUF);
2307         et_dma_mem_destroy(jd->jd_dtag, jd->jd_buf, jd->jd_dmap);
2308 }
2309
2310 static struct et_jslot *
2311 et_jalloc(struct et_jumbo_data *jd)
2312 {
2313         struct et_jslot *jslot;
2314
2315         lwkt_serialize_enter(&jd->jd_serializer);
2316
2317         jslot = SLIST_FIRST(&jd->jd_free_slots);
2318         if (jslot) {
2319                 SLIST_REMOVE_HEAD(&jd->jd_free_slots, jslot_link);
2320                 jslot->jslot_inuse = 1;
2321         }
2322
2323         lwkt_serialize_exit(&jd->jd_serializer);
2324         return jslot;
2325 }
2326
2327 static void
2328 et_jfree(void *xjslot)
2329 {
2330         struct et_jslot *jslot = xjslot;
2331         struct et_jumbo_data *jd = jslot->jslot_data;
2332
2333         if (&jd->jd_slots[jslot->jslot_index] != jslot) {
2334                 panic("%s wrong jslot!?\n", __func__);
2335         } else if (jslot->jslot_inuse == 0) {
2336                 panic("%s jslot already freed\n", __func__);
2337         } else {
2338                 lwkt_serialize_enter(&jd->jd_serializer);
2339
2340                 atomic_subtract_int(&jslot->jslot_inuse, 1);
2341                 if (jslot->jslot_inuse == 0) {
2342                         SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot,
2343                                           jslot_link);
2344                 }
2345
2346                 lwkt_serialize_exit(&jd->jd_serializer);
2347         }
2348 }
2349
2350 static void
2351 et_jref(void *xjslot)
2352 {
2353         struct et_jslot *jslot = xjslot;
2354         struct et_jumbo_data *jd = jslot->jslot_data;
2355
2356         if (&jd->jd_slots[jslot->jslot_index] != jslot)
2357                 panic("%s wrong jslot!?\n", __func__);
2358         else if (jslot->jslot_inuse == 0)
2359                 panic("%s jslot already freed\n", __func__);
2360         else
2361                 atomic_add_int(&jslot->jslot_inuse, 1);
2362 }
2363
2364 static int
2365 et_newbuf_jumbo(struct et_rxbuf_data *rbd, int buf_idx, int init)
2366 {
2367         struct et_softc *sc = rbd->rbd_softc;
2368         struct et_rxbuf *rb;
2369         struct mbuf *m;
2370         struct et_jslot *jslot;
2371         int error;
2372
2373         KASSERT(rbd->rbd_jumbo, ("calling %s with non-jumbo ring\n", __func__));
2374
2375         KKASSERT(buf_idx < ET_RX_NDESC);
2376         rb = &rbd->rbd_buf[buf_idx];
2377
2378         error = ENOBUFS;
2379
2380         MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2381         if (m == NULL) {
2382                 if (init) {
2383                         if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
2384                         return error;
2385                 } else {
2386                         goto back;
2387                 }
2388         }
2389
2390         jslot = et_jalloc(&sc->sc_jumbo_data);
2391         if (jslot == NULL) {
2392                 m_freem(m);
2393
2394                 if (init) {
2395                         if_printf(&sc->arpcom.ac_if,
2396                                   "jslot allocation failed\n");
2397                         return error;
2398                 } else {
2399                         goto back;
2400                 }
2401         }
2402
2403         m->m_ext.ext_arg = jslot;
2404         m->m_ext.ext_buf = jslot->jslot_buf;
2405         m->m_ext.ext_free = et_jfree;
2406         m->m_ext.ext_ref = et_jref;
2407         m->m_ext.ext_size = ET_JUMBO_FRAMELEN;
2408         m->m_flags |= M_EXT;
2409         m->m_data = m->m_ext.ext_buf;
2410         m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2411
2412         rb->rb_mbuf = m;
2413         rb->rb_paddr = jslot->jslot_paddr;
2414
2415         error = 0;
2416 back:
2417         et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
2418         return error;
2419 }
2420
2421 static void
2422 et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr)
2423 {
2424         struct et_rxdesc_ring *rx_ring = rbd->rbd_ring;
2425         struct et_rxdesc *desc;
2426
2427         KKASSERT(buf_idx < ET_RX_NDESC);
2428         desc = &rx_ring->rr_desc[buf_idx];
2429
2430         desc->rd_addr_hi = ET_ADDR_HI(paddr);
2431         desc->rd_addr_lo = ET_ADDR_LO(paddr);
2432         desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX);
2433 }