1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
33 #include "intel_ringbuffer.h"
34 #include <linux/workqueue.h>
36 extern struct drm_i915_private *i915_mch_dev;
38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
40 #define BEGIN_LP_RING(n) \
41 intel_ring_begin(LP_RING(dev_priv), (n))
44 intel_ring_emit(LP_RING(dev_priv), x)
46 #define ADVANCE_LP_RING() \
47 __intel_ring_advance(LP_RING(dev_priv))
50 * Lock test for when it's just for synchronization of ring access.
52 * In that case, we don't need to do it when GEM is initialized as nobody else
53 * has access to the ring.
55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
56 if (LP_RING(dev->dev_private)->buffer->obj == NULL) \
57 LOCK_TEST_WITH_RETURN(dev, file); \
61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
63 if (I915_NEED_GFX_HWS(dev_priv->dev))
64 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
66 return intel_read_status_page(LP_RING(dev_priv), reg);
69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
71 #define I915_BREADCRUMB_INDEX 0x21
73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
75 /* XXX: We don't care about dri1 */
79 static void i915_write_hws_pga(struct drm_device *dev)
81 struct drm_i915_private *dev_priv = dev->dev_private;
84 addr = dev_priv->status_page_dmah->busaddr;
85 if (INTEL_INFO(dev)->gen >= 4)
86 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
87 I915_WRITE(HWS_PGA, addr);
91 * Frees the hardware status page, whether it's a physical address or a virtual
92 * address set up by the X Server.
94 static void i915_free_hws(struct drm_device *dev)
96 struct drm_i915_private *dev_priv = dev->dev_private;
97 struct intel_engine_cs *ring = LP_RING(dev_priv);
99 if (dev_priv->status_page_dmah) {
100 drm_pci_free(dev, dev_priv->status_page_dmah);
101 dev_priv->status_page_dmah = NULL;
104 if (ring->status_page.gfx_addr) {
105 ring->status_page.gfx_addr = 0;
106 #if 0 /* We don't care about dri1 */
107 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
111 /* Need to rewrite hardware status page */
112 I915_WRITE(HWS_PGA, 0x1ffff000);
115 void i915_kernel_lost_context(struct drm_device * dev)
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct drm_i915_private *master_priv = dev_priv;
119 struct intel_engine_cs *ring = LP_RING(dev_priv);
120 struct intel_ringbuffer *ringbuf = ring->buffer;
123 * We should never lose context on the ring with modesetting
124 * as we don't expose it to userspace
126 if (drm_core_check_feature(dev, DRIVER_MODESET))
129 ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR;
130 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
131 ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE);
132 if (ringbuf->space < 0)
133 ringbuf->space += ringbuf->size;
136 if (!dev->primary->master)
139 master_priv = dev->primary->master->driver_priv;
141 if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv)
142 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
145 static int i915_dma_cleanup(struct drm_device * dev)
147 struct drm_i915_private *dev_priv = dev->dev_private;
150 /* Make sure interrupts are disabled here because the uninstall ioctl
151 * may not have been called from userspace and after dev_private
152 * is freed, it's too late.
154 if (dev->irq_enabled)
155 drm_irq_uninstall(dev);
157 mutex_lock(&dev->struct_mutex);
158 for (i = 0; i < I915_NUM_RINGS; i++)
159 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
160 mutex_unlock(&dev->struct_mutex);
162 /* Clear the HWS virtual address at teardown */
163 if (I915_NEED_GFX_HWS(dev))
169 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
171 struct drm_i915_private *dev_priv = dev->dev_private;
174 dev_priv->sarea = drm_getsarea(dev);
175 if (!dev_priv->sarea) {
176 DRM_ERROR("can not find sarea!\n");
177 i915_dma_cleanup(dev);
181 dev_priv->sarea_priv = (drm_i915_sarea_t *)
182 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
184 if (init->ring_size != 0) {
185 if (LP_RING(dev_priv)->buffer->obj != NULL) {
186 i915_dma_cleanup(dev);
187 DRM_ERROR("Client tried to initialize ringbuffer in "
192 ret = intel_render_ring_init_dri(dev,
196 i915_dma_cleanup(dev);
201 dev_priv->dri1.cpp = init->cpp;
202 dev_priv->dri1.back_offset = init->back_offset;
203 dev_priv->dri1.front_offset = init->front_offset;
204 dev_priv->dri1.current_page = 0;
205 dev_priv->sarea_priv->pf_current_page = 0;
208 /* Allow hardware batchbuffers unless told otherwise.
210 dev_priv->dri1.allow_batchbuffer = 1;
215 static int i915_dma_resume(struct drm_device * dev)
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 struct intel_engine_cs *ring = LP_RING(dev_priv);
220 DRM_DEBUG_DRIVER("%s\n", __func__);
222 if (ring->buffer->virtual_start == NULL) {
223 DRM_ERROR("can not ioremap virtual address for"
228 /* Program Hardware Status Page */
229 if (!ring->status_page.page_addr) {
230 DRM_ERROR("Can not find hardware status page\n");
233 DRM_DEBUG_DRIVER("hw status page @ %p\n",
234 ring->status_page.page_addr);
235 if (ring->status_page.gfx_addr != 0)
236 intel_ring_setup_status_page(ring);
238 i915_write_hws_pga(dev);
240 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
245 static int i915_dma_init(struct drm_device *dev, void *data,
246 struct drm_file *file_priv)
248 drm_i915_init_t *init = data;
251 if (drm_core_check_feature(dev, DRIVER_MODESET))
254 switch (init->func) {
256 retcode = i915_initialize(dev, init);
258 case I915_CLEANUP_DMA:
259 retcode = i915_dma_cleanup(dev);
261 case I915_RESUME_DMA:
262 retcode = i915_dma_resume(dev);
272 /* Implement basically the same security restrictions as hardware does
273 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
275 * Most of the calculations below involve calculating the size of a
276 * particular instruction. It's important to get the size right as
277 * that tells us where the next instruction to check is. Any illegal
278 * instruction detected will be given a size of zero, which is a
279 * signal to abort the rest of the buffer.
281 static int validate_cmd(int cmd)
283 switch (((cmd >> 29) & 0x7)) {
285 switch ((cmd >> 23) & 0x3f) {
287 return 1; /* MI_NOOP */
289 return 1; /* MI_FLUSH */
291 return 0; /* disallow everything else */
295 return 0; /* reserved */
297 return (cmd & 0xff) + 2; /* 2d commands */
299 if (((cmd >> 24) & 0x1f) <= 0x18)
302 switch ((cmd >> 24) & 0x1f) {
306 switch ((cmd >> 16) & 0xff) {
308 return (cmd & 0x1f) + 2;
310 return (cmd & 0xf) + 2;
312 return (cmd & 0xffff) + 2;
316 return (cmd & 0xffff) + 1;
320 if ((cmd & (1 << 23)) == 0) /* inline vertices */
321 return (cmd & 0x1ffff) + 2;
322 else if (cmd & (1 << 17)) /* indirect random */
323 if ((cmd & 0xffff) == 0)
324 return 0; /* unknown length, too hard */
326 return (((cmd & 0xffff) + 1) / 2) + 1;
328 return 2; /* indirect sequential */
339 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
341 struct drm_i915_private *dev_priv = dev->dev_private;
344 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8)
347 for (i = 0; i < dwords;) {
348 int sz = validate_cmd(buffer[i]);
349 if (sz == 0 || i + sz > dwords)
354 ret = BEGIN_LP_RING((dwords+1)&~1);
358 for (i = 0; i < dwords; i++)
369 i915_emit_box(struct drm_device *dev,
370 struct drm_clip_rect *box,
373 struct drm_i915_private *dev_priv = dev->dev_private;
376 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
377 box->y2 <= 0 || box->x2 <= 0) {
378 DRM_ERROR("Bad box %d,%d..%d,%d\n",
379 box->x1, box->y1, box->x2, box->y2);
383 if (INTEL_INFO(dev)->gen >= 4) {
384 ret = BEGIN_LP_RING(4);
388 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
389 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
390 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
393 ret = BEGIN_LP_RING(6);
397 OUT_RING(GFX_OP_DRAWRECT_INFO);
399 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
400 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
409 /* XXX: Emitting the counter should really be moved to part of the IRQ
410 * emit. For now, do it in both places:
413 static void i915_emit_breadcrumb(struct drm_device *dev)
415 struct drm_i915_private *dev_priv = dev->dev_private;
417 dev_priv->dri1.counter++;
418 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
419 dev_priv->dri1.counter = 0;
420 if (dev_priv->sarea_priv)
421 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
423 if (BEGIN_LP_RING(4) == 0) {
424 OUT_RING(MI_STORE_DWORD_INDEX);
425 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
426 OUT_RING(dev_priv->dri1.counter);
432 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
433 drm_i915_cmdbuffer_t *cmd,
434 struct drm_clip_rect *cliprects,
437 int nbox = cmd->num_cliprects;
438 int i = 0, count, ret;
441 DRM_ERROR("alignment");
445 i915_kernel_lost_context(dev);
447 count = nbox ? nbox : 1;
449 for (i = 0; i < count; i++) {
451 ret = i915_emit_box(dev, &cliprects[i],
457 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
462 i915_emit_breadcrumb(dev);
466 static int i915_dispatch_batchbuffer(struct drm_device * dev,
467 drm_i915_batchbuffer_t * batch,
468 struct drm_clip_rect *cliprects)
470 struct drm_i915_private *dev_priv = dev->dev_private;
471 int nbox = batch->num_cliprects;
474 if ((batch->start | batch->used) & 0x7) {
475 DRM_ERROR("alignment");
479 i915_kernel_lost_context(dev);
481 count = nbox ? nbox : 1;
482 for (i = 0; i < count; i++) {
484 ret = i915_emit_box(dev, &cliprects[i],
485 batch->DR1, batch->DR4);
490 if (!IS_I830(dev) && !IS_845G(dev)) {
491 ret = BEGIN_LP_RING(2);
495 if (INTEL_INFO(dev)->gen >= 4) {
496 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
497 OUT_RING(batch->start);
499 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
500 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
503 ret = BEGIN_LP_RING(4);
507 OUT_RING(MI_BATCH_BUFFER);
508 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
509 OUT_RING(batch->start + batch->used - 4);
516 if (IS_G4X(dev) || IS_GEN5(dev)) {
517 if (BEGIN_LP_RING(2) == 0) {
518 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
524 i915_emit_breadcrumb(dev);
528 static int i915_dispatch_flip(struct drm_device * dev)
530 struct drm_i915_private *dev_priv = dev->dev_private;
533 if (!dev_priv->sarea_priv)
536 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
538 dev_priv->dri1.current_page,
539 dev_priv->sarea_priv->pf_current_page);
541 i915_kernel_lost_context(dev);
543 ret = BEGIN_LP_RING(10);
547 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
550 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
552 if (dev_priv->dri1.current_page == 0) {
553 OUT_RING(dev_priv->dri1.back_offset);
554 dev_priv->dri1.current_page = 1;
556 OUT_RING(dev_priv->dri1.front_offset);
557 dev_priv->dri1.current_page = 0;
561 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
566 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
568 if (BEGIN_LP_RING(4) == 0) {
569 OUT_RING(MI_STORE_DWORD_INDEX);
570 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
571 OUT_RING(dev_priv->dri1.counter);
576 dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
580 static int i915_quiescent(struct drm_device *dev)
582 i915_kernel_lost_context(dev);
583 return intel_ring_idle(LP_RING(dev->dev_private));
586 static int i915_flush_ioctl(struct drm_device *dev, void *data,
587 struct drm_file *file_priv)
591 if (drm_core_check_feature(dev, DRIVER_MODESET))
594 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
596 mutex_lock(&dev->struct_mutex);
597 ret = i915_quiescent(dev);
598 mutex_unlock(&dev->struct_mutex);
603 static int i915_batchbuffer(struct drm_device *dev, void *data,
604 struct drm_file *file_priv)
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 drm_i915_sarea_t *sarea_priv;
608 drm_i915_batchbuffer_t *batch = data;
610 struct drm_clip_rect *cliprects = NULL;
612 if (drm_core_check_feature(dev, DRIVER_MODESET))
615 sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
617 if (!dev_priv->dri1.allow_batchbuffer) {
618 DRM_ERROR("Batchbuffer ioctl disabled\n");
622 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
623 batch->start, batch->used, batch->num_cliprects);
625 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
627 if (batch->num_cliprects < 0)
630 if (batch->num_cliprects) {
631 cliprects = kcalloc(batch->num_cliprects,
634 if (cliprects == NULL)
637 ret = copy_from_user(cliprects, batch->cliprects,
638 batch->num_cliprects *
639 sizeof(struct drm_clip_rect));
646 mutex_lock(&dev->struct_mutex);
647 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
648 mutex_unlock(&dev->struct_mutex);
651 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
659 static int i915_cmdbuffer(struct drm_device *dev, void *data,
660 struct drm_file *file_priv)
662 struct drm_i915_private *dev_priv = dev->dev_private;
663 drm_i915_sarea_t *sarea_priv;
664 drm_i915_cmdbuffer_t *cmdbuf = data;
665 struct drm_clip_rect *cliprects = NULL;
669 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
670 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
672 if (drm_core_check_feature(dev, DRIVER_MODESET))
675 sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
677 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
679 if (cmdbuf->num_cliprects < 0)
682 batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
683 if (batch_data == NULL)
686 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
689 goto fail_batch_free;
692 if (cmdbuf->num_cliprects) {
693 cliprects = kcalloc(cmdbuf->num_cliprects,
694 sizeof(*cliprects), GFP_KERNEL);
695 if (cliprects == NULL) {
697 goto fail_batch_free;
700 ret = copy_from_user(cliprects, cmdbuf->cliprects,
701 cmdbuf->num_cliprects *
702 sizeof(struct drm_clip_rect));
709 mutex_lock(&dev->struct_mutex);
710 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
711 mutex_unlock(&dev->struct_mutex);
713 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
718 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
728 static int i915_emit_irq(struct drm_device * dev)
730 struct drm_i915_private *dev_priv = dev->dev_private;
732 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
735 i915_kernel_lost_context(dev);
737 DRM_DEBUG_DRIVER("\n");
739 dev_priv->dri1.counter++;
740 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
741 dev_priv->dri1.counter = 1;
742 if (dev_priv->sarea_priv)
743 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
745 if (BEGIN_LP_RING(4) == 0) {
746 OUT_RING(MI_STORE_DWORD_INDEX);
747 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
748 OUT_RING(dev_priv->dri1.counter);
749 OUT_RING(MI_USER_INTERRUPT);
753 return dev_priv->dri1.counter;
756 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
758 struct drm_i915_private *dev_priv = dev->dev_private;
760 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
763 struct intel_engine_cs *ring = LP_RING(dev_priv);
765 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
766 READ_BREADCRUMB(dev_priv));
769 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
770 if (master_priv->sarea_priv)
771 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
775 if (master_priv->sarea_priv)
776 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
778 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
779 if (dev_priv->sarea_priv) {
780 dev_priv->sarea_priv->last_dispatch =
781 READ_BREADCRUMB(dev_priv);
786 if (dev_priv->sarea_priv)
787 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
790 if (ring->irq_get(ring)) {
791 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
792 READ_BREADCRUMB(dev_priv) >= irq_nr);
794 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
798 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
799 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
805 /* Needs the lock as it touches the ring.
807 static int i915_irq_emit(struct drm_device *dev, void *data,
808 struct drm_file *file_priv)
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 drm_i915_irq_emit_t *emit = data;
814 if (drm_core_check_feature(dev, DRIVER_MODESET))
817 if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) {
818 DRM_ERROR("called with no initialization\n");
822 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
824 mutex_lock(&dev->struct_mutex);
825 result = i915_emit_irq(dev);
826 mutex_unlock(&dev->struct_mutex);
828 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
829 DRM_ERROR("copy_to_user\n");
836 /* Doesn't need the hardware lock.
838 static int i915_irq_wait(struct drm_device *dev, void *data,
839 struct drm_file *file_priv)
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 drm_i915_irq_wait_t *irqwait = data;
844 if (drm_core_check_feature(dev, DRIVER_MODESET))
848 DRM_ERROR("called with no initialization\n");
852 return i915_wait_irq(dev, irqwait->irq_seq);
855 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
856 struct drm_file *file_priv)
858 struct drm_i915_private *dev_priv = dev->dev_private;
859 drm_i915_vblank_pipe_t *pipe = data;
861 if (drm_core_check_feature(dev, DRIVER_MODESET))
865 DRM_ERROR("called with no initialization\n");
869 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
875 * Schedule buffer swap at given vertical blank.
877 static int i915_vblank_swap(struct drm_device *dev, void *data,
878 struct drm_file *file_priv)
880 /* The delayed swap mechanism was fundamentally racy, and has been
881 * removed. The model was that the client requested a delayed flip/swap
882 * from the kernel, then waited for vblank before continuing to perform
883 * rendering. The problem was that the kernel might wake the client
884 * up before it dispatched the vblank swap (since the lock has to be
885 * held while touching the ringbuffer), in which case the client would
886 * clear and start the next frame before the swap occurred, and
887 * flicker would occur in addition to likely missing the vblank.
889 * In the absence of this ioctl, userland falls back to a correct path
890 * of waiting for a vblank, then dispatching the swap on its own.
891 * Context switching to userland and back is plenty fast enough for
892 * meeting the requirements of vblank swapping.
897 static int i915_flip_bufs(struct drm_device *dev, void *data,
898 struct drm_file *file_priv)
902 if (drm_core_check_feature(dev, DRIVER_MODESET))
905 DRM_DEBUG_DRIVER("%s\n", __func__);
907 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
909 mutex_lock(&dev->struct_mutex);
910 ret = i915_dispatch_flip(dev);
911 mutex_unlock(&dev->struct_mutex);
916 static int i915_getparam(struct drm_device *dev, void *data,
917 struct drm_file *file_priv)
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 drm_i915_getparam_t *param = data;
924 DRM_ERROR("called with no initialization\n");
928 switch (param->param) {
929 case I915_PARAM_IRQ_ACTIVE:
930 value = dev->irq_enabled ? 1 : 0;
932 case I915_PARAM_ALLOW_BATCHBUFFER:
933 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
935 case I915_PARAM_LAST_DISPATCH:
936 value = READ_BREADCRUMB(dev_priv);
938 case I915_PARAM_CHIPSET_ID:
939 value = dev->pdev->device;
941 case I915_PARAM_HAS_GEM:
944 case I915_PARAM_NUM_FENCES_AVAIL:
945 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
947 case I915_PARAM_HAS_OVERLAY:
948 value = dev_priv->overlay ? 1 : 0;
950 case I915_PARAM_HAS_PAGEFLIPPING:
953 case I915_PARAM_HAS_EXECBUF2:
957 case I915_PARAM_HAS_BSD:
958 value = intel_ring_initialized(&dev_priv->ring[VCS]);
960 case I915_PARAM_HAS_BLT:
961 value = intel_ring_initialized(&dev_priv->ring[BCS]);
963 case I915_PARAM_HAS_VEBOX:
964 value = intel_ring_initialized(&dev_priv->ring[VECS]);
966 case I915_PARAM_HAS_RELAXED_FENCING:
969 case I915_PARAM_HAS_COHERENT_RINGS:
972 case I915_PARAM_HAS_EXEC_CONSTANTS:
973 value = INTEL_INFO(dev)->gen >= 4;
975 case I915_PARAM_HAS_RELAXED_DELTA:
978 case I915_PARAM_HAS_GEN7_SOL_RESET:
981 case I915_PARAM_HAS_LLC:
982 value = HAS_LLC(dev);
984 case I915_PARAM_HAS_WT:
987 case I915_PARAM_HAS_ALIASING_PPGTT:
988 value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev);
990 case I915_PARAM_HAS_WAIT_TIMEOUT:
993 case I915_PARAM_HAS_SEMAPHORES:
994 value = i915_semaphore_is_enabled(dev);
996 case I915_PARAM_HAS_PINNED_BATCHES:
999 case I915_PARAM_HAS_EXEC_NO_RELOC:
1002 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1005 case I915_PARAM_CMD_PARSER_VERSION:
1006 value = i915_cmd_parser_get_version();
1009 DRM_DEBUG("Unknown parameter %d\n", param->param);
1013 if (copy_to_user(param->value, &value, sizeof(int))) {
1014 DRM_ERROR("copy_to_user failed\n");
1021 static int i915_setparam(struct drm_device *dev, void *data,
1022 struct drm_file *file_priv)
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 drm_i915_setparam_t *param = data;
1028 DRM_ERROR("called with no initialization\n");
1032 switch (param->param) {
1033 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1035 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1037 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1038 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1040 case I915_SETPARAM_NUM_USED_FENCES:
1041 if (param->value > dev_priv->num_fence_regs ||
1044 /* Userspace can use first N regs */
1045 dev_priv->fence_reg_start = param->value;
1048 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1056 static int i915_set_status_page(struct drm_device *dev, void *data,
1057 struct drm_file *file_priv)
1059 #if 0 /* We don't care about dri1 */
1060 struct drm_i915_private *dev_priv = dev->dev_private;
1061 drm_i915_hws_addr_t *hws = data;
1062 struct intel_engine_cs *ring;
1064 if (drm_core_check_feature(dev, DRIVER_MODESET))
1067 if (!I915_NEED_GFX_HWS(dev))
1071 DRM_ERROR("called with no initialization\n");
1075 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1076 WARN(1, "tried to set status page when mode setting active\n");
1080 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1082 ring = LP_RING(dev_priv);
1083 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1085 dev_priv->dri1.gfx_hws_cpu_addr =
1086 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1087 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1088 i915_dma_cleanup(dev);
1089 ring->status_page.gfx_addr = 0;
1090 DRM_ERROR("can not ioremap virtual address for"
1091 " G33 hw status page\n");
1095 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1096 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1098 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1099 ring->status_page.gfx_addr);
1100 DRM_DEBUG_DRIVER("load hws at %p\n",
1101 ring->status_page.page_addr);
1107 static int i915_get_bridge_dev(struct drm_device *dev)
1109 struct drm_i915_private *dev_priv = dev->dev_private;
1110 static struct pci_dev i915_bridge_dev;
1112 i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1113 if (!i915_bridge_dev.dev) {
1114 DRM_ERROR("bridge device not found\n");
1118 dev_priv->bridge_dev = &i915_bridge_dev;
1122 #define MCHBAR_I915 0x44
1123 #define MCHBAR_I965 0x48
1124 #define MCHBAR_SIZE (4*4096)
1126 #define DEVEN_REG 0x54
1127 #define DEVEN_MCHBAR_EN (1 << 28)
1129 /* Allocate space for the MCH regs if needed, return nonzero on error */
1131 intel_alloc_mchbar_resource(struct drm_device *dev)
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1136 u32 temp_lo, temp_hi = 0;
1139 if (INTEL_INFO(dev)->gen >= 4)
1140 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1141 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1142 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1144 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1147 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1151 /* Get some space for it */
1152 vga = device_get_parent(dev->dev);
1153 dev_priv->mch_res_rid = 0x100;
1154 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1155 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1156 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1157 if (dev_priv->mch_res == NULL) {
1158 DRM_ERROR("failed mchbar resource alloc\n");
1162 if (INTEL_INFO(dev)->gen >= 4)
1163 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1164 upper_32_bits(rman_get_start(dev_priv->mch_res)));
1166 pci_write_config_dword(dev_priv->bridge_dev, reg,
1167 lower_32_bits(rman_get_start(dev_priv->mch_res)));
1171 /* Setup MCHBAR if possible, return true if we should disable it again */
1173 intel_setup_mchbar(struct drm_device *dev)
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1180 if (IS_VALLEYVIEW(dev))
1183 dev_priv->mchbar_need_disable = false;
1185 if (IS_I915G(dev) || IS_I915GM(dev)) {
1186 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1187 enabled = !!(temp & DEVEN_MCHBAR_EN);
1189 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1193 /* If it's already enabled, don't have to do anything */
1197 if (intel_alloc_mchbar_resource(dev))
1200 dev_priv->mchbar_need_disable = true;
1202 /* Space is allocated or reserved, so enable it. */
1203 if (IS_I915G(dev) || IS_I915GM(dev)) {
1204 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1205 temp | DEVEN_MCHBAR_EN);
1207 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1208 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1213 intel_teardown_mchbar(struct drm_device *dev)
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1216 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1220 if (dev_priv->mchbar_need_disable) {
1221 if (IS_I915G(dev) || IS_I915GM(dev)) {
1222 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1223 temp &= ~DEVEN_MCHBAR_EN;
1224 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1226 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1228 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1232 if (dev_priv->mch_res != NULL) {
1233 vga = device_get_parent(dev->dev);
1234 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1235 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1236 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1237 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1238 dev_priv->mch_res = NULL;
1243 /* true = enable decode, false = disable decoder */
1244 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1246 struct drm_device *dev = cookie;
1248 intel_modeset_vga_set_state(dev, state);
1250 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1251 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1253 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1256 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1258 struct drm_device *dev = pci_get_drvdata(pdev);
1259 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1260 if (state == VGA_SWITCHEROO_ON) {
1261 pr_info("switched on\n");
1262 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1263 /* i915 resume handler doesn't set to D0 */
1264 pci_set_power_state(dev->pdev, PCI_D0);
1266 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1268 pr_err("switched off\n");
1269 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1270 i915_suspend(dev, pmm);
1271 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1275 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1277 struct drm_device *dev = pci_get_drvdata(pdev);
1280 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1281 * locking inversion with the driver load path. And the access here is
1282 * completely racy anyway. So don't bother with locking for now.
1284 return dev->open_count == 0;
1287 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1288 .set_gpu_state = i915_switcheroo_set_state,
1290 .can_switch = i915_switcheroo_can_switch,
1294 static int i915_load_modeset_init(struct drm_device *dev)
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1299 ret = intel_parse_bios(dev);
1301 DRM_INFO("failed to find VBIOS tables\n");
1304 /* If we have > 1 VGA cards, then we need to arbitrate access
1305 * to the common VGA resources.
1307 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1308 * then we do not take part in VGA arbitration and the
1309 * vga_client_register() fails with -ENODEV.
1311 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1312 if (ret && ret != -ENODEV)
1315 intel_register_dsm_handler();
1317 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1319 goto cleanup_vga_client;
1321 /* Initialise stolen first so that we may reserve preallocated
1322 * objects for the BIOS to KMS transition.
1324 ret = i915_gem_init_stolen(dev);
1326 goto cleanup_vga_switcheroo;
1329 intel_power_domains_init_hw(dev_priv);
1331 ret = drm_irq_install(dev, dev->irq);
1333 goto cleanup_gem_stolen;
1335 /* Important: The output setup functions called by modeset_init need
1336 * working irqs for e.g. gmbus and dp aux transfers. */
1337 intel_modeset_init(dev);
1339 ret = i915_gem_init(dev);
1344 INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1347 intel_modeset_gem_init(dev);
1349 /* Always safe in the mode setting case. */
1350 /* FIXME: do pre/post-mode set stuff in core KMS code */
1351 dev->vblank_disable_allowed = 1;
1352 if (INTEL_INFO(dev)->num_pipes == 0) {
1356 ret = intel_fbdev_init(dev);
1360 /* Only enable hotplug handling once the fbdev is fully set up. */
1361 intel_hpd_init(dev);
1364 * Some ports require correctly set-up hpd registers for detection to
1365 * work properly (leading to ghost connected connector status), e.g. VGA
1366 * on gm45. Hence we can only set up the initial fbdev config after hpd
1367 * irqs are fully enabled. Now we should scan for the initial config
1368 * only once hotplug handling is enabled, but due to screwed-up locking
1369 * around kms/fbdev init we can't protect the fdbev initial config
1370 * scanning against hotplug events. Hence do this first and ignore the
1371 * tiny window where we will loose hotplug notifactions.
1373 intel_fbdev_initial_config(dev);
1375 /* Only enable hotplug handling once the fbdev is fully set up. */
1376 dev_priv->enable_hotplug_processing = true;
1378 drm_kms_helper_poll_init(dev);
1383 mutex_lock(&dev->struct_mutex);
1384 i915_gem_cleanup_ringbuffer(dev);
1385 i915_gem_context_fini(dev);
1386 mutex_unlock(&dev->struct_mutex);
1387 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1389 drm_irq_uninstall(dev);
1392 i915_gem_cleanup_stolen(dev);
1393 cleanup_vga_switcheroo:
1394 vga_switcheroo_unregister_client(dev->pdev);
1396 vga_client_register(dev->pdev, NULL, NULL, NULL);
1403 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1405 struct drm_i915_master_private *master_priv;
1407 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1411 master->driver_priv = master_priv;
1415 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1417 struct drm_i915_master_private *master_priv = master->driver_priv;
1424 master->driver_priv = NULL;
1428 #if IS_ENABLED(CONFIG_FB)
1429 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1431 struct apertures_struct *ap;
1432 struct pci_dev *pdev = dev_priv->dev->pdev;
1435 ap = alloc_apertures(1);
1439 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1440 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1443 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1445 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1450 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1455 #if !defined(CONFIG_VGA_CONSOLE)
1456 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1460 #elif !defined(CONFIG_DUMMY_CONSOLE)
1461 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1466 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1470 DRM_INFO("Replacing VGA console driver\n");
1473 if (con_is_bound(&vga_con))
1474 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1476 ret = do_unregister_con_driver(&vga_con);
1478 /* Ignore "already unregistered". */
1488 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1491 const struct intel_device_info *info = &dev_priv->info;
1493 #define PRINT_S(name) "%s"
1495 #define PRINT_FLAG(name) info->name ? #name "," : ""
1497 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1498 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1500 dev_priv->dev->pdev->device,
1501 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1510 * Determine various intel_device_info fields at runtime.
1512 * Use it when either:
1513 * - it's judged too laborious to fill n static structures with the limit
1514 * when a simple if statement does the job,
1515 * - run-time checks (eg read fuse/strap registers) are needed.
1517 * This function needs to be called:
1518 * - after the MMIO has been setup as we are reading registers,
1519 * - after the PCH has been detected,
1520 * - before the first usage of the fields it can tweak.
1522 static void intel_device_info_runtime_init(struct drm_device *dev)
1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 struct intel_device_info *info;
1526 enum i915_pipe pipe;
1528 info = (struct intel_device_info *)&dev_priv->info;
1530 if (IS_VALLEYVIEW(dev))
1532 info->num_sprites[pipe] = 2;
1535 info->num_sprites[pipe] = 1;
1537 if (i915.disable_display) {
1538 DRM_INFO("Display disabled (module parameter)\n");
1539 info->num_pipes = 0;
1540 } else if (info->num_pipes > 0 &&
1541 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1542 !IS_VALLEYVIEW(dev)) {
1543 u32 fuse_strap = I915_READ(FUSE_STRAP);
1544 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1547 * SFUSE_STRAP is supposed to have a bit signalling the display
1548 * is fused off. Unfortunately it seems that, at least in
1549 * certain cases, fused off display means that PCH display
1550 * reads don't land anywhere. In that case, we read 0s.
1552 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1553 * should be set when taking over after the firmware.
1555 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1556 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1557 (dev_priv->pch_type == PCH_CPT &&
1558 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1559 DRM_INFO("Display fused off, disabling\n");
1560 info->num_pipes = 0;
1566 * i915_driver_load - setup chip and create an initial config
1568 * @flags: startup flags
1570 * The driver load routine has to do several things:
1571 * - drive output discovery via intel_modeset_init()
1572 * - initialize the memory manager
1573 * - allocate initial config memory
1574 * - setup the DRM framebuffer with the allocated memory
1576 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1578 struct drm_i915_private *dev_priv = dev->dev_private;
1579 struct intel_device_info *info, *device_info;
1580 unsigned long base, size;
1581 int ret = 0, mmio_bar, mmio_size;
1582 uint32_t aperture_size;
1583 static struct pci_dev i915_pdev;
1585 /* XXX: dev->pci_device not present in Linux drm */
1586 info = i915_get_device_id(dev->pci_device);
1588 /* XXX: struct pci_dev */
1589 i915_pdev.dev = dev->dev;
1590 dev->pdev = &i915_pdev;
1591 dev->pdev->device = dev->pci_device;
1593 /* Refuse to load on gen6+ without kms enabled. */
1594 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1595 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1596 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1600 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1601 if (dev_priv == NULL)
1604 dev->dev_private = (void *)dev_priv;
1605 dev_priv->dev = dev;
1607 /* copy initial configuration to dev_priv->info */
1608 device_info = (struct intel_device_info *)&dev_priv->info;
1609 *device_info = *info;
1611 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1612 lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1613 spin_init(&dev_priv->backlight_lock, "i915bl");
1614 lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
1615 spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
1616 lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1617 lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1619 intel_pm_setup(dev);
1621 intel_display_crc_init(dev);
1623 i915_dump_device_info(dev_priv);
1625 /* Not all pre-production machines fall into this category, only the
1626 * very first ones. Almost everything should work, except for maybe
1627 * suspend/resume. And we don't implement workarounds that affect only
1628 * pre-production machines. */
1629 if (IS_HSW_EARLY_SDV(dev))
1630 DRM_INFO("This is an early pre-production Haswell machine. "
1631 "It may not be fully functional.\n");
1633 if (i915_get_bridge_dev(dev)) {
1638 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1639 /* Before gen4, the registers and the GTT are behind different BARs.
1640 * However, from gen4 onwards, the registers and the GTT are shared
1641 * in the same BAR, so we want to restrict this ioremap from
1642 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1643 * the register BAR remains the same size for all the earlier
1644 * generations up to Ironlake.
1647 mmio_size = 512*1024;
1649 mmio_size = 2*1024*1024;
1652 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1653 if (!dev_priv->regs) {
1654 DRM_ERROR("failed to map registers\n");
1659 base = drm_get_resource_start(dev, mmio_bar);
1660 size = drm_get_resource_len(dev, mmio_bar);
1662 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1663 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1666 /* This must be called before any calls to HAS_PCH_* */
1667 intel_detect_pch(dev);
1669 intel_uncore_init(dev);
1671 ret = i915_gem_gtt_init(dev);
1675 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1676 ret = i915_kick_out_vgacon(dev_priv);
1678 DRM_ERROR("failed to remove conflicting VGA console\n");
1682 i915_kick_out_firmware_fb(dev_priv);
1686 pci_set_master(dev->pdev);
1688 /* overlay on gen2 is broken and can't address above 1G */
1690 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1692 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1693 * using 32bit addressing, overwriting memory if HWS is located
1696 * The documentation also mentions an issue with undefined
1697 * behaviour if any general state is accessed within a page above 4GB,
1698 * which also needs to be handled carefully.
1700 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1701 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1704 aperture_size = dev_priv->gtt.mappable_end;
1706 dev_priv->gtt.mappable =
1707 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1709 if (dev_priv->gtt.mappable == NULL) {
1714 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1717 /* The i915 workqueue is primarily used for batched retirement of
1718 * requests (and thus managing bo) once the task has been completed
1719 * by the GPU. i915_gem_retire_requests() is called directly when we
1720 * need high-priority retirement, such as waiting for an explicit
1723 * It is also used for periodic low-priority events, such as
1724 * idle-timers and recording error state.
1726 * All tasks on the workqueue are expected to acquire the dev mutex
1727 * so there is no point in running more than one instance of the
1728 * workqueue at any time. Use an ordered one.
1730 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1731 if (dev_priv->wq == NULL) {
1732 DRM_ERROR("Failed to create our workqueue.\n");
1737 intel_irq_init(dev);
1738 intel_uncore_sanitize(dev);
1740 /* Try to make sure MCHBAR is enabled before poking at it */
1741 intel_setup_mchbar(dev);
1742 intel_setup_gmbus(dev);
1743 intel_opregion_setup(dev);
1745 intel_setup_bios(dev);
1749 /* On the 945G/GM, the chipset reports the MSI capability on the
1750 * integrated graphics even though the support isn't actually there
1751 * according to the published specs. It doesn't appear to function
1752 * correctly in testing on 945G.
1753 * This may be a side effect of MSI having been made available for PEG
1754 * and the registers being closely associated.
1756 * According to chipset errata, on the 965GM, MSI interrupts may
1757 * be lost or delayed, but we use them anyways to avoid
1758 * stuck interrupts on some machines.
1761 if (!IS_I945G(dev) && !IS_I945GM(dev))
1762 pci_enable_msi(dev->pdev);
1765 intel_device_info_runtime_init(dev);
1767 if (INTEL_INFO(dev)->num_pipes) {
1768 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1770 goto out_gem_unload;
1773 intel_power_domains_init(dev_priv);
1775 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1776 ret = i915_load_modeset_init(dev);
1778 DRM_ERROR("failed to init modeset\n");
1779 goto out_power_well;
1782 /* Start out suspended in ums mode. */
1783 dev_priv->ums.mm_suspended = 1;
1787 i915_setup_sysfs(dev);
1790 if (INTEL_INFO(dev)->num_pipes) {
1791 /* Must be done after probing outputs */
1792 intel_opregion_init(dev);
1794 acpi_video_register();
1799 intel_gpu_ips_init(dev_priv);
1801 intel_init_runtime_pm(dev_priv);
1806 intel_power_domains_remove(dev_priv);
1807 drm_vblank_cleanup(dev);
1810 intel_teardown_gmbus(dev);
1811 intel_teardown_mchbar(dev);
1812 pm_qos_remove_request(&dev_priv->pm_qos);
1813 destroy_workqueue(dev_priv->wq);
1815 arch_phys_wc_del(dev_priv->gtt.mtrr);
1817 io_mapping_free(dev_priv->gtt.mappable);
1820 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1822 intel_uncore_fini(dev);
1828 int i915_driver_unload(struct drm_device *dev)
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1833 ret = i915_gem_suspend(dev);
1835 DRM_ERROR("failed to idle hardware: %d\n", ret);
1839 intel_fini_runtime_pm(dev_priv);
1841 intel_gpu_ips_teardown();
1843 /* The i915.ko module is still not prepared to be loaded when
1844 * the power well is not enabled, so just enable it in case
1845 * we're going to unload/reload. */
1846 intel_display_set_init_power(dev_priv, true);
1847 intel_power_domains_remove(dev_priv);
1850 i915_teardown_sysfs(dev);
1852 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1853 unregister_shrinker(&dev_priv->mm.shrinker);
1855 io_mapping_free(dev_priv->gtt.mappable);
1857 arch_phys_wc_del(dev_priv->gtt.mtrr);
1860 acpi_video_unregister();
1863 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1864 intel_fbdev_fini(dev);
1865 intel_modeset_cleanup(dev);
1867 cancel_work_sync(&dev_priv->console_resume_work);
1871 * free the memory space allocated for the child device
1872 * config parsed from VBT
1874 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1875 kfree(dev_priv->vbt.child_dev);
1876 dev_priv->vbt.child_dev = NULL;
1877 dev_priv->vbt.child_dev_num = 0;
1882 /* Free error state after interrupts are fully disabled. */
1883 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1884 cancel_work_sync(&dev_priv->gpu_error.work);
1886 i915_destroy_error_state(dev);
1889 intel_opregion_fini(dev);
1891 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1892 /* Flush any outstanding unpin_work. */
1893 flush_workqueue(dev_priv->wq);
1895 mutex_lock(&dev->struct_mutex);
1896 i915_gem_cleanup_ringbuffer(dev);
1897 i915_gem_context_fini(dev);
1898 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1899 mutex_unlock(&dev->struct_mutex);
1901 i915_gem_cleanup_stolen(dev);
1904 if (!I915_NEED_GFX_HWS(dev))
1908 WARN_ON(!list_empty(&dev_priv->vm_list));
1910 drm_vblank_cleanup(dev);
1912 intel_teardown_gmbus(dev);
1913 intel_teardown_mchbar(dev);
1915 bus_generic_detach(dev->dev);
1916 drm_rmmap(dev, dev_priv->mmio_map);
1918 destroy_workqueue(dev_priv->wq);
1919 pm_qos_remove_request(&dev_priv->pm_qos);
1921 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1923 intel_uncore_fini(dev);
1925 if (dev_priv->regs != NULL)
1926 pci_iounmap(dev->pdev, dev_priv->regs);
1929 pci_dev_put(dev_priv->bridge_dev);
1935 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1939 ret = i915_gem_open(dev, file);
1947 * i915_driver_lastclose - clean up after all DRM clients have exited
1950 * Take care of cleaning up after all DRM clients have exited. In the
1951 * mode setting case, we want to restore the kernel's initial mode (just
1952 * in case the last client left us in a bad state).
1954 * Additionally, in the non-mode setting case, we'll tear down the GTT
1955 * and DMA structures, since the kernel won't be using them, and clea
1958 void i915_driver_lastclose(struct drm_device * dev)
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1962 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1963 * goes right around and calls lastclose. Check for this and don't clean
1968 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1970 intel_fbdev_restore_mode(dev);
1971 vga_switcheroo_process_delayed_switch();
1976 i915_gem_lastclose(dev);
1978 i915_dma_cleanup(dev);
1981 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1983 mutex_lock(&dev->struct_mutex);
1984 i915_gem_context_close(dev, file_priv);
1985 i915_gem_release(dev, file_priv);
1986 mutex_unlock(&dev->struct_mutex);
1989 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1991 struct drm_i915_file_private *file_priv = file->driver_priv;
1993 if (file_priv && file_priv->bsd_ring)
1994 file_priv->bsd_ring = NULL;
1998 const struct drm_ioctl_desc i915_ioctls[] = {
1999 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2000 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2001 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2002 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2003 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2004 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2005 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2006 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2007 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2008 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2009 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2010 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2011 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2012 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2013 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2014 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2015 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2016 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2017 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2018 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2019 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2020 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2021 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2022 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
2023 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
2024 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2025 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2026 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2027 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2028 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2029 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2030 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2031 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2032 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2033 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2034 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2035 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2036 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2037 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2038 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2039 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2040 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2041 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2042 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2043 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
2044 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
2045 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
2046 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
2047 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2049 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2053 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
2056 * This is really ugly: Because old userspace abused the linux agp interface to
2057 * manage the gtt, we need to claim that all intel devices are agp. For
2058 * otherwise the drm core refuses to initialize the agp support code.
2060 int i915_driver_device_is_agp(struct drm_device * dev)