2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_polling.h"
34 #include <sys/param.h>
36 #include <sys/endian.h>
37 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
43 #include <sys/serialize.h>
44 #include <sys/serialize2.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48 #include <sys/systm.h>
51 #include <net/ethernet.h>
53 #include <net/if_arp.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/ifq_var.h>
57 #include <net/toeplitz.h>
58 #include <net/toeplitz2.h>
59 #include <net/vlan/if_vlan_var.h>
60 #include <net/vlan/if_vlan_ether.h>
61 #include <net/if_poll.h>
63 #include <netinet/in_systm.h>
64 #include <netinet/in.h>
65 #include <netinet/ip.h>
66 #include <netinet/tcp.h>
67 #include <netinet/udp.h>
69 #include <bus/pci/pcivar.h>
70 #include <bus/pci/pcireg.h>
72 #include <dev/netif/ig_hal/e1000_api.h>
73 #include <dev/netif/ig_hal/e1000_82575.h>
74 #include <dev/netif/igb/if_igb.h>
76 #define IGB_NAME "Intel(R) PRO/1000 "
77 #define IGB_DEVICE(id) \
78 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
79 #define IGB_DEVICE_NULL { 0, 0, NULL }
81 static struct igb_device {
86 IGB_DEVICE(82575EB_COPPER),
87 IGB_DEVICE(82575EB_FIBER_SERDES),
88 IGB_DEVICE(82575GB_QUAD_COPPER),
91 IGB_DEVICE(82576_NS_SERDES),
92 IGB_DEVICE(82576_FIBER),
93 IGB_DEVICE(82576_SERDES),
94 IGB_DEVICE(82576_SERDES_QUAD),
95 IGB_DEVICE(82576_QUAD_COPPER),
96 IGB_DEVICE(82576_QUAD_COPPER_ET2),
98 IGB_DEVICE(82580_COPPER),
99 IGB_DEVICE(82580_FIBER),
100 IGB_DEVICE(82580_SERDES),
101 IGB_DEVICE(82580_SGMII),
102 IGB_DEVICE(82580_COPPER_DUAL),
103 IGB_DEVICE(82580_QUAD_FIBER),
104 IGB_DEVICE(DH89XXCC_SERDES),
105 IGB_DEVICE(DH89XXCC_SGMII),
106 IGB_DEVICE(DH89XXCC_SFP),
107 IGB_DEVICE(DH89XXCC_BACKPLANE),
108 IGB_DEVICE(I350_COPPER),
109 IGB_DEVICE(I350_FIBER),
110 IGB_DEVICE(I350_SERDES),
111 IGB_DEVICE(I350_SGMII),
114 /* required last entry */
118 static int igb_probe(device_t);
119 static int igb_attach(device_t);
120 static int igb_detach(device_t);
121 static int igb_shutdown(device_t);
122 static int igb_suspend(device_t);
123 static int igb_resume(device_t);
125 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
126 static void igb_setup_ifp(struct igb_softc *);
127 static int igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
128 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
129 static void igb_add_sysctl(struct igb_softc *);
130 static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
131 static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
133 static void igb_vf_init_stats(struct igb_softc *);
134 static void igb_reset(struct igb_softc *);
135 static void igb_update_stats_counters(struct igb_softc *);
136 static void igb_update_vf_stats_counters(struct igb_softc *);
137 static void igb_update_link_status(struct igb_softc *);
138 static void igb_init_tx_unit(struct igb_softc *);
139 static void igb_init_rx_unit(struct igb_softc *);
141 static void igb_set_vlan(struct igb_softc *);
142 static void igb_set_multi(struct igb_softc *);
143 static void igb_set_promisc(struct igb_softc *);
144 static void igb_disable_promisc(struct igb_softc *);
146 static int igb_dma_alloc(struct igb_softc *);
147 static void igb_dma_free(struct igb_softc *);
148 static int igb_create_tx_ring(struct igb_tx_ring *);
149 static int igb_create_rx_ring(struct igb_rx_ring *);
150 static void igb_free_tx_ring(struct igb_tx_ring *);
151 static void igb_free_rx_ring(struct igb_rx_ring *);
152 static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
153 static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
154 static void igb_init_tx_ring(struct igb_tx_ring *);
155 static int igb_init_rx_ring(struct igb_rx_ring *);
156 static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
157 static int igb_encap(struct igb_tx_ring *, struct mbuf **);
159 static void igb_stop(struct igb_softc *);
160 static void igb_init(void *);
161 static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
162 static void igb_media_status(struct ifnet *, struct ifmediareq *);
163 static int igb_media_change(struct ifnet *);
164 static void igb_timer(void *);
165 static void igb_watchdog(struct ifnet *);
166 static void igb_start(struct ifnet *);
167 #ifdef DEVICE_POLLING
168 static void igb_poll(struct ifnet *, enum poll_cmd, int);
171 static void igb_intr(void *);
172 static void igb_rxeof(struct igb_rx_ring *, int);
173 static void igb_txeof(struct igb_tx_ring *);
174 static void igb_set_itr(struct igb_softc *);
175 static void igb_enable_intr(struct igb_softc *);
176 static void igb_disable_intr(struct igb_softc *);
178 /* Management and WOL Support */
179 static void igb_get_mgmt(struct igb_softc *);
180 static void igb_rel_mgmt(struct igb_softc *);
181 static void igb_get_hw_control(struct igb_softc *);
182 static void igb_rel_hw_control(struct igb_softc *);
183 static void igb_enable_wol(device_t);
185 static device_method_t igb_methods[] = {
186 /* Device interface */
187 DEVMETHOD(device_probe, igb_probe),
188 DEVMETHOD(device_attach, igb_attach),
189 DEVMETHOD(device_detach, igb_detach),
190 DEVMETHOD(device_shutdown, igb_shutdown),
191 DEVMETHOD(device_suspend, igb_suspend),
192 DEVMETHOD(device_resume, igb_resume),
196 static driver_t igb_driver = {
199 sizeof(struct igb_softc),
202 static devclass_t igb_devclass;
204 DECLARE_DUMMY_MODULE(if_igb);
205 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
206 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
208 static int igb_rxd = IGB_DEFAULT_RXD;
209 static int igb_txd = IGB_DEFAULT_TXD;
210 static int igb_msi_enable = 1;
211 static int igb_msix_enable = 1;
212 static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
213 static int igb_fc_setting = e1000_fc_full;
216 * DMA Coalescing, only for i350 - default to off,
217 * this feature is for power savings
219 static int igb_dma_coalesce = 0;
221 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
222 TUNABLE_INT("hw.igb.txd", &igb_txd);
223 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
224 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
225 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
228 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
229 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
232 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
234 /* Ignore Checksum bit is set */
235 if (staterr & E1000_RXD_STAT_IXSM)
238 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
240 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
242 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
243 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
244 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
245 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
246 mp->m_pkthdr.csum_data = htons(0xffff);
252 igb_probe(device_t dev)
254 const struct igb_device *d;
257 vid = pci_get_vendor(dev);
258 did = pci_get_device(dev);
260 for (d = igb_devices; d->desc != NULL; ++d) {
261 if (vid == d->vid && did == d->did) {
262 device_set_desc(dev, d->desc);
270 igb_attach(device_t dev)
272 struct igb_softc *sc = device_get_softc(dev);
273 struct ifnet *ifp = &sc->arpcom.ac_if;
274 uint16_t eeprom_data;
280 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
281 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
282 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
283 igb_sysctl_nvm_info, "I", "NVM Information");
285 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
286 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
287 OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
288 &igb_enable_aim, 1, "Interrupt Moderation");
290 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
291 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
292 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
293 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
296 callout_init_mp(&sc->timer);
298 sc->dev = sc->osdep.dev = dev;
301 * Determine hardware and mac type
303 sc->hw.vendor_id = pci_get_vendor(dev);
304 sc->hw.device_id = pci_get_device(dev);
305 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
306 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
307 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
309 if (e1000_set_mac_type(&sc->hw))
312 /* Are we a VF device? */
313 if (sc->hw.mac.type == e1000_vfadapt ||
314 sc->hw.mac.type == e1000_vfadapt_i350)
319 /* Enable bus mastering */
320 pci_enable_busmaster(dev);
325 sc->mem_rid = PCIR_BAR(0);
326 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
328 if (sc->mem_res == NULL) {
329 device_printf(dev, "Unable to allocate bus resource: memory\n");
333 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
334 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
336 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
341 sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
342 &sc->intr_rid, &intr_flags);
344 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
346 if (sc->intr_res == NULL) {
347 device_printf(dev, "Unable to allocate bus resource: "
353 /* Save PCI command register for Shared Code */
354 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
355 sc->hw.back = &sc->osdep;
357 sc->num_queues = 1; /* Defaults for Legacy or MSI */
358 sc->intr_rate = IGB_INTR_RATE;
360 /* Do Shared Code initialization */
361 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
362 device_printf(dev, "Setup of Shared code failed\n");
367 e1000_get_bus_info(&sc->hw);
369 sc->hw.mac.autoneg = DO_AUTO_NEG;
370 sc->hw.phy.autoneg_wait_to_complete = FALSE;
371 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
374 if (sc->hw.phy.media_type == e1000_media_type_copper) {
375 sc->hw.phy.mdix = AUTO_ALL_MODES;
376 sc->hw.phy.disable_polarity_correction = FALSE;
377 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
380 /* Set the frame limits assuming standard ethernet sized frames. */
381 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
382 sc->min_frame_size = ETHER_MIN_LEN;
384 /* Allocate RX/TX rings' busdma(9) stuffs */
385 error = igb_dma_alloc(sc);
389 /* Allocate the appropriate stats memory */
391 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
393 igb_vf_init_stats(sc);
395 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
399 /* Allocate multicast array memory. */
400 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
403 /* Some adapter-specific advanced features */
404 if (sc->hw.mac.type >= e1000_i350) {
406 igb_set_sysctl_value(adapter, "dma_coalesce",
407 "configure dma coalesce",
408 &adapter->dma_coalesce, igb_dma_coalesce);
409 igb_set_sysctl_value(adapter, "eee_disabled",
410 "enable Energy Efficient Ethernet",
411 &adapter->hw.dev_spec._82575.eee_disable,
414 sc->dma_coalesce = igb_dma_coalesce;
415 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
417 e1000_set_eee_i350(&sc->hw);
421 * Start from a known state, this is important in reading the nvm and
424 e1000_reset_hw(&sc->hw);
426 /* Make sure we have a good EEPROM before we read from it */
427 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
429 * Some PCI-E parts fail the first check due to
430 * the link being in sleep state, call it again,
431 * if it fails a second time its a real issue.
433 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
435 "The EEPROM Checksum Is Not Valid\n");
441 /* Copy the permanent MAC address out of the EEPROM */
442 if (e1000_read_mac_addr(&sc->hw) < 0) {
443 device_printf(dev, "EEPROM read error while reading MAC"
448 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
449 device_printf(dev, "Invalid MAC address\n");
456 ** Configure Interrupts
458 if ((adapter->msix > 1) && (igb_enable_msix))
459 error = igb_allocate_msix(adapter);
460 else /* MSI or Legacy */
461 error = igb_allocate_legacy(adapter);
466 /* Setup OS specific network interface */
469 /* Add sysctl tree, must after igb_setup_ifp() */
472 /* Now get a good starting state */
475 /* Initialize statistics */
476 igb_update_stats_counters(sc);
478 sc->hw.mac.get_link_status = 1;
479 igb_update_link_status(sc);
481 /* Indicate SOL/IDER usage */
482 if (e1000_check_reset_block(&sc->hw)) {
484 "PHY reset is blocked due to SOL/IDER session.\n");
487 /* Determine if we have to control management hardware */
488 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
493 /* APME bit in EEPROM is mapped to WUC.APME */
494 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
496 sc->wol = E1000_WUFC_MAG;
497 /* XXX disable WOL */
501 /* Register for VLAN events */
502 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
503 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
504 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
505 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
509 igb_add_hw_stats(adapter);
512 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, igb_intr, sc,
513 &sc->intr_tag, ifp->if_serializer);
515 device_printf(dev, "Failed to register interrupt handler");
516 ether_ifdetach(&sc->arpcom.ac_if);
520 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
521 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
531 igb_detach(device_t dev)
533 struct igb_softc *sc = device_get_softc(dev);
535 if (device_is_attached(dev)) {
536 struct ifnet *ifp = &sc->arpcom.ac_if;
538 ifnet_serialize_all(ifp);
542 e1000_phy_hw_reset(&sc->hw);
544 /* Give control back to firmware */
546 igb_rel_hw_control(sc);
549 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
550 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
554 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
556 ifnet_deserialize_all(ifp);
559 } else if (sc->mem_res != NULL) {
560 igb_rel_hw_control(sc);
562 bus_generic_detach(dev);
564 if (sc->intr_res != NULL) {
565 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
568 if (sc->intr_type == PCI_INTR_TYPE_MSI)
569 pci_release_msi(dev);
571 if (sc->mem_res != NULL) {
572 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
579 kfree(sc->mta, M_DEVBUF);
580 if (sc->stats != NULL)
581 kfree(sc->stats, M_DEVBUF);
583 if (sc->sysctl_tree != NULL)
584 sysctl_ctx_free(&sc->sysctl_ctx);
590 igb_shutdown(device_t dev)
592 return igb_suspend(dev);
596 igb_suspend(device_t dev)
598 struct igb_softc *sc = device_get_softc(dev);
599 struct ifnet *ifp = &sc->arpcom.ac_if;
601 ifnet_serialize_all(ifp);
606 igb_rel_hw_control(sc);
609 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
610 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
614 ifnet_deserialize_all(ifp);
616 return bus_generic_suspend(dev);
620 igb_resume(device_t dev)
622 struct igb_softc *sc = device_get_softc(dev);
623 struct ifnet *ifp = &sc->arpcom.ac_if;
625 ifnet_serialize_all(ifp);
632 ifnet_deserialize_all(ifp);
634 return bus_generic_resume(dev);
638 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
640 struct igb_softc *sc = ifp->if_softc;
641 struct ifreq *ifr = (struct ifreq *)data;
642 int max_frame_size, mask, reinit;
645 ASSERT_IFNET_SERIALIZED_ALL(ifp);
649 max_frame_size = 9234;
650 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
656 ifp->if_mtu = ifr->ifr_mtu;
657 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
660 if (ifp->if_flags & IFF_RUNNING)
665 if (ifp->if_flags & IFF_UP) {
666 if (ifp->if_flags & IFF_RUNNING) {
667 if ((ifp->if_flags ^ sc->if_flags) &
668 (IFF_PROMISC | IFF_ALLMULTI)) {
669 igb_disable_promisc(sc);
675 } else if (ifp->if_flags & IFF_RUNNING) {
678 sc->if_flags = ifp->if_flags;
683 if (ifp->if_flags & IFF_RUNNING) {
684 igb_disable_intr(sc);
686 #ifdef DEVICE_POLLING
687 if (!(ifp->if_flags & IFF_POLLING))
695 * As the speed/duplex settings are being
696 * changed, we need toreset the PHY.
698 sc->hw.phy.reset_disable = FALSE;
700 /* Check SOL/IDER usage */
701 if (e1000_check_reset_block(&sc->hw)) {
702 if_printf(ifp, "Media change is "
703 "blocked due to SOL/IDER session.\n");
709 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
714 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
715 if (mask & IFCAP_HWCSUM) {
716 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
719 if (mask & IFCAP_VLAN_HWTAGGING) {
720 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
723 if (reinit && (ifp->if_flags & IFF_RUNNING))
728 error = ether_ioctl(ifp, command, data);
737 struct igb_softc *sc = xsc;
738 struct ifnet *ifp = &sc->arpcom.ac_if;
741 ASSERT_IFNET_SERIALIZED_ALL(ifp);
745 /* Get the latest mac address, User can use a LAA */
746 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
748 /* Put the address into the Receive Address Array */
749 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
752 igb_update_link_status(sc);
754 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
756 /* Set hardware offload abilities */
757 if (ifp->if_capenable & IFCAP_TXCSUM)
758 ifp->if_hwassist = IGB_CSUM_FEATURES;
760 ifp->if_hwassist = 0;
762 /* Configure for OS presence */
765 /* Prepare transmit descriptors and buffers */
766 for (i = 0; i < sc->num_queues; ++i)
767 igb_init_tx_ring(&sc->tx_rings[i]);
768 igb_init_tx_unit(sc);
770 /* Setup Multicast table */
775 * Figure out the desired mbuf pool
776 * for doing jumbo/packetsplit
778 if (adapter->max_frame_size <= 2048)
779 adapter->rx_mbuf_sz = MCLBYTES;
780 else if (adapter->max_frame_size <= 4096)
781 adapter->rx_mbuf_sz = MJUMPAGESIZE;
783 adapter->rx_mbuf_sz = MJUM9BYTES;
785 sc->rx_mbuf_sz = MCLBYTES;
788 /* Prepare receive descriptors and buffers */
789 for (i = 0; i < sc->num_queues; ++i) {
792 error = igb_init_rx_ring(&sc->rx_rings[i]);
794 if_printf(ifp, "Could not setup receive structures\n");
799 igb_init_rx_unit(sc);
801 /* Enable VLAN support */
802 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
805 /* Don't lose promiscuous settings */
808 /* Configure interrupt moderation */
811 ifp->if_flags |= IFF_RUNNING;
812 ifp->if_flags &= ~IFF_OACTIVE;
814 callout_reset(&sc->timer, hz, igb_timer, sc);
815 e1000_clear_hw_cntrs_base_generic(&sc->hw);
818 if (adapter->msix > 1) /* Set up queue routing */
819 igb_configure_queues(adapter);
822 /* this clears any pending interrupts */
823 E1000_READ_REG(&sc->hw, E1000_ICR);
824 #ifdef DEVICE_POLLING
826 * Only enable interrupts if we are not polling, make sure
827 * they are off otherwise.
829 if (ifp->if_flags & IFF_POLLING)
830 igb_disable_intr(sc);
832 #endif /* DEVICE_POLLING */
835 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
838 /* Set Energy Efficient Ethernet */
839 e1000_set_eee_i350(&sc->hw);
841 /* Don't reset the phy next time init gets called */
842 sc->hw.phy.reset_disable = TRUE;
846 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
848 struct igb_softc *sc = ifp->if_softc;
849 u_char fiber_type = IFM_1000_SX;
851 ASSERT_IFNET_SERIALIZED_ALL(ifp);
853 igb_update_link_status(sc);
855 ifmr->ifm_status = IFM_AVALID;
856 ifmr->ifm_active = IFM_ETHER;
858 if (!sc->link_active)
861 ifmr->ifm_status |= IFM_ACTIVE;
863 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
864 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
865 ifmr->ifm_active |= fiber_type | IFM_FDX;
867 switch (sc->link_speed) {
869 ifmr->ifm_active |= IFM_10_T;
873 ifmr->ifm_active |= IFM_100_TX;
877 ifmr->ifm_active |= IFM_1000_T;
880 if (sc->link_duplex == FULL_DUPLEX)
881 ifmr->ifm_active |= IFM_FDX;
883 ifmr->ifm_active |= IFM_HDX;
888 igb_media_change(struct ifnet *ifp)
890 struct igb_softc *sc = ifp->if_softc;
891 struct ifmedia *ifm = &sc->media;
893 ASSERT_IFNET_SERIALIZED_ALL(ifp);
895 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
898 switch (IFM_SUBTYPE(ifm->ifm_media)) {
900 sc->hw.mac.autoneg = DO_AUTO_NEG;
901 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
907 sc->hw.mac.autoneg = DO_AUTO_NEG;
908 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
912 sc->hw.mac.autoneg = FALSE;
913 sc->hw.phy.autoneg_advertised = 0;
914 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
915 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
917 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
921 sc->hw.mac.autoneg = FALSE;
922 sc->hw.phy.autoneg_advertised = 0;
923 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
924 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
926 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
930 if_printf(ifp, "Unsupported media type\n");
940 igb_set_promisc(struct igb_softc *sc)
942 struct ifnet *ifp = &sc->arpcom.ac_if;
943 struct e1000_hw *hw = &sc->hw;
947 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
951 reg = E1000_READ_REG(hw, E1000_RCTL);
952 if (ifp->if_flags & IFF_PROMISC) {
953 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
954 E1000_WRITE_REG(hw, E1000_RCTL, reg);
955 } else if (ifp->if_flags & IFF_ALLMULTI) {
956 reg |= E1000_RCTL_MPE;
957 reg &= ~E1000_RCTL_UPE;
958 E1000_WRITE_REG(hw, E1000_RCTL, reg);
963 igb_disable_promisc(struct igb_softc *sc)
965 struct e1000_hw *hw = &sc->hw;
969 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
972 reg = E1000_READ_REG(hw, E1000_RCTL);
973 reg &= ~E1000_RCTL_UPE;
974 reg &= ~E1000_RCTL_MPE;
975 E1000_WRITE_REG(hw, E1000_RCTL, reg);
979 igb_set_multi(struct igb_softc *sc)
981 struct ifnet *ifp = &sc->arpcom.ac_if;
982 struct ifmultiaddr *ifma;
983 uint32_t reg_rctl = 0;
988 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
990 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
991 if (ifma->ifma_addr->sa_family != AF_LINK)
994 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
997 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
998 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1002 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1003 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1004 reg_rctl |= E1000_RCTL_MPE;
1005 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1007 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1012 igb_timer(void *xsc)
1014 struct igb_softc *sc = xsc;
1015 struct ifnet *ifp = &sc->arpcom.ac_if;
1017 ifnet_serialize_all(ifp);
1019 igb_update_link_status(sc);
1020 igb_update_stats_counters(sc);
1022 callout_reset(&sc->timer, hz, igb_timer, sc);
1024 ifnet_deserialize_all(ifp);
1028 igb_update_link_status(struct igb_softc *sc)
1030 struct ifnet *ifp = &sc->arpcom.ac_if;
1031 struct e1000_hw *hw = &sc->hw;
1032 uint32_t link_check, thstat, ctrl;
1034 link_check = thstat = ctrl = 0;
1036 /* Get the cached link value or read for real */
1037 switch (hw->phy.media_type) {
1038 case e1000_media_type_copper:
1039 if (hw->mac.get_link_status) {
1040 /* Do the work to read phy */
1041 e1000_check_for_link(hw);
1042 link_check = !hw->mac.get_link_status;
1048 case e1000_media_type_fiber:
1049 e1000_check_for_link(hw);
1050 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1053 case e1000_media_type_internal_serdes:
1054 e1000_check_for_link(hw);
1055 link_check = hw->mac.serdes_has_link;
1058 /* VF device is type_unknown */
1059 case e1000_media_type_unknown:
1060 e1000_check_for_link(hw);
1061 link_check = !hw->mac.get_link_status;
1067 /* Check for thermal downshift or shutdown */
1068 if (hw->mac.type == e1000_i350) {
1069 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1070 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1073 /* Now we check if a transition has happened */
1074 if (link_check && sc->link_active == 0) {
1075 e1000_get_speed_and_duplex(hw,
1076 &sc->link_speed, &sc->link_duplex);
1078 if_printf(ifp, "Link is up %d Mbps %s\n",
1080 sc->link_duplex == FULL_DUPLEX ?
1081 "Full Duplex" : "Half Duplex");
1083 sc->link_active = 1;
1085 ifp->if_baudrate = sc->link_speed * 1000000;
1086 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1087 (thstat & E1000_THSTAT_LINK_THROTTLE))
1088 if_printf(ifp, "Link: thermal downshift\n");
1089 /* This can sleep */
1090 ifp->if_link_state = LINK_STATE_UP;
1091 if_link_state_change(ifp);
1092 } else if (!link_check && sc->link_active == 1) {
1093 ifp->if_baudrate = sc->link_speed = 0;
1094 sc->link_duplex = 0;
1096 if_printf(ifp, "Link is Down\n");
1097 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1098 (thstat & E1000_THSTAT_PWR_DOWN))
1099 if_printf(ifp, "Link: thermal shutdown\n");
1100 sc->link_active = 0;
1101 /* This can sleep */
1102 ifp->if_link_state = LINK_STATE_DOWN;
1103 if_link_state_change(ifp);
1108 igb_stop(struct igb_softc *sc)
1110 struct ifnet *ifp = &sc->arpcom.ac_if;
1113 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1115 igb_disable_intr(sc);
1117 callout_stop(&sc->timer);
1119 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1122 e1000_reset_hw(&sc->hw);
1123 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1125 e1000_led_off(&sc->hw);
1126 e1000_cleanup_led(&sc->hw);
1128 for (i = 0; i < sc->num_queues; ++i)
1129 igb_free_tx_ring(&sc->tx_rings[i]);
1130 for (i = 0; i < sc->num_queues; ++i)
1131 igb_free_rx_ring(&sc->rx_rings[i]);
1135 igb_reset(struct igb_softc *sc)
1137 struct ifnet *ifp = &sc->arpcom.ac_if;
1138 struct e1000_hw *hw = &sc->hw;
1139 struct e1000_fc_info *fc = &hw->fc;
1143 /* Let the firmware know the OS is in control */
1144 igb_get_hw_control(sc);
1147 * Packet Buffer Allocation (PBA)
1148 * Writing PBA sets the receive portion of the buffer
1149 * the remainder is used for the transmit buffer.
1151 switch (hw->mac.type) {
1153 pba = E1000_PBA_32K;
1158 pba = E1000_READ_REG(hw, E1000_RXPBS);
1159 pba &= E1000_RXPBS_SIZE_MASK_82576;
1164 case e1000_vfadapt_i350:
1165 pba = E1000_READ_REG(hw, E1000_RXPBS);
1166 pba = e1000_rxpbs_adjust_82580(pba);
1168 /* XXX pba = E1000_PBA_35K; */
1174 /* Special needs in case of Jumbo frames */
1175 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1176 uint32_t tx_space, min_tx, min_rx;
1178 pba = E1000_READ_REG(hw, E1000_PBA);
1179 tx_space = pba >> 16;
1182 min_tx = (sc->max_frame_size +
1183 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1184 min_tx = roundup2(min_tx, 1024);
1186 min_rx = sc->max_frame_size;
1187 min_rx = roundup2(min_rx, 1024);
1189 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1190 pba = pba - (min_tx - tx_space);
1192 * if short on rx space, rx wins
1193 * and must trump tx adjustment
1198 E1000_WRITE_REG(hw, E1000_PBA, pba);
1202 * These parameters control the automatic generation (Tx) and
1203 * response (Rx) to Ethernet PAUSE frames.
1204 * - High water mark should allow for at least two frames to be
1205 * received after sending an XOFF.
1206 * - Low water mark works best when it is very near the high water mark.
1207 * This allows the receiver to restart by sending XON when it has
1210 hwm = min(((pba << 10) * 9 / 10),
1211 ((pba << 10) - 2 * sc->max_frame_size));
1213 if (hw->mac.type < e1000_82576) {
1214 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1215 fc->low_water = fc->high_water - 8;
1217 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1218 fc->low_water = fc->high_water - 16;
1220 fc->pause_time = IGB_FC_PAUSE_TIME;
1221 fc->send_xon = TRUE;
1223 /* Issue a global reset */
1225 E1000_WRITE_REG(hw, E1000_WUC, 0);
1227 if (e1000_init_hw(hw) < 0)
1228 if_printf(ifp, "Hardware Initialization Failed\n");
1230 /* Setup DMA Coalescing */
1231 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1234 hwm = (pba - 4) << 10;
1235 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1236 & E1000_DMACR_DMACTHR_MASK;
1238 /* transition to L0x or L1 if available..*/
1239 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1241 /* timer = +-1000 usec in 32usec intervals */
1243 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1245 /* No lower threshold */
1246 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1248 /* set hwm to PBA - 2 * max frame size */
1249 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1251 /* Set the interval before transition */
1252 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1253 reg |= 0x800000FF; /* 255 usec */
1254 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1256 /* free space in tx packet buffer to wake from DMA coal */
1257 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1258 (20480 - (2 * sc->max_frame_size)) >> 6);
1260 /* make low power state decision controlled by DMA coal */
1261 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1262 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1263 reg | E1000_PCIEMISC_LX_DECISION);
1264 if_printf(ifp, "DMA Coalescing enabled\n");
1267 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1268 e1000_get_phy_info(hw);
1269 e1000_check_for_link(hw);
1273 igb_setup_ifp(struct igb_softc *sc)
1275 struct ifnet *ifp = &sc->arpcom.ac_if;
1277 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1280 ifp->if_init = igb_init;
1281 ifp->if_ioctl = igb_ioctl;
1282 ifp->if_start = igb_start;
1283 #ifdef DEVICE_POLLING
1284 ifp->if_poll = igb_poll;
1286 ifp->if_watchdog = igb_watchdog;
1288 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1289 ifq_set_ready(&ifp->if_snd);
1291 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1293 ifp->if_capabilities =
1294 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1295 ifp->if_capenable = ifp->if_capabilities;
1296 ifp->if_hwassist = IGB_CSUM_FEATURES;
1299 * Tell the upper layer(s) we support long frames
1301 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1304 * Specify the media types supported by this adapter and register
1305 * callbacks to update media and link information
1307 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1308 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1309 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1310 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1312 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1314 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1315 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1317 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1318 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1320 if (sc->hw.phy.type != e1000_phy_ife) {
1321 ifmedia_add(&sc->media,
1322 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1323 ifmedia_add(&sc->media,
1324 IFM_ETHER | IFM_1000_T, 0, NULL);
1327 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1328 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1332 igb_add_sysctl(struct igb_softc *sc)
1334 sysctl_ctx_init(&sc->sysctl_ctx);
1335 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1336 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1337 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1338 if (sc->sysctl_tree == NULL) {
1339 device_printf(sc->dev, "can't add sysctl node\n");
1343 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1344 OID_AUTO, "rxd", CTLFLAG_RD, &sc->num_rx_desc, 0, NULL);
1345 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1346 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
1348 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1349 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1350 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1352 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1353 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1354 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1355 "# segments per TX interrupt");
1359 igb_dma_alloc(struct igb_softc *sc)
1363 /* First allocate the top level queue structs */
1364 sc->queues = kmalloc(sizeof(struct igb_queue) * sc->num_queues,
1365 M_DEVBUF, M_WAITOK | M_ZERO);
1368 * Create top level busdma tag
1370 error = bus_dma_tag_create(NULL, 1, 0,
1371 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1372 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1375 device_printf(sc->dev, "could not create top level DMA tag\n");
1380 * Allocate TX descriptor rings and buffers
1382 sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->num_queues,
1383 M_DEVBUF, M_WAITOK | M_ZERO);
1384 for (i = 0; i < sc->num_queues; ++i) {
1385 struct igb_tx_ring *txr = &sc->tx_rings[i];
1387 /* Set up some basics */
1391 error = igb_create_tx_ring(txr);
1397 * Allocate RX descriptor rings and buffers
1399 sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->num_queues,
1400 M_DEVBUF, M_WAITOK | M_ZERO);
1401 for (i = 0; i < sc->num_queues; ++i) {
1402 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1404 /* Set up some basics */
1408 error = igb_create_rx_ring(rxr);
1414 * Finally set up the queue holding structs
1416 for (i = 0; i < sc->num_queues; i++) {
1417 struct igb_queue *que = &sc->queues[i];
1420 que->txr = &sc->tx_rings[i];
1421 que->rxr = &sc->rx_rings[i];
1427 igb_dma_free(struct igb_softc *sc)
1431 if (sc->queues != NULL)
1432 kfree(sc->queues, M_DEVBUF);
1434 if (sc->tx_rings != NULL) {
1435 for (i = 0; i < sc->num_queues; ++i)
1436 igb_destroy_tx_ring(&sc->tx_rings[i], sc->num_tx_desc);
1437 kfree(sc->tx_rings, M_DEVBUF);
1440 if (sc->rx_rings != NULL) {
1441 for (i = 0; i < sc->num_queues; ++i)
1442 igb_destroy_rx_ring(&sc->rx_rings[i], sc->num_rx_desc);
1443 kfree(sc->rx_rings, M_DEVBUF);
1448 igb_create_tx_ring(struct igb_tx_ring *txr)
1450 int tsize, error, i;
1453 * Validate number of transmit descriptors. It must not exceed
1454 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1456 if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1457 (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1458 device_printf(txr->sc->dev,
1459 "Using %d TX descriptors instead of %d!\n",
1460 IGB_DEFAULT_TXD, igb_txd);
1461 txr->sc->num_tx_desc = IGB_DEFAULT_TXD;
1463 txr->sc->num_tx_desc = igb_txd;
1467 * Allocate TX descriptor ring
1469 tsize = roundup2(txr->sc->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1471 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1472 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1473 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1474 if (txr->txdma.dma_vaddr == NULL) {
1475 device_printf(txr->sc->dev,
1476 "Unable to allocate TX Descriptor memory\n");
1479 txr->tx_base = txr->txdma.dma_vaddr;
1480 bzero(txr->tx_base, tsize);
1482 txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->sc->num_tx_desc,
1483 M_DEVBUF, M_WAITOK | M_ZERO);
1486 * Allocate TX head write-back buffer
1488 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1489 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1490 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1491 if (txr->tx_hdr == NULL) {
1492 device_printf(txr->sc->dev,
1493 "Unable to allocate TX head write-back buffer\n");
1498 * Create DMA tag for TX buffers
1500 error = bus_dma_tag_create(txr->sc->parent_tag,
1501 1, 0, /* alignment, bounds */
1502 BUS_SPACE_MAXADDR, /* lowaddr */
1503 BUS_SPACE_MAXADDR, /* highaddr */
1504 NULL, NULL, /* filter, filterarg */
1505 IGB_TSO_SIZE, /* maxsize */
1506 IGB_MAX_SCATTER, /* nsegments */
1507 PAGE_SIZE, /* maxsegsize */
1508 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1509 BUS_DMA_ONEBPAGE, /* flags */
1512 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1513 kfree(txr->tx_buf, M_DEVBUF);
1519 * Create DMA maps for TX buffers
1521 for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1522 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1524 error = bus_dmamap_create(txr->tx_tag,
1525 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1527 device_printf(txr->sc->dev,
1528 "Unable to create TX DMA map\n");
1529 igb_destroy_tx_ring(txr, i);
1535 * Initialize various watermark
1537 txr->spare_desc = IGB_TX_SPARE;
1538 txr->intr_nsegs = txr->sc->num_tx_desc / 16;
1539 txr->oact_hi_desc = txr->sc->num_tx_desc / 2;
1540 txr->oact_lo_desc = txr->sc->num_tx_desc / 8;
1541 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1542 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1543 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1544 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1550 igb_free_tx_ring(struct igb_tx_ring *txr)
1554 for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1555 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1557 if (txbuf->m_head != NULL) {
1558 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1559 m_freem(txbuf->m_head);
1560 txbuf->m_head = NULL;
1566 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1570 if (txr->txdma.dma_vaddr != NULL) {
1571 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1572 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1573 txr->txdma.dma_map);
1574 bus_dma_tag_destroy(txr->txdma.dma_tag);
1575 txr->txdma.dma_vaddr = NULL;
1578 if (txr->tx_hdr != NULL) {
1579 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1580 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1582 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1586 if (txr->tx_buf == NULL)
1589 for (i = 0; i < ndesc; ++i) {
1590 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1592 KKASSERT(txbuf->m_head == NULL);
1593 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1595 bus_dma_tag_destroy(txr->tx_tag);
1597 kfree(txr->tx_buf, M_DEVBUF);
1602 igb_init_tx_ring(struct igb_tx_ring *txr)
1604 /* Clear the old descriptor contents */
1606 sizeof(union e1000_adv_tx_desc) * txr->sc->num_tx_desc);
1608 /* Clear TX head write-back buffer */
1612 txr->next_avail_desc = 0;
1613 txr->next_to_clean = 0;
1616 /* Set number of descriptors available */
1617 txr->tx_avail = txr->sc->num_tx_desc;
1621 igb_init_tx_unit(struct igb_softc *sc)
1623 struct e1000_hw *hw = &sc->hw;
1627 /* Setup the Tx Descriptor Rings */
1628 for (i = 0; i < sc->num_queues; ++i) {
1629 struct igb_tx_ring *txr = &sc->tx_rings[i];
1630 uint64_t bus_addr = txr->txdma.dma_paddr;
1631 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1632 uint32_t txdctl = 0;
1633 uint32_t dca_txctrl;
1635 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1636 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1637 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1638 (uint32_t)(bus_addr >> 32));
1639 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1640 (uint32_t)bus_addr);
1642 /* Setup the HW Tx Head and Tail descriptor pointers */
1643 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1644 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1646 txdctl |= IGB_TX_PTHRESH;
1647 txdctl |= IGB_TX_HTHRESH << 8;
1648 txdctl |= IGB_TX_WTHRESH << 16;
1649 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1650 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1652 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1653 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1654 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1656 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1657 (uint32_t)(hdr_paddr >> 32));
1658 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1659 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1665 e1000_config_collision_dist(hw);
1667 /* Program the Transmit Control Register */
1668 tctl = E1000_READ_REG(hw, E1000_TCTL);
1669 tctl &= ~E1000_TCTL_CT;
1670 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1671 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1673 /* This write will effectively turn on the transmit unit. */
1674 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1678 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1680 struct e1000_adv_tx_context_desc *TXD;
1681 struct igb_tx_buf *txbuf;
1682 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1683 struct ether_vlan_header *eh;
1684 struct ip *ip = NULL;
1685 int ehdrlen, ctxd, ip_hlen = 0;
1686 uint16_t etype, vlantag = 0;
1687 boolean_t offload = TRUE;
1689 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1692 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1693 ctxd = txr->next_avail_desc;
1694 txbuf = &txr->tx_buf[ctxd];
1695 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1698 * In advanced descriptors the vlan tag must
1699 * be placed into the context descriptor, thus
1700 * we need to be here just for that setup.
1702 if (mp->m_flags & M_VLANTAG) {
1703 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1704 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1705 } else if (!offload) {
1710 * Determine where frame payload starts.
1711 * Jump over vlan headers if already present,
1712 * helpful for QinQ too.
1714 KASSERT(mp->m_len >= ETHER_HDR_LEN,
1715 ("igb_txctx_pullup is not called (eh)?\n"));
1716 eh = mtod(mp, struct ether_vlan_header *);
1717 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1718 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1719 ("igb_txctx_pullup is not called (evh)?\n"));
1720 etype = ntohs(eh->evl_proto);
1721 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1723 etype = ntohs(eh->evl_encap_proto);
1724 ehdrlen = ETHER_HDR_LEN;
1727 /* Set the ether header length */
1728 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1732 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1733 ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1735 /* NOTE: We could only safely access ip.ip_vhl part */
1736 ip = (struct ip *)(mp->m_data + ehdrlen);
1737 ip_hlen = ip->ip_hl << 2;
1739 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1740 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1744 case ETHERTYPE_IPV6:
1745 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1746 ip_hlen = sizeof(struct ip6_hdr);
1747 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1756 vlan_macip_lens |= ip_hlen;
1757 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1759 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1760 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1761 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1762 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1764 /* 82575 needs the queue index added */
1765 if (txr->sc->hw.mac.type == e1000_82575)
1766 mss_l4len_idx = txr->me << 4;
1768 /* Now copy bits into descriptor */
1769 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1770 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1771 TXD->seqnum_seed = htole32(0);
1772 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1774 txbuf->m_head = NULL;
1776 /* We've consumed the first desc, adjust counters */
1777 if (++ctxd == txr->sc->num_tx_desc)
1779 txr->next_avail_desc = ctxd;
1786 igb_txeof(struct igb_tx_ring *txr)
1788 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1789 int first, hdr, avail;
1791 if (txr->tx_avail == txr->sc->num_tx_desc)
1794 first = txr->next_to_clean;
1795 hdr = *(txr->tx_hdr);
1800 avail = txr->tx_avail;
1801 while (first != hdr) {
1802 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1805 if (txbuf->m_head) {
1806 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1807 m_freem(txbuf->m_head);
1808 txbuf->m_head = NULL;
1811 if (++first == txr->sc->num_tx_desc)
1814 txr->next_to_clean = first;
1815 txr->tx_avail = avail;
1818 * If we have a minimum free, clear IFF_OACTIVE
1819 * to tell the stack that it is OK to send packets.
1821 if (IGB_IS_NOT_OACTIVE(txr)) {
1822 ifp->if_flags &= ~IFF_OACTIVE;
1825 * We have enough TX descriptors, turn off
1826 * the watchdog. We allow small amount of
1827 * packets (roughly intr_nsegs) pending on
1828 * the transmit ring.
1835 igb_create_rx_ring(struct igb_rx_ring *rxr)
1837 int rsize, i, error;
1840 * Validate number of receive descriptors. It must not exceed
1841 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1843 if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1844 (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1845 device_printf(rxr->sc->dev,
1846 "Using %d RX descriptors instead of %d!\n",
1847 IGB_DEFAULT_RXD, igb_rxd);
1848 rxr->sc->num_rx_desc = IGB_DEFAULT_RXD;
1850 rxr->sc->num_rx_desc = igb_rxd;
1854 * Allocate RX descriptor ring
1856 rsize = roundup2(rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1858 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1859 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1860 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1861 &rxr->rxdma.dma_paddr);
1862 if (rxr->rxdma.dma_vaddr == NULL) {
1863 device_printf(rxr->sc->dev,
1864 "Unable to allocate RxDescriptor memory\n");
1867 rxr->rx_base = rxr->rxdma.dma_vaddr;
1868 bzero(rxr->rx_base, rsize);
1870 rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->sc->num_rx_desc,
1871 M_DEVBUF, M_WAITOK | M_ZERO);
1874 * Create DMA tag for RX buffers
1876 error = bus_dma_tag_create(rxr->sc->parent_tag,
1877 1, 0, /* alignment, bounds */
1878 BUS_SPACE_MAXADDR, /* lowaddr */
1879 BUS_SPACE_MAXADDR, /* highaddr */
1880 NULL, NULL, /* filter, filterarg */
1881 MCLBYTES, /* maxsize */
1883 MCLBYTES, /* maxsegsize */
1884 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1887 device_printf(rxr->sc->dev,
1888 "Unable to create RX payload DMA tag\n");
1889 kfree(rxr->rx_buf, M_DEVBUF);
1895 * Create spare DMA map for RX buffers
1897 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
1900 device_printf(rxr->sc->dev,
1901 "Unable to create spare RX DMA maps\n");
1902 bus_dma_tag_destroy(rxr->rx_tag);
1903 kfree(rxr->rx_buf, M_DEVBUF);
1909 * Create DMA maps for RX buffers
1911 for (i = 0; i < rxr->sc->num_rx_desc; i++) {
1912 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1914 error = bus_dmamap_create(rxr->rx_tag,
1915 BUS_DMA_WAITOK, &rxbuf->map);
1917 device_printf(rxr->sc->dev,
1918 "Unable to create RX DMA maps\n");
1919 igb_destroy_rx_ring(rxr, i);
1927 igb_free_rx_ring(struct igb_rx_ring *rxr)
1931 for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
1932 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1934 if (rxbuf->m_head != NULL) {
1935 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
1936 m_freem(rxbuf->m_head);
1937 rxbuf->m_head = NULL;
1941 if (rxr->fmp != NULL)
1948 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
1952 if (rxr->rxdma.dma_vaddr != NULL) {
1953 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
1954 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
1955 rxr->rxdma.dma_map);
1956 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
1957 rxr->rxdma.dma_vaddr = NULL;
1960 if (rxr->rx_buf == NULL)
1963 for (i = 0; i < ndesc; ++i) {
1964 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1966 KKASSERT(rxbuf->m_head == NULL);
1967 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
1969 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
1970 bus_dma_tag_destroy(rxr->rx_tag);
1972 kfree(rxr->rx_buf, M_DEVBUF);
1977 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
1979 rxd->read.pkt_addr = htole64(rxbuf->paddr);
1980 rxd->wb.upper.status_error = 0;
1984 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
1987 bus_dma_segment_t seg;
1989 struct igb_rx_buf *rxbuf;
1992 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1995 if_printf(&rxr->sc->arpcom.ac_if,
1996 "Unable to allocate RX mbuf\n");
2000 m->m_len = m->m_pkthdr.len = MCLBYTES;
2002 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2003 m_adj(m, ETHER_ALIGN);
2005 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2006 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2010 if_printf(&rxr->sc->arpcom.ac_if,
2011 "Unable to load RX mbuf\n");
2016 rxbuf = &rxr->rx_buf[i];
2017 if (rxbuf->m_head != NULL)
2018 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2021 rxbuf->map = rxr->rx_sparemap;
2022 rxr->rx_sparemap = map;
2025 rxbuf->paddr = seg.ds_addr;
2027 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2032 igb_init_rx_ring(struct igb_rx_ring *rxr)
2036 /* Clear the ring contents */
2038 rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2040 /* Now replenish the ring mbufs */
2041 for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
2044 error = igb_newbuf(rxr, i, TRUE);
2049 /* Setup our descriptor indices */
2050 rxr->next_to_check = 0;
2054 rxr->discard = FALSE;
2060 igb_init_rx_unit(struct igb_softc *sc)
2062 struct ifnet *ifp = &sc->arpcom.ac_if;
2063 struct e1000_hw *hw = &sc->hw;
2064 uint32_t rctl, rxcsum, srrctl = 0;
2068 * Make sure receives are disabled while setting
2069 * up the descriptor ring
2071 rctl = E1000_READ_REG(hw, E1000_RCTL);
2072 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2076 ** Set up for header split
2078 if (igb_header_split) {
2079 /* Use a standard mbuf for the header */
2080 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2081 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2084 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2087 ** Set up for jumbo frames
2089 if (ifp->if_mtu > ETHERMTU) {
2090 rctl |= E1000_RCTL_LPE;
2092 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2093 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2094 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2095 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2096 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2097 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2099 /* Set maximum packet len */
2100 psize = adapter->max_frame_size;
2101 /* are we on a vlan? */
2102 if (adapter->ifp->if_vlantrunk != NULL)
2103 psize += VLAN_TAG_SIZE;
2104 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2106 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2107 rctl |= E1000_RCTL_SZ_2048;
2110 rctl &= ~E1000_RCTL_LPE;
2111 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2112 rctl |= E1000_RCTL_SZ_2048;
2115 /* Setup the Base and Length of the Rx Descriptor Rings */
2116 for (i = 0; i < sc->num_queues; ++i) {
2117 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2118 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2121 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2122 sc->num_rx_desc * sizeof(struct e1000_rx_desc));
2123 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2124 (uint32_t)(bus_addr >> 32));
2125 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2126 (uint32_t)bus_addr);
2127 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2128 /* Enable this Queue */
2129 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2130 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2131 rxdctl &= 0xFFF00000;
2132 rxdctl |= IGB_RX_PTHRESH;
2133 rxdctl |= IGB_RX_HTHRESH << 8;
2134 rxdctl |= IGB_RX_WTHRESH << 16;
2135 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2139 * Setup for RX MultiQueue
2141 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2143 if (adapter->num_queues >1) {
2144 u32 random[10], mrqc, shift = 0;
2150 arc4rand(&random, sizeof(random), 0);
2151 if (adapter->hw.mac.type == e1000_82575)
2153 /* Warning FM follows */
2154 for (int i = 0; i < 128; i++) {
2156 (i % adapter->num_queues) << shift;
2159 E1000_RETA(i >> 2), reta.dword);
2161 /* Now fill in hash table */
2162 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2163 for (int i = 0; i < 10; i++)
2164 E1000_WRITE_REG_ARRAY(hw,
2165 E1000_RSSRK(0), i, random[i]);
2167 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2168 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2169 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2170 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2171 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2172 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2173 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2174 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2176 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2179 ** NOTE: Receive Full-Packet Checksum Offload
2180 ** is mutually exclusive with Multiqueue. However
2181 ** this is not the same as TCP/IP checksums which
2184 rxcsum |= E1000_RXCSUM_PCSD;
2189 if (ifp->if_capenable & IFCAP_RXCSUM)
2190 rxcsum |= E1000_RXCSUM_IPPCSE;
2192 rxcsum &= ~E1000_RXCSUM_TUOFL;
2194 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2196 /* Setup the Receive Control Register */
2197 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2198 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2199 E1000_RCTL_RDMTS_HALF |
2200 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2201 /* Strip CRC bytes. */
2202 rctl |= E1000_RCTL_SECRC;
2203 /* Make sure VLAN Filters are off */
2204 rctl &= ~E1000_RCTL_VFE;
2205 /* Don't store bad packets */
2206 rctl &= ~E1000_RCTL_SBP;
2208 /* Enable Receives */
2209 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2212 * Setup the HW Rx Head and Tail Descriptor Pointers
2213 * - needs to be after enable
2215 for (i = 0; i < sc->num_queues; ++i) {
2216 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2218 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2219 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->sc->num_rx_desc - 1);
2224 igb_rxeof(struct igb_rx_ring *rxr, int count)
2226 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2227 union e1000_adv_rx_desc *cur;
2231 i = rxr->next_to_check;
2232 cur = &rxr->rx_base[i];
2233 staterr = le32toh(cur->wb.upper.status_error);
2235 if ((staterr & E1000_RXD_STAT_DD) == 0)
2238 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2239 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2240 struct mbuf *m = NULL;
2243 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2247 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2249 struct mbuf *mp = rxbuf->m_head;
2253 len = le16toh(cur->wb.upper.length);
2254 if (rxr->sc->hw.mac.type == e1000_i350 &&
2255 (staterr & E1000_RXDEXT_STATERR_LB))
2256 vlan = be16toh(cur->wb.upper.vlan);
2258 vlan = le16toh(cur->wb.upper.vlan);
2260 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2261 BUS_DMASYNC_POSTREAD);
2263 if (igb_newbuf(rxr, i, FALSE) != 0) {
2269 if (rxr->fmp == NULL) {
2270 mp->m_pkthdr.len = len;
2274 rxr->lmp->m_next = mp;
2275 rxr->lmp = rxr->lmp->m_next;
2276 rxr->fmp->m_pkthdr.len += len;
2284 m->m_pkthdr.rcvif = ifp;
2287 if (ifp->if_capenable & IFCAP_RXCSUM)
2288 igb_rxcsum(staterr, m);
2290 if (staterr & E1000_RXD_STAT_VP) {
2291 m->m_pkthdr.ether_vlantag = vlan;
2292 m->m_flags |= M_VLANTAG;
2296 if (ifp->if_capenable & IFCAP_RSS) {
2297 pi = emx_rssinfo(m, &pi0, mrq,
2305 igb_setup_rxdesc(cur, rxbuf);
2307 rxr->discard = TRUE;
2309 rxr->discard = FALSE;
2310 if (rxr->fmp != NULL) {
2319 ether_input_pkt(ifp, m, NULL);
2321 /* Advance our pointers to the next descriptor. */
2322 if (++i == rxr->sc->num_rx_desc)
2325 cur = &rxr->rx_base[i];
2326 staterr = le32toh(cur->wb.upper.status_error);
2328 rxr->next_to_check = i;
2331 i = rxr->sc->num_rx_desc - 1;
2332 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2337 igb_set_vlan(struct igb_softc *sc)
2339 struct e1000_hw *hw = &sc->hw;
2342 struct ifnet *ifp = sc->arpcom.ac_if;
2346 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2350 reg = E1000_READ_REG(hw, E1000_CTRL);
2351 reg |= E1000_CTRL_VME;
2352 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2355 /* Enable the Filter Table */
2356 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2357 reg = E1000_READ_REG(hw, E1000_RCTL);
2358 reg &= ~E1000_RCTL_CFIEN;
2359 reg |= E1000_RCTL_VFE;
2360 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2364 /* Update the frame size */
2365 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2366 sc->max_frame_size + VLAN_TAG_SIZE);
2369 /* Don't bother with table if no vlans */
2370 if ((adapter->num_vlans == 0) ||
2371 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2374 ** A soft reset zero's out the VFTA, so
2375 ** we need to repopulate it now.
2377 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2378 if (adapter->shadow_vfta[i] != 0) {
2379 if (adapter->vf_ifp)
2380 e1000_vfta_set_vf(hw,
2381 adapter->shadow_vfta[i], TRUE);
2383 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2384 i, adapter->shadow_vfta[i]);
2390 igb_enable_intr(struct igb_softc *sc)
2392 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
2394 /* With RSS set up what to auto clear */
2396 uint32_t mask = (sc->que_mask | sc->link_mask);
2398 E1000_WRITE_REG(&sc->hw, E1000_EIAC, mask);
2399 E1000_WRITE_REG(&sc->hw, E1000_EIAM, mask);
2400 E1000_WRITE_REG(&sc->hw, E1000_EIMS, mask);
2401 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2403 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2405 E1000_WRITE_FLUSH(&sc->hw);
2409 igb_disable_intr(struct igb_softc *sc)
2411 if (sc->msix_mem != NULL) {
2412 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2413 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2415 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2416 E1000_WRITE_FLUSH(&sc->hw);
2418 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
2422 * Bit of a misnomer, what this really means is
2423 * to enable OS management of the system... aka
2424 * to disable special hardware management features
2427 igb_get_mgmt(struct igb_softc *sc)
2429 if (sc->has_manage) {
2430 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2431 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2433 /* disable hardware interception of ARP */
2434 manc &= ~E1000_MANC_ARP_EN;
2436 /* enable receiving management packets to the host */
2437 manc |= E1000_MANC_EN_MNG2HOST;
2438 manc2h |= 1 << 5; /* Mng Port 623 */
2439 manc2h |= 1 << 6; /* Mng Port 664 */
2440 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2441 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2446 * Give control back to hardware management controller
2450 igb_rel_mgmt(struct igb_softc *sc)
2452 if (sc->has_manage) {
2453 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2455 /* Re-enable hardware interception of ARP */
2456 manc |= E1000_MANC_ARP_EN;
2457 manc &= ~E1000_MANC_EN_MNG2HOST;
2459 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2464 * Sets CTRL_EXT:DRV_LOAD bit.
2466 * For ASF and Pass Through versions of f/w this means that
2467 * the driver is loaded.
2470 igb_get_hw_control(struct igb_softc *sc)
2477 /* Let firmware know the driver has taken over */
2478 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2479 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2480 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2484 * Resets CTRL_EXT:DRV_LOAD bit.
2486 * For ASF and Pass Through versions of f/w this means that the
2487 * driver is no longer loaded.
2490 igb_rel_hw_control(struct igb_softc *sc)
2497 /* Let firmware taken over control of h/w */
2498 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2499 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2500 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2504 igb_is_valid_ether_addr(const uint8_t *addr)
2506 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2508 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2514 * Enable PCI Wake On Lan capability
2517 igb_enable_wol(device_t dev)
2519 uint16_t cap, status;
2522 /* First find the capabilities pointer*/
2523 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2525 /* Read the PM Capabilities */
2526 id = pci_read_config(dev, cap, 1);
2527 if (id != PCIY_PMG) /* Something wrong */
2531 * OK, we have the power capabilities,
2532 * so now get the status register
2534 cap += PCIR_POWER_STATUS;
2535 status = pci_read_config(dev, cap, 2);
2536 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2537 pci_write_config(dev, cap, status, 2);
2541 igb_update_stats_counters(struct igb_softc *sc)
2543 struct e1000_hw *hw = &sc->hw;
2544 struct e1000_hw_stats *stats;
2545 struct ifnet *ifp = &sc->arpcom.ac_if;
2548 * The virtual function adapter has only a
2549 * small controlled set of stats, do only
2553 igb_update_vf_stats_counters(sc);
2558 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2559 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2561 E1000_READ_REG(hw,E1000_SYMERRS);
2562 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2565 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2566 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2567 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2568 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2570 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2571 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2572 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2573 stats->dc += E1000_READ_REG(hw, E1000_DC);
2574 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2575 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2576 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2579 * For watchdog management we need to know if we have been
2580 * paused during the last interval, so capture that here.
2582 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2583 stats->xoffrxc += sc->pause_frames;
2584 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2585 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2586 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2587 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2588 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2589 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2590 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2591 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2592 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2593 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2594 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2595 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2597 /* For the 64-bit byte counters the low dword must be read first. */
2598 /* Both registers clear on the read of the high dword */
2600 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2601 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2602 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2603 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2605 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2606 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2607 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2608 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2609 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2611 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2612 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2614 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2615 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2616 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2617 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2618 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2619 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2620 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2621 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2622 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2623 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2625 /* Interrupt Counts */
2627 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2628 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2629 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2630 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2631 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2632 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2633 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2634 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2635 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2637 /* Host to Card Statistics */
2639 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2640 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2641 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2642 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2643 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2644 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2645 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2646 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2647 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2648 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2649 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2650 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2651 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2652 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2654 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2655 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2656 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2657 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2658 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2659 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2661 ifp->if_collisions = stats->colc;
2664 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2665 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2668 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2670 /* Driver specific counters */
2671 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2672 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2673 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2674 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2675 sc->packet_buf_alloc_tx =
2676 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2677 sc->packet_buf_alloc_rx =
2678 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2682 igb_vf_init_stats(struct igb_softc *sc)
2684 struct e1000_hw *hw = &sc->hw;
2685 struct e1000_vf_stats *stats;
2688 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2689 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2690 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2691 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2692 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2696 igb_update_vf_stats_counters(struct igb_softc *sc)
2698 struct e1000_hw *hw = &sc->hw;
2699 struct e1000_vf_stats *stats;
2701 if (sc->link_speed == 0)
2705 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2706 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2707 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2708 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2709 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2712 #ifdef DEVICE_POLLING
2715 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2717 struct igb_softc *sc = ifp->if_softc;
2720 ASSERT_SERIALIZED(ifp->if_serializer);
2724 igb_disable_intr(sc);
2727 case POLL_DEREGISTER:
2728 igb_enable_intr(sc);
2731 case POLL_AND_CHECK_STATUS:
2732 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2733 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2734 sc->hw.mac.get_link_status = 1;
2735 igb_update_link_status(sc);
2739 if (ifp->if_flags & IFF_RUNNING) {
2740 igb_rxeof(sc->queues[0].rxr, count);
2742 igb_txeof(sc->queues[0].txr);
2743 if (!ifq_is_empty(&ifp->if_snd))
2750 #endif /* DEVICE_POLLING */
2755 struct igb_softc *sc = xsc;
2756 struct ifnet *ifp = &sc->arpcom.ac_if;
2759 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2761 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2764 if (reg_icr == 0xffffffff)
2767 /* Definitely not our interrupt. */
2771 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
2774 if (ifp->if_flags & IFF_RUNNING) {
2775 igb_rxeof(sc->queues[0].rxr, -1);
2777 igb_txeof(sc->queues[0].txr);
2778 if (!ifq_is_empty(&ifp->if_snd))
2782 /* Link status change */
2783 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2784 sc->hw.mac.get_link_status = 1;
2785 igb_update_link_status(sc);
2788 if (reg_icr & E1000_ICR_RXO)
2793 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
2795 struct mbuf *m = *m0;
2796 struct ether_header *eh;
2799 txr->ctx_try_pullup++;
2801 len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
2803 if (__predict_false(!M_WRITABLE(m))) {
2804 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2810 eh = mtod(m, struct ether_header *);
2812 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2813 len += EVL_ENCAPLEN;
2815 if (m->m_len < len) {
2824 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2826 m = m_pullup(m, ETHER_HDR_LEN);
2828 txr->ctx_pullup1_failed++;
2834 eh = mtod(m, struct ether_header *);
2836 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2837 len += EVL_ENCAPLEN;
2839 if (m->m_len < len) {
2841 m = m_pullup(m, len);
2843 txr->ctx_pullup2_failed++;
2853 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
2855 bus_dma_segment_t segs[IGB_MAX_SCATTER];
2857 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
2858 union e1000_adv_tx_desc *txd = NULL;
2859 struct mbuf *m_head = *m_headp;
2860 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
2861 int maxsegs, nsegs, i, j, error, last = 0;
2862 uint32_t hdrlen = 0;
2864 if (m_head->m_len < IGB_TXCSUM_MINHL &&
2865 ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
2866 (m_head->m_flags & M_VLANTAG))) {
2868 * Make sure that ethernet header and ip.ip_hl are in
2869 * contiguous memory, since if TXCSUM or VLANTAG is
2870 * enabled, later TX context descriptor's setup need
2871 * to access ip.ip_hl.
2873 error = igb_txctx_pullup(txr, m_headp);
2875 KKASSERT(*m_headp == NULL);
2881 /* Set basic descriptor constants */
2882 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
2883 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
2884 if (m_head->m_flags & M_VLANTAG)
2885 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2888 * Map the packet for DMA.
2890 tx_buf = &txr->tx_buf[txr->next_avail_desc];
2891 tx_buf_mapped = tx_buf;
2894 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
2895 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
2896 if (maxsegs > IGB_MAX_SCATTER)
2897 maxsegs = IGB_MAX_SCATTER;
2899 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
2900 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2902 if (error == ENOBUFS)
2903 txr->sc->mbuf_defrag_failed++;
2905 txr->sc->no_tx_dma_setup++;
2911 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
2917 * Set up the context descriptor:
2918 * used when any hardware offload is done.
2919 * This includes CSUM, VLAN, and TSO. It
2920 * will use the first descriptor.
2922 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2923 if (igb_tso_setup(txr, m_head, &hdrlen)) {
2924 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2925 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2926 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2929 } else if (igb_tx_ctx_setup(txr, m_head))
2930 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2932 if (igb_txctx(txr, m_head)) {
2933 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
2934 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
2935 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
2940 txr->tx_nsegs += nsegs;
2941 if (txr->tx_nsegs >= txr->intr_nsegs) {
2943 * Report Status (RS) is turned on every intr_nsegs
2944 * descriptors (roughly).
2947 cmd_rs = E1000_ADVTXD_DCMD_RS;
2950 /* Calculate payload length */
2951 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
2952 << E1000_ADVTXD_PAYLEN_SHIFT);
2954 /* 82575 needs the queue index added */
2955 if (txr->sc->hw.mac.type == e1000_82575)
2956 olinfo_status |= txr->me << 4;
2958 /* Set up our transmit descriptors */
2959 i = txr->next_avail_desc;
2960 for (j = 0; j < nsegs; j++) {
2962 bus_addr_t seg_addr;
2964 tx_buf = &txr->tx_buf[i];
2965 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
2966 seg_addr = segs[j].ds_addr;
2967 seg_len = segs[j].ds_len;
2969 txd->read.buffer_addr = htole64(seg_addr);
2970 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
2971 txd->read.olinfo_status = htole32(olinfo_status);
2973 if (++i == txr->sc->num_tx_desc)
2975 tx_buf->m_head = NULL;
2978 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
2979 txr->next_avail_desc = i;
2980 txr->tx_avail -= nsegs;
2982 tx_buf->m_head = m_head;
2983 tx_buf_mapped->map = tx_buf->map;
2987 * Last Descriptor of Packet needs End Of Packet (EOP)
2989 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
2992 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
2993 * that this frame is available to transmit.
2995 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3002 igb_start(struct ifnet *ifp)
3004 struct igb_softc *sc = ifp->if_softc;
3005 struct igb_tx_ring *txr = sc->queues[0].txr;
3006 struct mbuf *m_head;
3008 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3010 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3013 if (!sc->link_active) {
3014 ifq_purge(&ifp->if_snd);
3018 if (!IGB_IS_NOT_OACTIVE(txr))
3021 while (!ifq_is_empty(&ifp->if_snd)) {
3022 if (IGB_IS_OACTIVE(txr)) {
3023 ifp->if_flags |= IFF_OACTIVE;
3024 /* Set watchdog on */
3029 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3033 if (igb_encap(txr, &m_head)) {
3038 /* Send a copy of the frame to the BPF listener */
3039 ETHER_BPF_MTAP(ifp, m_head);
3044 igb_watchdog(struct ifnet *ifp)
3046 struct igb_softc *sc = ifp->if_softc;
3047 struct igb_tx_ring *txr = sc->queues[0].txr;
3049 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3052 * If flow control has paused us since last checking
3053 * it invalidates the watchdog timing, so dont run it.
3055 if (sc->pause_frames) {
3056 sc->pause_frames = 0;
3061 if_printf(ifp, "Watchdog timeout -- resetting\n");
3062 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3063 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3064 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3065 if_printf(ifp, "TX(%d) desc avail = %d, "
3066 "Next TX to Clean = %d\n",
3067 txr->me, txr->tx_avail, txr->next_to_clean);
3070 sc->watchdog_events++;
3073 if (!ifq_is_empty(&ifp->if_snd))
3078 igb_set_itr(struct igb_softc *sc)
3082 if (sc->intr_rate > 0) {
3083 if (sc->hw.mac.type == e1000_82575) {
3084 itr = 1000000000 / 256 / sc->intr_rate;
3087 * Document is wrong on the 2 bits left shift
3090 itr = 1000000 / sc->intr_rate;
3095 if (sc->hw.mac.type == e1000_82575)
3098 itr |= E1000_EITR_CNT_IGNR;
3099 E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3103 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3105 struct igb_softc *sc = (void *)arg1;
3106 struct ifnet *ifp = &sc->arpcom.ac_if;
3107 int error, intr_rate;
3109 intr_rate = sc->intr_rate;
3110 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3111 if (error || req->newptr == NULL)
3116 ifnet_serialize_all(ifp);
3118 sc->intr_rate = intr_rate;
3119 if (ifp->if_flags & IFF_RUNNING)
3122 ifnet_deserialize_all(ifp);
3125 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3130 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3132 struct igb_softc *sc = (void *)arg1;
3133 struct ifnet *ifp = &sc->arpcom.ac_if;
3134 struct igb_tx_ring *txr = sc->queues[0].txr;
3137 nsegs = txr->intr_nsegs;
3138 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3139 if (error || req->newptr == NULL)
3144 ifnet_serialize_all(ifp);
3146 if (nsegs >= sc->num_tx_desc - txr->oact_lo_desc ||
3147 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3151 txr->intr_nsegs = nsegs;
3154 ifnet_deserialize_all(ifp);