1 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
35 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.30 2005/05/26 22:49:17 joerg Exp $
39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
41 * Permission to use, copy, modify, and distribute this software for any
42 * purpose with or without fee is hereby granted, provided that the above
43 * copyright notice and this permission notice appear in all copies.
45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
55 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
56 * the SK-984x series adapters, both single port and dual port.
58 * The XaQti XMAC II datasheet,
59 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
60 * The SysKonnect GEnesis manual, http://www.syskonnect.com
62 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
63 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
64 * convenience to others until Vitesse corrects this problem:
66 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
68 * Written by Bill Paul <wpaul@ee.columbia.edu>
69 * Department of Electrical Engineering
70 * Columbia University, New York City
74 * The SysKonnect gigabit ethernet adapters consist of two main
75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
77 * components and a PHY while the GEnesis controller provides a PCI
78 * interface with DMA support. Each card may have between 512K and
79 * 2MB of SRAM on board depending on the configuration.
81 * The SysKonnect GEnesis controller can have either one or two XMAC
82 * chips connected to it, allowing single or dual port NIC configurations.
83 * SysKonnect has the distinction of being the only vendor on the market
84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
86 * XMAC registers. This driver takes advantage of these features to allow
87 * both XMACs to operate as independent interfaces.
90 #include <sys/param.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/socket.h>
97 #include <sys/queue.h>
100 #include <net/ifq_var.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
108 #include <vm/vm.h> /* for vtophys */
109 #include <vm/pmap.h> /* for vtophys */
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 #include <dev/netif/mii_layer/mii.h>
116 #include <dev/netif/mii_layer/miivar.h>
117 #include <dev/netif/mii_layer/brgphyreg.h>
119 #include <bus/pci/pcireg.h>
120 #include <bus/pci/pcivar.h>
123 #define SK_USEIOSPACE
126 #include "if_skreg.h"
127 #include "xmaciireg.h"
128 #include "yukonreg.h"
130 /* "controller miibus0" required. See GENERIC if you get errors here. */
131 #include "miibus_if.h"
133 static struct sk_type sk_devs[] = {
134 { VENDORID_SK, DEVICEID_SK_V1,
135 "SysKonnect Gigabit Ethernet (V1.0)" },
136 { VENDORID_SK, DEVICEID_SK_V2,
137 "SysKonnect Gigabit Ethernet (V2.0)" },
138 { VENDORID_MARVELL, DEVICEID_SK_V2,
139 "Marvell Gigabit Ethernet" },
140 { VENDORID_3COM, DEVICEID_3COM_3C940,
141 "3Com 3C940 Gigabit Ethernet" },
142 { VENDORID_LINKSYS, DEVICEID_LINKSYS_EG1032,
143 "Linksys EG1032 Gigabit Ethernet" },
144 { VENDORID_DLINK, DEVICEID_DLINK_DGE530T,
145 "D-Link DGE-530T Gigabit Ethernet" },
149 static int skc_probe(device_t);
150 static int skc_attach(device_t);
151 static int skc_detach(device_t);
152 static void skc_shutdown(device_t);
153 static int sk_probe(device_t);
154 static int sk_attach(device_t);
155 static int sk_detach(device_t);
156 static void sk_tick(void *);
157 static void sk_intr(void *);
158 static void sk_intr_bcom(struct sk_if_softc *);
159 static void sk_intr_xmac(struct sk_if_softc *);
160 static void sk_intr_yukon(struct sk_if_softc *);
161 static void sk_rxeof(struct sk_if_softc *);
162 static void sk_txeof(struct sk_if_softc *);
163 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *);
164 static void sk_start(struct ifnet *);
165 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
166 static void sk_init(void *);
167 static void sk_init_xmac(struct sk_if_softc *);
168 static void sk_init_yukon(struct sk_if_softc *);
169 static void sk_stop(struct sk_if_softc *);
170 static void sk_watchdog(struct ifnet *);
171 static int sk_ifmedia_upd(struct ifnet *);
172 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
173 static void sk_reset(struct sk_softc *);
174 static int sk_newbuf(struct sk_if_softc *, struct sk_chain *,
176 static int sk_alloc_jumbo_mem(struct sk_if_softc *);
177 static void *sk_jalloc(struct sk_if_softc *);
178 static void sk_jfree(caddr_t, u_int);
179 static void sk_jref(caddr_t, u_int);
180 static int sk_init_rx_ring(struct sk_if_softc *);
181 static void sk_init_tx_ring(struct sk_if_softc *);
182 static uint32_t sk_win_read_4(struct sk_softc *, int);
183 static uint16_t sk_win_read_2(struct sk_softc *, int);
184 static uint8_t sk_win_read_1(struct sk_softc *, int);
185 static void sk_win_write_4(struct sk_softc *, int, uint32_t);
186 static void sk_win_write_2(struct sk_softc *, int, uint32_t);
187 static void sk_win_write_1(struct sk_softc *, int, uint32_t);
188 static uint8_t sk_vpd_readbyte(struct sk_softc *, int);
189 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int);
190 static void sk_vpd_read(struct sk_softc *);
192 static int sk_miibus_readreg(device_t, int, int);
193 static int sk_miibus_writereg(device_t, int, int, int);
194 static void sk_miibus_statchg(device_t);
196 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
197 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
198 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
200 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
201 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
202 static void sk_marv_miibus_statchg(struct sk_if_softc *);
204 static uint32_t xmac_calchash(caddr_t);
205 static uint32_t gmac_calchash(caddr_t);
206 static void sk_setfilt(struct sk_if_softc *, caddr_t, int);
207 static void sk_setmulti(struct sk_if_softc *);
208 static void sk_setpromisc(struct sk_if_softc *);
211 #define SK_RES SYS_RES_IOPORT
212 #define SK_RID SK_PCI_LOIO
214 #define SK_RES SYS_RES_MEMORY
215 #define SK_RID SK_PCI_LOMEM
219 * Note that we have newbus methods for both the GEnesis controller
220 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
221 * the miibus code is a child of the XMACs. We need to do it this way
222 * so that the miibus drivers can access the PHY registers on the
223 * right PHY. It's not quite what I had in mind, but it's the only
224 * design that achieves the desired effect.
226 static device_method_t skc_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, skc_probe),
229 DEVMETHOD(device_attach, skc_attach),
230 DEVMETHOD(device_detach, skc_detach),
231 DEVMETHOD(device_shutdown, skc_shutdown),
234 DEVMETHOD(bus_print_child, bus_generic_print_child),
235 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
240 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
241 static devclass_t skc_devclass;
243 static device_method_t sk_methods[] = {
244 /* Device interface */
245 DEVMETHOD(device_probe, sk_probe),
246 DEVMETHOD(device_attach, sk_attach),
247 DEVMETHOD(device_detach, sk_detach),
248 DEVMETHOD(device_shutdown, bus_generic_shutdown),
251 DEVMETHOD(bus_print_child, bus_generic_print_child),
252 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
255 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
256 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
257 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
262 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
263 static devclass_t sk_devclass;
265 DECLARE_DUMMY_MODULE(if_sk);
266 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
267 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
268 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
270 #define SK_SETBIT(sc, reg, x) \
271 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
273 #define SK_CLRBIT(sc, reg, x) \
274 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
276 #define SK_WIN_SETBIT_4(sc, reg, x) \
277 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
279 #define SK_WIN_CLRBIT_4(sc, reg, x) \
280 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
282 #define SK_WIN_SETBIT_2(sc, reg, x) \
283 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
285 #define SK_WIN_CLRBIT_2(sc, reg, x) \
286 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
289 sk_win_read_4(struct sk_softc *sc, int reg)
292 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
293 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
295 return(CSR_READ_4(sc, reg));
300 sk_win_read_2(struct sk_softc *sc, int reg)
303 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
304 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
306 return(CSR_READ_2(sc, reg));
311 sk_win_read_1(struct sk_softc *sc, int reg)
314 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
315 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
317 return(CSR_READ_1(sc, reg));
322 sk_win_write_4(struct sk_softc *sc, int reg, uint32_t val)
325 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
326 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
328 CSR_WRITE_4(sc, reg, val);
333 sk_win_write_2(struct sk_softc *sc, int reg, uint32_t val)
336 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
337 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
339 CSR_WRITE_2(sc, reg, val);
344 sk_win_write_1(struct sk_softc *sc, int reg, uint32_t val)
347 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
348 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
350 CSR_WRITE_1(sc, reg, val);
355 * The VPD EEPROM contains Vital Product Data, as suggested in
356 * the PCI 2.1 specification. The VPD data is separared into areas
357 * denoted by resource IDs. The SysKonnect VPD contains an ID string
358 * resource (the name of the adapter), a read-only area resource
359 * containing various key/data fields and a read/write area which
360 * can be used to store asset management information or log messages.
361 * We read the ID string and read-only into buffers attached to
362 * the controller softc structure for later use. At the moment,
363 * we only use the ID string during sk_attach().
366 sk_vpd_readbyte(struct sk_softc *sc, int addr)
370 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
371 for (i = 0; i < SK_TIMEOUT; i++) {
373 if (sk_win_read_2(sc,
374 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
381 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
385 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr)
390 ptr = (uint8_t *)res;
391 for (i = 0; i < sizeof(struct vpd_res); i++)
392 ptr[i] = sk_vpd_readbyte(sc, i + addr);
396 sk_vpd_read(struct sk_softc *sc)
401 if (sc->sk_vpd_prodname != NULL)
402 free(sc->sk_vpd_prodname, M_DEVBUF);
403 if (sc->sk_vpd_readonly != NULL)
404 free(sc->sk_vpd_readonly, M_DEVBUF);
405 sc->sk_vpd_prodname = NULL;
406 sc->sk_vpd_readonly = NULL;
408 sk_vpd_read_res(sc, &res, pos);
410 if (res.vr_id != VPD_RES_ID) {
411 printf("skc%d: bad VPD resource id: expected %x got %x\n",
412 sc->sk_unit, VPD_RES_ID, res.vr_id);
417 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
418 for (i = 0; i < res.vr_len; i++)
419 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
420 sc->sk_vpd_prodname[i] = '\0';
423 sk_vpd_read_res(sc, &res, pos);
425 if (res.vr_id != VPD_RES_READ) {
426 printf("skc%d: bad VPD resource id: expected %x got %x\n",
427 sc->sk_unit, VPD_RES_READ, res.vr_id);
432 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
433 for (i = 0; i < res.vr_len + 1; i++)
434 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
438 sk_miibus_readreg(device_t dev, int phy, int reg)
440 struct sk_if_softc *sc_if = device_get_softc(dev);
442 switch(sc_if->sk_softc->sk_type) {
444 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
446 return(sk_marv_miibus_readreg(sc_if, phy, reg));
453 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
455 struct sk_if_softc *sc_if = device_get_softc(dev);
457 switch(sc_if->sk_softc->sk_type) {
459 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
461 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
468 sk_miibus_statchg(device_t dev)
470 struct sk_if_softc *sc_if = device_get_softc(dev);
472 switch(sc_if->sk_softc->sk_type) {
474 sk_xmac_miibus_statchg(sc_if);
477 sk_marv_miibus_statchg(sc_if);
483 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
487 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
490 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
491 SK_XM_READ_2(sc_if, XM_PHY_DATA);
492 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
493 for (i = 0; i < SK_TIMEOUT; i++) {
495 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
496 XM_MMUCMD_PHYDATARDY)
500 if (i == SK_TIMEOUT) {
501 printf("sk%d: phy failed to come ready\n",
507 return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
511 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
515 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
516 for (i = 0; i < SK_TIMEOUT; i++) {
517 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
521 if (i == SK_TIMEOUT) {
522 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
526 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
527 for (i = 0; i < SK_TIMEOUT; i++) {
529 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
534 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
540 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
542 struct mii_data *mii;
544 mii = device_get_softc(sc_if->sk_miibus);
547 * If this is a GMII PHY, manually set the XMAC's
548 * duplex mode accordingly.
550 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
551 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
552 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
554 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
559 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
565 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
566 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
570 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
571 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
573 for (i = 0; i < SK_TIMEOUT; i++) {
575 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
576 if (val & YU_SMICR_READ_VALID)
580 if (i == SK_TIMEOUT) {
581 printf("sk%d: phy failed to come ready\n",
586 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
592 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
596 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
597 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
598 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
600 for (i = 0; i < SK_TIMEOUT; i++) {
602 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
610 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
614 #define XMAC_POLY 0xEDB88320
615 #define GMAC_POLY 0x04C11DB7L
619 xmac_calchash(caddr_t addr)
621 uint32_t idx, bit, data, crc;
623 /* Compute CRC for the address value. */
624 crc = 0xFFFFFFFF; /* initial value */
626 for (idx = 0; idx < 6; idx++) {
627 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
628 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? XMAC_POLY : 0);
631 return (~crc & ((1 << HASH_BITS) - 1));
635 gmac_calchash(caddr_t addr)
637 uint32_t idx, bit, crc, tmpData, data;
639 /* Compute CRC for the address value. */
640 crc = 0xFFFFFFFF; /* initial value */
642 for (idx = 0; idx < 6; idx++) {
645 /* Change bit order in byte. */
647 for (bit = 0; bit < 8; bit++) {
649 data |= 1 << (7 - bit);
652 data &= ~(1 << (7 - bit));
659 for (bit = 0; bit < 8; bit++) {
660 if (crc & 0x80000000) {
661 crc = (crc << 1) ^ GMAC_POLY;
668 return (crc & ((1 << HASH_BITS) - 1));
671 static void sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
675 base = XM_RXFILT_ENTRY(slot);
677 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
678 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
679 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
683 sk_setmulti(struct sk_if_softc *sc_if)
685 struct sk_softc *sc = sc_if->sk_softc;
686 struct ifnet *ifp = &sc_if->arpcom.ac_if;
687 uint32_t hashes[2] = { 0, 0 };
689 struct ifmultiaddr *ifma;
690 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
692 /* First, zot all the existing filters. */
693 switch(sc->sk_type) {
695 for (i = 1; i < XM_RXFILT_MAX; i++)
696 sk_setfilt(sc_if, (caddr_t)&dummy, i);
698 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
699 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
702 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
703 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
704 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
705 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
709 /* Now program new ones. */
710 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
711 hashes[0] = 0xFFFFFFFF;
712 hashes[1] = 0xFFFFFFFF;
715 /* First find the tail of the list. */
716 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
717 if (ifma->ifma_link.le_next == NULL)
720 /* Now traverse the list backwards. */
721 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
722 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
723 if (ifma->ifma_addr->sa_family != AF_LINK)
726 * Program the first XM_RXFILT_MAX multicast groups
727 * into the perfect filter. For all others,
728 * use the hash table.
730 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
732 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
737 switch(sc->sk_type) {
740 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
742 hashes[0] |= (1 << h);
744 hashes[1] |= (1 << (h - 32));
749 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
751 hashes[0] |= (1 << h);
753 hashes[1] |= (1 << (h - 32));
759 switch(sc->sk_type) {
761 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
762 XM_MODE_RX_USE_PERFECT);
763 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
764 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
767 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
768 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
769 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
770 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
776 sk_setpromisc(struct sk_if_softc *sc_if)
778 struct sk_softc *sc = sc_if->sk_softc;
779 struct ifnet *ifp = &sc_if->arpcom.ac_if;
781 switch(sc->sk_type) {
783 if (ifp->if_flags & IFF_PROMISC) {
784 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
786 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
790 if (ifp->if_flags & IFF_PROMISC) {
791 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
792 YU_RCR_UFLEN | YU_RCR_MUFLEN);
794 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
795 YU_RCR_UFLEN | YU_RCR_MUFLEN);
802 sk_init_rx_ring(struct sk_if_softc *sc_if)
804 struct sk_chain_data *cd = &sc_if->sk_cdata;
805 struct sk_ring_data *rd = sc_if->sk_rdata;
808 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
810 for (i = 0; i < SK_RX_RING_CNT; i++) {
811 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
812 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
814 if (i == (SK_RX_RING_CNT - 1)) {
815 cd->sk_rx_chain[i].sk_next =
817 rd->sk_rx_ring[i].sk_next =
818 vtophys(&rd->sk_rx_ring[0]);
820 cd->sk_rx_chain[i].sk_next =
821 &cd->sk_rx_chain[i + 1];
822 rd->sk_rx_ring[i].sk_next =
823 vtophys(&rd->sk_rx_ring[i + 1]);
827 sc_if->sk_cdata.sk_rx_prod = 0;
828 sc_if->sk_cdata.sk_rx_cons = 0;
834 sk_init_tx_ring(struct sk_if_softc *sc_if)
836 struct sk_chain_data *cd = &sc_if->sk_cdata;
837 struct sk_ring_data *rd = sc_if->sk_rdata;
840 bzero(sc_if->sk_rdata->sk_tx_ring,
841 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
843 for (i = 0; i < SK_TX_RING_CNT; i++) {
844 nexti = (i == (SK_TX_RING_CNT - 1)) ? 0 : i + 1;
845 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
846 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti];
847 rd->sk_tx_ring[i].sk_next = vtophys(&rd->sk_tx_ring[nexti]);
850 sc_if->sk_cdata.sk_tx_prod = 0;
851 sc_if->sk_cdata.sk_tx_cons = 0;
852 sc_if->sk_cdata.sk_tx_cnt = 0;
856 sk_newbuf(struct sk_if_softc *sc_if, struct sk_chain *c, struct mbuf *m)
858 struct mbuf *m_new = NULL;
859 struct sk_rx_desc *r;
864 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
868 /* Allocate the jumbo buffer */
869 buf = sk_jalloc(sc_if);
873 printf("sk%d: jumbo allocation failed "
874 "-- packet dropped!\n", sc_if->sk_unit);
879 /* Attach the buffer to the mbuf */
880 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
881 m_new->m_flags |= M_EXT | M_EXT_OLD;
882 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
883 m_new->m_len = SK_MCLBYTES;
884 m_new->m_ext.ext_nfree.old = sk_jfree;
885 m_new->m_ext.ext_nref.old = sk_jref;
888 * We're re-using a previously allocated mbuf;
889 * be sure to re-init pointers and lengths to
893 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES;
894 m_new->m_data = m_new->m_ext.ext_buf;
898 * Adjust alignment so packet payload begins on a
899 * longword boundary. Mandatory for Alpha, useful on
902 m_adj(m_new, ETHER_ALIGN);
906 r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
907 r->sk_ctl = m_new->m_len | SK_RXSTAT;
913 * Allocate jumbo buffer storage. The SysKonnect adapters support
914 * "jumbograms" (9K frames), although SysKonnect doesn't currently
915 * use them in their drivers. In order for us to use them, we need
916 * large 9K receive buffers, however standard mbuf clusters are only
917 * 2048 bytes in size. Consequently, we need to allocate and manage
918 * our own jumbo buffer pool. Fortunately, this does not require an
919 * excessive amount of additional code.
922 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
926 struct sk_jpool_entry *entry;
928 /* Grab a big chunk o' storage. */
929 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
930 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
932 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
933 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
937 SLIST_INIT(&sc_if->sk_jfree_listhead);
938 SLIST_INIT(&sc_if->sk_jinuse_listhead);
941 * Now divide it up into 9K pieces and save the addresses
942 * in an array. Note that we play an evil trick here by using
943 * the first few bytes in the buffer to hold the the address
944 * of the softc structure for this interface. This is because
945 * sk_jfree() needs it, but it is called by the mbuf management
946 * code which will not pass it to us explicitly.
948 ptr = sc_if->sk_cdata.sk_jumbo_buf;
949 for (i = 0; i < SK_JSLOTS; i++) {
951 aptr = (uint64_t **)ptr;
952 aptr[0] = (uint64_t *)sc_if;
953 ptr += sizeof(uint64_t);
954 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr;
955 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0;
957 entry = malloc(sizeof(struct sk_jpool_entry),
960 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
961 sc_if->sk_cdata.sk_jumbo_buf = NULL;
962 printf("sk%d: no memory for jumbo "
963 "buffer queue!\n", sc_if->sk_unit);
967 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
968 entry, jpool_entries);
975 * Allocate a jumbo buffer.
978 sk_jalloc(struct sk_if_softc *sc_if)
980 struct sk_jpool_entry *entry;
982 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
986 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
991 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
992 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
993 sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1;
994 return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf);
998 * Adjust usage count on a jumbo buffer. In general this doesn't
999 * get used much because our jumbo buffers don't get passed around
1000 * a lot, but it's implemented for correctness.
1003 sk_jref(caddr_t buf, u_int size)
1005 struct sk_if_softc *sc_if;
1009 /* Extract the softc struct pointer. */
1010 aptr = (uint64_t **)(buf - sizeof(uint64_t));
1011 sc_if = (struct sk_if_softc *)(aptr[0]);
1014 panic("sk_jref: can't find softc pointer!");
1016 if (size != SK_MCLBYTES)
1017 panic("sk_jref: adjusting refcount of buf of wrong size!");
1019 /* calculate the slot this buffer belongs to */
1021 i = ((vm_offset_t)aptr
1022 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1024 if ((i < 0) || (i >= SK_JSLOTS))
1025 panic("sk_jref: asked to reference buffer "
1026 "that we don't manage!");
1027 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1028 panic("sk_jref: buffer already free!");
1030 sc_if->sk_cdata.sk_jslots[i].sk_inuse++;
1034 * Release a jumbo buffer.
1037 sk_jfree(caddr_t buf, u_int size)
1039 struct sk_if_softc *sc_if;
1042 struct sk_jpool_entry *entry;
1044 /* Extract the softc struct pointer. */
1045 aptr = (uint64_t **)(buf - sizeof(uint64_t));
1046 sc_if = (struct sk_if_softc *)(aptr[0]);
1049 panic("sk_jfree: can't find softc pointer!");
1051 if (size != SK_MCLBYTES)
1052 panic("sk_jfree: freeing buffer of wrong size!");
1054 /* calculate the slot this buffer belongs to */
1056 i = ((vm_offset_t)aptr
1057 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1059 if ((i < 0) || (i >= SK_JSLOTS))
1060 panic("sk_jfree: asked to free buffer that we don't manage!");
1061 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1062 panic("sk_jfree: buffer already free!");
1064 sc_if->sk_cdata.sk_jslots[i].sk_inuse--;
1065 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) {
1066 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
1068 panic("sk_jfree: buffer not in use!");
1070 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead,
1072 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1073 entry, jpool_entries);
1079 * Set media options.
1082 sk_ifmedia_upd(struct ifnet *ifp)
1084 struct sk_if_softc *sc_if = ifp->if_softc;
1085 struct mii_data *mii;
1087 mii = device_get_softc(sc_if->sk_miibus);
1095 * Report current media status.
1098 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1100 struct sk_if_softc *sc_if;
1101 struct mii_data *mii;
1103 sc_if = ifp->if_softc;
1104 mii = device_get_softc(sc_if->sk_miibus);
1107 ifmr->ifm_active = mii->mii_media_active;
1108 ifmr->ifm_status = mii->mii_media_status;
1112 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1114 struct sk_if_softc *sc_if = ifp->if_softc;
1115 struct ifreq *ifr = (struct ifreq *)data;
1116 struct mii_data *mii;
1124 error = ether_ioctl(ifp, command, data);
1127 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1130 ifp->if_mtu = ifr->ifr_mtu;
1135 if (ifp->if_flags & IFF_UP) {
1136 if (ifp->if_flags & IFF_RUNNING) {
1137 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1139 sk_setpromisc(sc_if);
1145 if (ifp->if_flags & IFF_RUNNING)
1148 sc_if->sk_if_flags = ifp->if_flags;
1158 mii = device_get_softc(sc_if->sk_miibus);
1159 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1172 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1173 * IDs against our list and return a device name if we find a match.
1176 skc_probe(device_t dev)
1179 uint16_t vendor, product;
1181 vendor = pci_get_vendor(dev);
1182 product = pci_get_device(dev);
1184 for (t = sk_devs; t->sk_name != NULL; t++) {
1185 if (vendor == t->sk_vid && product == t->sk_did) {
1186 device_set_desc(dev, t->sk_name);
1195 * Force the GEnesis into reset, then bring it out of reset.
1198 sk_reset(struct sk_softc *sc)
1200 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1201 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1202 if (sc->sk_type == SK_YUKON)
1203 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1206 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1208 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1209 if (sc->sk_type == SK_YUKON)
1210 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1212 if (sc->sk_type == SK_GENESIS) {
1213 /* Configure packet arbiter */
1214 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1215 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1216 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1217 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1218 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1221 /* Enable RAM interface */
1222 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1225 * Configure interrupt moderation. The moderation timer
1226 * defers interrupts specified in the interrupt moderation
1227 * timer mask based on the timeout specified in the interrupt
1228 * moderation timer init register. Each bit in the timer
1229 * register represents 18.825ns, so to specify a timeout in
1230 * microseconds, we have to multiply by 54.
1232 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1233 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1234 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1235 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1239 sk_probe(device_t dev)
1241 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1244 * Not much to do here. We always know there will be
1245 * at least one XMAC present, and if there are two,
1246 * skc_attach() will create a second device instance
1249 switch (sc->sk_type) {
1251 device_set_desc(dev, "XaQti Corp. XMAC II");
1254 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1262 * Each XMAC chip is attached as a separate logical IP interface.
1263 * Single port cards will have only one logical interface of course.
1266 sk_attach(device_t dev)
1268 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1269 struct sk_if_softc *sc_if = device_get_softc(dev);
1273 port = *(int *)device_get_ivars(dev);
1274 free(device_get_ivars(dev), M_DEVBUF);
1275 device_set_ivars(dev, NULL);
1276 sc_if->sk_dev = dev;
1277 callout_init(&sc_if->sk_tick_timer);
1279 sc_if->sk_dev = dev;
1280 sc_if->sk_unit = device_get_unit(dev);
1281 sc_if->sk_port = port;
1282 sc_if->sk_softc = sc;
1283 sc->sk_if[port] = sc_if;
1284 if (port == SK_PORT_A)
1285 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1286 if (port == SK_PORT_B)
1287 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1290 * Get station address for this interface. Note that
1291 * dual port cards actually come with three station
1292 * addresses: one for each port, plus an extra. The
1293 * extra one is used by the SysKonnect driver software
1294 * as a 'virtual' station address for when both ports
1295 * are operating in failover mode. Currently we don't
1296 * use this extra address.
1298 for (i = 0; i < ETHER_ADDR_LEN; i++)
1299 sc_if->arpcom.ac_enaddr[i] =
1300 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1303 * Set up RAM buffer addresses. The NIC will have a certain
1304 * amount of SRAM on it, somewhere between 512K and 2MB. We
1305 * need to divide this up a) between the transmitter and
1306 * receiver and b) between the two XMACs, if this is a
1307 * dual port NIC. Our algotithm is to divide up the memory
1308 * evenly so that everyone gets a fair share.
1310 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1311 uint32_t chunk, val;
1313 chunk = sc->sk_ramsize / 2;
1314 val = sc->sk_rboff / sizeof(uint64_t);
1315 sc_if->sk_rx_ramstart = val;
1316 val += (chunk / sizeof(uint64_t));
1317 sc_if->sk_rx_ramend = val - 1;
1318 sc_if->sk_tx_ramstart = val;
1319 val += (chunk / sizeof(uint64_t));
1320 sc_if->sk_tx_ramend = val - 1;
1322 uint32_t chunk, val;
1324 chunk = sc->sk_ramsize / 4;
1325 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1327 sc_if->sk_rx_ramstart = val;
1328 val += (chunk / sizeof(uint64_t));
1329 sc_if->sk_rx_ramend = val - 1;
1330 sc_if->sk_tx_ramstart = val;
1331 val += (chunk / sizeof(uint64_t));
1332 sc_if->sk_tx_ramend = val - 1;
1335 /* Read and save PHY type and set PHY address */
1336 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1337 switch(sc_if->sk_phytype) {
1338 case SK_PHYTYPE_XMAC:
1339 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1341 case SK_PHYTYPE_BCOM:
1342 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1344 case SK_PHYTYPE_MARV_COPPER:
1345 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1348 printf("skc%d: unsupported PHY type: %d\n",
1349 sc->sk_unit, sc_if->sk_phytype);
1353 /* Allocate the descriptor queues. */
1354 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1355 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1357 if (sc_if->sk_rdata == NULL) {
1358 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1359 sc->sk_if[port] = NULL;
1363 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1365 /* Try to allocate memory for jumbo buffers. */
1366 if (sk_alloc_jumbo_mem(sc_if)) {
1367 printf("sk%d: jumbo buffer allocation failed\n",
1369 contigfree(sc_if->sk_rdata,
1370 sizeof(struct sk_ring_data), M_DEVBUF);
1371 sc->sk_if[port] = NULL;
1375 ifp = &sc_if->arpcom.ac_if;
1376 ifp->if_softc = sc_if;
1377 if_initname(ifp, "sk", sc_if->sk_unit);
1378 ifp->if_mtu = ETHERMTU;
1379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1380 ifp->if_ioctl = sk_ioctl;
1381 ifp->if_start = sk_start;
1382 ifp->if_watchdog = sk_watchdog;
1383 ifp->if_init = sk_init;
1384 ifp->if_baudrate = 1000000000;
1385 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1386 ifq_set_ready(&ifp->if_snd);
1391 switch (sc->sk_type) {
1393 sk_init_xmac(sc_if);
1396 sk_init_yukon(sc_if);
1400 if (mii_phy_probe(dev, &sc_if->sk_miibus,
1401 sk_ifmedia_upd, sk_ifmedia_sts)) {
1402 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1403 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1405 contigfree(sc_if->sk_rdata,
1406 sizeof(struct sk_ring_data), M_DEVBUF);
1411 * Call MI attach routine.
1413 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr);
1414 callout_init(&sc_if->sk_tick_timer);
1420 * Attach the interface. Allocate softc structures, do ifmedia
1421 * setup and ethernet/BPF attach.
1424 skc_attach(device_t dev)
1426 struct sk_softc *sc;
1427 int error = 0, *port, rid, s, unit;
1433 sc = device_get_softc(dev);
1434 unit = device_get_unit(dev);
1435 switch (pci_get_device(dev)) {
1436 case DEVICEID_SK_V1:
1437 sc->sk_type = SK_GENESIS;
1439 case DEVICEID_SK_V2:
1440 case DEVICEID_3COM_3C940:
1441 case DEVICEID_LINKSYS_EG1032:
1442 case DEVICEID_DLINK_DGE530T:
1443 sc->sk_type = SK_YUKON;
1448 * Handle power management nonsense.
1450 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1451 if (command == 0x01) {
1452 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1453 if (command & SK_PSTATE_MASK) {
1454 uint32_t iobase, membase, irq;
1456 /* Save important PCI config data. */
1457 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1458 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1459 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1461 /* Reset the power state. */
1462 printf("skc%d: chip is in D%d power mode "
1463 "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1464 command &= 0xFFFFFFFC;
1465 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1467 /* Restore PCI config data. */
1468 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1469 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1470 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1475 * Map control/status registers.
1477 command = pci_read_config(dev, PCIR_COMMAND, 4);
1478 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1479 pci_write_config(dev, PCIR_COMMAND, command, 4);
1480 command = pci_read_config(dev, PCIR_COMMAND, 4);
1482 #ifdef SK_USEIOSPACE
1483 if ((command & PCIM_CMD_PORTEN) == 0) {
1484 printf("skc%d: failed to enable I/O ports!\n", unit);
1489 if ((command & PCIM_CMD_MEMEN) == 0) {
1490 printf("skc%d: failed to enable memory mapping!\n", unit);
1497 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE);
1499 if (sc->sk_res == NULL) {
1500 printf("sk%d: couldn't map ports/memory\n", unit);
1505 sc->sk_btag = rman_get_bustag(sc->sk_res);
1506 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1508 /* Allocate interrupt */
1510 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1511 RF_SHAREABLE | RF_ACTIVE);
1513 if (sc->sk_irq == NULL) {
1514 printf("skc%d: couldn't map interrupt\n", unit);
1515 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1520 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1522 &sc->sk_intrhand, NULL);
1525 printf("skc%d: couldn't set up irq\n", unit);
1526 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1527 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1531 /* Reset the adapter. */
1536 /* Read and save vital product data from EEPROM. */
1539 skrs = sk_win_read_1(sc, SK_EPROM0);
1540 if (sc->sk_type == SK_GENESIS) {
1541 /* Read and save RAM size and RAMbuffer offset */
1543 case SK_RAMSIZE_512K_64:
1544 sc->sk_ramsize = 0x80000;
1545 sc->sk_rboff = SK_RBOFF_0;
1547 case SK_RAMSIZE_1024K_64:
1548 sc->sk_ramsize = 0x100000;
1549 sc->sk_rboff = SK_RBOFF_80000;
1551 case SK_RAMSIZE_1024K_128:
1552 sc->sk_ramsize = 0x100000;
1553 sc->sk_rboff = SK_RBOFF_0;
1555 case SK_RAMSIZE_2048K_128:
1556 sc->sk_ramsize = 0x200000;
1557 sc->sk_rboff = SK_RBOFF_0;
1560 printf("skc%d: unknown ram size: %d\n",
1561 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1562 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1563 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1564 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1569 } else { /* SK_YUKON */
1571 sc->sk_ramsize = 0x20000;
1573 sc->sk_ramsize = skrs * (1<<12);
1575 sc->sk_rboff = SK_RBOFF_0;
1578 /* Read and save physical media type */
1579 switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1580 case SK_PMD_1000BASESX:
1581 sc->sk_pmd = IFM_1000_SX;
1583 case SK_PMD_1000BASELX:
1584 sc->sk_pmd = IFM_1000_LX;
1586 case SK_PMD_1000BASECX:
1587 sc->sk_pmd = IFM_1000_CX;
1589 case SK_PMD_1000BASETX:
1590 sc->sk_pmd = IFM_1000_T;
1593 printf("skc%d: unknown media type: 0x%x\n",
1594 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1595 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1596 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1597 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1602 /* Announce the product name. */
1603 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1604 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1605 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1607 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1609 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1610 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1611 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1613 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1616 /* Turn on the 'driver is loaded' LED. */
1617 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1619 bus_generic_attach(dev);
1627 sk_detach(device_t dev)
1629 struct sk_if_softc *sc_if = device_get_softc(dev);
1630 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1636 ether_ifdetach(ifp);
1637 bus_generic_detach(dev);
1638 if (sc_if->sk_miibus != NULL)
1639 device_delete_child(dev, sc_if->sk_miibus);
1640 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1641 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1649 skc_detach(device_t dev)
1651 struct sk_softc *sc;
1656 sc = device_get_softc(dev);
1658 bus_generic_detach(dev);
1659 if (sc->sk_devs[SK_PORT_A] != NULL)
1660 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1661 if (sc->sk_devs[SK_PORT_B] != NULL)
1662 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1664 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1665 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1666 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1674 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1676 struct sk_tx_desc *f = NULL;
1678 uint32_t cnt = 0, cur, frag;
1681 cur = frag = *txidx;
1684 * Start packing the mbufs in this chain into
1685 * the fragment pointers. Stop when we run out
1686 * of fragments or hit the end of the mbuf chain.
1688 for (m = m_head; m != NULL; m = m->m_next) {
1689 if (m->m_len != 0) {
1690 if ((SK_TX_RING_CNT -
1691 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1693 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1694 f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1695 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1697 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1699 f->sk_ctl |= SK_TXCTL_OWN;
1701 SK_INC(frag, SK_TX_RING_CNT);
1709 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1710 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1711 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1712 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1713 sc_if->sk_cdata.sk_tx_cnt += cnt;
1721 sk_start(struct ifnet *ifp)
1723 struct sk_if_softc *sc_if = ifp->if_softc;
1724 struct sk_softc *sc = sc_if->sk_softc;
1725 struct mbuf *m_head = NULL;
1728 idx = sc_if->sk_cdata.sk_tx_prod;
1730 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1731 m_head = ifq_poll(&ifp->if_snd);
1736 * Pack the data into the transmit ring. If we
1737 * don't have room, set the OACTIVE flag and wait
1738 * for the NIC to drain the ring.
1740 if (sk_encap(sc_if, m_head, &idx)) {
1741 ifp->if_flags |= IFF_OACTIVE;
1744 m_head = ifq_dequeue(&ifp->if_snd);
1746 BPF_MTAP(ifp, m_head);
1750 sc_if->sk_cdata.sk_tx_prod = idx;
1751 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1753 /* Set a timeout in case the chip goes out to lunch. */
1759 sk_watchdog(struct ifnet *ifp)
1761 struct sk_if_softc *sc_if;
1763 sc_if = ifp->if_softc;
1765 printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1770 skc_shutdown(device_t dev)
1772 struct sk_softc *sc = device_get_softc(dev);
1774 /* Turn off the 'driver is loaded' LED. */
1775 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1778 * Reset the GEnesis controller. Doing this should also
1779 * assert the resets on the attached XMAC(s).
1785 sk_rxeof(struct sk_if_softc *sc_if)
1787 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1789 struct sk_chain *cur_rx;
1790 int i, total_len = 0;
1793 i = sc_if->sk_cdata.sk_rx_prod;
1794 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1796 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1797 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1798 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1799 m = cur_rx->sk_mbuf;
1800 cur_rx->sk_mbuf = NULL;
1801 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1802 SK_INC(i, SK_RX_RING_CNT);
1804 if (rxstat & XM_RXSTAT_ERRFRAME) {
1806 sk_newbuf(sc_if, cur_rx, m);
1811 * Try to allocate a new jumbo buffer. If that
1812 * fails, copy the packet to mbufs and put the
1813 * jumbo buffer back in the ring so it can be
1814 * re-used. If allocating mbufs fails, then we
1815 * have to drop the packet.
1817 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1819 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1820 total_len + ETHER_ALIGN, 0, ifp, NULL);
1821 sk_newbuf(sc_if, cur_rx, m);
1823 printf("sk%d: no receive buffers "
1824 "available -- packet dropped!\n",
1829 m_adj(m0, ETHER_ALIGN);
1832 m->m_pkthdr.rcvif = ifp;
1833 m->m_pkthdr.len = m->m_len = total_len;
1837 (*ifp->if_input)(ifp, m);
1840 sc_if->sk_cdata.sk_rx_prod = i;
1844 sk_txeof(struct sk_if_softc *sc_if)
1846 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1847 struct sk_tx_desc *cur_tx = NULL;
1851 * Go through our tx ring and free mbufs for those
1852 * frames that have been sent.
1854 idx = sc_if->sk_cdata.sk_tx_cons;
1855 while(idx != sc_if->sk_cdata.sk_tx_prod) {
1856 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1857 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1859 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1861 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1862 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1863 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1865 sc_if->sk_cdata.sk_tx_cnt--;
1866 SK_INC(idx, SK_TX_RING_CNT);
1870 sc_if->sk_cdata.sk_tx_cons = idx;
1873 ifp->if_flags &= ~IFF_OACTIVE;
1877 sk_tick(void *xsc_if)
1879 struct sk_if_softc *sc_if = xsc_if;
1880 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1881 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
1884 if ((ifp->if_flags & IFF_UP) == 0)
1887 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1888 sk_intr_bcom(sc_if);
1893 * According to SysKonnect, the correct way to verify that
1894 * the link has come back up is to poll bit 0 of the GPIO
1895 * register three times. This pin has the signal from the
1896 * link_sync pin connected to it; if we read the same link
1897 * state 3 times in a row, we know the link is up.
1899 for (i = 0; i < 3; i++) {
1900 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1905 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
1909 /* Turn the GP0 interrupt back on. */
1910 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1911 SK_XM_READ_2(sc_if, XM_ISR);
1914 callout_stop(&sc_if->sk_tick_timer);
1918 sk_intr_bcom(struct sk_if_softc *sc_if)
1920 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1921 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
1924 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1927 * Read the PHY interrupt register to make sure
1928 * we clear any pending interrupts.
1930 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
1932 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1933 sk_init_xmac(sc_if);
1937 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
1939 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
1942 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
1944 /* Turn off the link LED. */
1945 SK_IF_WRITE_1(sc_if, 0,
1946 SK_LINKLED1_CTL, SK_LINKLED_OFF);
1948 } else if (status & BRGPHY_ISR_LNK_CHG) {
1949 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
1950 BRGPHY_MII_IMR, 0xFF00);
1953 /* Turn on the link LED. */
1954 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
1955 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
1956 SK_LINKLED_BLINK_OFF);
1960 callout_reset(&sc_if->sk_tick_timer, hz,
1965 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1969 sk_intr_xmac(struct sk_if_softc *sc_if)
1973 status = SK_XM_READ_2(sc_if, XM_ISR);
1976 * Link has gone down. Start MII tick timeout to
1977 * watch for link resync.
1979 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
1980 if (status & XM_ISR_GP0_SET) {
1981 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1982 callout_reset(&sc_if->sk_tick_timer, hz,
1986 if (status & XM_ISR_AUTONEG_DONE) {
1987 callout_reset(&sc_if->sk_tick_timer, hz,
1992 if (status & XM_IMR_TX_UNDERRUN)
1993 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
1995 if (status & XM_IMR_RX_OVERRUN)
1996 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
1998 status = SK_XM_READ_2(sc_if, XM_ISR);
2002 sk_intr_yukon(struct sk_if_softc *sc_if)
2006 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2012 struct sk_softc *sc = xsc;
2013 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2014 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_A];
2015 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2019 ifp0 = &sc_if0->arpcom.ac_if;
2021 ifp1 = &sc_if1->arpcom.ac_if;
2024 status = CSR_READ_4(sc, SK_ISSR);
2025 if ((status & sc->sk_intrmask) == 0)
2028 /* Handle receive interrupts first. */
2029 if (status & SK_ISR_RX1_EOF) {
2031 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2032 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2034 if (status & SK_ISR_RX2_EOF) {
2036 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2037 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2040 /* Then transmit interrupts. */
2041 if (status & SK_ISR_TX1_S_EOF) {
2043 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2044 SK_TXBMU_CLR_IRQ_EOF);
2046 if (status & SK_ISR_TX2_S_EOF) {
2048 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2049 SK_TXBMU_CLR_IRQ_EOF);
2052 /* Then MAC interrupts. */
2053 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
2054 if (sc->sk_type == SK_GENESIS)
2055 sk_intr_xmac(sc_if0);
2057 sk_intr_yukon(sc_if0);
2060 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
2061 if (sc->sk_type == SK_GENESIS)
2062 sk_intr_xmac(sc_if1);
2064 sk_intr_yukon(sc_if0);
2067 if (status & SK_ISR_EXTERNAL_REG) {
2069 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2070 sk_intr_bcom(sc_if0);
2072 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2073 sk_intr_bcom(sc_if1);
2077 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2079 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2081 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd))
2086 sk_init_xmac(struct sk_if_softc *sc_if)
2088 struct sk_softc *sc = sc_if->sk_softc;
2089 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2090 struct sk_bcom_hack bhack[] = {
2091 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2092 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2093 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2096 /* Unreset the XMAC. */
2097 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2100 /* Reset the XMAC's internal state. */
2101 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2103 /* Save the XMAC II revision */
2104 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2107 * Perform additional initialization for external PHYs,
2108 * namely for the 1000baseTX cards that use the XMAC's
2111 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2115 /* Take PHY out of reset. */
2116 val = sk_win_read_4(sc, SK_GPIO);
2117 if (sc_if->sk_port == SK_PORT_A)
2118 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2120 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2121 sk_win_write_4(sc, SK_GPIO, val);
2123 /* Enable GMII mode on the XMAC. */
2124 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2126 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2127 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2129 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2130 BRGPHY_MII_IMR, 0xFFF0);
2133 * Early versions of the BCM5400 apparently have
2134 * a bug that requires them to have their reserved
2135 * registers initialized to some magic values. I don't
2136 * know what the numbers do, I'm just the messenger.
2138 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2140 while(bhack[i].reg) {
2141 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2142 bhack[i].reg, bhack[i].val);
2148 /* Set station address */
2149 SK_XM_WRITE_2(sc_if, XM_PAR0,
2150 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2151 SK_XM_WRITE_2(sc_if, XM_PAR1,
2152 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2153 SK_XM_WRITE_2(sc_if, XM_PAR2,
2154 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2155 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2157 if (ifp->if_flags & IFF_BROADCAST)
2158 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2160 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2162 /* We don't need the FCS appended to the packet. */
2163 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2165 /* We want short frames padded to 60 bytes. */
2166 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2169 * Enable the reception of all error frames. This is is
2170 * a necessary evil due to the design of the XMAC. The
2171 * XMAC's receive FIFO is only 8K in size, however jumbo
2172 * frames can be up to 9000 bytes in length. When bad
2173 * frame filtering is enabled, the XMAC's RX FIFO operates
2174 * in 'store and forward' mode. For this to work, the
2175 * entire frame has to fit into the FIFO, but that means
2176 * that jumbo frames larger than 8192 bytes will be
2177 * truncated. Disabling all bad frame filtering causes
2178 * the RX FIFO to operate in streaming mode, in which
2179 * case the XMAC will start transfering frames out of the
2180 * RX FIFO as soon as the FIFO threshold is reached.
2182 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2183 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2184 XM_MODE_RX_INRANGELEN);
2186 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2187 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2189 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2192 * Bump up the transmit threshold. This helps hold off transmit
2193 * underruns when we're blasting traffic from both ports at once.
2195 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2197 /* Set promiscuous mode */
2198 sk_setpromisc(sc_if);
2200 /* Set multicast filter */
2203 /* Clear and enable interrupts */
2204 SK_XM_READ_2(sc_if, XM_ISR);
2205 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2206 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2208 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2210 /* Configure MAC arbiter */
2211 switch(sc_if->sk_xmac_rev) {
2212 case XM_XMAC_REV_B2:
2213 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2214 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2215 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2216 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2217 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2218 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2219 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2220 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2221 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2223 case XM_XMAC_REV_C1:
2224 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2225 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2226 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2227 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2228 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2229 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2230 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2231 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2232 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2237 sk_win_write_2(sc, SK_MACARB_CTL,
2238 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2244 sk_init_yukon(struct sk_if_softc *sc_if)
2246 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2251 /* GMAC and GPHY Reset */
2252 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2253 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2255 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2256 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2259 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2260 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2262 switch(sc_if->sk_softc->sk_pmd) {
2265 phy |= SK_GPHY_FIBER;
2270 phy |= SK_GPHY_COPPER;
2274 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2276 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2277 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2278 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2280 /* unused read of the interrupt source register */
2281 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2283 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2285 /* MIB Counter Clear Mode set */
2286 reg |= YU_PAR_MIB_CLR;
2287 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2289 /* MIB Counter Clear Mode clear */
2290 reg &= ~YU_PAR_MIB_CLR;
2291 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2293 /* receive control reg */
2294 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2296 /* transmit parameter register */
2297 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2298 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2300 /* serial mode register */
2301 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2302 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2303 reg |= YU_SMR_MFL_JUMBO;
2304 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2306 /* Setup Yukon's address */
2307 for (i = 0; i < 3; i++) {
2308 /* Write Source Address 1 (unicast filter) */
2309 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2310 sc_if->arpcom.ac_enaddr[i * 2] |
2311 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2314 for (i = 0; i < 3; i++) {
2315 reg = sk_win_read_2(sc_if->sk_softc,
2316 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2317 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2320 /* Set promiscuous mode */
2321 sk_setpromisc(sc_if);
2323 /* Set multicast filter */
2326 /* enable interrupt mask for counter overflows */
2327 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2328 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2329 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2331 /* Configure RX MAC FIFO */
2332 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2333 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2335 /* Configure TX MAC FIFO */
2336 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2337 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2341 * Note that to properly initialize any part of the GEnesis chip,
2342 * you first have to take it out of reset mode.
2347 struct sk_if_softc *sc_if = xsc;
2348 struct sk_softc *sc = sc_if->sk_softc;
2349 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2350 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2356 /* Cancel pending I/O and free all RX/TX buffers. */
2359 if (sc->sk_type == SK_GENESIS) {
2360 /* Configure LINK_SYNC LED */
2361 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2362 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2363 SK_LINKLED_LINKSYNC_ON);
2365 /* Configure RX LED */
2366 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2367 SK_RXLEDCTL_COUNTER_START);
2369 /* Configure TX LED */
2370 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2371 SK_TXLEDCTL_COUNTER_START);
2374 /* Configure I2C registers */
2376 /* Configure XMAC(s) */
2377 switch (sc->sk_type) {
2379 sk_init_xmac(sc_if);
2382 sk_init_yukon(sc_if);
2387 if (sc->sk_type == SK_GENESIS) {
2388 /* Configure MAC FIFOs */
2389 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2390 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2391 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2393 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2394 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2395 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2398 /* Configure transmit arbiter(s) */
2399 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2400 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2402 /* Configure RAMbuffers */
2403 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2404 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2405 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2406 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2407 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2408 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2410 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2411 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2412 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2413 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2414 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2415 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2416 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2418 /* Configure BMUs */
2419 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2420 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2421 vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2422 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2424 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2425 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2426 vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2427 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2429 /* Init descriptors */
2430 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2431 printf("sk%d: initialization failed: no "
2432 "memory for rx buffers\n", sc_if->sk_unit);
2437 sk_init_tx_ring(sc_if);
2439 /* Configure interrupt handling */
2440 CSR_READ_4(sc, SK_ISSR);
2441 if (sc_if->sk_port == SK_PORT_A)
2442 sc->sk_intrmask |= SK_INTRS1;
2444 sc->sk_intrmask |= SK_INTRS2;
2446 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2448 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2451 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2453 switch(sc->sk_type) {
2455 /* Enable XMACs TX and RX state machines */
2456 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2457 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2458 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB);
2461 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2462 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2463 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2464 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2467 ifp->if_flags |= IFF_RUNNING;
2468 ifp->if_flags &= ~IFF_OACTIVE;
2474 sk_stop(struct sk_if_softc *sc_if)
2477 struct sk_softc *sc = sc_if->sk_softc;
2478 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2480 callout_stop(&sc_if->sk_tick_timer);
2482 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2485 /* Put PHY back into reset. */
2486 val = sk_win_read_4(sc, SK_GPIO);
2487 if (sc_if->sk_port == SK_PORT_A) {
2488 val |= SK_GPIO_DIR0;
2489 val &= ~SK_GPIO_DAT0;
2491 val |= SK_GPIO_DIR2;
2492 val &= ~SK_GPIO_DAT2;
2494 sk_win_write_4(sc, SK_GPIO, val);
2497 /* Turn off various components of this interface. */
2498 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2499 switch (sc->sk_type) {
2501 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2502 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2505 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2506 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2509 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2510 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2511 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2512 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2513 SK_RBCTL_RESET | SK_RBCTL_OFF);
2514 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2515 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2516 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2517 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2518 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2520 /* Disable interrupts */
2521 if (sc_if->sk_port == SK_PORT_A)
2522 sc->sk_intrmask &= ~SK_INTRS1;
2524 sc->sk_intrmask &= ~SK_INTRS2;
2525 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2527 SK_XM_READ_2(sc_if, XM_ISR);
2528 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2530 /* Free RX and TX mbufs still in the queues. */
2531 for (i = 0; i < SK_RX_RING_CNT; i++) {
2532 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2533 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2534 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2538 for (i = 0; i < SK_TX_RING_CNT; i++) {
2539 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2540 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2541 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2545 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);