sys/dev/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/export.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_edid.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37
  38 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  39
  40 /**
  41  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  42  * @intel_dp: DP struct
  43  *
  44  * If a CPU or PCH DP output is attached to an eDP panel, this function
  45  * will return true, and false otherwise.
  46  */
  47 static bool is_edp(struct intel_dp *intel_dp)
  48 {
  49         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  50
  51         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  52 }
  53
  54 /**
  55  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  56  * @intel_dp: DP struct
  57  *
  58  * Returns true if the given DP struct corresponds to a PCH DP port attached
  59  * to an eDP panel, false otherwise.  Helpful for determining whether we
  60  * may need FDI resources for a given DP output or not.
  61  */
  62 static bool is_pch_edp(struct intel_dp *intel_dp)
  63 {
  64         return intel_dp->is_pch_edp;
  65 }
  66
  67 /**
  68  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  69  * @intel_dp: DP struct
  70  *
  71  * Returns true if the given DP struct corresponds to a CPU eDP port.
  72  */
  73 static bool is_cpu_edp(struct intel_dp *intel_dp)
  74 {
  75         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  76 }
  77
  78 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  79 {
  80         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  81
  82         return intel_dig_port->base.base.dev;
  83 }
  84
  85 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  86 {
  87         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  88 }
  89
  90 /**
  91  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  92  * @encoder: DRM encoder
  93  *
  94  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  95  * by intel_display.c.
  96  */
  97 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  98 {
  99         struct intel_dp *intel_dp;
 100
 101         if (!encoder)
 102                 return false;
 103
 104         intel_dp = enc_to_intel_dp(encoder);
 105
 106         return is_pch_edp(intel_dp);
 107 }
 108
 109 static void intel_dp_link_down(struct intel_dp *intel_dp);
 110
 111 static int
 112 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 113 {
 114         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 115
 116         switch (max_link_bw) {
 117         case DP_LINK_BW_1_62:
 118         case DP_LINK_BW_2_7:
 119                 break;
 120         default:
 121                 max_link_bw = DP_LINK_BW_1_62;
 122                 break;
 123         }
 124         return max_link_bw;
 125 }
 126
 127 /*
 128  * The units on the numbers in the next two are... bizarre.  Examples will
 129  * make it clearer; this one parallels an example in the eDP spec.
 130  *
 131  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 132  *
 133  *     270000 * 1 * 8 / 10 == 216000
 134  *
 135  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 136  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 137  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 138  * 119000.  At 18bpp that's 2142000 kilobits per second.
 139  *
 140  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 141  * get the result in decakilobits instead of kilobits.
 142  */
 143
 144 static int
 145 intel_dp_link_required(int pixel_clock, int bpp)
 146 {
 147         return (pixel_clock * bpp + 9) / 10;
 148 }
 149
 150 static int
 151 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 152 {
 153         return (max_link_clock * max_lanes * 8) / 10;
 154 }
 155
 156 static int
 157 intel_dp_mode_valid(struct drm_connector *connector,
 158                     struct drm_display_mode *mode)
 159 {
 160         struct intel_dp *intel_dp = intel_attached_dp(connector);
 161         struct intel_connector *intel_connector = to_intel_connector(connector);
 162         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 163         int target_clock = mode->clock;
 164         int max_rate, mode_rate, max_lanes, max_link_clock;
 165
 166         if (is_edp(intel_dp) && fixed_mode) {
 167                 if (mode->hdisplay > fixed_mode->hdisplay)
 168                         return MODE_PANEL;
 169
 170                 if (mode->vdisplay > fixed_mode->vdisplay)
 171                         return MODE_PANEL;
 172
 173                 target_clock = fixed_mode->clock;
 174         }
 175
 176         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 177         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 178
 179         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 180         mode_rate = intel_dp_link_required(target_clock, 18);
 181
 182         if (mode_rate > max_rate)
 183                 return MODE_CLOCK_HIGH;
 184
 185         if (mode->clock < 10000)
 186                 return MODE_CLOCK_LOW;
 187
 188         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 189                 return MODE_H_ILLEGAL;
 190
 191         return MODE_OK;
 192 }
 193
 194 static uint32_t
 195 pack_aux(uint8_t *src, int src_bytes)
 196 {
 197         int     i;
 198         uint32_t v = 0;
 199
 200         if (src_bytes > 4)
 201                 src_bytes = 4;
 202         for (i = 0; i < src_bytes; i++)
 203                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 204         return v;
 205 }
 206
 207 static void
 208 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 209 {
 210         int i;
 211         if (dst_bytes > 4)
 212                 dst_bytes = 4;
 213         for (i = 0; i < dst_bytes; i++)
 214                 dst[i] = src >> ((3-i) * 8);
 215 }
 216
 217 /* hrawclock is 1/4 the FSB frequency */
 218 static int
 219 intel_hrawclk(struct drm_device *dev)
 220 {
 221         struct drm_i915_private *dev_priv = dev->dev_private;
 222         uint32_t clkcfg;
 223
 224         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 225         if (IS_VALLEYVIEW(dev))
 226                 return 200;
 227
 228         clkcfg = I915_READ(CLKCFG);
 229         switch (clkcfg & CLKCFG_FSB_MASK) {
 230         case CLKCFG_FSB_400:
 231                 return 100;
 232         case CLKCFG_FSB_533:
 233                 return 133;
 234         case CLKCFG_FSB_667:
 235                 return 166;
 236         case CLKCFG_FSB_800:
 237                 return 200;
 238         case CLKCFG_FSB_1067:
 239                 return 266;
 240         case CLKCFG_FSB_1333:
 241                 return 333;
 242         /* these two are just a guess; one of them might be right */
 243         case CLKCFG_FSB_1600:
 244         case CLKCFG_FSB_1600_ALT:
 245                 return 400;
 246         default:
 247                 return 133;
 248         }
 249 }
 250
 251 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 252 {
 253         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         u32 pp_stat_reg;
 256
 257         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 258         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 259 }
 260
 261 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 262 {
 263         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265         u32 pp_ctrl_reg;
 266
 267         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 268         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 269 }
 270
 271 static void
 272 intel_dp_check_edp(struct intel_dp *intel_dp)
 273 {
 274         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 275         struct drm_i915_private *dev_priv = dev->dev_private;
 276         u32 pp_stat_reg, pp_ctrl_reg;
 277
 278         if (!is_edp(intel_dp))
 279                 return;
 280
 281         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 282         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 283
 284         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 285                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 286                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 287                                 I915_READ(pp_stat_reg),
 288                                 I915_READ(pp_ctrl_reg));
 289         }
 290 }
 291
 292 static uint32_t
 293 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 294 {
 295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 296         struct drm_device *dev = intel_dig_port->base.base.dev;
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 299         uint32_t status;
 300         bool done;
 301
 302 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 303         if (has_aux_irq)
 304                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 305                                           msecs_to_jiffies_timeout(10));
 306         else
 307                 done = wait_for_atomic(C, 10) == 0;
 308         if (!done)
 309                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 310                           has_aux_irq);
 311 #undef C
 312
 313         return status;
 314 }
 315
 316 static int
 317 intel_dp_aux_ch(struct intel_dp *intel_dp,
 318                 uint8_t *send, int send_bytes,
 319                 uint8_t *recv, int recv_size)
 320 {
 321         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 322         struct drm_device *dev = intel_dig_port->base.base.dev;
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 325         uint32_t ch_data = ch_ctl + 4;
 326         int i, ret, recv_bytes;
 327         uint32_t status;
 328         uint32_t aux_clock_divider;
 329         int try, precharge;
 330         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 331
 332         /* dp aux is extremely sensitive to irq latency, hence request the
 333          * lowest possible wakeup latency and so prevent the cpu from going into
 334          * deep sleep states.
 335          */
 336         pm_qos_update_request(&dev_priv->pm_qos, 0);
 337
 338         intel_dp_check_edp(intel_dp);
 339         /* The clock divider is based off the hrawclk,
 340          * and would like to run at 2MHz. So, take the
 341          * hrawclk value and divide by 2 and use that
 342          *
 343          * Note that PCH attached eDP panels should use a 125MHz input
 344          * clock divider.
 345          */
 346         if (is_cpu_edp(intel_dp)) {
 347                 if (HAS_DDI(dev))
 348                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 349                 else if (IS_VALLEYVIEW(dev))
 350                         aux_clock_divider = 100;
 351                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 352                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 353                 else
 354                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 355         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 356                 /* Workaround for non-ULT HSW */
 357                 aux_clock_divider = 74;
 358         } else if (HAS_PCH_SPLIT(dev)) {
 359                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 360         } else {
 361                 aux_clock_divider = intel_hrawclk(dev) / 2;
 362         }
 363
 364         if (IS_GEN6(dev))
 365                 precharge = 3;
 366         else
 367                 precharge = 5;
 368
 369         /* Try to wait for any previous AUX channel activity */
 370         for (try = 0; try < 3; try++) {
 371                 status = I915_READ_NOTRACE(ch_ctl);
 372                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 373                         break;
 374                 msleep(1);
 375         }
 376
 377         if (try == 3) {
 378                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 379                      I915_READ(ch_ctl));
 380                 ret = -EBUSY;
 381                 goto out;
 382         }
 383
 384         /* Must try at least 3 times according to DP spec */
 385         for (try = 0; try < 5; try++) {
 386                 /* Load the send data into the aux channel data registers */
 387                 for (i = 0; i < send_bytes; i += 4)
 388                         I915_WRITE(ch_data + i,
 389                                    pack_aux(send + i, send_bytes - i));
 390
 391                 /* Send the command and wait for it to complete */
 392                 I915_WRITE(ch_ctl,
 393                            DP_AUX_CH_CTL_SEND_BUSY |
 394                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 395                            DP_AUX_CH_CTL_TIME_OUT_400us |
 396                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 397                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 398                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 399                            DP_AUX_CH_CTL_DONE |
 400                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 401                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 402
 403                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 404
 405                 /* Clear done status and any errors */
 406                 I915_WRITE(ch_ctl,
 407                            status |
 408                            DP_AUX_CH_CTL_DONE |
 409                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 410                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 411
 412                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 413                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 414                         continue;
 415                 if (status & DP_AUX_CH_CTL_DONE)
 416                         break;
 417         }
 418
 419         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 420                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 421                 ret = -EBUSY;
 422                 goto out;
 423         }
 424
 425         /* Check for timeout or receive error.
 426          * Timeouts occur when the sink is not connected
 427          */
 428         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 429                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 430                 ret = -EIO;
 431                 goto out;
 432         }
 433
 434         /* Timeouts occur when the device isn't connected, so they're
 435          * "normal" -- don't fill the kernel log with these */
 436         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 437                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 438                 ret = -ETIMEDOUT;
 439                 goto out;
 440         }
 441
 442         /* Unload any bytes sent back from the other side */
 443         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 444                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 445         if (recv_bytes > recv_size)
 446                 recv_bytes = recv_size;
 447
 448         for (i = 0; i < recv_bytes; i += 4)
 449                 unpack_aux(I915_READ(ch_data + i),
 450                            recv + i, recv_bytes - i);
 451
 452         ret = recv_bytes;
 453 out:
 454         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 455
 456         return ret;
 457 }
 458
 459 /* Write data to the aux channel in native mode */
 460 static int
 461 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 462                           uint16_t address, uint8_t *send, int send_bytes)
 463 {
 464         int ret;
 465         uint8_t msg[20];
 466         int msg_bytes;
 467         uint8_t ack;
 468
 469         intel_dp_check_edp(intel_dp);
 470         if (send_bytes > 16)
 471                 return -1;
 472         msg[0] = AUX_NATIVE_WRITE << 4;
 473         msg[1] = address >> 8;
 474         msg[2] = address & 0xff;
 475         msg[3] = send_bytes - 1;
 476         memcpy(&msg[4], send, send_bytes);
 477         msg_bytes = send_bytes + 4;
 478         for (;;) {
 479                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 480                 if (ret < 0)
 481                         return ret;
 482                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 483                         break;
 484                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 485                         udelay(100);
 486                 else
 487                         return -EIO;
 488         }
 489         return send_bytes;
 490 }
 491
 492 /* Write a single byte to the aux channel in native mode */
 493 static int
 494 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 495                             uint16_t address, uint8_t byte)
 496 {
 497         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 498 }
 499
 500 /* read bytes from a native aux channel */
 501 static int
 502 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 503                          uint16_t address, uint8_t *recv, int recv_bytes)
 504 {
 505         uint8_t msg[4];
 506         int msg_bytes;
 507         uint8_t reply[20];
 508         int reply_bytes;
 509         uint8_t ack;
 510         int ret;
 511
 512         intel_dp_check_edp(intel_dp);
 513         msg[0] = AUX_NATIVE_READ << 4;
 514         msg[1] = address >> 8;
 515         msg[2] = address & 0xff;
 516         msg[3] = recv_bytes - 1;
 517
 518         msg_bytes = 4;
 519         reply_bytes = recv_bytes + 1;
 520
 521         for (;;) {
 522                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 523                                       reply, reply_bytes);
 524                 if (ret == 0)
 525                         return -EPROTO;
 526                 if (ret < 0)
 527                         return ret;
 528                 ack = reply[0];
 529                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 530                         memcpy(recv, reply + 1, ret - 1);
 531                         return ret - 1;
 532                 }
 533                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 534                         udelay(100);
 535                 else
 536                         return -EIO;
 537         }
 538 }
 539
 540 static int
 541 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
 542                     uint8_t write_byte, uint8_t *read_byte)
 543 {
 544         struct iic_dp_aux_data *data = device_get_softc(adapter);
 545         struct intel_dp *intel_dp = data->priv;
 546         uint16_t address = data->address;
 547         uint8_t msg[5];
 548         uint8_t reply[2];
 549         unsigned retry;
 550         int msg_bytes;
 551         int reply_bytes;
 552         int ret;
 553
 554         intel_dp_check_edp(intel_dp);
 555         /* Set up the command byte */
 556         if (mode & MODE_I2C_READ)
 557                 msg[0] = AUX_I2C_READ << 4;
 558         else
 559                 msg[0] = AUX_I2C_WRITE << 4;
 560
 561         if (!(mode & MODE_I2C_STOP))
 562                 msg[0] |= AUX_I2C_MOT << 4;
 563
 564         msg[1] = address >> 8;
 565         msg[2] = address;
 566
 567         switch (mode) {
 568         case MODE_I2C_WRITE:
 569                 msg[3] = 0;
 570                 msg[4] = write_byte;
 571                 msg_bytes = 5;
 572                 reply_bytes = 1;
 573                 break;
 574         case MODE_I2C_READ:
 575                 msg[3] = 0;
 576                 msg_bytes = 4;
 577                 reply_bytes = 2;
 578                 break;
 579         default:
 580                 msg_bytes = 3;
 581                 reply_bytes = 1;
 582                 break;
 583         }
 584
 585         for (retry = 0; retry < 5; retry++) {
 586                 ret = intel_dp_aux_ch(intel_dp,
 587                                       msg, msg_bytes,
 588                                       reply, reply_bytes);
 589                 if (ret < 0) {
 590                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 591                         return ret;
 592                 }
 593
 594                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 595                 case AUX_NATIVE_REPLY_ACK:
 596                         /* I2C-over-AUX Reply field is only valid
 597                          * when paired with AUX ACK.
 598                          */
 599                         break;
 600                 case AUX_NATIVE_REPLY_NACK:
 601                         DRM_DEBUG_KMS("aux_ch native nack\n");
 602                         return -EREMOTEIO;
 603                 case AUX_NATIVE_REPLY_DEFER:
 604                         udelay(100);
 605                         continue;
 606                 default:
 607                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 608                                   reply[0]);
 609                         return -EREMOTEIO;
 610                 }
 611
 612                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 613                 case AUX_I2C_REPLY_ACK:
 614                         if (mode == MODE_I2C_READ) {
 615                                 *read_byte = reply[1];
 616                         }
 617                         return (0/*reply_bytes - 1*/);
 618                 case AUX_I2C_REPLY_NACK:
 619                         DRM_DEBUG_KMS("aux_i2c nack\n");
 620                         return -EREMOTEIO;
 621                 case AUX_I2C_REPLY_DEFER:
 622                         DRM_DEBUG_KMS("aux_i2c defer\n");
 623                         udelay(100);
 624                         break;
 625                 default:
 626                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 627                         return -EREMOTEIO;
 628                 }
 629         }
 630
 631         DRM_ERROR("too many retries, giving up\n");
 632         return -EREMOTEIO;
 633 }
 634
 635 static int
 636 intel_dp_i2c_init(struct intel_dp *intel_dp,
 637                   struct intel_connector *intel_connector, const char *name)
 638 {
 639         int     ret;
 640
 641         DRM_DEBUG_KMS("i2c_init %s\n", name);
 642
 643         ironlake_edp_panel_vdd_on(intel_dp);
 644         ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
 645             intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
 646             &intel_dp->adapter);
 647         ironlake_edp_panel_vdd_off(intel_dp, false);
 648         return ret;
 649 }
 650
 651 bool
 652 intel_dp_compute_config(struct intel_encoder *encoder,
 653                         struct intel_crtc_config *pipe_config)
 654 {
 655         struct drm_device *dev = encoder->base.dev;
 656         struct drm_i915_private *dev_priv = dev->dev_private;
 657         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 658         struct drm_display_mode *mode = &pipe_config->requested_mode;
 659         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 660         struct intel_connector *intel_connector = intel_dp->attached_connector;
 661         int lane_count, clock;
 662         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 663         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 664         int bpp, mode_rate;
 665         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 666         int target_clock, link_avail, link_clock;
 667
 668         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
 669                 pipe_config->has_pch_encoder = true;
 670
 671         pipe_config->has_dp_encoder = true;
 672
 673         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 674                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 675                                        adjusted_mode);
 676                 intel_pch_panel_fitting(dev,
 677                                         intel_connector->panel.fitting_mode,
 678                                         mode, adjusted_mode);
 679         }
 680         /* We need to take the panel's fixed mode into account. */
 681         target_clock = adjusted_mode->clock;
 682
 683         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 684                 return false;
 685
 686         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 687                       "max bw %02x pixel clock %iKHz\n",
 688                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 689
 690         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 691          * bpc in between. */
 692         bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
 693         if (is_edp(intel_dp) && dev_priv->edp.bpp)
 694                 bpp = min_t(int, bpp, dev_priv->edp.bpp);
 695
 696         for (; bpp >= 6*3; bpp -= 2*3) {
 697                 mode_rate = intel_dp_link_required(target_clock, bpp);
 698
 699                 for (clock = 0; clock <= max_clock; clock++) {
 700                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 701                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 702                                 link_avail = intel_dp_max_data_rate(link_clock,
 703                                                                     lane_count);
 704
 705                                 if (mode_rate <= link_avail) {
 706                                         goto found;
 707                                 }
 708                         }
 709                 }
 710         }
 711
 712         return false;
 713
 714 found:
 715         if (intel_dp->color_range_auto) {
 716                 /*
 717                  * See:
 718                  * CEA-861-E - 5.1 Default Encoding Parameters
 719                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 720                  */
 721                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 722                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 723                 else
 724                         intel_dp->color_range = 0;
 725         }
 726
 727         if (intel_dp->color_range)
 728                 pipe_config->limited_color_range = true;
 729
 730         intel_dp->link_bw = bws[clock];
 731         intel_dp->lane_count = lane_count;
 732         adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 733         pipe_config->pipe_bpp = bpp;
 734         pipe_config->pixel_target_clock = target_clock;
 735
 736         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 737                       intel_dp->link_bw, intel_dp->lane_count,
 738                       adjusted_mode->clock, bpp);
 739         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 740                       mode_rate, link_avail);
 741
 742         intel_link_compute_m_n(bpp, lane_count,
 743                                target_clock, adjusted_mode->clock,
 744                                &pipe_config->dp_m_n);
 745
 746         return true;
 747 }
 748
 749 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 750 {
 751         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 752         intel_dp->link_configuration[0] = intel_dp->link_bw;
 753         intel_dp->link_configuration[1] = intel_dp->lane_count;
 754         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 755         /*
 756          * Check for DPCD version > 1.1 and enhanced framing support
 757          */
 758         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 759             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 760                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 761         }
 762 }
 763
 764 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 765 {
 766         struct drm_device *dev = crtc->dev;
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         u32 dpa_ctl;
 769
 770         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 771         dpa_ctl = I915_READ(DP_A);
 772         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 773
 774         if (clock < 200000) {
 775                 /* For a long time we've carried around a ILK-DevA w/a for the
 776                  * 160MHz clock. If we're really unlucky, it's still required.
 777                  */
 778                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 779                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 780         } else {
 781                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 782         }
 783
 784         I915_WRITE(DP_A, dpa_ctl);
 785
 786         POSTING_READ(DP_A);
 787         udelay(500);
 788 }
 789
 790 static void
 791 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 792                   struct drm_display_mode *adjusted_mode)
 793 {
 794         struct drm_device *dev = encoder->dev;
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 797         struct drm_crtc *crtc = encoder->crtc;
 798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 799
 800         /*
 801          * There are four kinds of DP registers:
 802          *
 803          *      IBX PCH
 804          *      SNB CPU
 805          *      IVB CPU
 806          *      CPT PCH
 807          *
 808          * IBX PCH and CPU are the same for almost everything,
 809          * except that the CPU DP PLL is configured in this
 810          * register
 811          *
 812          * CPT PCH is quite different, having many bits moved
 813          * to the TRANS_DP_CTL register instead. That
 814          * configuration happens (oddly) in ironlake_pch_enable
 815          */
 816
 817         /* Preserve the BIOS-computed detected bit. This is
 818          * supposed to be read-only.
 819          */
 820         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 821
 822         /* Handle DP bits in common between all three register formats */
 823         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 824
 825         switch (intel_dp->lane_count) {
 826         case 1:
 827                 intel_dp->DP |= DP_PORT_WIDTH_1;
 828                 break;
 829         case 2:
 830                 intel_dp->DP |= DP_PORT_WIDTH_2;
 831                 break;
 832         case 4:
 833                 intel_dp->DP |= DP_PORT_WIDTH_4;
 834                 break;
 835         }
 836         if (intel_dp->has_audio) {
 837                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 838                                  pipe_name(intel_crtc->pipe));
 839                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 840                 intel_write_eld(encoder, adjusted_mode);
 841         }
 842
 843         intel_dp_init_link_config(intel_dp);
 844
 845         /* Split out the IBX/CPU vs CPT settings */
 846
 847         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 848                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 849                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 850                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 851                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 852                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 853
 854                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 855                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 856
 857                 intel_dp->DP |= intel_crtc->pipe << 29;
 858
 859                 /* don't miss out required setting for eDP */
 860                 if (adjusted_mode->clock < 200000)
 861                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 862                 else
 863                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 864         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 865                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 866                         intel_dp->DP |= intel_dp->color_range;
 867
 868                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 869                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 870                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 871                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 872                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 873
 874                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 875                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 876
 877                 if (intel_crtc->pipe == 1)
 878                         intel_dp->DP |= DP_PIPEB_SELECT;
 879
 880                 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 881                         /* don't miss out required setting for eDP */
 882                         if (adjusted_mode->clock < 200000)
 883                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 884                         else
 885                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 886                 }
 887         } else {
 888                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 889         }
 890
 891         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 892                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 893 }
 894
 895 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 896 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 897
 898 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 899 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 900
 901 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 902 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 903
 904 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 905                                        u32 mask,
 906                                        u32 value)
 907 {
 908         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 909         struct drm_i915_private *dev_priv = dev->dev_private;
 910         u32 pp_stat_reg, pp_ctrl_reg;
 911
 912         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 913         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 914
 915         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 916                         mask, value,
 917                         I915_READ(pp_stat_reg),
 918                         I915_READ(pp_ctrl_reg));
 919
 920         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 921                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 922                                 I915_READ(pp_stat_reg),
 923                                 I915_READ(pp_ctrl_reg));
 924         }
 925 }
 926
 927 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 928 {
 929         DRM_DEBUG_KMS("Wait for panel power on\n");
 930         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 931 }
 932
 933 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 934 {
 935         DRM_DEBUG_KMS("Wait for panel power off time\n");
 936         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 937 }
 938
 939 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 940 {
 941         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 942         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 943 }
 944
 945
 946 /* Read the current pp_control value, unlocking the register if it
 947  * is locked
 948  */
 949
 950 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 951 {
 952         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         u32 control;
 955         u32 pp_ctrl_reg;
 956
 957         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 958         control = I915_READ(pp_ctrl_reg);
 959
 960         control &= ~PANEL_UNLOCK_MASK;
 961         control |= PANEL_UNLOCK_REGS;
 962         return control;
 963 }
 964
 965 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 966 {
 967         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         u32 pp;
 970         u32 pp_stat_reg, pp_ctrl_reg;
 971
 972         if (!is_edp(intel_dp))
 973                 return;
 974         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 975
 976         WARN(intel_dp->want_panel_vdd,
 977              "eDP VDD already requested on\n");
 978
 979         intel_dp->want_panel_vdd = true;
 980
 981         if (ironlake_edp_have_panel_vdd(intel_dp)) {
 982                 DRM_DEBUG_KMS("eDP VDD already on\n");
 983                 return;
 984         }
 985
 986         if (!ironlake_edp_have_panel_power(intel_dp))
 987                 ironlake_wait_panel_power_cycle(intel_dp);
 988
 989         pp = ironlake_get_pp_control(intel_dp);
 990         pp |= EDP_FORCE_VDD;
 991
 992         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 993         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 994
 995         I915_WRITE(pp_ctrl_reg, pp);
 996         POSTING_READ(pp_ctrl_reg);
 997         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 998                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
 999         /*
1000          * If the panel wasn't on, delay before accessing aux channel
1001          */
1002         if (!ironlake_edp_have_panel_power(intel_dp)) {
1003                 DRM_DEBUG_KMS("eDP was not running\n");
1004                 msleep(intel_dp->panel_power_up_delay);
1005         }
1006 }
1007
1008 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1009 {
1010         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012         u32 pp;
1013         u32 pp_stat_reg, pp_ctrl_reg;
1014
1015         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1016
1017         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1018                 pp = ironlake_get_pp_control(intel_dp);
1019                 pp &= ~EDP_FORCE_VDD;
1020
1021                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1022                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1023
1024                 I915_WRITE(pp_ctrl_reg, pp);
1025                 POSTING_READ(pp_ctrl_reg);
1026
1027                 /* Make sure sequencer is idle before allowing subsequent activity */
1028                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1029                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1030                 msleep(intel_dp->panel_power_down_delay);
1031         }
1032 }
1033
1034 static void ironlake_panel_vdd_work(struct work_struct *__work)
1035 {
1036         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1037                                                  struct intel_dp, panel_vdd_work);
1038         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1039
1040         mutex_lock(&dev->mode_config.mutex);
1041         ironlake_panel_vdd_off_sync(intel_dp);
1042         mutex_unlock(&dev->mode_config.mutex);
1043 }
1044
1045 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1046 {
1047         if (!is_edp(intel_dp))
1048                 return;
1049
1050         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1051         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1052
1053         intel_dp->want_panel_vdd = false;
1054
1055         if (sync) {
1056                 ironlake_panel_vdd_off_sync(intel_dp);
1057         } else {
1058                 /*
1059                  * Queue the timer to fire a long
1060                  * time from now (relative to the power down delay)
1061                  * to keep the panel power up across a sequence of operations
1062                  */
1063                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1064                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1065         }
1066 }
1067
1068 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1069 {
1070         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 pp;
1073         u32 pp_ctrl_reg;
1074
1075         if (!is_edp(intel_dp))
1076                 return;
1077
1078         DRM_DEBUG_KMS("Turn eDP power on\n");
1079
1080         if (ironlake_edp_have_panel_power(intel_dp)) {
1081                 DRM_DEBUG_KMS("eDP power already on\n");
1082                 return;
1083         }
1084
1085         ironlake_wait_panel_power_cycle(intel_dp);
1086
1087         pp = ironlake_get_pp_control(intel_dp);
1088         if (IS_GEN5(dev)) {
1089                 /* ILK workaround: disable reset around power sequence */
1090                 pp &= ~PANEL_POWER_RESET;
1091                 I915_WRITE(PCH_PP_CONTROL, pp);
1092                 POSTING_READ(PCH_PP_CONTROL);
1093         }
1094
1095         pp |= POWER_TARGET_ON;
1096         if (!IS_GEN5(dev))
1097                 pp |= PANEL_POWER_RESET;
1098
1099         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1100
1101         I915_WRITE(pp_ctrl_reg, pp);
1102         POSTING_READ(pp_ctrl_reg);
1103
1104         ironlake_wait_panel_on(intel_dp);
1105
1106         if (IS_GEN5(dev)) {
1107                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1108                 I915_WRITE(PCH_PP_CONTROL, pp);
1109                 POSTING_READ(PCH_PP_CONTROL);
1110         }
1111 }
1112
1113 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1114 {
1115         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1116         struct drm_i915_private *dev_priv = dev->dev_private;
1117         u32 pp;
1118         u32 pp_ctrl_reg;
1119
1120         if (!is_edp(intel_dp))
1121                 return;
1122
1123         DRM_DEBUG_KMS("Turn eDP power off\n");
1124
1125         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1126
1127         pp = ironlake_get_pp_control(intel_dp);
1128         /* We need to switch off panel power _and_ force vdd, for otherwise some
1129          * panels get very unhappy and cease to work. */
1130         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1131
1132         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1133
1134         I915_WRITE(pp_ctrl_reg, pp);
1135         POSTING_READ(pp_ctrl_reg);
1136
1137         intel_dp->want_panel_vdd = false;
1138
1139         ironlake_wait_panel_off(intel_dp);
1140 }
1141
1142 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1143 {
1144         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1145         struct drm_device *dev = intel_dig_port->base.base.dev;
1146         struct drm_i915_private *dev_priv = dev->dev_private;
1147         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1148         u32 pp;
1149         u32 pp_ctrl_reg;
1150
1151         if (!is_edp(intel_dp))
1152                 return;
1153
1154         DRM_DEBUG_KMS("\n");
1155         /*
1156          * If we enable the backlight right away following a panel power
1157          * on, we may see slight flicker as the panel syncs with the eDP
1158          * link.  So delay a bit to make sure the image is solid before
1159          * allowing it to appear.
1160          */
1161         msleep(intel_dp->backlight_on_delay);
1162         pp = ironlake_get_pp_control(intel_dp);
1163         pp |= EDP_BLC_ENABLE;
1164
1165         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1166
1167         I915_WRITE(pp_ctrl_reg, pp);
1168         POSTING_READ(pp_ctrl_reg);
1169
1170         intel_panel_enable_backlight(dev, pipe);
1171 }
1172
1173 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1174 {
1175         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1176         struct drm_i915_private *dev_priv = dev->dev_private;
1177         u32 pp;
1178         u32 pp_ctrl_reg;
1179
1180         if (!is_edp(intel_dp))
1181                 return;
1182
1183         intel_panel_disable_backlight(dev);
1184
1185         DRM_DEBUG_KMS("\n");
1186         pp = ironlake_get_pp_control(intel_dp);
1187         pp &= ~EDP_BLC_ENABLE;
1188
1189         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1190
1191         I915_WRITE(pp_ctrl_reg, pp);
1192         POSTING_READ(pp_ctrl_reg);
1193         msleep(intel_dp->backlight_off_delay);
1194 }
1195
1196 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1197 {
1198         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1199         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1200         struct drm_device *dev = crtc->dev;
1201         struct drm_i915_private *dev_priv = dev->dev_private;
1202         u32 dpa_ctl;
1203
1204         assert_pipe_disabled(dev_priv,
1205                              to_intel_crtc(crtc)->pipe);
1206
1207         DRM_DEBUG_KMS("\n");
1208         dpa_ctl = I915_READ(DP_A);
1209         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1210         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1211
1212         /* We don't adjust intel_dp->DP while tearing down the link, to
1213          * facilitate link retraining (e.g. after hotplug). Hence clear all
1214          * enable bits here to ensure that we don't enable too much. */
1215         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1216         intel_dp->DP |= DP_PLL_ENABLE;
1217         I915_WRITE(DP_A, intel_dp->DP);
1218         POSTING_READ(DP_A);
1219         udelay(200);
1220 }
1221
1222 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1223 {
1224         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1225         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1226         struct drm_device *dev = crtc->dev;
1227         struct drm_i915_private *dev_priv = dev->dev_private;
1228         u32 dpa_ctl;
1229
1230         assert_pipe_disabled(dev_priv,
1231                              to_intel_crtc(crtc)->pipe);
1232
1233         dpa_ctl = I915_READ(DP_A);
1234         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1235              "dp pll off, should be on\n");
1236         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1237
1238         /* We can't rely on the value tracked for the DP register in
1239          * intel_dp->DP because link_down must not change that (otherwise link
1240          * re-training will fail. */
1241         dpa_ctl &= ~DP_PLL_ENABLE;
1242         I915_WRITE(DP_A, dpa_ctl);
1243         POSTING_READ(DP_A);
1244         udelay(200);
1245 }
1246
1247 /* If the sink supports it, try to set the power state appropriately */
1248 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1249 {
1250         int ret, i;
1251
1252         /* Should have a valid DPCD by this point */
1253         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1254                 return;
1255
1256         if (mode != DRM_MODE_DPMS_ON) {
1257                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1258                                                   DP_SET_POWER_D3);
1259                 if (ret != 1)
1260                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1261         } else {
1262                 /*
1263                  * When turning on, we need to retry for 1ms to give the sink
1264                  * time to wake up.
1265                  */
1266                 for (i = 0; i < 3; i++) {
1267                         ret = intel_dp_aux_native_write_1(intel_dp,
1268                                                           DP_SET_POWER,
1269                                                           DP_SET_POWER_D0);
1270                         if (ret == 1)
1271                                 break;
1272                         msleep(1);
1273                 }
1274         }
1275 }
1276
1277 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1278                                   enum i915_pipe *pipe)
1279 {
1280         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1281         struct drm_device *dev = encoder->base.dev;
1282         struct drm_i915_private *dev_priv = dev->dev_private;
1283         u32 tmp = I915_READ(intel_dp->output_reg);
1284
1285         if (!(tmp & DP_PORT_EN))
1286                 return false;
1287
1288         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1289                 *pipe = PORT_TO_PIPE_CPT(tmp);
1290         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1291                 *pipe = PORT_TO_PIPE(tmp);
1292         } else {
1293                 u32 trans_sel;
1294                 u32 trans_dp;
1295                 int i;
1296
1297                 switch (intel_dp->output_reg) {
1298                 case PCH_DP_B:
1299                         trans_sel = TRANS_DP_PORT_SEL_B;
1300                         break;
1301                 case PCH_DP_C:
1302                         trans_sel = TRANS_DP_PORT_SEL_C;
1303                         break;
1304                 case PCH_DP_D:
1305                         trans_sel = TRANS_DP_PORT_SEL_D;
1306                         break;
1307                 default:
1308                         return true;
1309                 }
1310
1311                 for_each_pipe(i) {
1312                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1313                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1314                                 *pipe = i;
1315                                 return true;
1316                         }
1317                 }
1318
1319                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1320                               intel_dp->output_reg);
1321         }
1322
1323         return true;
1324 }
1325
1326 static void intel_disable_dp(struct intel_encoder *encoder)
1327 {
1328         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1329
1330         /* Make sure the panel is off before trying to change the mode. But also
1331          * ensure that we have vdd while we switch off the panel. */
1332         ironlake_edp_panel_vdd_on(intel_dp);
1333         ironlake_edp_backlight_off(intel_dp);
1334         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1335         ironlake_edp_panel_off(intel_dp);
1336
1337         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1338         if (!is_cpu_edp(intel_dp))
1339                 intel_dp_link_down(intel_dp);
1340 }
1341
1342 static void intel_post_disable_dp(struct intel_encoder *encoder)
1343 {
1344         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1345         struct drm_device *dev = encoder->base.dev;
1346
1347         if (is_cpu_edp(intel_dp)) {
1348                 intel_dp_link_down(intel_dp);
1349                 if (!IS_VALLEYVIEW(dev))
1350                         ironlake_edp_pll_off(intel_dp);
1351         }
1352 }
1353
1354 static void intel_enable_dp(struct intel_encoder *encoder)
1355 {
1356         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1357         struct drm_device *dev = encoder->base.dev;
1358         struct drm_i915_private *dev_priv = dev->dev_private;
1359         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1360
1361         if (WARN_ON(dp_reg & DP_PORT_EN))
1362                 return;
1363
1364         ironlake_edp_panel_vdd_on(intel_dp);
1365         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1366         intel_dp_start_link_train(intel_dp);
1367         ironlake_edp_panel_on(intel_dp);
1368         ironlake_edp_panel_vdd_off(intel_dp, true);
1369         intel_dp_complete_link_train(intel_dp);
1370         intel_dp_stop_link_train(intel_dp);
1371         ironlake_edp_backlight_on(intel_dp);
1372 }
1373
1374 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1375 {
1376         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1377         struct drm_device *dev = encoder->base.dev;
1378
1379         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1380                 ironlake_edp_pll_on(intel_dp);
1381 }
1382
1383 /*
1384  * Native read with retry for link status and receiver capability reads for
1385  * cases where the sink may still be asleep.
1386  */
1387 static bool
1388 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1389                                uint8_t *recv, int recv_bytes)
1390 {
1391         int ret, i;
1392
1393         /*
1394          * Sinks are *supposed* to come up within 1ms from an off state,
1395          * but we're also supposed to retry 3 times per the spec.
1396          */
1397         for (i = 0; i < 3; i++) {
1398                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1399                                                recv_bytes);
1400                 if (ret == recv_bytes)
1401                         return true;
1402                 msleep(1);
1403         }
1404
1405         return false;
1406 }
1407
1408 /*
1409  * Fetch AUX CH registers 0x202 - 0x207 which contain
1410  * link status information
1411  */
1412 static bool
1413 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1414 {
1415         return intel_dp_aux_native_read_retry(intel_dp,
1416                                               DP_LANE0_1_STATUS,
1417                                               link_status,
1418                                               DP_LINK_STATUS_SIZE);
1419 }
1420
1421 #if 0
1422 static char     *voltage_names[] = {
1423         "0.4V", "0.6V", "0.8V", "1.2V"
1424 };
1425 static char     *pre_emph_names[] = {
1426         "0dB", "3.5dB", "6dB", "9.5dB"
1427 };
1428 static char     *link_train_names[] = {
1429         "pattern 1", "pattern 2", "idle", "off"
1430 };
1431 #endif
1432
1433 /*
1434  * These are source-specific values; current Intel hardware supports
1435  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1436  */
1437
1438 static uint8_t
1439 intel_dp_voltage_max(struct intel_dp *intel_dp)
1440 {
1441         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1442
1443         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1444                 return DP_TRAIN_VOLTAGE_SWING_800;
1445         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1446                 return DP_TRAIN_VOLTAGE_SWING_1200;
1447         else
1448                 return DP_TRAIN_VOLTAGE_SWING_800;
1449 }
1450
1451 static uint8_t
1452 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1453 {
1454         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1455
1456         if (HAS_DDI(dev)) {
1457                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1458                 case DP_TRAIN_VOLTAGE_SWING_400:
1459                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1460                 case DP_TRAIN_VOLTAGE_SWING_600:
1461                         return DP_TRAIN_PRE_EMPHASIS_6;
1462                 case DP_TRAIN_VOLTAGE_SWING_800:
1463                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1464                 case DP_TRAIN_VOLTAGE_SWING_1200:
1465                 default:
1466                         return DP_TRAIN_PRE_EMPHASIS_0;
1467                 }
1468         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1469                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1470                 case DP_TRAIN_VOLTAGE_SWING_400:
1471                         return DP_TRAIN_PRE_EMPHASIS_6;
1472                 case DP_TRAIN_VOLTAGE_SWING_600:
1473                 case DP_TRAIN_VOLTAGE_SWING_800:
1474                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1475                 default:
1476                         return DP_TRAIN_PRE_EMPHASIS_0;
1477                 }
1478         } else {
1479                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1480                 case DP_TRAIN_VOLTAGE_SWING_400:
1481                         return DP_TRAIN_PRE_EMPHASIS_6;
1482                 case DP_TRAIN_VOLTAGE_SWING_600:
1483                         return DP_TRAIN_PRE_EMPHASIS_6;
1484                 case DP_TRAIN_VOLTAGE_SWING_800:
1485                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1486                 case DP_TRAIN_VOLTAGE_SWING_1200:
1487                 default:
1488                         return DP_TRAIN_PRE_EMPHASIS_0;
1489                 }
1490         }
1491 }
1492
1493 static void
1494 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1495 {
1496         uint8_t v = 0;
1497         uint8_t p = 0;
1498         int lane;
1499         uint8_t voltage_max;
1500         uint8_t preemph_max;
1501
1502         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1503                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1504                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1505
1506                 if (this_v > v)
1507                         v = this_v;
1508                 if (this_p > p)
1509                         p = this_p;
1510         }
1511
1512         voltage_max = intel_dp_voltage_max(intel_dp);
1513         if (v >= voltage_max)
1514                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1515
1516         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1517         if (p >= preemph_max)
1518                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1519
1520         for (lane = 0; lane < 4; lane++)
1521                 intel_dp->train_set[lane] = v | p;
1522 }
1523
1524 static uint32_t
1525 intel_gen4_signal_levels(uint8_t train_set)
1526 {
1527         uint32_t        signal_levels = 0;
1528
1529         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1530         case DP_TRAIN_VOLTAGE_SWING_400:
1531         default:
1532                 signal_levels |= DP_VOLTAGE_0_4;
1533                 break;
1534         case DP_TRAIN_VOLTAGE_SWING_600:
1535                 signal_levels |= DP_VOLTAGE_0_6;
1536                 break;
1537         case DP_TRAIN_VOLTAGE_SWING_800:
1538                 signal_levels |= DP_VOLTAGE_0_8;
1539                 break;
1540         case DP_TRAIN_VOLTAGE_SWING_1200:
1541                 signal_levels |= DP_VOLTAGE_1_2;
1542                 break;
1543         }
1544         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1545         case DP_TRAIN_PRE_EMPHASIS_0:
1546         default:
1547                 signal_levels |= DP_PRE_EMPHASIS_0;
1548                 break;
1549         case DP_TRAIN_PRE_EMPHASIS_3_5:
1550                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1551                 break;
1552         case DP_TRAIN_PRE_EMPHASIS_6:
1553                 signal_levels |= DP_PRE_EMPHASIS_6;
1554                 break;
1555         case DP_TRAIN_PRE_EMPHASIS_9_5:
1556                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1557                 break;
1558         }
1559         return signal_levels;
1560 }
1561
1562 /* Gen6's DP voltage swing and pre-emphasis control */
1563 static uint32_t
1564 intel_gen6_edp_signal_levels(uint8_t train_set)
1565 {
1566         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1567                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1568         switch (signal_levels) {
1569         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1570         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1571                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1572         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1573                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1574         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1575         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1576                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1577         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1578         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1579                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1580         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1581         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1582                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1583         default:
1584                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1585                               "0x%x\n", signal_levels);
1586                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1587         }
1588 }
1589
1590 /* Gen7's DP voltage swing and pre-emphasis control */
1591 static uint32_t
1592 intel_gen7_edp_signal_levels(uint8_t train_set)
1593 {
1594         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1595                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1596         switch (signal_levels) {
1597         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1598                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1599         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1600                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1601         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1602                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1603
1604         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1605                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1606         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1607                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1608
1609         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1610                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1611         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1612                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1613
1614         default:
1615                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1616                               "0x%x\n", signal_levels);
1617                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1618         }
1619 }
1620
1621 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1622 static uint32_t
1623 intel_hsw_signal_levels(uint8_t train_set)
1624 {
1625         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1626                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1627         switch (signal_levels) {
1628         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1629                 return DDI_BUF_EMP_400MV_0DB_HSW;
1630         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1631                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1632         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1633                 return DDI_BUF_EMP_400MV_6DB_HSW;
1634         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1635                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1636
1637         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1638                 return DDI_BUF_EMP_600MV_0DB_HSW;
1639         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1640                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1641         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1642                 return DDI_BUF_EMP_600MV_6DB_HSW;
1643
1644         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1645                 return DDI_BUF_EMP_800MV_0DB_HSW;
1646         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1647                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1648         default:
1649                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1650                               "0x%x\n", signal_levels);
1651                 return DDI_BUF_EMP_400MV_0DB_HSW;
1652         }
1653 }
1654
1655 /* Properly updates "DP" with the correct signal levels. */
1656 static void
1657 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1658 {
1659         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1660         struct drm_device *dev = intel_dig_port->base.base.dev;
1661         uint32_t signal_levels, mask;
1662         uint8_t train_set = intel_dp->train_set[0];
1663
1664         if (HAS_DDI(dev)) {
1665                 signal_levels = intel_hsw_signal_levels(train_set);
1666                 mask = DDI_BUF_EMP_MASK;
1667         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1668                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1669                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1670         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1671                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1672                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1673         } else {
1674                 signal_levels = intel_gen4_signal_levels(train_set);
1675                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1676         }
1677
1678         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1679
1680         *DP = (*DP & ~mask) | signal_levels;
1681 }
1682
1683 static bool
1684 intel_dp_set_link_train(struct intel_dp *intel_dp,
1685                         uint32_t dp_reg_value,
1686                         uint8_t dp_train_pat)
1687 {
1688         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1689         struct drm_device *dev = intel_dig_port->base.base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         enum port port = intel_dig_port->port;
1692         int ret;
1693
1694         if (HAS_DDI(dev)) {
1695                 uint32_t temp = I915_READ(DP_TP_CTL(port));
1696
1697                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1698                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1699                 else
1700                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1701
1702                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1703                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1704                 case DP_TRAINING_PATTERN_DISABLE:
1705                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1706
1707                         break;
1708                 case DP_TRAINING_PATTERN_1:
1709                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1710                         break;
1711                 case DP_TRAINING_PATTERN_2:
1712                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1713                         break;
1714                 case DP_TRAINING_PATTERN_3:
1715                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1716                         break;
1717                 }
1718                 I915_WRITE(DP_TP_CTL(port), temp);
1719
1720         } else if (HAS_PCH_CPT(dev) &&
1721                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1722                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1723
1724                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1725                 case DP_TRAINING_PATTERN_DISABLE:
1726                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1727                         break;
1728                 case DP_TRAINING_PATTERN_1:
1729                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1730                         break;
1731                 case DP_TRAINING_PATTERN_2:
1732                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1733                         break;
1734                 case DP_TRAINING_PATTERN_3:
1735                         DRM_ERROR("DP training pattern 3 not supported\n");
1736                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1737                         break;
1738                 }
1739
1740         } else {
1741                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1742
1743                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1744                 case DP_TRAINING_PATTERN_DISABLE:
1745                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1746                         break;
1747                 case DP_TRAINING_PATTERN_1:
1748                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1749                         break;
1750                 case DP_TRAINING_PATTERN_2:
1751                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1752                         break;
1753                 case DP_TRAINING_PATTERN_3:
1754                         DRM_ERROR("DP training pattern 3 not supported\n");
1755                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1756                         break;
1757                 }
1758         }
1759
1760         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1761         POSTING_READ(intel_dp->output_reg);
1762
1763         intel_dp_aux_native_write_1(intel_dp,
1764                                     DP_TRAINING_PATTERN_SET,
1765                                     dp_train_pat);
1766
1767         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1768             DP_TRAINING_PATTERN_DISABLE) {
1769                 ret = intel_dp_aux_native_write(intel_dp,
1770                                                 DP_TRAINING_LANE0_SET,
1771                                                 intel_dp->train_set,
1772                                                 intel_dp->lane_count);
1773                 if (ret != intel_dp->lane_count)
1774                         return false;
1775         }
1776
1777         return true;
1778 }
1779
1780 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1781 {
1782         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1783         struct drm_device *dev = intel_dig_port->base.base.dev;
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785         enum port port = intel_dig_port->port;
1786         uint32_t val;
1787
1788         if (!HAS_DDI(dev))
1789                 return;
1790
1791         val = I915_READ(DP_TP_CTL(port));
1792         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1793         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1794         I915_WRITE(DP_TP_CTL(port), val);
1795
1796         /*
1797          * On PORT_A we can have only eDP in SST mode. There the only reason
1798          * we need to set idle transmission mode is to work around a HW issue
1799          * where we enable the pipe while not in idle link-training mode.
1800          * In this case there is requirement to wait for a minimum number of
1801          * idle patterns to be sent.
1802          */
1803         if (port == PORT_A)
1804                 return;
1805
1806         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
1807                      1))
1808                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1809 }
1810
1811 /* Enable corresponding port and start training pattern 1 */
1812 void
1813 intel_dp_start_link_train(struct intel_dp *intel_dp)
1814 {
1815         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1816         struct drm_device *dev = encoder->dev;
1817         int i;
1818         uint8_t voltage;
1819         bool clock_recovery = false;
1820         int voltage_tries, loop_tries;
1821         uint32_t DP = intel_dp->DP;
1822
1823         if (HAS_DDI(dev))
1824                 intel_ddi_prepare_link_retrain(encoder);
1825
1826         /* Write the link configuration data */
1827         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1828                                   intel_dp->link_configuration,
1829                                   DP_LINK_CONFIGURATION_SIZE);
1830
1831         DP |= DP_PORT_EN;
1832
1833         memset(intel_dp->train_set, 0, 4);
1834         voltage = 0xff;
1835         voltage_tries = 0;
1836         loop_tries = 0;
1837         clock_recovery = false;
1838         for (;;) {
1839                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1840                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1841
1842                 intel_dp_set_signal_levels(intel_dp, &DP);
1843
1844                 /* Set training pattern 1 */
1845                 if (!intel_dp_set_link_train(intel_dp, DP,
1846                                              DP_TRAINING_PATTERN_1 |
1847                                              DP_LINK_SCRAMBLING_DISABLE))
1848                         break;
1849
1850                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1851                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1852                         DRM_ERROR("failed to get link status\n");
1853                         break;
1854                 }
1855
1856                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1857                         DRM_DEBUG_KMS("clock recovery OK\n");
1858                         clock_recovery = true;
1859                         break;
1860                 }
1861
1862                 /* Check to see if we've tried the max voltage */
1863                 for (i = 0; i < intel_dp->lane_count; i++)
1864                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1865                                 break;
1866                 if (i == intel_dp->lane_count) {
1867                         ++loop_tries;
1868                         if (loop_tries == 5) {
1869                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1870                                 break;
1871                         }
1872                         memset(intel_dp->train_set, 0, 4);
1873                         voltage_tries = 0;
1874                         continue;
1875                 }
1876
1877                 /* Check to see if we've tried the same voltage 5 times */
1878                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1879                         ++voltage_tries;
1880                         if (voltage_tries == 5) {
1881                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1882                                 break;
1883                         }
1884                 } else
1885                         voltage_tries = 0;
1886                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1887
1888                 /* Compute new intel_dp->train_set as requested by target */
1889                 intel_get_adjust_train(intel_dp, link_status);
1890         }
1891
1892         intel_dp->DP = DP;
1893 }
1894
1895 void
1896 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1897 {
1898         bool channel_eq = false;
1899         int tries, cr_tries;
1900         uint32_t DP = intel_dp->DP;
1901
1902         /* channel equalization */
1903         tries = 0;
1904         cr_tries = 0;
1905         channel_eq = false;
1906         for (;;) {
1907                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1908
1909                 if (cr_tries > 5) {
1910                         DRM_ERROR("failed to train DP, aborting\n");
1911                         intel_dp_link_down(intel_dp);
1912                         break;
1913                 }
1914
1915                 intel_dp_set_signal_levels(intel_dp, &DP);
1916
1917                 /* channel eq pattern */
1918                 if (!intel_dp_set_link_train(intel_dp, DP,
1919                                              DP_TRAINING_PATTERN_2 |
1920                                              DP_LINK_SCRAMBLING_DISABLE))
1921                         break;
1922
1923                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1924                 if (!intel_dp_get_link_status(intel_dp, link_status))
1925                         break;
1926
1927                 /* Make sure clock is still ok */
1928                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1929                         intel_dp_start_link_train(intel_dp);
1930                         cr_tries++;
1931                         continue;
1932                 }
1933
1934                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1935                         channel_eq = true;
1936                         break;
1937                 }
1938
1939                 /* Try 5 times, then try clock recovery if that fails */
1940                 if (tries > 5) {
1941                         intel_dp_link_down(intel_dp);
1942                         intel_dp_start_link_train(intel_dp);
1943                         tries = 0;
1944                         cr_tries++;
1945                         continue;
1946                 }
1947
1948                 /* Compute new intel_dp->train_set as requested by target */
1949                 intel_get_adjust_train(intel_dp, link_status);
1950                 ++tries;
1951         }
1952
1953         intel_dp_set_idle_link_train(intel_dp);
1954
1955         intel_dp->DP = DP;
1956
1957         if (channel_eq)
1958                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
1959
1960 }
1961
1962 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
1963 {
1964         intel_dp_set_link_train(intel_dp, intel_dp->DP,
1965                                 DP_TRAINING_PATTERN_DISABLE);
1966 }
1967
1968 static void
1969 intel_dp_link_down(struct intel_dp *intel_dp)
1970 {
1971         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1972         struct drm_device *dev = intel_dig_port->base.base.dev;
1973         struct drm_i915_private *dev_priv = dev->dev_private;
1974         struct intel_crtc *intel_crtc =
1975                 to_intel_crtc(intel_dig_port->base.base.crtc);
1976         uint32_t DP = intel_dp->DP;
1977
1978         /*
1979          * DDI code has a strict mode set sequence and we should try to respect
1980          * it, otherwise we might hang the machine in many different ways. So we
1981          * really should be disabling the port only on a complete crtc_disable
1982          * sequence. This function is just called under two conditions on DDI
1983          * code:
1984          * - Link train failed while doing crtc_enable, and on this case we
1985          *   really should respect the mode set sequence and wait for a
1986          *   crtc_disable.
1987          * - Someone turned the monitor off and intel_dp_check_link_status
1988          *   called us. We don't need to disable the whole port on this case, so
1989          *   when someone turns the monitor on again,
1990          *   intel_ddi_prepare_link_retrain will take care of redoing the link
1991          *   train.
1992          */
1993         if (HAS_DDI(dev))
1994                 return;
1995
1996         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1997                 return;
1998
1999         DRM_DEBUG_KMS("\n");
2000
2001         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2002                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2003                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2004         } else {
2005                 DP &= ~DP_LINK_TRAIN_MASK;
2006                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2007         }
2008         POSTING_READ(intel_dp->output_reg);
2009
2010         /* We don't really know why we're doing this */
2011         intel_wait_for_vblank(dev, intel_crtc->pipe);
2012
2013         if (HAS_PCH_IBX(dev) &&
2014             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2015                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2016
2017                 /* Hardware workaround: leaving our transcoder select
2018                  * set to transcoder B while it's off will prevent the
2019                  * corresponding HDMI output on transcoder A.
2020                  *
2021                  * Combine this with another hardware workaround:
2022                  * transcoder select bit can only be cleared while the
2023                  * port is enabled.
2024                  */
2025                 DP &= ~DP_PIPEB_SELECT;
2026                 I915_WRITE(intel_dp->output_reg, DP);
2027
2028                 /* Changes to enable or select take place the vblank
2029                  * after being written.
2030                  */
2031                 if (WARN_ON(crtc == NULL)) {
2032                         /* We should never try to disable a port without a crtc
2033                          * attached. For paranoia keep the code around for a
2034                          * bit. */
2035                         POSTING_READ(intel_dp->output_reg);
2036                         msleep(50);
2037                 } else
2038                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2039         }
2040
2041         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2042         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2043         POSTING_READ(intel_dp->output_reg);
2044         msleep(intel_dp->panel_power_down_delay);
2045 }
2046
2047 static bool
2048 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2049 {
2050         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2051
2052         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2053                                            sizeof(intel_dp->dpcd)) == 0)
2054                 return false; /* aux transfer failed */
2055
2056         ksnprintf(dpcd_hex_dump,
2057                   sizeof(dpcd_hex_dump),
2058                   "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2059                   intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2060                   intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2061                   intel_dp->dpcd[6], intel_dp->dpcd[7]);
2062         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2063
2064         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2065                 return false; /* DPCD not present */
2066
2067         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2068               DP_DWN_STRM_PORT_PRESENT))
2069                 return true; /* native DP sink */
2070
2071         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2072                 return true; /* no per-port downstream info */
2073
2074         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2075                                            intel_dp->downstream_ports,
2076                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2077                 return false; /* downstream port status fetch failed */
2078
2079         return true;
2080 }
2081
2082 static void
2083 intel_dp_probe_oui(struct intel_dp *intel_dp)
2084 {
2085         u8 buf[3];
2086
2087         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2088                 return;
2089
2090         ironlake_edp_panel_vdd_on(intel_dp);
2091
2092         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2093                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2094                               buf[0], buf[1], buf[2]);
2095
2096         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2097                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2098                               buf[0], buf[1], buf[2]);
2099
2100         ironlake_edp_panel_vdd_off(intel_dp, false);
2101 }
2102
2103 static bool
2104 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2105 {
2106         int ret;
2107
2108         ret = intel_dp_aux_native_read_retry(intel_dp,
2109                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2110                                              sink_irq_vector, 1);
2111         if (!ret)
2112                 return false;
2113
2114         return true;
2115 }
2116
2117 static void
2118 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2119 {
2120         /* NAK by default */
2121         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2122 }
2123
2124 /*
2125  * According to DP spec
2126  * 5.1.2:
2127  *  1. Read DPCD
2128  *  2. Configure link according to Receiver Capabilities
2129  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2130  *  4. Check link status on receipt of hot-plug interrupt
2131  */
2132
2133 void
2134 intel_dp_check_link_status(struct intel_dp *intel_dp)
2135 {
2136         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2137         u8 sink_irq_vector;
2138         u8 link_status[DP_LINK_STATUS_SIZE];
2139
2140         if (!intel_encoder->connectors_active)
2141                 return;
2142
2143         if (WARN_ON(!intel_encoder->base.crtc))
2144                 return;
2145
2146         /* Try to read receiver status if the link appears to be up */
2147         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2148                 intel_dp_link_down(intel_dp);
2149                 return;
2150         }
2151
2152         /* Now read the DPCD to see if it's actually running */
2153         if (!intel_dp_get_dpcd(intel_dp)) {
2154                 intel_dp_link_down(intel_dp);
2155                 return;
2156         }
2157
2158         /* Try to read the source of the interrupt */
2159         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2160             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2161                 /* Clear interrupt source */
2162                 intel_dp_aux_native_write_1(intel_dp,
2163                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2164                                             sink_irq_vector);
2165
2166                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2167                         intel_dp_handle_test_request(intel_dp);
2168                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2169                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2170         }
2171
2172         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2173                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2174                               drm_get_encoder_name(&intel_encoder->base));
2175                 intel_dp_start_link_train(intel_dp);
2176                 intel_dp_complete_link_train(intel_dp);
2177                 intel_dp_stop_link_train(intel_dp);
2178         }
2179 }
2180
2181 /* XXX this is probably wrong for multiple downstream ports */
2182 static enum drm_connector_status
2183 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2184 {
2185         uint8_t *dpcd = intel_dp->dpcd;
2186         bool hpd;
2187         uint8_t type;
2188
2189         if (!intel_dp_get_dpcd(intel_dp))
2190                 return connector_status_disconnected;
2191
2192         /* if there's no downstream port, we're done */
2193         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2194                 return connector_status_connected;
2195
2196         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2197         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2198         if (hpd) {
2199                 uint8_t reg;
2200                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2201                                                     &reg, 1))
2202                         return connector_status_unknown;
2203                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2204                                               : connector_status_disconnected;
2205         }
2206
2207         /* If no HPD, poke DDC gently */
2208         if (drm_probe_ddc(intel_dp->adapter))
2209                 return connector_status_connected;
2210
2211         /* Well we tried, say unknown for unreliable port types */
2212         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2213         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2214                 return connector_status_unknown;
2215
2216         /* Anything else is out of spec, warn and ignore */
2217         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2218         return connector_status_disconnected;
2219 }
2220
2221 static enum drm_connector_status
2222 ironlake_dp_detect(struct intel_dp *intel_dp)
2223 {
2224         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2225         struct drm_i915_private *dev_priv = dev->dev_private;
2226         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2227         enum drm_connector_status status;
2228
2229         /* Can't disconnect eDP, but you can close the lid... */
2230         if (is_edp(intel_dp)) {
2231                 status = intel_panel_detect(dev);
2232                 if (status == connector_status_unknown)
2233                         status = connector_status_connected;
2234                 return status;
2235         }
2236
2237         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2238                 return connector_status_disconnected;
2239
2240         return intel_dp_detect_dpcd(intel_dp);
2241 }
2242
2243 static enum drm_connector_status
2244 g4x_dp_detect(struct intel_dp *intel_dp)
2245 {
2246         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2247         struct drm_i915_private *dev_priv = dev->dev_private;
2248         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2249         uint32_t bit;
2250
2251         /* Can't disconnect eDP, but you can close the lid... */
2252         if (is_edp(intel_dp)) {
2253                 enum drm_connector_status status;
2254
2255                 status = intel_panel_detect(dev);
2256                 if (status == connector_status_unknown)
2257                         status = connector_status_connected;
2258                 return status;
2259         }
2260
2261         switch (intel_dig_port->port) {
2262         case PORT_B:
2263                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2264                 break;
2265         case PORT_C:
2266                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2267                 break;
2268         case PORT_D:
2269                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2270                 break;
2271         default:
2272                 return connector_status_unknown;
2273         }
2274
2275         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2276                 return connector_status_disconnected;
2277
2278         return intel_dp_detect_dpcd(intel_dp);
2279 }
2280
2281 static struct edid *
2282 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
2283 {
2284         struct intel_connector *intel_connector = to_intel_connector(connector);
2285
2286         /* use cached edid if we have one */
2287         if (intel_connector->edid) {
2288                 struct edid *edid;
2289                 int size;
2290
2291                 /* invalid edid */
2292                 if (IS_ERR(intel_connector->edid))
2293                         return NULL;
2294
2295                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2296                 edid = kmalloc(size, M_DRM, M_WAITOK);
2297                 if (!edid)
2298                         return NULL;
2299
2300                 memcpy(edid, intel_connector->edid, size);
2301                 return edid;
2302         }
2303
2304         return drm_get_edid(connector, adapter);
2305 }
2306
2307 static int
2308 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
2309 {
2310         struct intel_connector *intel_connector = to_intel_connector(connector);
2311
2312         /* use cached edid if we have one */
2313         if (intel_connector->edid) {
2314                 /* invalid edid */
2315                 if (IS_ERR(intel_connector->edid))
2316                         return 0;
2317
2318                 return intel_connector_update_modes(connector,
2319                                                     intel_connector->edid);
2320         }
2321
2322         return intel_ddc_get_modes(connector, adapter);
2323 }
2324
2325 static enum drm_connector_status
2326 intel_dp_detect(struct drm_connector *connector, bool force)
2327 {
2328         struct intel_dp *intel_dp = intel_attached_dp(connector);
2329         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2330         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2331         struct drm_device *dev = connector->dev;
2332         enum drm_connector_status status;
2333         struct edid *edid = NULL;
2334
2335         intel_dp->has_audio = false;
2336
2337         if (HAS_PCH_SPLIT(dev))
2338                 status = ironlake_dp_detect(intel_dp);
2339         else
2340                 status = g4x_dp_detect(intel_dp);
2341
2342         if (status != connector_status_connected)
2343                 return status;
2344
2345         intel_dp_probe_oui(intel_dp);
2346
2347         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2348                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2349         } else {
2350                 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2351                 if (edid) {
2352                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2353                         kfree(edid);
2354                 }
2355         }
2356
2357         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2358                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2359         return connector_status_connected;
2360 }
2361
2362 static int intel_dp_get_modes(struct drm_connector *connector)
2363 {
2364         struct intel_dp *intel_dp = intel_attached_dp(connector);
2365         struct intel_connector *intel_connector = to_intel_connector(connector);
2366         struct drm_device *dev = connector->dev;
2367         int ret;
2368
2369         /* We should parse the EDID data and find out if it has an audio sink
2370          */
2371
2372         ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
2373         if (ret)
2374                 return ret;
2375
2376         /* if eDP has no EDID, fall back to fixed mode */
2377         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2378                 struct drm_display_mode *mode;
2379                 mode = drm_mode_duplicate(dev,
2380                                           intel_connector->panel.fixed_mode);
2381                 if (mode) {
2382                         drm_mode_probed_add(connector, mode);
2383                         return 1;
2384                 }
2385         }
2386         return 0;
2387 }
2388
2389 static bool
2390 intel_dp_detect_audio(struct drm_connector *connector)
2391 {
2392         struct intel_dp *intel_dp = intel_attached_dp(connector);
2393         struct edid *edid;
2394         bool has_audio = false;
2395
2396         edid = intel_dp_get_edid(connector, intel_dp->adapter);
2397         if (edid) {
2398                 has_audio = drm_detect_monitor_audio(edid);
2399                 kfree(edid);
2400         }
2401
2402         return has_audio;
2403 }
2404
2405 static int
2406 intel_dp_set_property(struct drm_connector *connector,
2407                       struct drm_property *property,
2408                       uint64_t val)
2409 {
2410         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2411         struct intel_connector *intel_connector = to_intel_connector(connector);
2412         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2413         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2414         int ret;
2415
2416         ret = drm_object_property_set_value(&connector->base, property, val);
2417         if (ret)
2418                 return ret;
2419
2420         if (property == dev_priv->force_audio_property) {
2421                 int i = val;
2422                 bool has_audio;
2423
2424                 if (i == intel_dp->force_audio)
2425                         return 0;
2426
2427                 intel_dp->force_audio = i;
2428
2429                 if (i == HDMI_AUDIO_AUTO)
2430                         has_audio = intel_dp_detect_audio(connector);
2431                 else
2432                         has_audio = (i == HDMI_AUDIO_ON);
2433
2434                 if (has_audio == intel_dp->has_audio)
2435                         return 0;
2436
2437                 intel_dp->has_audio = has_audio;
2438                 goto done;
2439         }
2440
2441         if (property == dev_priv->broadcast_rgb_property) {
2442                 bool old_auto = intel_dp->color_range_auto;
2443                 uint32_t old_range = intel_dp->color_range;
2444
2445                 switch (val) {
2446                 case INTEL_BROADCAST_RGB_AUTO:
2447                         intel_dp->color_range_auto = true;
2448                         break;
2449                 case INTEL_BROADCAST_RGB_FULL:
2450                         intel_dp->color_range_auto = false;
2451                         intel_dp->color_range = 0;
2452                         break;
2453                 case INTEL_BROADCAST_RGB_LIMITED:
2454                         intel_dp->color_range_auto = false;
2455                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2456                         break;
2457                 default:
2458                         return -EINVAL;
2459                 }
2460
2461                 if (old_auto == intel_dp->color_range_auto &&
2462                     old_range == intel_dp->color_range)
2463                         return 0;
2464
2465                 goto done;
2466         }
2467
2468         if (is_edp(intel_dp) &&
2469             property == connector->dev->mode_config.scaling_mode_property) {
2470                 if (val == DRM_MODE_SCALE_NONE) {
2471                         DRM_DEBUG_KMS("no scaling not supported\n");
2472                         return -EINVAL;
2473                 }
2474
2475                 if (intel_connector->panel.fitting_mode == val) {
2476                         /* the eDP scaling property is not changed */
2477                         return 0;
2478                 }
2479                 intel_connector->panel.fitting_mode = val;
2480
2481                 goto done;
2482         }
2483
2484         return -EINVAL;
2485
2486 done:
2487         if (intel_encoder->base.crtc)
2488                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2489
2490         return 0;
2491 }
2492
2493 static void
2494 intel_dp_destroy(struct drm_connector *connector)
2495 {
2496         struct intel_dp *intel_dp = intel_attached_dp(connector);
2497         struct intel_connector *intel_connector = to_intel_connector(connector);
2498
2499         if (!IS_ERR_OR_NULL(intel_connector->edid))
2500                 kfree(intel_connector->edid);
2501
2502         if (is_edp(intel_dp))
2503                 intel_panel_fini(&intel_connector->panel);
2504
2505 #if 0
2506         drm_sysfs_connector_remove(connector);
2507 #endif
2508         drm_connector_cleanup(connector);
2509         kfree(connector);
2510 }
2511
2512 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2513 {
2514         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2515         struct intel_dp *intel_dp = &intel_dig_port->dp;
2516         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2517
2518         if (intel_dp->dp_iic_bus != NULL) {
2519                 if (intel_dp->adapter != NULL) {
2520                         device_delete_child(intel_dp->dp_iic_bus,
2521                             intel_dp->adapter);
2522                 }
2523                 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
2524         }
2525         drm_encoder_cleanup(encoder);
2526         if (is_edp(intel_dp)) {
2527                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2528                 mutex_lock(&dev->mode_config.mutex);
2529                 ironlake_panel_vdd_off_sync(intel_dp);
2530                 mutex_unlock(&dev->mode_config.mutex);
2531         }
2532         kfree(intel_dig_port);
2533 }
2534
2535 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2536         .mode_set = intel_dp_mode_set,
2537 };
2538
2539 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2540         .dpms = intel_connector_dpms,
2541         .detect = intel_dp_detect,
2542         .fill_modes = drm_helper_probe_single_connector_modes,
2543         .set_property = intel_dp_set_property,
2544         .destroy = intel_dp_destroy,
2545 };
2546
2547 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2548         .get_modes = intel_dp_get_modes,
2549         .mode_valid = intel_dp_mode_valid,
2550         .best_encoder = intel_best_encoder,
2551 };
2552
2553 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2554         .destroy = intel_dp_encoder_destroy,
2555 };
2556
2557 static void
2558 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2559 {
2560         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2561
2562         intel_dp_check_link_status(intel_dp);
2563 }
2564
2565 /* Return which DP Port should be selected for Transcoder DP control */
2566 int
2567 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2568 {
2569         struct drm_device *dev = crtc->dev;
2570         struct intel_encoder *intel_encoder;
2571         struct intel_dp *intel_dp;
2572
2573         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2574                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2575
2576                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2577                     intel_encoder->type == INTEL_OUTPUT_EDP)
2578                         return intel_dp->output_reg;
2579         }
2580
2581         return -1;
2582 }
2583
2584 /* check the VBT to see whether the eDP is on DP-D port */
2585 bool intel_dpd_is_edp(struct drm_device *dev)
2586 {
2587         struct drm_i915_private *dev_priv = dev->dev_private;
2588         struct child_device_config *p_child;
2589         int i;
2590
2591         if (!dev_priv->child_dev_num)
2592                 return false;
2593
2594         for (i = 0; i < dev_priv->child_dev_num; i++) {
2595                 p_child = dev_priv->child_dev + i;
2596
2597                 if (p_child->dvo_port == PORT_IDPD &&
2598                     p_child->device_type == DEVICE_TYPE_eDP)
2599                         return true;
2600         }
2601         return false;
2602 }
2603
2604 static void
2605 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2606 {
2607         struct intel_connector *intel_connector = to_intel_connector(connector);
2608
2609         intel_attach_force_audio_property(connector);
2610         intel_attach_broadcast_rgb_property(connector);
2611         intel_dp->color_range_auto = true;
2612
2613         if (is_edp(intel_dp)) {
2614                 drm_mode_create_scaling_mode_property(connector->dev);
2615                 drm_object_attach_property(
2616                         &connector->base,
2617                         connector->dev->mode_config.scaling_mode_property,
2618                         DRM_MODE_SCALE_ASPECT);
2619                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2620         }
2621 }
2622
2623 static void
2624 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2625                                     struct intel_dp *intel_dp,
2626                                     struct edp_power_seq *out)
2627 {
2628         struct drm_i915_private *dev_priv = dev->dev_private;
2629         struct edp_power_seq cur, vbt, spec, final;
2630         u32 pp_on, pp_off, pp_div, pp;
2631         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2632
2633         if (HAS_PCH_SPLIT(dev)) {
2634                 pp_control_reg = PCH_PP_CONTROL;
2635                 pp_on_reg = PCH_PP_ON_DELAYS;
2636                 pp_off_reg = PCH_PP_OFF_DELAYS;
2637                 pp_div_reg = PCH_PP_DIVISOR;
2638         } else {
2639                 pp_control_reg = PIPEA_PP_CONTROL;
2640                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2641                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2642                 pp_div_reg = PIPEA_PP_DIVISOR;
2643         }
2644
2645         /* Workaround: Need to write PP_CONTROL with the unlock key as
2646          * the very first thing. */
2647         pp = ironlake_get_pp_control(intel_dp);
2648         I915_WRITE(pp_control_reg, pp);
2649
2650         pp_on = I915_READ(pp_on_reg);
2651         pp_off = I915_READ(pp_off_reg);
2652         pp_div = I915_READ(pp_div_reg);
2653
2654         /* Pull timing values out of registers */
2655         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2656                 PANEL_POWER_UP_DELAY_SHIFT;
2657
2658         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2659                 PANEL_LIGHT_ON_DELAY_SHIFT;
2660
2661         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2662                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2663
2664         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2665                 PANEL_POWER_DOWN_DELAY_SHIFT;
2666
2667         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2668                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2669
2670         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2671                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2672
2673         vbt = dev_priv->edp.pps;
2674
2675         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2676          * our hw here, which are all in 100usec. */
2677         spec.t1_t3 = 210 * 10;
2678         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2679         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2680         spec.t10 = 500 * 10;
2681         /* This one is special and actually in units of 100ms, but zero
2682          * based in the hw (so we need to add 100 ms). But the sw vbt
2683          * table multiplies it with 1000 to make it in units of 100usec,
2684          * too. */
2685         spec.t11_t12 = (510 + 100) * 10;
2686
2687         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2688                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2689
2690         /* Use the max of the register settings and vbt. If both are
2691          * unset, fall back to the spec limits. */
2692 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2693                                        spec.field : \
2694                                        max(cur.field, vbt.field))
2695         assign_final(t1_t3);
2696         assign_final(t8);
2697         assign_final(t9);
2698         assign_final(t10);
2699         assign_final(t11_t12);
2700 #undef assign_final
2701
2702 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2703         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2704         intel_dp->backlight_on_delay = get_delay(t8);
2705         intel_dp->backlight_off_delay = get_delay(t9);
2706         intel_dp->panel_power_down_delay = get_delay(t10);
2707         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2708 #undef get_delay
2709
2710         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2711                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2712                       intel_dp->panel_power_cycle_delay);
2713
2714         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2715                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2716
2717         if (out)
2718                 *out = final;
2719 }
2720
2721 static void
2722 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2723                                               struct intel_dp *intel_dp,
2724                                               struct edp_power_seq *seq)
2725 {
2726         struct drm_i915_private *dev_priv = dev->dev_private;
2727         u32 pp_on, pp_off, pp_div, port_sel = 0;
2728         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2729         int pp_on_reg, pp_off_reg, pp_div_reg;
2730
2731         if (HAS_PCH_SPLIT(dev)) {
2732                 pp_on_reg = PCH_PP_ON_DELAYS;
2733                 pp_off_reg = PCH_PP_OFF_DELAYS;
2734                 pp_div_reg = PCH_PP_DIVISOR;
2735         } else {
2736                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2737                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2738                 pp_div_reg = PIPEA_PP_DIVISOR;
2739         }
2740
2741         if (IS_VALLEYVIEW(dev))
2742                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2743
2744         /* And finally store the new values in the power sequencer. */
2745         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2746                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2747         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2748                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2749         /* Compute the divisor for the pp clock, simply match the Bspec
2750          * formula. */
2751         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2752         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2753                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2754
2755         /* Haswell doesn't have any port selection bits for the panel
2756          * power sequencer any more. */
2757         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2758                 if (is_cpu_edp(intel_dp))
2759                         port_sel = PANEL_POWER_PORT_DP_A;
2760                 else
2761                         port_sel = PANEL_POWER_PORT_DP_D;
2762         }
2763
2764         pp_on |= port_sel;
2765
2766         I915_WRITE(pp_on_reg, pp_on);
2767         I915_WRITE(pp_off_reg, pp_off);
2768         I915_WRITE(pp_div_reg, pp_div);
2769
2770         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2771                       I915_READ(pp_on_reg),
2772                       I915_READ(pp_off_reg),
2773                       I915_READ(pp_div_reg));
2774 }
2775
2776 void
2777 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2778                         struct intel_connector *intel_connector)
2779 {
2780         struct drm_connector *connector = &intel_connector->base;
2781         struct intel_dp *intel_dp = &intel_dig_port->dp;
2782         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2783         struct drm_device *dev = intel_encoder->base.dev;
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct drm_display_mode *fixed_mode = NULL;
2786         struct edp_power_seq power_seq = { 0 };
2787         enum port port = intel_dig_port->port;
2788         const char *name = NULL;
2789         int type;
2790
2791         /* Preserve the current hw state. */
2792         intel_dp->DP = I915_READ(intel_dp->output_reg);
2793         intel_dp->attached_connector = intel_connector;
2794
2795         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2796                 if (intel_dpd_is_edp(dev))
2797                         intel_dp->is_pch_edp = true;
2798
2799         /*
2800          * FIXME : We need to initialize built-in panels before external panels.
2801          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2802          */
2803         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2804                 type = DRM_MODE_CONNECTOR_eDP;
2805                 intel_encoder->type = INTEL_OUTPUT_EDP;
2806         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2807                 type = DRM_MODE_CONNECTOR_eDP;
2808                 intel_encoder->type = INTEL_OUTPUT_EDP;
2809         } else {
2810                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2811                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2812                  * rewrite it.
2813                  */
2814                 type = DRM_MODE_CONNECTOR_DisplayPort;
2815         }
2816
2817         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2818         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2819
2820         connector->interlace_allowed = true;
2821         connector->doublescan_allowed = 0;
2822
2823         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2824                           ironlake_panel_vdd_work);
2825
2826         intel_connector_attach_encoder(intel_connector, intel_encoder);
2827 #if 0
2828         drm_sysfs_connector_add(connector);
2829 #endif
2830
2831         if (HAS_DDI(dev))
2832                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2833         else
2834                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2835
2836         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2837         if (HAS_DDI(dev)) {
2838                 switch (intel_dig_port->port) {
2839                 case PORT_A:
2840                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2841                         break;
2842                 case PORT_B:
2843                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2844                         break;
2845                 case PORT_C:
2846                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2847                         break;
2848                 case PORT_D:
2849                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2850                         break;
2851                 default:
2852                         BUG();
2853                 }
2854         }
2855
2856         /* Set up the DDC bus. */
2857         switch (port) {
2858         case PORT_A:
2859                 intel_encoder->hpd_pin = HPD_PORT_A;
2860                 name = "DPDDC-A";
2861                 break;
2862         case PORT_B:
2863                 intel_encoder->hpd_pin = HPD_PORT_B;
2864                 name = "DPDDC-B";
2865                 break;
2866         case PORT_C:
2867                 intel_encoder->hpd_pin = HPD_PORT_C;
2868                 name = "DPDDC-C";
2869                 break;
2870         case PORT_D:
2871                 intel_encoder->hpd_pin = HPD_PORT_D;
2872                 name = "DPDDC-D";
2873                 break;
2874         default:
2875                 BUG();
2876         }
2877
2878         if (is_edp(intel_dp))
2879                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2880
2881         intel_dp_i2c_init(intel_dp, intel_connector, name);
2882
2883         /* Cache DPCD and EDID for edp. */
2884         if (is_edp(intel_dp)) {
2885                 bool ret;
2886                 struct drm_display_mode *scan;
2887                 struct edid *edid;
2888
2889                 ironlake_edp_panel_vdd_on(intel_dp);
2890                 ret = intel_dp_get_dpcd(intel_dp);
2891                 ironlake_edp_panel_vdd_off(intel_dp, false);
2892
2893                 if (ret) {
2894                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2895                                 dev_priv->no_aux_handshake =
2896                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2897                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2898                 } else {
2899                         /* if this fails, presume the device is a ghost */
2900                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2901                         intel_dp_encoder_destroy(&intel_encoder->base);
2902                         intel_dp_destroy(connector);
2903                         return;
2904                 }
2905
2906                 /* We now know it's not a ghost, init power sequence regs. */
2907                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2908                                                               &power_seq);
2909
2910                 ironlake_edp_panel_vdd_on(intel_dp);
2911                 edid = drm_get_edid(connector, intel_dp->adapter);
2912                 if (edid) {
2913                         if (drm_add_edid_modes(connector, edid)) {
2914                                 drm_mode_connector_update_edid_property(connector, edid);
2915                                 drm_edid_to_eld(connector, edid);
2916                         } else {
2917                                 kfree(edid);
2918                                 edid = ERR_PTR(-EINVAL);
2919                         }
2920                 } else {
2921                         edid = ERR_PTR(-ENOENT);
2922                 }
2923                 intel_connector->edid = edid;
2924
2925                 /* prefer fixed mode from EDID if available */
2926                 list_for_each_entry(scan, &connector->probed_modes, head) {
2927                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2928                                 fixed_mode = drm_mode_duplicate(dev, scan);
2929                                 break;
2930                         }
2931                 }
2932
2933                 /* fallback to VBT if available for eDP */
2934                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2935                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2936                         if (fixed_mode)
2937                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2938                 }
2939
2940                 ironlake_edp_panel_vdd_off(intel_dp, false);
2941         }
2942
2943         if (is_edp(intel_dp)) {
2944                 intel_panel_init(&intel_connector->panel, fixed_mode);
2945                 intel_panel_setup_backlight(connector);
2946         }
2947
2948         intel_dp_add_properties(intel_dp, connector);
2949
2950         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2951          * 0xd.  Failure to do so will result in spurious interrupts being
2952          * generated on the port when a cable is not attached.
2953          */
2954         if (IS_G4X(dev) && !IS_GM45(dev)) {
2955                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2956                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2957         }
2958 }
2959
2960 void
2961 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2962 {
2963         struct intel_digital_port *intel_dig_port;
2964         struct intel_encoder *intel_encoder;
2965         struct drm_encoder *encoder;
2966         struct intel_connector *intel_connector;
2967
2968         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2969         if (!intel_dig_port)
2970                 return;
2971
2972         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2973         if (!intel_connector) {
2974                 kfree(intel_dig_port);
2975                 return;
2976         }
2977
2978         intel_encoder = &intel_dig_port->base;
2979         encoder = &intel_encoder->base;
2980
2981         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2982                          DRM_MODE_ENCODER_TMDS);
2983         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2984
2985         intel_encoder->compute_config = intel_dp_compute_config;
2986         intel_encoder->enable = intel_enable_dp;
2987         intel_encoder->pre_enable = intel_pre_enable_dp;
2988         intel_encoder->disable = intel_disable_dp;
2989         intel_encoder->post_disable = intel_post_disable_dp;
2990         intel_encoder->get_hw_state = intel_dp_get_hw_state;
2991
2992         intel_dig_port->port = port;
2993         intel_dig_port->dp.output_reg = output_reg;
2994
2995         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2996         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2997         intel_encoder->cloneable = false;
2998         intel_encoder->hot_plug = intel_dp_hot_plug;
2999
3000         intel_dp_init_connector(intel_dig_port, intel_connector);
3001 }