sys/dev/drm/radeon/r600_cp.c

   1 /*-
   2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Dave Airlie <airlied@redhat.com>
  26  *     Alex Deucher <alexander.deucher@amd.com>
  27  * __FBSDID("$FreeBSD: src/sys/dev/drm/r600_cp.c,v 1.10 2009/08/23 14:55:57 rnoland Exp $");
  28  */
  29
  30 #include "dev/drm/drmP.h"
  31 #include "dev/drm/drm.h"
  32 #include "dev/drm/radeon_drm.h"
  33 #include "radeon_drv.h"
  34
  35 #include "r600_microcode.h"
  36
  37 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  38 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  39
  40 #define R600_PTE_VALID     (1 << 0)
  41 #define R600_PTE_SYSTEM    (1 << 1)
  42 #define R600_PTE_SNOOPED   (1 << 2)
  43 #define R600_PTE_READABLE  (1 << 5)
  44 #define R600_PTE_WRITEABLE (1 << 6)
  45
  46 /* MAX values used for gfx init */
  47 #define R6XX_MAX_SH_GPRS           256
  48 #define R6XX_MAX_TEMP_GPRS         16
  49 #define R6XX_MAX_SH_THREADS        256
  50 #define R6XX_MAX_SH_STACK_ENTRIES  4096
  51 #define R6XX_MAX_BACKENDS          8
  52 #define R6XX_MAX_BACKENDS_MASK     0xff
  53 #define R6XX_MAX_SIMDS             8
  54 #define R6XX_MAX_SIMDS_MASK        0xff
  55 #define R6XX_MAX_PIPES             8
  56 #define R6XX_MAX_PIPES_MASK        0xff
  57
  58 #define R7XX_MAX_SH_GPRS           256
  59 #define R7XX_MAX_TEMP_GPRS         16
  60 #define R7XX_MAX_SH_THREADS        256
  61 #define R7XX_MAX_SH_STACK_ENTRIES  4096
  62 #define R7XX_MAX_BACKENDS          8
  63 #define R7XX_MAX_BACKENDS_MASK     0xff
  64 #define R7XX_MAX_SIMDS             16
  65 #define R7XX_MAX_SIMDS_MASK        0xffff
  66 #define R7XX_MAX_PIPES             8
  67 #define R7XX_MAX_PIPES_MASK        0xff
  68
  69 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
  70 {
  71         int i;
  72
  73         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  74
  75         for (i = 0; i < dev_priv->usec_timeout; i++) {
  76                 int slots;
  77                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
  78                         slots = (RADEON_READ(R600_GRBM_STATUS)
  79                                  & R700_CMDFIFO_AVAIL_MASK);
  80                 else
  81                         slots = (RADEON_READ(R600_GRBM_STATUS)
  82                                  & R600_CMDFIFO_AVAIL_MASK);
  83                 if (slots >= entries)
  84                         return 0;
  85                 DRM_UDELAY(1);
  86         }
  87         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
  88                  RADEON_READ(R600_GRBM_STATUS),
  89                  RADEON_READ(R600_GRBM_STATUS2));
  90
  91         return -EBUSY;
  92 }
  93
  94 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
  95 {
  96         int i, ret;
  97
  98         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  99
 100         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 101                 ret = r600_do_wait_for_fifo(dev_priv, 8);
 102         else
 103                 ret = r600_do_wait_for_fifo(dev_priv, 16);
 104         if (ret)
 105                 return ret;
 106         for (i = 0; i < dev_priv->usec_timeout; i++) {
 107                 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
 108                         return 0;
 109                 DRM_UDELAY(1);
 110         }
 111         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 112                  RADEON_READ(R600_GRBM_STATUS),
 113                  RADEON_READ(R600_GRBM_STATUS2));
 114
 115         return -EBUSY;
 116 }
 117
 118 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 119 {
 120 #ifdef __linux__
 121         struct drm_sg_mem *entry = dev->sg;
 122         int max_pages;
 123         int pages;
 124         int i;
 125 #endif
 126         if (gart_info->bus_addr) {
 127 #ifdef __linux__
 128                 max_pages = (gart_info->table_size / sizeof(u32));
 129                 pages = (entry->pages <= max_pages)
 130                   ? entry->pages : max_pages;
 131
 132                 for (i = 0; i < pages; i++) {
 133                         if (!entry->busaddr[i])
 134                                 break;
 135                         pci_unmap_single(dev->pdev, entry->busaddr[i],
 136                                          PAGE_SIZE, PCI_DMA_TODEVICE);
 137                 }
 138 #endif
 139                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 140                         gart_info->bus_addr = 0;
 141         }
 142 }
 143
 144 /* R600 has page table setup */
 145 int r600_page_table_init(struct drm_device *dev)
 146 {
 147         drm_radeon_private_t *dev_priv = dev->dev_private;
 148         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 149         struct drm_sg_mem *entry = dev->sg;
 150         int ret = 0;
 151         int i, j;
 152         int max_pages, pages;
 153         u64 *pci_gart, page_base;
 154         dma_addr_t entry_addr;
 155
 156         /* okay page table is available - lets rock */
 157
 158         /* PTEs are 64-bits */
 159         pci_gart = (u64 *)gart_info->addr;
 160
 161         max_pages = (gart_info->table_size / sizeof(u64));
 162         pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
 163
 164         memset(pci_gart, 0, max_pages * sizeof(u64));
 165
 166         for (i = 0; i < pages; i++) {
 167 #ifdef __linux__
 168                 entry->busaddr[i] = pci_map_single(dev->pdev,
 169                                                    page_address(entry->
 170                                                                 pagelist[i]),
 171                                                    PAGE_SIZE, PCI_DMA_TODEVICE);
 172                 if (entry->busaddr[i] == 0) {
 173                         DRM_ERROR("unable to map PCIGART pages!\n");
 174                         r600_page_table_cleanup(dev, gart_info);
 175                         goto done;
 176                 }
 177 #endif
 178                 entry_addr = entry->busaddr[i];
 179                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 180                         page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
 181                         page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 182                         page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 183
 184                         *pci_gart = page_base;
 185
 186                         if ((i % 128) == 0)
 187                                 DRM_DEBUG("page entry %d: 0x%016llx\n",
 188                                     i, (unsigned long long)page_base);
 189                         pci_gart++;
 190                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 191                 }
 192         }
 193         ret = 1;
 194 #ifdef __linux__
 195 done:
 196 #endif
 197         return ret;
 198 }
 199
 200 static void r600_vm_flush_gart_range(struct drm_device *dev)
 201 {
 202         drm_radeon_private_t *dev_priv = dev->dev_private;
 203         u32 resp, countdown = 1000;
 204         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 205         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 206         RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
 207
 208         do {
 209                 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
 210                 countdown--;
 211                 DRM_UDELAY(1);
 212         } while (((resp & 0xf0) == 0) && countdown);
 213 }
 214
 215 static void r600_vm_init(struct drm_device *dev)
 216 {
 217         drm_radeon_private_t *dev_priv = dev->dev_private;
 218         /* initialise the VM to use the page table we constructed up there */
 219         u32 vm_c0, i;
 220         u32 mc_rd_a;
 221         u32 vm_l2_cntl, vm_l2_cntl3;
 222         /* okay set up the PCIE aperture type thingo */
 223         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 224         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 225         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 226
 227         /* setup MC RD a */
 228         mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
 229                 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
 230                 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
 231
 232         RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
 233         RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
 234
 235         RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
 236         RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
 237
 238         RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
 239         RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
 240
 241         RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
 242         RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
 243
 244         RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
 245         RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
 246
 247         RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
 248         RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
 249
 250         RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
 251         RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
 252
 253         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 254         vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
 255         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 256
 257         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 258         vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
 259                        R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
 260                        R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
 261         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 262
 263         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 264
 265         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 266
 267         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 268
 269         /* disable all other contexts */
 270         for (i = 1; i < 8; i++)
 271                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 272
 273         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 274         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 275         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 276
 277         r600_vm_flush_gart_range(dev);
 278 }
 279
 280 /* load r600 microcode */
 281 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 282 {
 283         const u32 (*cp)[3];
 284         const u32 *pfp;
 285         int i;
 286
 287         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 288         case CHIP_R600:
 289                 DRM_INFO("Loading R600 Microcode\n");
 290                 cp  = R600_cp_microcode;
 291                 pfp = R600_pfp_microcode;
 292                 break;
 293         case CHIP_RV610:
 294                 DRM_INFO("Loading RV610 Microcode\n");
 295                 cp  = RV610_cp_microcode;
 296                 pfp = RV610_pfp_microcode;
 297                 break;
 298         case CHIP_RV630:
 299                 DRM_INFO("Loading RV630 Microcode\n");
 300                 cp  = RV630_cp_microcode;
 301                 pfp = RV630_pfp_microcode;
 302                 break;
 303         case CHIP_RV620:
 304                 DRM_INFO("Loading RV620 Microcode\n");
 305                 cp  = RV620_cp_microcode;
 306                 pfp = RV620_pfp_microcode;
 307                 break;
 308         case CHIP_RV635:
 309                 DRM_INFO("Loading RV635 Microcode\n");
 310                 cp  = RV635_cp_microcode;
 311                 pfp = RV635_pfp_microcode;
 312                 break;
 313         case CHIP_RV670:
 314                 DRM_INFO("Loading RV670 Microcode\n");
 315                 cp  = RV670_cp_microcode;
 316                 pfp = RV670_pfp_microcode;
 317                 break;
 318         case CHIP_RS780:
 319         case CHIP_RS880:
 320                 DRM_INFO("Loading RS780/RS880 Microcode\n");
 321                 cp  = RS780_cp_microcode;
 322                 pfp = RS780_pfp_microcode;
 323                 break;
 324         default:
 325                 return;
 326         }
 327
 328         r600_do_cp_stop(dev_priv);
 329
 330         RADEON_WRITE(R600_CP_RB_CNTL,
 331                      R600_RB_NO_UPDATE |
 332                      R600_RB_BLKSZ(15) |
 333                      R600_RB_BUFSZ(3));
 334
 335         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 336         RADEON_READ(R600_GRBM_SOFT_RESET);
 337         DRM_UDELAY(15000);
 338         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 339
 340         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 341
 342         for (i = 0; i < PM4_UCODE_SIZE; i++) {
 343                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
 344                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
 345                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
 346         }
 347
 348         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 349         for (i = 0; i < PFP_UCODE_SIZE; i++)
 350                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 351
 352         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 353         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 354         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 355 }
 356
 357 static void r700_vm_init(struct drm_device *dev)
 358 {
 359         drm_radeon_private_t *dev_priv = dev->dev_private;
 360         /* initialise the VM to use the page table we constructed up there */
 361         u32 vm_c0, i;
 362         u32 mc_vm_md_l1;
 363         u32 vm_l2_cntl, vm_l2_cntl3;
 364         /* okay set up the PCIE aperture type thingo */
 365         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 366         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 367         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 368
 369         mc_vm_md_l1 = R700_ENABLE_L1_TLB |
 370             R700_ENABLE_L1_FRAGMENT_PROCESSING |
 371             R700_SYSTEM_ACCESS_MODE_IN_SYS |
 372             R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 373             R700_EFFECTIVE_L1_TLB_SIZE(5) |
 374             R700_EFFECTIVE_L1_QUEUE_SIZE(5);
 375
 376         RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
 377         RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
 378         RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
 379         RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
 380         RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
 381         RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
 382         RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
 383
 384         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 385         vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
 386         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 387
 388         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 389         vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
 390         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 391
 392         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 393
 394         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 395
 396         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 397
 398         /* disable all other contexts */
 399         for (i = 1; i < 8; i++)
 400                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 401
 402         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 403         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 404         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 405
 406         r600_vm_flush_gart_range(dev);
 407 }
 408
 409 /* load r600 microcode */
 410 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 411 {
 412         const u32 *pfp;
 413         const u32 *cp;
 414         int i;
 415
 416         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 417         case CHIP_RV770:
 418                 DRM_INFO("Loading RV770/RV790 Microcode\n");
 419                 pfp = RV770_pfp_microcode;
 420                 cp  = RV770_cp_microcode;
 421                 break;
 422         case CHIP_RV730:
 423         case CHIP_RV740:
 424                 DRM_INFO("Loading RV730/RV740 Microcode\n");
 425                 pfp = RV730_pfp_microcode;
 426                 cp  = RV730_cp_microcode;
 427                 break;
 428         case CHIP_RV710:
 429                 DRM_INFO("Loading RV710 Microcode\n");
 430                 pfp = RV710_pfp_microcode;
 431                 cp  = RV710_cp_microcode;
 432                 break;
 433         default:
 434                 return;
 435         }
 436
 437         r600_do_cp_stop(dev_priv);
 438
 439         RADEON_WRITE(R600_CP_RB_CNTL,
 440                      R600_RB_NO_UPDATE |
 441                      (15 << 8) |
 442                      (3 << 0));
 443
 444         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 445         RADEON_READ(R600_GRBM_SOFT_RESET);
 446         DRM_UDELAY(15000);
 447         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 448
 449         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 450         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 451                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
 452         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 453
 454         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 455         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 456                 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
 457         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 458
 459         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 460         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 461         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 462 }
 463
 464 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
 465 {
 466         u32 tmp;
 467
 468         /* Start with assuming that writeback doesn't work */
 469         dev_priv->writeback_works = 0;
 470
 471         /* Writeback doesn't seem to work everywhere, test it here and possibly
 472          * enable it if it appears to work
 473          */
 474         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
 475
 476         RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
 477
 478         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 479                 u32 val;
 480
 481                 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
 482                 if (val == 0xdeadbeef)
 483                         break;
 484                 DRM_UDELAY(1);
 485         }
 486
 487         if (tmp < dev_priv->usec_timeout) {
 488                 dev_priv->writeback_works = 1;
 489                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 490         } else {
 491                 dev_priv->writeback_works = 0;
 492                 DRM_INFO("writeback test failed\n");
 493         }
 494         if (radeon_no_wb == 1) {
 495                 dev_priv->writeback_works = 0;
 496                 DRM_INFO("writeback forced off\n");
 497         }
 498
 499         if (!dev_priv->writeback_works) {
 500                 /* Disable writeback to avoid unnecessary bus master transfer */
 501                 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
 502                              RADEON_RB_NO_UPDATE);
 503                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
 504         }
 505 }
 506
 507 int r600_do_engine_reset(struct drm_device *dev)
 508 {
 509         drm_radeon_private_t *dev_priv = dev->dev_private;
 510         u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
 511
 512         DRM_INFO("Resetting GPU\n");
 513
 514         cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
 515         cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
 516         RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
 517
 518         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
 519         RADEON_READ(R600_GRBM_SOFT_RESET);
 520         DRM_UDELAY(50);
 521         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 522         RADEON_READ(R600_GRBM_SOFT_RESET);
 523
 524         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
 525         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
 526         RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
 527
 528         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
 529         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
 530         RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
 531         RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
 532
 533         /* Reset the CP ring */
 534         r600_do_cp_reset(dev_priv);
 535
 536         /* The CP is no longer running after an engine reset */
 537         dev_priv->cp_running = 0;
 538
 539         /* Reset any pending vertex, indirect buffers */
 540         radeon_freelist_reset(dev);
 541
 542         return 0;
 543
 544 }
 545
 546 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 547                                              u32 num_backends,
 548                                              u32 backend_disable_mask)
 549 {
 550         u32 backend_map = 0;
 551         u32 enabled_backends_mask;
 552         u32 enabled_backends_count;
 553         u32 cur_pipe;
 554         u32 swizzle_pipe[R6XX_MAX_PIPES];
 555         u32 cur_backend;
 556         u32 i;
 557
 558         if (num_tile_pipes > R6XX_MAX_PIPES)
 559                 num_tile_pipes = R6XX_MAX_PIPES;
 560         if (num_tile_pipes < 1)
 561                 num_tile_pipes = 1;
 562         if (num_backends > R6XX_MAX_BACKENDS)
 563                 num_backends = R6XX_MAX_BACKENDS;
 564         if (num_backends < 1)
 565                 num_backends = 1;
 566
 567         enabled_backends_mask = 0;
 568         enabled_backends_count = 0;
 569         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 570                 if (((backend_disable_mask >> i) & 1) == 0) {
 571                         enabled_backends_mask |= (1 << i);
 572                         ++enabled_backends_count;
 573                 }
 574                 if (enabled_backends_count == num_backends)
 575                         break;
 576         }
 577
 578         if (enabled_backends_count == 0) {
 579                 enabled_backends_mask = 1;
 580                 enabled_backends_count = 1;
 581         }
 582
 583         if (enabled_backends_count != num_backends)
 584                 num_backends = enabled_backends_count;
 585
 586         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 587         switch (num_tile_pipes) {
 588         case 1:
 589                 swizzle_pipe[0] = 0;
 590                 break;
 591         case 2:
 592                 swizzle_pipe[0] = 0;
 593                 swizzle_pipe[1] = 1;
 594                 break;
 595         case 3:
 596                 swizzle_pipe[0] = 0;
 597                 swizzle_pipe[1] = 1;
 598                 swizzle_pipe[2] = 2;
 599                 break;
 600         case 4:
 601                 swizzle_pipe[0] = 0;
 602                 swizzle_pipe[1] = 1;
 603                 swizzle_pipe[2] = 2;
 604                 swizzle_pipe[3] = 3;
 605                 break;
 606         case 5:
 607                 swizzle_pipe[0] = 0;
 608                 swizzle_pipe[1] = 1;
 609                 swizzle_pipe[2] = 2;
 610                 swizzle_pipe[3] = 3;
 611                 swizzle_pipe[4] = 4;
 612                 break;
 613         case 6:
 614                 swizzle_pipe[0] = 0;
 615                 swizzle_pipe[1] = 2;
 616                 swizzle_pipe[2] = 4;
 617                 swizzle_pipe[3] = 5;
 618                 swizzle_pipe[4] = 1;
 619                 swizzle_pipe[5] = 3;
 620                 break;
 621         case 7:
 622                 swizzle_pipe[0] = 0;
 623                 swizzle_pipe[1] = 2;
 624                 swizzle_pipe[2] = 4;
 625                 swizzle_pipe[3] = 6;
 626                 swizzle_pipe[4] = 1;
 627                 swizzle_pipe[5] = 3;
 628                 swizzle_pipe[6] = 5;
 629                 break;
 630         case 8:
 631                 swizzle_pipe[0] = 0;
 632                 swizzle_pipe[1] = 2;
 633                 swizzle_pipe[2] = 4;
 634                 swizzle_pipe[3] = 6;
 635                 swizzle_pipe[4] = 1;
 636                 swizzle_pipe[5] = 3;
 637                 swizzle_pipe[6] = 5;
 638                 swizzle_pipe[7] = 7;
 639                 break;
 640         }
 641
 642         cur_backend = 0;
 643         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 644                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 645                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 646
 647                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 648
 649                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 650         }
 651
 652         return backend_map;
 653 }
 654
 655 static int r600_count_pipe_bits(uint32_t val)
 656 {
 657         int i, ret = 0;
 658         for (i = 0; i < 32; i++) {
 659                 ret += val & 1;
 660                 val >>= 1;
 661         }
 662         return ret;
 663 }
 664
 665 static void r600_gfx_init(struct drm_device *dev,
 666                           drm_radeon_private_t *dev_priv)
 667 {
 668         int i, j, num_qd_pipes;
 669         u32 sx_debug_1;
 670         u32 tc_cntl;
 671         u32 arb_pop;
 672         u32 num_gs_verts_per_thread;
 673         u32 vgt_gs_per_es;
 674         u32 gs_prim_buffer_depth = 0;
 675         u32 sq_ms_fifo_sizes;
 676         u32 sq_config;
 677         u32 sq_gpr_resource_mgmt_1 = 0;
 678         u32 sq_gpr_resource_mgmt_2 = 0;
 679         u32 sq_thread_resource_mgmt = 0;
 680         u32 sq_stack_resource_mgmt_1 = 0;
 681         u32 sq_stack_resource_mgmt_2 = 0;
 682         u32 hdp_host_path_cntl;
 683         u32 backend_map;
 684         u32 gb_tiling_config = 0;
 685         u32 cc_rb_backend_disable = 0;
 686         u32 cc_gc_shader_pipe_config = 0;
 687         u32 ramcfg;
 688
 689         /* setup chip specs */
 690         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 691         case CHIP_R600:
 692                 dev_priv->r600_max_pipes = 4;
 693                 dev_priv->r600_max_tile_pipes = 8;
 694                 dev_priv->r600_max_simds = 4;
 695                 dev_priv->r600_max_backends = 4;
 696                 dev_priv->r600_max_gprs = 256;
 697                 dev_priv->r600_max_threads = 192;
 698                 dev_priv->r600_max_stack_entries = 256;
 699                 dev_priv->r600_max_hw_contexts = 8;
 700                 dev_priv->r600_max_gs_threads = 16;
 701                 dev_priv->r600_sx_max_export_size = 128;
 702                 dev_priv->r600_sx_max_export_pos_size = 16;
 703                 dev_priv->r600_sx_max_export_smx_size = 128;
 704                 dev_priv->r600_sq_num_cf_insts = 2;
 705                 break;
 706         case CHIP_RV630:
 707         case CHIP_RV635:
 708                 dev_priv->r600_max_pipes = 2;
 709                 dev_priv->r600_max_tile_pipes = 2;
 710                 dev_priv->r600_max_simds = 3;
 711                 dev_priv->r600_max_backends = 1;
 712                 dev_priv->r600_max_gprs = 128;
 713                 dev_priv->r600_max_threads = 192;
 714                 dev_priv->r600_max_stack_entries = 128;
 715                 dev_priv->r600_max_hw_contexts = 8;
 716                 dev_priv->r600_max_gs_threads = 4;
 717                 dev_priv->r600_sx_max_export_size = 128;
 718                 dev_priv->r600_sx_max_export_pos_size = 16;
 719                 dev_priv->r600_sx_max_export_smx_size = 128;
 720                 dev_priv->r600_sq_num_cf_insts = 2;
 721                 break;
 722         case CHIP_RV610:
 723         case CHIP_RS780:
 724         case CHIP_RS880:
 725         case CHIP_RV620:
 726                 dev_priv->r600_max_pipes = 1;
 727                 dev_priv->r600_max_tile_pipes = 1;
 728                 dev_priv->r600_max_simds = 2;
 729                 dev_priv->r600_max_backends = 1;
 730                 dev_priv->r600_max_gprs = 128;
 731                 dev_priv->r600_max_threads = 192;
 732                 dev_priv->r600_max_stack_entries = 128;
 733                 dev_priv->r600_max_hw_contexts = 4;
 734                 dev_priv->r600_max_gs_threads = 4;
 735                 dev_priv->r600_sx_max_export_size = 128;
 736                 dev_priv->r600_sx_max_export_pos_size = 16;
 737                 dev_priv->r600_sx_max_export_smx_size = 128;
 738                 dev_priv->r600_sq_num_cf_insts = 1;
 739                 break;
 740         case CHIP_RV670:
 741                 dev_priv->r600_max_pipes = 4;
 742                 dev_priv->r600_max_tile_pipes = 4;
 743                 dev_priv->r600_max_simds = 4;
 744                 dev_priv->r600_max_backends = 4;
 745                 dev_priv->r600_max_gprs = 192;
 746                 dev_priv->r600_max_threads = 192;
 747                 dev_priv->r600_max_stack_entries = 256;
 748                 dev_priv->r600_max_hw_contexts = 8;
 749                 dev_priv->r600_max_gs_threads = 16;
 750                 dev_priv->r600_sx_max_export_size = 128;
 751                 dev_priv->r600_sx_max_export_pos_size = 16;
 752                 dev_priv->r600_sx_max_export_smx_size = 128;
 753                 dev_priv->r600_sq_num_cf_insts = 2;
 754                 break;
 755         default:
 756                 break;
 757         }
 758
 759         /* Initialize HDP */
 760         j = 0;
 761         for (i = 0; i < 32; i++) {
 762                 RADEON_WRITE((0x2c14 + j), 0x00000000);
 763                 RADEON_WRITE((0x2c18 + j), 0x00000000);
 764                 RADEON_WRITE((0x2c1c + j), 0x00000000);
 765                 RADEON_WRITE((0x2c20 + j), 0x00000000);
 766                 RADEON_WRITE((0x2c24 + j), 0x00000000);
 767                 j += 0x18;
 768         }
 769
 770         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
 771
 772         /* setup tiling, simd, pipe config */
 773         ramcfg = RADEON_READ(R600_RAMCFG);
 774
 775         switch (dev_priv->r600_max_tile_pipes) {
 776         case 1:
 777                 gb_tiling_config |= R600_PIPE_TILING(0);
 778                 break;
 779         case 2:
 780                 gb_tiling_config |= R600_PIPE_TILING(1);
 781                 break;
 782         case 4:
 783                 gb_tiling_config |= R600_PIPE_TILING(2);
 784                 break;
 785         case 8:
 786                 gb_tiling_config |= R600_PIPE_TILING(3);
 787                 break;
 788         default:
 789                 break;
 790         }
 791
 792         gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
 793
 794         gb_tiling_config |= R600_GROUP_SIZE(0);
 795
 796         if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
 797                 gb_tiling_config |= R600_ROW_TILING(3);
 798                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
 799         } else {
 800                 gb_tiling_config |=
 801                         R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 802                 gb_tiling_config |=
 803                         R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 804         }
 805
 806         gb_tiling_config |= R600_BANK_SWAPS(1);
 807
 808         backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
 809                                                         dev_priv->r600_max_backends,
 810                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
 811         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
 812
 813         cc_gc_shader_pipe_config =
 814                 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
 815         cc_gc_shader_pipe_config |=
 816                 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
 817
 818         cc_rb_backend_disable =
 819                 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
 820
 821         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
 822         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 823         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 824
 825         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 826         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 827         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 828
 829         num_qd_pipes =
 830                 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
 831         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
 832         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
 833
 834         /* set HW defaults for 3D engine */
 835         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
 836                                                 R600_ROQ_IB2_START(0x2b)));
 837
 838         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
 839                                               R600_ROQ_END(0x40)));
 840
 841         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
 842                                         R600_SYNC_GRADIENT |
 843                                         R600_SYNC_WALKER |
 844                                         R600_SYNC_ALIGNER));
 845
 846         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
 847                 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
 848
 849         sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
 850         sx_debug_1 |= R600_SMX_EVENT_RELEASE;
 851         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
 852                 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
 853         RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
 854
 855         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 856             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 857             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 858             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 859             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 860             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
 861                 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 862         else
 863                 RADEON_WRITE(R600_DB_DEBUG, 0);
 864
 865         RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
 866                                           R600_DEPTH_FLUSH(16) |
 867                                           R600_DEPTH_PENDING_FREE(4) |
 868                                           R600_DEPTH_CACHELINE_FREE(16)));
 869         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
 870         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
 871
 872         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
 873         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
 874
 875         sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
 876         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 877             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 878             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 879             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
 880                 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
 881                                     R600_FETCH_FIFO_HIWATER(0xa) |
 882                                     R600_DONE_FIFO_HIWATER(0xe0) |
 883                                     R600_ALU_UPDATE_FIFO_HIWATER(0x8));
 884         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 885                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
 886                 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
 887                 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
 888         }
 889         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 890
 891         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 892          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 893          */
 894         sq_config = RADEON_READ(R600_SQ_CONFIG);
 895         sq_config &= ~(R600_PS_PRIO(3) |
 896                        R600_VS_PRIO(3) |
 897                        R600_GS_PRIO(3) |
 898                        R600_ES_PRIO(3));
 899         sq_config |= (R600_DX9_CONSTS |
 900                       R600_VC_ENABLE |
 901                       R600_PS_PRIO(0) |
 902                       R600_VS_PRIO(1) |
 903                       R600_GS_PRIO(2) |
 904                       R600_ES_PRIO(3));
 905
 906         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
 907                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
 908                                           R600_NUM_VS_GPRS(124) |
 909                                           R600_NUM_CLAUSE_TEMP_GPRS(4));
 910                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
 911                                           R600_NUM_ES_GPRS(0));
 912                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
 913                                            R600_NUM_VS_THREADS(48) |
 914                                            R600_NUM_GS_THREADS(4) |
 915                                            R600_NUM_ES_THREADS(4));
 916                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
 917                                             R600_NUM_VS_STACK_ENTRIES(128));
 918                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
 919                                             R600_NUM_ES_STACK_ENTRIES(0));
 920         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 921                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 922                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 923                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
 924                 /* no vertex cache */
 925                 sq_config &= ~R600_VC_ENABLE;
 926
 927                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 928                                           R600_NUM_VS_GPRS(44) |
 929                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 930                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 931                                           R600_NUM_ES_GPRS(17));
 932                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 933                                            R600_NUM_VS_THREADS(78) |
 934                                            R600_NUM_GS_THREADS(4) |
 935                                            R600_NUM_ES_THREADS(31));
 936                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 937                                             R600_NUM_VS_STACK_ENTRIES(40));
 938                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 939                                             R600_NUM_ES_STACK_ENTRIES(16));
 940         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 941                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
 942                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 943                                           R600_NUM_VS_GPRS(44) |
 944                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 945                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
 946                                           R600_NUM_ES_GPRS(18));
 947                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 948                                            R600_NUM_VS_THREADS(78) |
 949                                            R600_NUM_GS_THREADS(4) |
 950                                            R600_NUM_ES_THREADS(31));
 951                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 952                                             R600_NUM_VS_STACK_ENTRIES(40));
 953                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 954                                             R600_NUM_ES_STACK_ENTRIES(16));
 955         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
 956                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 957                                           R600_NUM_VS_GPRS(44) |
 958                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 959                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 960                                           R600_NUM_ES_GPRS(17));
 961                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 962                                            R600_NUM_VS_THREADS(78) |
 963                                            R600_NUM_GS_THREADS(4) |
 964                                            R600_NUM_ES_THREADS(31));
 965                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
 966                                             R600_NUM_VS_STACK_ENTRIES(64));
 967                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
 968                                             R600_NUM_ES_STACK_ENTRIES(64));
 969         }
 970
 971         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
 972         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 973         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 974         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 975         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 976         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 977
 978         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 979             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 980             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 981             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
 982                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
 983         else
 984                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
 985
 986         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
 987                                                     R600_S0_Y(0x4) |
 988                                                     R600_S1_X(0x4) |
 989                                                     R600_S1_Y(0xc)));
 990         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
 991                                                     R600_S0_Y(0xe) |
 992                                                     R600_S1_X(0x2) |
 993                                                     R600_S1_Y(0x2) |
 994                                                     R600_S2_X(0xa) |
 995                                                     R600_S2_Y(0x6) |
 996                                                     R600_S3_X(0x6) |
 997                                                     R600_S3_Y(0xa)));
 998         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
 999                                                         R600_S0_Y(0xb) |
1000                                                         R600_S1_X(0x4) |
1001                                                         R600_S1_Y(0xc) |
1002                                                         R600_S2_X(0x1) |
1003                                                         R600_S2_Y(0x6) |
1004                                                         R600_S3_X(0xa) |
1005                                                         R600_S3_Y(0xe)));
1006         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1007                                                         R600_S4_Y(0x1) |
1008                                                         R600_S5_X(0x0) |
1009                                                         R600_S5_Y(0x0) |
1010                                                         R600_S6_X(0xb) |
1011                                                         R600_S6_Y(0x4) |
1012                                                         R600_S7_X(0x7) |
1013                                                         R600_S7_Y(0x8)));
1014
1015
1016         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1017         case CHIP_R600:
1018         case CHIP_RV630:
1019         case CHIP_RV635:
1020                 gs_prim_buffer_depth = 0;
1021                 break;
1022         case CHIP_RV610:
1023         case CHIP_RS780:
1024         case CHIP_RS880:
1025         case CHIP_RV620:
1026                 gs_prim_buffer_depth = 32;
1027                 break;
1028         case CHIP_RV670:
1029                 gs_prim_buffer_depth = 128;
1030                 break;
1031         default:
1032                 break;
1033         }
1034
1035         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1036         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1037         /* Max value for this is 256 */
1038         if (vgt_gs_per_es > 256)
1039                 vgt_gs_per_es = 256;
1040
1041         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1042         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1043         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1044         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1045
1046         /* more default values. 2D/3D driver should adjust as needed */
1047         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1048         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1049         RADEON_WRITE(R600_SX_MISC, 0);
1050         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1051         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1052         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1053         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1054         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1055         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1056
1057         /* clear render buffer base addresses */
1058         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1059         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1060         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1061         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1062         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1063         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1064         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1065         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1066
1067         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1068         case CHIP_RV610:
1069         case CHIP_RS780:
1070         case CHIP_RS880:
1071         case CHIP_RV620:
1072                 tc_cntl = R600_TC_L2_SIZE(8);
1073                 break;
1074         case CHIP_RV630:
1075         case CHIP_RV635:
1076                 tc_cntl = R600_TC_L2_SIZE(4);
1077                 break;
1078         case CHIP_R600:
1079                 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1080                 break;
1081         default:
1082                 tc_cntl = R600_TC_L2_SIZE(0);
1083                 break;
1084         }
1085
1086         RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1087
1088         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1089         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1090
1091         arb_pop = RADEON_READ(R600_ARB_POP);
1092         arb_pop |= R600_ENABLE_TC128;
1093         RADEON_WRITE(R600_ARB_POP, arb_pop);
1094
1095         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1096         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1097                                           R600_NUM_CLIP_SEQ(3)));
1098         RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1099
1100 }
1101
1102 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1103                                              u32 num_backends,
1104                                              u32 backend_disable_mask)
1105 {
1106         u32 backend_map = 0;
1107         u32 enabled_backends_mask;
1108         u32 enabled_backends_count;
1109         u32 cur_pipe;
1110         u32 swizzle_pipe[R7XX_MAX_PIPES];
1111         u32 cur_backend;
1112         u32 i;
1113
1114         if (num_tile_pipes > R7XX_MAX_PIPES)
1115                 num_tile_pipes = R7XX_MAX_PIPES;
1116         if (num_tile_pipes < 1)
1117                 num_tile_pipes = 1;
1118         if (num_backends > R7XX_MAX_BACKENDS)
1119                 num_backends = R7XX_MAX_BACKENDS;
1120         if (num_backends < 1)
1121                 num_backends = 1;
1122
1123         enabled_backends_mask = 0;
1124         enabled_backends_count = 0;
1125         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1126                 if (((backend_disable_mask >> i) & 1) == 0) {
1127                         enabled_backends_mask |= (1 << i);
1128                         ++enabled_backends_count;
1129                 }
1130                 if (enabled_backends_count == num_backends)
1131                         break;
1132         }
1133
1134         if (enabled_backends_count == 0) {
1135                 enabled_backends_mask = 1;
1136                 enabled_backends_count = 1;
1137         }
1138
1139         if (enabled_backends_count != num_backends)
1140                 num_backends = enabled_backends_count;
1141
1142         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1143         switch (num_tile_pipes) {
1144         case 1:
1145                 swizzle_pipe[0] = 0;
1146                 break;
1147         case 2:
1148                 swizzle_pipe[0] = 0;
1149                 swizzle_pipe[1] = 1;
1150                 break;
1151         case 3:
1152                 swizzle_pipe[0] = 0;
1153                 swizzle_pipe[1] = 2;
1154                 swizzle_pipe[2] = 1;
1155                 break;
1156         case 4:
1157                 swizzle_pipe[0] = 0;
1158                 swizzle_pipe[1] = 2;
1159                 swizzle_pipe[2] = 3;
1160                 swizzle_pipe[3] = 1;
1161                 break;
1162         case 5:
1163                 swizzle_pipe[0] = 0;
1164                 swizzle_pipe[1] = 2;
1165                 swizzle_pipe[2] = 4;
1166                 swizzle_pipe[3] = 1;
1167                 swizzle_pipe[4] = 3;
1168                 break;
1169         case 6:
1170                 swizzle_pipe[0] = 0;
1171                 swizzle_pipe[1] = 2;
1172                 swizzle_pipe[2] = 4;
1173                 swizzle_pipe[3] = 5;
1174                 swizzle_pipe[4] = 3;
1175                 swizzle_pipe[5] = 1;
1176                 break;
1177         case 7:
1178                 swizzle_pipe[0] = 0;
1179                 swizzle_pipe[1] = 2;
1180                 swizzle_pipe[2] = 4;
1181                 swizzle_pipe[3] = 6;
1182                 swizzle_pipe[4] = 3;
1183                 swizzle_pipe[5] = 1;
1184                 swizzle_pipe[6] = 5;
1185                 break;
1186         case 8:
1187                 swizzle_pipe[0] = 0;
1188                 swizzle_pipe[1] = 2;
1189                 swizzle_pipe[2] = 4;
1190                 swizzle_pipe[3] = 6;
1191                 swizzle_pipe[4] = 3;
1192                 swizzle_pipe[5] = 1;
1193                 swizzle_pipe[6] = 7;
1194                 swizzle_pipe[7] = 5;
1195                 break;
1196         }
1197
1198         cur_backend = 0;
1199         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1200                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1201                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1202
1203                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1204
1205                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1206         }
1207
1208         return backend_map;
1209 }
1210
1211 static void r700_gfx_init(struct drm_device *dev,
1212                           drm_radeon_private_t *dev_priv)
1213 {
1214         int i, j, num_qd_pipes;
1215         u32 sx_debug_1;
1216         u32 smx_dc_ctl0;
1217         u32 num_gs_verts_per_thread;
1218         u32 vgt_gs_per_es;
1219         u32 gs_prim_buffer_depth = 0;
1220         u32 sq_ms_fifo_sizes;
1221         u32 sq_config;
1222         u32 sq_thread_resource_mgmt;
1223         u32 hdp_host_path_cntl;
1224         u32 sq_dyn_gpr_size_simd_ab_0;
1225         u32 backend_map;
1226         u32 gb_tiling_config = 0;
1227         u32 cc_rb_backend_disable = 0;
1228         u32 cc_gc_shader_pipe_config = 0;
1229         u32 mc_arb_ramcfg;
1230         u32 db_debug4;
1231
1232         /* setup chip specs */
1233         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1234         case CHIP_RV770:
1235                 dev_priv->r600_max_pipes = 4;
1236                 dev_priv->r600_max_tile_pipes = 8;
1237                 dev_priv->r600_max_simds = 10;
1238                 dev_priv->r600_max_backends = 4;
1239                 dev_priv->r600_max_gprs = 256;
1240                 dev_priv->r600_max_threads = 248;
1241                 dev_priv->r600_max_stack_entries = 512;
1242                 dev_priv->r600_max_hw_contexts = 8;
1243                 dev_priv->r600_max_gs_threads = 16 * 2;
1244                 dev_priv->r600_sx_max_export_size = 128;
1245                 dev_priv->r600_sx_max_export_pos_size = 16;
1246                 dev_priv->r600_sx_max_export_smx_size = 112;
1247                 dev_priv->r600_sq_num_cf_insts = 2;
1248
1249                 dev_priv->r700_sx_num_of_sets = 7;
1250                 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1251                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1252                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1253                 break;
1254         case CHIP_RV740:
1255                 dev_priv->r600_max_pipes = 4;
1256                 dev_priv->r600_max_tile_pipes = 4;
1257                 dev_priv->r600_max_simds = 8;
1258                 dev_priv->r600_max_backends = 4;
1259                 dev_priv->r600_max_gprs = 256;
1260                 dev_priv->r600_max_threads = 248;
1261                 dev_priv->r600_max_stack_entries = 512;
1262                 dev_priv->r600_max_hw_contexts = 8;
1263                 dev_priv->r600_max_gs_threads = 16 * 2;
1264                 dev_priv->r600_sx_max_export_size = 256;
1265                 dev_priv->r600_sx_max_export_pos_size = 32;
1266                 dev_priv->r600_sx_max_export_smx_size = 224;
1267                 dev_priv->r600_sq_num_cf_insts = 2;
1268
1269                 dev_priv->r700_sx_num_of_sets = 7;
1270                 dev_priv->r700_sc_prim_fifo_size = 0x100;
1271                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1272                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1273
1274                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1275                         dev_priv->r600_sx_max_export_pos_size -= 16;
1276                         dev_priv->r600_sx_max_export_smx_size += 16;
1277                 }
1278                 break;
1279         case CHIP_RV730:
1280                 dev_priv->r600_max_pipes = 2;
1281                 dev_priv->r600_max_tile_pipes = 4;
1282                 dev_priv->r600_max_simds = 8;
1283                 dev_priv->r600_max_backends = 2;
1284                 dev_priv->r600_max_gprs = 128;
1285                 dev_priv->r600_max_threads = 248;
1286                 dev_priv->r600_max_stack_entries = 256;
1287                 dev_priv->r600_max_hw_contexts = 8;
1288                 dev_priv->r600_max_gs_threads = 16 * 2;
1289                 dev_priv->r600_sx_max_export_size = 256;
1290                 dev_priv->r600_sx_max_export_pos_size = 32;
1291                 dev_priv->r600_sx_max_export_smx_size = 224;
1292                 dev_priv->r600_sq_num_cf_insts = 2;
1293
1294                 dev_priv->r700_sx_num_of_sets = 7;
1295                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1296                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1297                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1298
1299                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1300                         dev_priv->r600_sx_max_export_pos_size -= 16;
1301                         dev_priv->r600_sx_max_export_smx_size += 16;
1302                 }
1303                 break;
1304         case CHIP_RV710:
1305                 dev_priv->r600_max_pipes = 2;
1306                 dev_priv->r600_max_tile_pipes = 2;
1307                 dev_priv->r600_max_simds = 2;
1308                 dev_priv->r600_max_backends = 1;
1309                 dev_priv->r600_max_gprs = 256;
1310                 dev_priv->r600_max_threads = 192;
1311                 dev_priv->r600_max_stack_entries = 256;
1312                 dev_priv->r600_max_hw_contexts = 4;
1313                 dev_priv->r600_max_gs_threads = 8 * 2;
1314                 dev_priv->r600_sx_max_export_size = 128;
1315                 dev_priv->r600_sx_max_export_pos_size = 16;
1316                 dev_priv->r600_sx_max_export_smx_size = 112;
1317                 dev_priv->r600_sq_num_cf_insts = 1;
1318
1319                 dev_priv->r700_sx_num_of_sets = 7;
1320                 dev_priv->r700_sc_prim_fifo_size = 0x40;
1321                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1322                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1323                 break;
1324         default:
1325                 break;
1326         }
1327
1328         /* Initialize HDP */
1329         j = 0;
1330         for (i = 0; i < 32; i++) {
1331                 RADEON_WRITE((0x2c14 + j), 0x00000000);
1332                 RADEON_WRITE((0x2c18 + j), 0x00000000);
1333                 RADEON_WRITE((0x2c1c + j), 0x00000000);
1334                 RADEON_WRITE((0x2c20 + j), 0x00000000);
1335                 RADEON_WRITE((0x2c24 + j), 0x00000000);
1336                 j += 0x18;
1337         }
1338
1339         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1340
1341         /* setup tiling, simd, pipe config */
1342         mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1343
1344         switch (dev_priv->r600_max_tile_pipes) {
1345         case 1:
1346                 gb_tiling_config |= R600_PIPE_TILING(0);
1347                 break;
1348         case 2:
1349                 gb_tiling_config |= R600_PIPE_TILING(1);
1350                 break;
1351         case 4:
1352                 gb_tiling_config |= R600_PIPE_TILING(2);
1353                 break;
1354         case 8:
1355                 gb_tiling_config |= R600_PIPE_TILING(3);
1356                 break;
1357         default:
1358                 break;
1359         }
1360
1361         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1362                 gb_tiling_config |= R600_BANK_TILING(1);
1363         else
1364                 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1365
1366         gb_tiling_config |= R600_GROUP_SIZE(0);
1367
1368         if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1369                 gb_tiling_config |= R600_ROW_TILING(3);
1370                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1371         } else {
1372                 gb_tiling_config |=
1373                         R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1374                 gb_tiling_config |=
1375                         R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1376         }
1377
1378         gb_tiling_config |= R600_BANK_SWAPS(1);
1379
1380         backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1381                                                         dev_priv->r600_max_backends,
1382                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
1383         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1384
1385         cc_gc_shader_pipe_config =
1386                 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1387         cc_gc_shader_pipe_config |=
1388                 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1389
1390         cc_rb_backend_disable =
1391                 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1392
1393         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
1394         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1395         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1396
1397         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
1398         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
1399         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1400
1401         RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1402         RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1403         RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1404         RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1405         RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1406
1407         num_qd_pipes =
1408                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1409         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1410         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1411
1412         /* set HW defaults for 3D engine */
1413         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1414                                                 R600_ROQ_IB2_START(0x2b)));
1415
1416         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1417
1418         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1419                                         R600_SYNC_GRADIENT |
1420                                         R600_SYNC_WALKER |
1421                                         R600_SYNC_ALIGNER));
1422
1423         sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1424         sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1425         RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1426
1427         smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1428         smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1429         smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1430         RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1431
1432         RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1433                                           R700_GS_FLUSH_CTL(4) |
1434                                           R700_ACK_FLUSH_CTL(3) |
1435                                           R700_SYNC_FLUSH_CTL));
1436
1437         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1438                 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1439         else {
1440                 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1441                 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1442                 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1443         }
1444
1445         RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1446                                                    R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1447                                                    R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1448
1449         RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1450                                                  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1451                                                  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1452
1453         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1454
1455         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1456
1457         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1458
1459         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1460
1461         RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1462
1463         sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1464                             R600_DONE_FIFO_HIWATER(0xe0) |
1465                             R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1466         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1467         case CHIP_RV770:
1468                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1469                 break;
1470         case CHIP_RV740:
1471         case CHIP_RV730:
1472         case CHIP_RV710:
1473         default:
1474                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1475                 break;
1476         }
1477         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1478
1479         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1480          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1481          */
1482         sq_config = RADEON_READ(R600_SQ_CONFIG);
1483         sq_config &= ~(R600_PS_PRIO(3) |
1484                        R600_VS_PRIO(3) |
1485                        R600_GS_PRIO(3) |
1486                        R600_ES_PRIO(3));
1487         sq_config |= (R600_DX9_CONSTS |
1488                       R600_VC_ENABLE |
1489                       R600_EXPORT_SRC_C |
1490                       R600_PS_PRIO(0) |
1491                       R600_VS_PRIO(1) |
1492                       R600_GS_PRIO(2) |
1493                       R600_ES_PRIO(3));
1494         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1495                 /* no vertex cache */
1496                 sq_config &= ~R600_VC_ENABLE;
1497
1498         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1499
1500         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1501                                                     R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1502                                                     R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1503
1504         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1505                                                     R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1506
1507         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1508                                    R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1509                                    R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1510         if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1511                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1512         else
1513                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1514         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1515
1516         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1517                                                      R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1518
1519         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1520                                                      R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1521
1522         sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1523                                      R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1524                                      R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1525                                      R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1526
1527         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1528         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1529         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1530         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1531         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1532         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1533         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1534         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1535
1536         RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1537                                                      R700_FORCE_EOV_MAX_REZ_CNT(255)));
1538
1539         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1540                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1541                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1542         else
1543                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1544                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1545
1546         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1547         case CHIP_RV770:
1548         case CHIP_RV740:
1549         case CHIP_RV730:
1550                 gs_prim_buffer_depth = 384;
1551                 break;
1552         case CHIP_RV710:
1553                 gs_prim_buffer_depth = 128;
1554                 break;
1555         default:
1556                 break;
1557         }
1558
1559         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1560         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1561         /* Max value for this is 256 */
1562         if (vgt_gs_per_es > 256)
1563                 vgt_gs_per_es = 256;
1564
1565         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1566         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1567         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1568
1569         /* more default values. 2D/3D driver should adjust as needed */
1570         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1571         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1572         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1573         RADEON_WRITE(R600_SX_MISC, 0);
1574         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1575         RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1576         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1577         RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1578         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1579         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1580         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1581         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1582
1583         /* clear render buffer base addresses */
1584         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1585         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1586         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1587         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1588         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1589         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1590         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1591         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1592
1593         RADEON_WRITE(R700_TCP_CNTL, 0);
1594
1595         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1596         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1597
1598         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1599
1600         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1601                                           R600_NUM_CLIP_SEQ(3)));
1602
1603 }
1604
1605 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1606                                        drm_radeon_private_t *dev_priv,
1607                                        struct drm_file *file_priv)
1608 {
1609         u32 ring_start;
1610         u64 rptr_addr;
1611
1612         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1613                 r700_gfx_init(dev, dev_priv);
1614         else
1615                 r600_gfx_init(dev, dev_priv);
1616
1617         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1618         RADEON_READ(R600_GRBM_SOFT_RESET);
1619         DRM_UDELAY(15000);
1620         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1621
1622
1623         /* Set ring buffer size */
1624 #ifdef __BIG_ENDIAN
1625         RADEON_WRITE(R600_CP_RB_CNTL,
1626                      RADEON_BUF_SWAP_32BIT |
1627                      RADEON_RB_NO_UPDATE |
1628                      (dev_priv->ring.rptr_update_l2qw << 8) |
1629                      dev_priv->ring.size_l2qw);
1630 #else
1631         RADEON_WRITE(R600_CP_RB_CNTL,
1632                      RADEON_RB_NO_UPDATE |
1633                      (dev_priv->ring.rptr_update_l2qw << 8) |
1634                      dev_priv->ring.size_l2qw);
1635 #endif
1636
1637         RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1638
1639         /* Set the write pointer delay */
1640         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1641
1642 #ifdef __BIG_ENDIAN
1643         RADEON_WRITE(R600_CP_RB_CNTL,
1644                      RADEON_BUF_SWAP_32BIT |
1645                      RADEON_RB_NO_UPDATE |
1646                      RADEON_RB_RPTR_WR_ENA |
1647                      (dev_priv->ring.rptr_update_l2qw << 8) |
1648                      dev_priv->ring.size_l2qw);
1649 #else
1650         RADEON_WRITE(R600_CP_RB_CNTL,
1651                      RADEON_RB_NO_UPDATE |
1652                      RADEON_RB_RPTR_WR_ENA |
1653                      (dev_priv->ring.rptr_update_l2qw << 8) |
1654                      dev_priv->ring.size_l2qw);
1655 #endif
1656
1657         /* Initialize the ring buffer's read and write pointers */
1658         RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1659         RADEON_WRITE(R600_CP_RB_WPTR, 0);
1660         SET_RING_HEAD(dev_priv, 0);
1661         dev_priv->ring.tail = 0;
1662
1663 #if __OS_HAS_AGP
1664         if (dev_priv->flags & RADEON_IS_AGP) {
1665                 rptr_addr = dev_priv->ring_rptr->offset
1666                         - dev->agp->base +
1667                         dev_priv->gart_vm_start;
1668         } else
1669 #endif
1670         {
1671                 rptr_addr = dev_priv->ring_rptr->offset
1672                         - ((unsigned long) dev->sg->virtual)
1673                         + dev_priv->gart_vm_start;
1674         }
1675         RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1676                      rptr_addr & 0xffffffff);
1677         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1678                      upper_32_bits(rptr_addr));
1679
1680 #ifdef __BIG_ENDIAN
1681         RADEON_WRITE(R600_CP_RB_CNTL,
1682                      RADEON_BUF_SWAP_32BIT |
1683                      (dev_priv->ring.rptr_update_l2qw << 8) |
1684                      dev_priv->ring.size_l2qw);
1685 #else
1686         RADEON_WRITE(R600_CP_RB_CNTL,
1687                      (dev_priv->ring.rptr_update_l2qw << 8) |
1688                      dev_priv->ring.size_l2qw);
1689 #endif
1690
1691 #if __OS_HAS_AGP
1692         if (dev_priv->flags & RADEON_IS_AGP) {
1693                 /* XXX */
1694                 radeon_write_agp_base(dev_priv, dev->agp->base);
1695
1696                 /* XXX */
1697                 radeon_write_agp_location(dev_priv,
1698                              (((dev_priv->gart_vm_start - 1 +
1699                                 dev_priv->gart_size) & 0xffff0000) |
1700                               (dev_priv->gart_vm_start >> 16)));
1701
1702                 ring_start = (dev_priv->cp_ring->offset
1703                               - dev->agp->base
1704                               + dev_priv->gart_vm_start);
1705         } else
1706 #endif
1707                 ring_start = (dev_priv->cp_ring->offset
1708                               - (unsigned long)dev->sg->virtual
1709                               + dev_priv->gart_vm_start);
1710
1711         RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1712
1713         RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1714
1715         RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1716
1717         /* Initialize the scratch register pointer.  This will cause
1718          * the scratch register values to be written out to memory
1719          * whenever they are updated.
1720          *
1721          * We simply put this behind the ring read pointer, this works
1722          * with PCI GART as well as (whatever kind of) AGP GART
1723          */
1724         {
1725                 u64 scratch_addr;
1726
1727                 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1728                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1729                 scratch_addr += R600_SCRATCH_REG_OFFSET;
1730                 scratch_addr >>= 8;
1731                 scratch_addr &= 0xffffffff;
1732
1733                 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1734         }
1735
1736         RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1737
1738         /* Turn on bus mastering */
1739         radeon_enable_bm(dev_priv);
1740
1741         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1742         RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1743
1744         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1745         RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1746
1747         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1748         RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1749
1750         /* reset sarea copies of these */
1751         if (dev_priv->sarea_priv) {
1752                 dev_priv->sarea_priv->last_frame = 0;
1753                 dev_priv->sarea_priv->last_dispatch = 0;
1754                 dev_priv->sarea_priv->last_clear = 0;
1755         }
1756
1757         r600_do_wait_for_idle(dev_priv);
1758
1759 }
1760
1761 int r600_do_cleanup_cp(struct drm_device *dev)
1762 {
1763         drm_radeon_private_t *dev_priv = dev->dev_private;
1764         DRM_DEBUG("\n");
1765
1766         /* Make sure interrupts are disabled here because the uninstall ioctl
1767          * may not have been called from userspace and after dev_private
1768          * is freed, it's too late.
1769          */
1770         if (dev->irq_enabled)
1771                 drm_irq_uninstall(dev);
1772
1773 #if __OS_HAS_AGP
1774         if (dev_priv->flags & RADEON_IS_AGP) {
1775                 if (dev_priv->cp_ring != NULL) {
1776                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1777                         dev_priv->cp_ring = NULL;
1778                 }
1779                 if (dev_priv->ring_rptr != NULL) {
1780                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1781                         dev_priv->ring_rptr = NULL;
1782                 }
1783                 if (dev->agp_buffer_map != NULL) {
1784                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1785                         dev->agp_buffer_map = NULL;
1786                 }
1787         } else
1788 #endif
1789         {
1790
1791                 if (dev_priv->gart_info.bus_addr)
1792                         r600_page_table_cleanup(dev, &dev_priv->gart_info);
1793
1794                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1795                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1796                         dev_priv->gart_info.addr = 0;
1797                 }
1798         }
1799         /* only clear to the start of flags */
1800         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1801
1802         return 0;
1803 }
1804
1805 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1806                     struct drm_file *file_priv)
1807 {
1808         drm_radeon_private_t *dev_priv = dev->dev_private;
1809
1810         DRM_DEBUG("\n");
1811
1812         /* if we require new memory map but we don't have it fail */
1813         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1814                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1815                 r600_do_cleanup_cp(dev);
1816                 return -EINVAL;
1817         }
1818
1819         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1820                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1821                 dev_priv->flags &= ~RADEON_IS_AGP;
1822                 /* The writeback test succeeds, but when writeback is enabled,
1823                  * the ring buffer read ptr update fails after first 128 bytes.
1824                  */
1825                 radeon_no_wb = 1;
1826         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1827                  && !init->is_pci) {
1828                 DRM_DEBUG("Restoring AGP flag\n");
1829                 dev_priv->flags |= RADEON_IS_AGP;
1830         }
1831
1832         dev_priv->usec_timeout = init->usec_timeout;
1833         if (dev_priv->usec_timeout < 1 ||
1834             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1835                 DRM_DEBUG("TIMEOUT problem!\n");
1836                 r600_do_cleanup_cp(dev);
1837                 return -EINVAL;
1838         }
1839
1840         /* Enable vblank on CRTC1 for older X servers
1841          */
1842         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1843
1844         dev_priv->do_boxes = 0;
1845         dev_priv->cp_mode = init->cp_mode;
1846
1847         /* We don't support anything other than bus-mastering ring mode,
1848          * but the ring can be in either AGP or PCI space for the ring
1849          * read pointer.
1850          */
1851         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1852             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1853                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1854                 r600_do_cleanup_cp(dev);
1855                 return -EINVAL;
1856         }
1857
1858         switch (init->fb_bpp) {
1859         case 16:
1860                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1861                 break;
1862         case 32:
1863         default:
1864                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1865                 break;
1866         }
1867         dev_priv->front_offset = init->front_offset;
1868         dev_priv->front_pitch = init->front_pitch;
1869         dev_priv->back_offset = init->back_offset;
1870         dev_priv->back_pitch = init->back_pitch;
1871
1872         dev_priv->ring_offset = init->ring_offset;
1873         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1874         dev_priv->buffers_offset = init->buffers_offset;
1875         dev_priv->gart_textures_offset = init->gart_textures_offset;
1876
1877         dev_priv->sarea = drm_getsarea(dev);
1878         if (!dev_priv->sarea) {
1879                 DRM_ERROR("could not find sarea!\n");
1880                 r600_do_cleanup_cp(dev);
1881                 return -EINVAL;
1882         }
1883
1884         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1885         if (!dev_priv->cp_ring) {
1886                 DRM_ERROR("could not find cp ring region!\n");
1887                 r600_do_cleanup_cp(dev);
1888                 return -EINVAL;
1889         }
1890         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1891         if (!dev_priv->ring_rptr) {
1892                 DRM_ERROR("could not find ring read pointer!\n");
1893                 r600_do_cleanup_cp(dev);
1894                 return -EINVAL;
1895         }
1896         dev->agp_buffer_token = init->buffers_offset;
1897         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1898         if (!dev->agp_buffer_map) {
1899                 DRM_ERROR("could not find dma buffer region!\n");
1900                 r600_do_cleanup_cp(dev);
1901                 return -EINVAL;
1902         }
1903
1904         if (init->gart_textures_offset) {
1905                 dev_priv->gart_textures =
1906                     drm_core_findmap(dev, init->gart_textures_offset);
1907                 if (!dev_priv->gart_textures) {
1908                         DRM_ERROR("could not find GART texture region!\n");
1909                         r600_do_cleanup_cp(dev);
1910                         return -EINVAL;
1911                 }
1912         }
1913
1914         dev_priv->sarea_priv =
1915             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1916                                     init->sarea_priv_offset);
1917
1918 #if __OS_HAS_AGP
1919         /* XXX */
1920         if (dev_priv->flags & RADEON_IS_AGP) {
1921                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1922                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1923                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1924                 if (!dev_priv->cp_ring->handle ||
1925                     !dev_priv->ring_rptr->handle ||
1926                     !dev->agp_buffer_map->handle) {
1927                         DRM_ERROR("could not find ioremap agp regions!\n");
1928                         r600_do_cleanup_cp(dev);
1929                         return -EINVAL;
1930                 }
1931         } else
1932 #endif
1933         {
1934                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1935                 dev_priv->ring_rptr->handle =
1936                     (void *)dev_priv->ring_rptr->offset;
1937                 dev->agp_buffer_map->handle =
1938                     (void *)dev->agp_buffer_map->offset;
1939
1940                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1941                           dev_priv->cp_ring->handle);
1942                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1943                           dev_priv->ring_rptr->handle);
1944                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1945                           dev->agp_buffer_map->handle);
1946         }
1947
1948         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1949         dev_priv->fb_size =
1950                 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1951                 - dev_priv->fb_location;
1952
1953         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1954                                         ((dev_priv->front_offset
1955                                           + dev_priv->fb_location) >> 10));
1956
1957         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1958                                        ((dev_priv->back_offset
1959                                          + dev_priv->fb_location) >> 10));
1960
1961         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1962                                         ((dev_priv->depth_offset
1963                                           + dev_priv->fb_location) >> 10));
1964
1965         dev_priv->gart_size = init->gart_size;
1966
1967         /* New let's set the memory map ... */
1968         if (dev_priv->new_memmap) {
1969                 u32 base = 0;
1970
1971                 DRM_INFO("Setting GART location based on new memory map\n");
1972
1973                 /* If using AGP, try to locate the AGP aperture at the same
1974                  * location in the card and on the bus, though we have to
1975                  * align it down.
1976                  */
1977 #if __OS_HAS_AGP
1978                 /* XXX */
1979                 if (dev_priv->flags & RADEON_IS_AGP) {
1980                         base = dev->agp->base;
1981                         /* Check if valid */
1982                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1983                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1984                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1985                                          dev->agp->base);
1986                                 base = 0;
1987                         }
1988                 }
1989 #endif
1990                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1991                 if (base == 0) {
1992                         base = dev_priv->fb_location + dev_priv->fb_size;
1993                         if (base < dev_priv->fb_location ||
1994                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1995                                 base = dev_priv->fb_location
1996                                         - dev_priv->gart_size;
1997                 }
1998                 dev_priv->gart_vm_start = base & 0xffc00000u;
1999                 if (dev_priv->gart_vm_start != base)
2000                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2001                                  base, dev_priv->gart_vm_start);
2002         }
2003
2004 #if __OS_HAS_AGP
2005         /* XXX */
2006         if (dev_priv->flags & RADEON_IS_AGP)
2007                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2008                                                  - dev->agp->base
2009                                                  + dev_priv->gart_vm_start);
2010         else
2011 #endif
2012                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2013                                                  - (unsigned long)dev->sg->virtual
2014                                                  + dev_priv->gart_vm_start);
2015
2016         DRM_DEBUG("fb 0x%08x size %d\n",
2017                   (unsigned int) dev_priv->fb_location,
2018                   (unsigned int) dev_priv->fb_size);
2019         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2020         DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2021                   (unsigned int) dev_priv->gart_vm_start);
2022         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2023                   dev_priv->gart_buffers_offset);
2024
2025         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2026         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2027                               + init->ring_size / sizeof(u32));
2028         dev_priv->ring.size = init->ring_size;
2029         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2030
2031         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2032         dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2033
2034         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2035         dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2036
2037         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2038
2039         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2040
2041 #if __OS_HAS_AGP
2042         if (dev_priv->flags & RADEON_IS_AGP) {
2043                 /* XXX turn off pcie gart */
2044         } else
2045 #endif
2046         {
2047                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2048                 /* if we have an offset set from userspace */
2049                 if (!dev_priv->pcigart_offset_set) {
2050                         DRM_ERROR("Need gart offset from userspace\n");
2051                         r600_do_cleanup_cp(dev);
2052                         return -EINVAL;
2053                 }
2054
2055                 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2056
2057                 dev_priv->gart_info.bus_addr =
2058                         dev_priv->pcigart_offset + dev_priv->fb_location;
2059                 dev_priv->gart_info.mapping.offset =
2060                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2061                 dev_priv->gart_info.mapping.size =
2062                         dev_priv->gart_info.table_size;
2063
2064                 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2065                 if (!dev_priv->gart_info.mapping.handle) {
2066                         DRM_ERROR("ioremap failed.\n");
2067                         r600_do_cleanup_cp(dev);
2068                         return -EINVAL;
2069                 }
2070
2071                 dev_priv->gart_info.addr =
2072                         dev_priv->gart_info.mapping.handle;
2073
2074                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2075                           dev_priv->gart_info.addr,
2076                           dev_priv->pcigart_offset);
2077
2078                 if (!r600_page_table_init(dev)) {
2079                         DRM_ERROR("Failed to init GART table\n");
2080                         r600_do_cleanup_cp(dev);
2081                         return -EINVAL;
2082                 }
2083
2084                 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2085                         r700_vm_init(dev);
2086                 else
2087                         r600_vm_init(dev);
2088         }
2089
2090         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2091                 r700_cp_load_microcode(dev_priv);
2092         else
2093                 r600_cp_load_microcode(dev_priv);
2094
2095         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2096
2097         dev_priv->last_buf = 0;
2098
2099         r600_do_engine_reset(dev);
2100         r600_test_writeback(dev_priv);
2101
2102         r600_cs_init(dev);
2103
2104         return 0;
2105 }
2106
2107 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2108 {
2109         drm_radeon_private_t *dev_priv = dev->dev_private;
2110
2111         DRM_DEBUG("\n");
2112         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2113                 r700_vm_init(dev);
2114                 r700_cp_load_microcode(dev_priv);
2115         } else {
2116                 r600_vm_init(dev);
2117                 r600_cp_load_microcode(dev_priv);
2118         }
2119         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2120         r600_do_engine_reset(dev);
2121
2122         return 0;
2123 }
2124
2125 /* Wait for the CP to go idle.
2126  */
2127 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2128 {
2129         RING_LOCALS;
2130         DRM_DEBUG("\n");
2131
2132         BEGIN_RING(5);
2133         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2134         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2135         /* wait for 3D idle clean */
2136         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2137         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2138         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2139
2140         ADVANCE_RING();
2141         COMMIT_RING();
2142
2143         return r600_do_wait_for_idle(dev_priv);
2144 }
2145
2146 /* Start the Command Processor.
2147  */
2148 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2149 {
2150         u32 cp_me;
2151         RING_LOCALS;
2152         DRM_DEBUG("\n");
2153
2154         BEGIN_RING(7);
2155         OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2156         OUT_RING(0x00000001);
2157         if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2158                 OUT_RING(0x00000003);
2159         else
2160                 OUT_RING(0x00000000);
2161         OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2162         OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2163         OUT_RING(0x00000000);
2164         OUT_RING(0x00000000);
2165         ADVANCE_RING();
2166         COMMIT_RING();
2167
2168         /* set the mux and reset the halt bit */
2169         cp_me = 0xff;
2170         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2171
2172         dev_priv->cp_running = 1;
2173
2174 }
2175
2176 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2177 {
2178         u32 cur_read_ptr;
2179         DRM_DEBUG("\n");
2180
2181         cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2182         RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2183         SET_RING_HEAD(dev_priv, cur_read_ptr);
2184         dev_priv->ring.tail = cur_read_ptr;
2185 }
2186
2187 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2188 {
2189         uint32_t cp_me;
2190
2191         DRM_DEBUG("\n");
2192
2193         cp_me = 0xff | R600_CP_ME_HALT;
2194
2195         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2196
2197         dev_priv->cp_running = 0;
2198 }
2199
2200 int r600_cp_dispatch_indirect(struct drm_device *dev,
2201                               struct drm_buf *buf, int start, int end)
2202 {
2203         drm_radeon_private_t *dev_priv = dev->dev_private;
2204         RING_LOCALS;
2205
2206         if (start != end) {
2207                 unsigned long offset = (dev_priv->gart_buffers_offset
2208                                         + buf->offset + start);
2209                 int dwords = (end - start + 3) / sizeof(u32);
2210
2211                 DRM_DEBUG("dwords:%d\n", dwords);
2212                 DRM_DEBUG("offset 0x%lx\n", offset);
2213
2214
2215                 /* Indirect buffer data must be a multiple of 16 dwords.
2216                  * pad the data with a Type-2 CP packet.
2217                  */
2218                 while (dwords & 0xf) {
2219                         u32 *data = (u32 *)
2220                             ((char *)dev->agp_buffer_map->handle
2221                              + buf->offset + start);
2222                         data[dwords++] = RADEON_CP_PACKET2;
2223                 }
2224
2225                 /* Fire off the indirect buffer */
2226                 BEGIN_RING(4);
2227                 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2228                 OUT_RING((offset & 0xfffffffc));
2229                 OUT_RING((upper_32_bits(offset) & 0xff));
2230                 OUT_RING(dwords);
2231                 ADVANCE_RING();
2232         }
2233
2234         return 0;
2235 }
2236
2237 void r600_cp_dispatch_swap(struct drm_device * dev)
2238 {
2239         drm_radeon_private_t *dev_priv = dev->dev_private;
2240         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2241         int nbox = sarea_priv->nbox;
2242         struct drm_clip_rect *pbox = sarea_priv->boxes;
2243         int i, cpp, src_pitch, dst_pitch;
2244         uint64_t src, dst;
2245         RING_LOCALS;
2246         DRM_DEBUG("\n");
2247
2248         if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2249                 cpp = 4;
2250         else
2251                 cpp = 2;
2252
2253         if (dev_priv->sarea_priv->pfCurrentPage == 0) {
2254                 src_pitch = dev_priv->back_pitch;
2255                 dst_pitch = dev_priv->front_pitch;
2256                 src = dev_priv->back_offset + dev_priv->fb_location;
2257                 dst = dev_priv->front_offset + dev_priv->fb_location;
2258         } else {
2259                 src_pitch = dev_priv->front_pitch;
2260                 dst_pitch = dev_priv->back_pitch;
2261                 src = dev_priv->front_offset + dev_priv->fb_location;
2262                 dst = dev_priv->back_offset + dev_priv->fb_location;
2263         }
2264
2265         if (r600_prepare_blit_copy(dev)) {
2266                 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2267                 return;
2268         }
2269         for (i = 0; i < nbox; i++) {
2270                 int x = pbox[i].x1;
2271                 int y = pbox[i].y1;
2272                 int w = pbox[i].x2 - x;
2273                 int h = pbox[i].y2 - y;
2274
2275                 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2276
2277                 r600_blit_swap(dev,
2278                                src, dst,
2279                                x, y, x, y, w, h,
2280                                src_pitch, dst_pitch, cpp);
2281         }
2282         r600_done_blit_copy(dev);
2283
2284         /* Increment the frame counter.  The client-side 3D driver must
2285          * throttle the framerate by waiting for this value before
2286          * performing the swapbuffer ioctl.
2287          */
2288         dev_priv->sarea_priv->last_frame++;
2289
2290         BEGIN_RING(3);
2291         R600_FRAME_AGE(dev_priv->sarea_priv->last_frame);
2292         ADVANCE_RING();
2293 }
2294
2295 int r600_cp_dispatch_texture(struct drm_device * dev,
2296                              struct drm_file *file_priv,
2297                              drm_radeon_texture_t * tex,
2298                              drm_radeon_tex_image_t * image)
2299 {
2300         drm_radeon_private_t *dev_priv = dev->dev_private;
2301         struct drm_buf *buf;
2302         u32 *buffer;
2303         const u8 __user *data;
2304         int size, pass_size;
2305         u64 src_offset, dst_offset;
2306
2307         if (!radeon_check_offset(dev_priv, tex->offset)) {
2308                 DRM_ERROR("Invalid destination offset\n");
2309                 return -EINVAL;
2310         }
2311
2312         /* this might fail for zero-sized uploads - are those illegal? */
2313         if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2314                 DRM_ERROR("Invalid final destination offset\n");
2315                 return -EINVAL;
2316         }
2317
2318         size = tex->height * tex->pitch;
2319
2320         if (size == 0)
2321                 return 0;
2322
2323         dst_offset = tex->offset;
2324
2325         r600_prepare_blit_copy(dev);
2326         do {
2327                 data = (const u8 __user *)image->data;
2328                 pass_size = size;
2329
2330                 buf = radeon_freelist_get(dev);
2331                 if (!buf) {
2332                         DRM_DEBUG("EAGAIN\n");
2333                         if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2334                                 return -EFAULT;
2335                         return -EAGAIN;
2336                 }
2337
2338                 if (pass_size > buf->total)
2339                         pass_size = buf->total;
2340
2341                 /* Dispatch the indirect buffer.
2342                  */
2343                 buffer =
2344                     (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2345
2346                 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2347                         DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2348                         return -EFAULT;
2349                 }
2350
2351                 buf->file_priv = file_priv;
2352                 buf->used = pass_size;
2353                 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2354
2355                 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2356
2357                 radeon_cp_discard_buffer(dev, buf);
2358
2359                 /* Update the input parameters for next time */
2360                 image->data = (const u8 __user *)image->data + pass_size;
2361                 dst_offset += pass_size;
2362                 size -= pass_size;
2363         } while (size > 0);
2364         r600_done_blit_copy(dev);
2365
2366         return 0;
2367 }