2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
39 #include <sys/mplock2.h>
42 #include <vm/vm_param.h>
44 #include <vm/vm_kern.h>
45 #include <vm/vm_extern.h>
47 #include <vm/vm_map.h>
53 #include <machine/smp.h>
54 #include <machine_base/apic/apicreg.h>
55 #include <machine/atomic.h>
56 #include <machine/cpufunc.h>
57 #include <machine_base/apic/lapic.h>
58 #include <machine_base/apic/ioapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/icu/icu_var.h>
69 #include <machine_base/apic/ioapic_abi.h>
70 #include <machine/intr_machdep.h> /* IPIs */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define CMOS_REG (0x70)
77 #define CMOS_DATA (0x71)
78 #define BIOS_RESET (0x0f)
79 #define BIOS_WARM (0x0a)
82 * this code MUST be enabled here and in mpboot.s.
83 * it follows the very early stages of AP boot by placing values in CMOS ram.
84 * it NORMALLY will never be needed and thus the primitive method for enabling.
87 #if defined(CHECK_POINTS)
88 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
89 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
91 #define CHECK_INIT(D); \
92 CHECK_WRITE(0x34, (D)); \
93 CHECK_WRITE(0x35, (D)); \
94 CHECK_WRITE(0x36, (D)); \
95 CHECK_WRITE(0x37, (D)); \
96 CHECK_WRITE(0x38, (D)); \
97 CHECK_WRITE(0x39, (D));
99 #define CHECK_PRINT(S); \
100 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
109 #else /* CHECK_POINTS */
111 #define CHECK_INIT(D)
112 #define CHECK_PRINT(S)
114 #endif /* CHECK_POINTS */
117 * Values to send to the POST hardware.
119 #define MP_BOOTADDRESS_POST 0x10
120 #define MP_PROBE_POST 0x11
121 #define MPTABLE_PASS1_POST 0x12
123 #define MP_START_POST 0x13
124 #define MP_ENABLE_POST 0x14
125 #define MPTABLE_PASS2_POST 0x15
127 #define START_ALL_APS_POST 0x16
128 #define INSTALL_AP_TRAMP_POST 0x17
129 #define START_AP_POST 0x18
131 #define MP_ANNOUNCE_POST 0x19
133 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
134 int current_postcode;
136 /** XXX FIXME: what system files declare these??? */
137 extern struct region_descriptor r_gdt, r_idt;
139 int mp_naps; /* # of Applications processors */
143 extern int64_t tsc_offsets[];
145 #ifdef SMP /* APIC-IO */
146 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
149 /* AP uses this during bootstrap. Do not staticize. */
153 struct pcb stoppcbs[MAXCPU];
155 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
158 * Local data and functions.
161 static u_int boot_address;
162 static int mp_finish;
163 static int mp_finish_lapic;
165 static void mp_enable(u_int boot_addr);
167 static int start_all_aps(u_int boot_addr);
169 static void install_ap_tramp(u_int boot_addr);
171 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
172 static int smitest(void);
173 static void cpu_simple_setup(void);
175 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
176 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
177 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
178 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
179 static u_int bootMP_size;
185 * Calculate usable address in base memory for AP trampoline code.
188 mp_bootaddress(u_int basemem)
190 POSTCODE(MP_BOOTADDRESS_POST);
192 base_memory = basemem;
194 bootMP_size = mptramp_end - mptramp_start;
195 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
196 if (((basemem * 1024) - boot_address) < bootMP_size)
197 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
198 /* 3 levels of page table pages */
199 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
201 return mptramp_pagetables;
205 * Startup the SMP processors.
210 POSTCODE(MP_START_POST);
211 mp_enable(boot_address);
216 * Print various information about the SMP system hardware and setup.
223 POSTCODE(MP_ANNOUNCE_POST);
225 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
226 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
227 for (x = 1; x <= mp_naps; ++x)
228 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
231 kprintf(" Warning: APIC I/O disabled\n");
235 * AP cpu's call this to sync up protected mode.
237 * WARNING! %gs is not set up on entry. This routine sets up %gs.
243 int x, myid = bootAP;
245 struct mdglobaldata *md;
246 struct privatespace *ps;
248 ps = &CPU_prvspace[myid];
250 gdt_segs[GPROC0_SEL].ssd_base =
251 (long) &ps->mdglobaldata.gd_common_tss;
252 ps->mdglobaldata.mi.gd_prvspace = ps;
254 /* We fill the 32-bit segment descriptors */
255 for (x = 0; x < NGDT; x++) {
256 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
257 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
259 /* And now a 64-bit one */
260 ssdtosyssd(&gdt_segs[GPROC0_SEL],
261 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
263 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
264 r_gdt.rd_base = (long) &gdt[myid * NGDT];
265 lgdt(&r_gdt); /* does magic intra-segment return */
267 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
268 wrmsr(MSR_FSBASE, 0); /* User value */
269 wrmsr(MSR_GSBASE, (u_int64_t)ps);
270 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
276 mdcpu->gd_currentldt = _default_ldt;
279 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
280 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
282 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
284 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
286 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
288 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
289 md->gd_common_tssd = *md->gd_tss_gdt;
291 /* double fault stack */
292 md->gd_common_tss.tss_ist1 =
293 (long)&md->mi.gd_prvspace->idlestack[
294 sizeof(md->mi.gd_prvspace->idlestack)];
299 * Set to a known state:
300 * Set by mpboot.s: CR0_PG, CR0_PE
301 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
304 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
307 /* Set up the fast syscall stuff */
308 msr = rdmsr(MSR_EFER) | EFER_SCE;
309 wrmsr(MSR_EFER, msr);
310 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
311 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
312 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
313 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
314 wrmsr(MSR_STAR, msr);
315 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
317 pmap_set_opt(); /* PSE/4MB pages, etc */
319 /* Initialize the PAT MSR. */
323 /* set up CPU registers and state */
326 /* set up SSE/NX registers */
329 /* set up FPU state on the AP */
330 npxinit(__INITIAL_NPXCW__);
332 /* disable the APIC, just to be SURE */
333 lapic->svr &= ~APIC_SVR_ENABLE;
336 /*******************************************************************
337 * local functions and data
341 * start the SMP system
344 mp_enable(u_int boot_addr)
348 POSTCODE(MP_ENABLE_POST);
350 error = lapic_config();
352 if (apic_io_enable) {
354 icu_reinit_noioapic();
360 /* Initialize BSP's local APIC */
363 /* start each Application Processor */
364 start_all_aps(boot_addr);
366 if (apic_io_enable) {
367 error = ioapic_config();
370 icu_reinit_noioapic();
371 lapic_fixup_noioapic();
377 * start each AP in our list
380 start_all_aps(u_int boot_addr)
382 vm_offset_t va = boot_address + KERNBASE;
383 u_int64_t *pt4, *pt3, *pt2;
390 u_long mpbioswarmvec;
391 struct mdglobaldata *gd;
392 struct privatespace *ps;
394 POSTCODE(START_ALL_APS_POST);
396 /* install the AP 1st level boot code */
397 pmap_kenter(va, boot_address);
398 cpu_invlpg((void *)va); /* JG XXX */
399 bcopy(mptramp_start, (void *)va, bootMP_size);
401 /* Locate the page tables, they'll be below the trampoline */
402 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
403 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
404 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
406 /* Create the initial 1GB replicated page tables */
407 for (i = 0; i < 512; i++) {
408 /* Each slot of the level 4 pages points to the same level 3 page */
409 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
410 pt4[i] |= PG_V | PG_RW | PG_U;
412 /* Each slot of the level 3 pages points to the same level 2 page */
413 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
414 pt3[i] |= PG_V | PG_RW | PG_U;
416 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
417 pt2[i] = i * (2 * 1024 * 1024);
418 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
421 /* save the current value of the warm-start vector */
422 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
423 outb(CMOS_REG, BIOS_RESET);
424 mpbiosreason = inb(CMOS_DATA);
426 /* setup a vector to our boot code */
427 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
428 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
429 outb(CMOS_REG, BIOS_RESET);
430 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
433 * If we have a TSC we can figure out the SMI interrupt rate.
434 * The SMI does not necessarily use a constant rate. Spend
435 * up to 250ms trying to figure it out.
438 if (cpu_feature & CPUID_TSC) {
439 set_apic_timer(275000);
440 smilast = read_apic_timer();
441 for (x = 0; x < 20 && read_apic_timer(); ++x) {
442 smicount = smitest();
443 if (smibest == 0 || smilast - smicount < smibest)
444 smibest = smilast - smicount;
447 if (smibest > 250000)
450 smibest = smibest * (int64_t)1000000 /
451 get_apic_timer_frequency();
455 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
456 1000000 / smibest, smibest);
459 for (x = 1; x <= mp_naps; ++x) {
461 /* This is a bit verbose, it will go away soon. */
463 /* first page of AP's private space */
464 pg = x * x86_64_btop(sizeof(struct privatespace));
466 /* allocate new private data page(s) */
467 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
468 MDGLOBALDATA_BASEALLOC_SIZE);
470 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
471 bzero(gd, sizeof(*gd));
472 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
474 /* prime data page for it to use */
475 mi_gdinit(&gd->mi, x);
477 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
478 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
480 /* setup a vector to our boot code */
481 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
482 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
483 outb(CMOS_REG, BIOS_RESET);
484 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
487 * Setup the AP boot stack
489 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
492 /* attempt to start the Application Processor */
493 CHECK_INIT(99); /* setup checkpoints */
494 if (!start_ap(gd, boot_addr, smibest)) {
495 kprintf("\nAP #%d (PHY# %d) failed!\n",
496 x, CPUID_TO_APICID(x));
497 CHECK_PRINT("trace"); /* show checkpoints */
498 /* better panic as the AP may be running loose */
499 kprintf("panic y/n? [y] ");
503 CHECK_PRINT("trace"); /* show checkpoints */
506 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
509 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
510 for (shift = 0; (1 << shift) <= ncpus; ++shift)
513 ncpus2_shift = shift;
515 ncpus2_mask = ncpus2 - 1;
517 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
518 if ((1 << shift) < ncpus)
520 ncpus_fit = 1 << shift;
521 ncpus_fit_mask = ncpus_fit - 1;
523 /* build our map of 'other' CPUs */
524 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
525 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
526 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
528 /* restore the warmstart vector */
529 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
530 outb(CMOS_REG, BIOS_RESET);
531 outb(CMOS_DATA, mpbiosreason);
534 * NOTE! The idlestack for the BSP was setup by locore. Finish
535 * up, clean out the P==V mapping we did earlier.
540 * Wait all APs to finish initializing LAPIC
544 kprintf("SMP: Waiting APs LAPIC initialization\n");
545 if (cpu_feature & CPUID_TSC)
546 tsc0_offset = rdtsc();
549 while (smp_lapic_mask != smp_startup_mask) {
551 if (cpu_feature & CPUID_TSC)
552 tsc0_offset = rdtsc();
554 while (try_mplock() == 0)
557 /* number of APs actually started */
563 * load the 1st level AP boot code into base memory.
566 /* targets for relocation */
567 extern void bigJump(void);
568 extern void bootCodeSeg(void);
569 extern void bootDataSeg(void);
570 extern void MPentry(void);
572 extern u_int mp_gdtbase;
577 install_ap_tramp(u_int boot_addr)
580 int size = *(int *) ((u_long) & bootMP_size);
581 u_char *src = (u_char *) ((u_long) bootMP);
582 u_char *dst = (u_char *) boot_addr + KERNBASE;
583 u_int boot_base = (u_int) bootMP;
588 POSTCODE(INSTALL_AP_TRAMP_POST);
590 for (x = 0; x < size; ++x)
594 * modify addresses in code we just moved to basemem. unfortunately we
595 * need fairly detailed info about mpboot.s for this to work. changes
596 * to mpboot.s might require changes here.
599 /* boot code is located in KERNEL space */
600 dst = (u_char *) boot_addr + KERNBASE;
602 /* modify the lgdt arg */
603 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
604 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
606 /* modify the ljmp target for MPentry() */
607 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
608 *dst32 = ((u_int) MPentry - KERNBASE);
610 /* modify the target for boot code segment */
611 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
612 dst8 = (u_int8_t *) (dst16 + 1);
613 *dst16 = (u_int) boot_addr & 0xffff;
614 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
616 /* modify the target for boot data segment */
617 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
618 dst8 = (u_int8_t *) (dst16 + 1);
619 *dst16 = (u_int) boot_addr & 0xffff;
620 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
626 * This function starts the AP (application processor) identified
627 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
628 * to accomplish this. This is necessary because of the nuances
629 * of the different hardware we might encounter. It ain't pretty,
630 * but it seems to work.
632 * NOTE: eventually an AP gets to ap_init(), which is called just
633 * before the AP goes into the LWKT scheduler's idle loop.
636 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
640 u_long icr_lo, icr_hi;
642 POSTCODE(START_AP_POST);
644 /* get the PHYSICAL APIC ID# */
645 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
647 /* calculate the vector */
648 vector = (boot_addr >> 12) & 0xff;
650 /* We don't want anything interfering */
653 /* Make sure the target cpu sees everything */
657 * Try to detect when a SMI has occurred, wait up to 200ms.
659 * If a SMI occurs during an AP reset but before we issue
660 * the STARTUP command, the AP may brick. To work around
661 * this problem we hold off doing the AP startup until
662 * after we have detected the SMI. Hopefully another SMI
663 * will not occur before we finish the AP startup.
665 * Retries don't seem to help. SMIs have a window of opportunity
666 * and if USB->legacy keyboard emulation is enabled in the BIOS
667 * the interrupt rate can be quite high.
669 * NOTE: Don't worry about the L1 cache load, it might bloat
670 * ldelta a little but ndelta will be so huge when the SMI
671 * occurs the detection logic will still work fine.
674 set_apic_timer(200000);
679 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
680 * and running the target CPU. OR this INIT IPI might be latched (P5
681 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
684 * see apic/apicreg.h for icr bit definitions.
686 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
690 * Setup the address for the target AP. We can setup
691 * icr_hi once and then just trigger operations with
694 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
695 icr_hi |= (physical_cpu << 24);
696 icr_lo = lapic->icr_lo & 0xfff00000;
697 lapic->icr_hi = icr_hi;
700 * Do an INIT IPI: assert RESET
702 * Use edge triggered mode to assert INIT
704 lapic->icr_lo = icr_lo | 0x00004500;
705 while (lapic->icr_lo & APIC_DELSTAT_MASK)
709 * The spec calls for a 10ms delay but we may have to use a
710 * MUCH lower delay to avoid bricking an AP due to a fast SMI
711 * interrupt. We have other loops here too and dividing by 2
712 * doesn't seem to be enough even after subtracting 350us,
715 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
716 * interrupt was detected we use the full 10ms.
720 else if (smibest < 150 * 4 + 350)
722 else if ((smibest - 350) / 4 < 10000)
723 u_sleep((smibest - 350) / 4);
728 * Do an INIT IPI: deassert RESET
730 * Use level triggered mode to deassert. It is unclear
731 * why we need to do this.
733 lapic->icr_lo = icr_lo | 0x00008500;
734 while (lapic->icr_lo & APIC_DELSTAT_MASK)
736 u_sleep(150); /* wait 150us */
739 * Next we do a STARTUP IPI: the previous INIT IPI might still be
740 * latched, (P5 bug) this 1st STARTUP would then terminate
741 * immediately, and the previously started INIT IPI would continue. OR
742 * the previous INIT IPI has already run. and this STARTUP IPI will
743 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
746 lapic->icr_lo = icr_lo | 0x00000600 | vector;
747 while (lapic->icr_lo & APIC_DELSTAT_MASK)
749 u_sleep(200); /* wait ~200uS */
752 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
753 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
754 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
755 * recognized after hardware RESET or INIT IPI.
757 lapic->icr_lo = icr_lo | 0x00000600 | vector;
758 while (lapic->icr_lo & APIC_DELSTAT_MASK)
761 /* Resume normal operation */
764 /* wait for it to start, see ap_init() */
765 set_apic_timer(5000000);/* == 5 seconds */
766 while (read_apic_timer()) {
767 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
768 return 1; /* return SUCCESS */
771 return 0; /* return FAILURE */
786 while (read_apic_timer()) {
788 for (count = 0; count < 100; ++count)
789 ntsc = rdtsc(); /* force loop to occur */
791 ndelta = ntsc - ltsc;
794 if (ndelta > ldelta * 2)
797 ldelta = ntsc - ltsc;
800 return(read_apic_timer());
804 * Synchronously flush the TLB on all other CPU's. The current cpu's
805 * TLB is not flushed. If the caller wishes to flush the current cpu's
806 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
808 * NOTE: If for some reason we were unable to start all cpus we cannot
809 * safely use broadcast IPIs.
812 static cpumask_t smp_invltlb_req;
814 #define SMP_INVLTLB_DEBUG
820 struct mdglobaldata *md = mdcpu;
821 #ifdef SMP_INVLTLB_DEBUG
826 crit_enter_gd(&md->mi);
827 md->gd_invltlb_ret = 0;
828 ++md->mi.gd_cnt.v_smpinvltlb;
829 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
830 #ifdef SMP_INVLTLB_DEBUG
833 if (smp_startup_mask == smp_active_mask) {
834 all_but_self_ipi(XINVLTLB_OFFSET);
836 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
837 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
840 #ifdef SMP_INVLTLB_DEBUG
842 kprintf("smp_invltlb: ipi sent\n");
844 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
845 (smp_active_mask & ~md->mi.gd_cpumask)) {
848 #ifdef SMP_INVLTLB_DEBUG
850 if (++count == 400000000) {
852 kprintf("smp_invltlb: endless loop %08lx %08lx, "
853 "rflags %016jx retry",
854 (long)md->gd_invltlb_ret,
855 (long)smp_invltlb_req,
856 (intmax_t)read_rflags());
857 __asm __volatile ("sti");
862 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
867 kprintf("bcpu %d\n", bcpu);
868 xgd = globaldata_find(bcpu);
869 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
872 Debugger("giving up");
878 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
879 crit_exit_gd(&md->mi);
886 * Called from Xinvltlb assembly with interrupts disabled. We didn't
887 * bother to bump the critical section count or nested interrupt count
888 * so only do very low level operations here.
891 smp_invltlb_intr(void)
893 struct mdglobaldata *md = mdcpu;
894 struct mdglobaldata *omd;
899 mask = smp_invltlb_req;
902 cpu = BSFCPUMASK(mask);
903 mask &= ~CPUMASK(cpu);
904 omd = (struct mdglobaldata *)globaldata_find(cpu);
905 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
912 * When called the executing CPU will send an IPI to all other CPUs
913 * requesting that they halt execution.
915 * Usually (but not necessarily) called with 'other_cpus' as its arg.
917 * - Signals all CPUs in map to stop.
918 * - Waits for each to stop.
925 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
926 * from executing at same time.
929 stop_cpus(cpumask_t map)
931 map &= smp_active_mask;
933 /* send the Xcpustop IPI to all CPUs in map */
934 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
936 while ((stopped_cpus & map) != map)
944 * Called by a CPU to restart stopped CPUs.
946 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
948 * - Signals all CPUs in map to restart.
949 * - Waits for each to restart.
957 restart_cpus(cpumask_t map)
959 /* signal other cpus to restart */
960 started_cpus = map & smp_active_mask;
962 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
969 * This is called once the mpboot code has gotten us properly relocated
970 * and the MMU turned on, etc. ap_init() is actually the idle thread,
971 * and when it returns the scheduler will call the real cpu_idle() main
972 * loop for the idlethread. Interrupts are disabled on entry and should
973 * remain disabled at return.
981 * Adjust smp_startup_mask to signal the BSP that we have started
982 * up successfully. Note that we do not yet hold the BGL. The BSP
983 * is waiting for our signal.
985 * We can't set our bit in smp_active_mask yet because we are holding
986 * interrupts physically disabled and remote cpus could deadlock
987 * trying to send us an IPI.
989 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
993 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
994 * non-zero, then get the MP lock.
996 * Note: We are in a critical section.
998 * Note: we are the idle thread, we can only spin.
1000 * Note: The load fence is memory volatile and prevents the compiler
1001 * from improperly caching mp_finish_lapic, and the cpu from improperly
1004 while (mp_finish_lapic == 0)
1006 while (try_mplock() == 0)
1009 if (cpu_feature & CPUID_TSC) {
1011 * The BSP is constantly updating tsc0_offset, figure out
1012 * the relative difference to synchronize ktrdump.
1014 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1017 /* BSP may have changed PTD while we're waiting for the lock */
1020 /* Build our map of 'other' CPUs. */
1021 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1023 /* A quick check from sanity claus */
1024 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1025 if (mycpu->gd_cpuid != cpu_id) {
1026 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1027 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1028 cpu_id, (lapic->id & 0xff000000) >> 24);
1030 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1032 panic("cpuid mismatch! boom!!");
1035 /* Initialize AP's local APIC for irq's */
1038 /* LAPIC initialization is done */
1039 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1042 /* Let BSP move onto the next initialization stage */
1046 * Interlock for finalization. Wait until mp_finish is non-zero,
1047 * then get the MP lock.
1049 * Note: We are in a critical section.
1051 * Note: we are the idle thread, we can only spin.
1053 * Note: The load fence is memory volatile and prevents the compiler
1054 * from improperly caching mp_finish, and the cpu from improperly
1057 while (mp_finish == 0)
1059 while (try_mplock() == 0)
1062 /* BSP may have changed PTD while we're waiting for the lock */
1065 /* Set memory range attributes for this CPU to match the BSP */
1066 mem_range_AP_init();
1069 * Once we go active we must process any IPIQ messages that may
1070 * have been queued, because no actual IPI will occur until we
1071 * set our bit in the smp_active_mask. If we don't the IPI
1072 * message interlock could be left set which would also prevent
1075 * The idle loop doesn't expect the BGL to be held and while
1076 * lwkt_switch() normally cleans things up this is a special case
1077 * because we returning almost directly into the idle loop.
1079 * The idle thread is never placed on the runq, make sure
1080 * nothing we've done put it there.
1082 KKASSERT(get_mplock_count(curthread) == 1);
1083 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1086 * Enable interrupts here. idle_restore will also do it, but
1087 * doing it here lets us clean up any strays that got posted to
1088 * the CPU during the AP boot while we are still in a critical
1091 __asm __volatile("sti; pause; pause"::);
1092 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1094 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1095 lwkt_process_ipiq();
1098 * Releasing the mp lock lets the BSP finish up the SMP init
1101 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1105 * Get SMP fully working before we start initializing devices.
1113 kprintf("Finish MP startup\n");
1115 while (smp_active_mask != smp_startup_mask)
1117 while (try_mplock() == 0)
1120 kprintf("Active CPU Mask: %016jx\n",
1121 (uintmax_t)smp_active_mask);
1125 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1128 cpu_send_ipiq(int dcpu)
1130 if (CPUMASK(dcpu) & smp_active_mask)
1131 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1134 #if 0 /* single_apic_ipi_passive() not working yet */
1136 * Returns 0 on failure, 1 on success
1139 cpu_send_ipiq_passive(int dcpu)
1142 if (CPUMASK(dcpu) & smp_active_mask) {
1143 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1144 APIC_DELMODE_FIXED);
1151 cpu_simple_setup(void)
1153 /* build our map of 'other' CPUs */
1154 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1155 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1156 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1160 if (cpu_feature & CPUID_TSC)
1161 tsc0_offset = rdtsc();