3 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 2001-2006, Intel Corporation
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived from
20 * this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
35 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
37 * This code is derived from software contributed to The DragonFly Project
38 * by Matthew Dillon <dillon@backplane.com>
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
50 * 3. Neither the name of The DragonFly Project nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific, prior written permission.
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
57 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
58 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
59 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
60 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
61 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
62 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
64 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.51 2006/12/09 01:44:23 swildner Exp $
71 * SERIALIZATION API RULES:
73 * - If the driver uses the same serializer for the interrupt as for the
74 * ifnet, most of the serialization will be done automatically for the
77 * - ifmedia entry points will be serialized by the ifmedia code using the
80 * - if_* entry points except for if_input will be serialized by the IF
81 * and protocol layers.
83 * - The device driver must be sure to serialize access from timeout code
84 * installed by the device driver.
86 * - The device driver typically holds the serializer at the time it wishes
87 * to call if_input. If so, it should pass the serializer to if_input and
88 * note that the serializer might be dropped temporarily by if_input
89 * (e.g. in case it has to bridge the packet to another interface).
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
96 #include "opt_polling.h"
98 #include <dev/netif/em/if_em.h>
99 #include <net/ifq_var.h>
101 /*********************************************************************
102 * Set this to one to display debug statistics
103 *********************************************************************/
104 int em_display_debug_stats = 0;
106 /*********************************************************************
108 *********************************************************************/
110 char em_driver_version[] = "6.1.4";
113 /*********************************************************************
114 * PCI Device ID Table
116 * Used by probe to select devices to load on
117 * Last field stores an index into em_strings
118 * Last entry must be all 0s
120 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
121 *********************************************************************/
123 static em_vendor_info_t em_vendor_info_array[] =
125 /* Intel(R) PRO/1000 Network Connection */
126 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0},
127 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
128 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0},
129 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
130 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0},
132 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0},
133 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0},
134 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
135 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0},
136 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0},
137 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
139 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0},
141 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
142 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
144 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
145 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
146 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
147 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
149 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
150 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
151 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
152 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
153 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
155 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
156 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
157 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
158 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
159 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
160 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
161 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0},
162 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
163 PCI_ANY_ID, PCI_ANY_ID, 0},
165 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0},
166 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0},
168 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
169 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
170 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
171 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
172 PCI_ANY_ID, PCI_ANY_ID, 0},
174 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
175 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
176 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
177 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0},
179 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0},
180 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0},
181 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0},
183 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
184 PCI_ANY_ID, PCI_ANY_ID, 0},
185 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
186 PCI_ANY_ID, PCI_ANY_ID, 0},
187 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
188 PCI_ANY_ID, PCI_ANY_ID, 0},
189 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
190 PCI_ANY_ID, PCI_ANY_ID, 0},
192 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
193 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0},
194 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0},
196 { 0x8086, 0x101A, PCI_ANY_ID, PCI_ANY_ID, 0},
197 { 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0},
198 /* required last entry */
202 /*********************************************************************
203 * Table of branding strings for all supported NICs.
204 *********************************************************************/
206 static const char *em_strings[] = {
207 "Intel(R) PRO/1000 Network Connection"
210 /*********************************************************************
211 * Function prototypes
212 *********************************************************************/
213 static int em_probe(device_t);
214 static int em_attach(device_t);
215 static int em_detach(device_t);
216 static int em_shutdown(device_t);
217 static void em_intr(void *);
218 static void em_start(struct ifnet *);
219 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
220 static void em_watchdog(struct ifnet *);
221 static void em_init(void *);
222 static void em_stop(void *);
223 static void em_media_status(struct ifnet *, struct ifmediareq *);
224 static int em_media_change(struct ifnet *);
225 static void em_identify_hardware(struct adapter *);
226 static int em_allocate_pci_resource(device_t);
227 static void em_free_pci_resource(device_t);
228 static void em_local_timer(void *);
229 static int em_hardware_init(struct adapter *);
230 static void em_setup_interface(device_t, struct adapter *);
231 static int em_setup_transmit_structures(struct adapter *);
232 static void em_initialize_transmit_unit(struct adapter *);
233 static int em_setup_receive_structures(struct adapter *);
234 static void em_initialize_receive_unit(struct adapter *);
235 static void em_enable_intr(struct adapter *);
236 static void em_disable_intr(struct adapter *);
237 static void em_free_transmit_structures(struct adapter *);
238 static void em_free_receive_structures(struct adapter *);
239 static void em_update_stats_counters(struct adapter *);
240 static void em_clean_transmit_interrupts(struct adapter *);
241 static int em_allocate_receive_structures(struct adapter *);
242 static int em_allocate_transmit_structures(struct adapter *);
243 static void em_process_receive_interrupts(struct adapter *, int);
244 static void em_receive_checksum(struct adapter *, struct em_rx_desc *,
246 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *,
247 uint32_t *, uint32_t *);
248 static void em_set_promisc(struct adapter *);
249 static void em_disable_promisc(struct adapter *);
250 static void em_set_multi(struct adapter *);
251 static void em_print_hw_stats(struct adapter *);
252 static void em_print_link_status(struct adapter *);
253 static int em_get_buf(int i, struct adapter *, struct mbuf *, int how);
254 static void em_enable_vlans(struct adapter *);
255 static void em_disable_vlans(struct adapter *);
256 static int em_encap(struct adapter *, struct mbuf *);
257 static void em_smartspeed(struct adapter *);
258 static int em_82547_fifo_workaround(struct adapter *, int);
259 static void em_82547_update_fifo_head(struct adapter *, int);
260 static int em_82547_tx_fifo_reset(struct adapter *);
261 static void em_82547_move_tail(void *);
262 static void em_82547_move_tail_serialized(struct adapter *);
263 static int em_dma_malloc(struct adapter *, bus_size_t,
264 struct em_dma_alloc *, int);
265 static void em_dma_free(struct adapter *, struct em_dma_alloc *);
266 static void em_print_debug_info(struct adapter *);
267 static int em_is_valid_ether_addr(uint8_t *);
268 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
269 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
270 static uint32_t em_fill_descriptors(uint64_t address, uint32_t length,
271 PDESC_ARRAY desc_array);
272 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
273 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
274 static void em_add_int_delay_sysctl(struct adapter *, const char *,
276 struct em_int_delay_info *, int, int);
278 /*********************************************************************
279 * FreeBSD Device Interface Entry Points
280 *********************************************************************/
282 static device_method_t em_methods[] = {
283 /* Device interface */
284 DEVMETHOD(device_probe, em_probe),
285 DEVMETHOD(device_attach, em_attach),
286 DEVMETHOD(device_detach, em_detach),
287 DEVMETHOD(device_shutdown, em_shutdown),
291 static driver_t em_driver = {
292 "em", em_methods, sizeof(struct adapter),
295 static devclass_t em_devclass;
297 DECLARE_DUMMY_MODULE(if_em);
298 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, 0, 0);
300 /*********************************************************************
301 * Tunable default values.
302 *********************************************************************/
304 #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
305 #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
307 static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV);
308 static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR);
309 static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV);
310 static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV);
311 static int em_int_throttle_ceil = 10000;
312 static int em_rxd = EM_DEFAULT_RXD;
313 static int em_txd = EM_DEFAULT_TXD;
314 static int em_smart_pwr_down = FALSE;
316 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt);
317 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt);
318 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt);
319 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt);
320 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
321 TUNABLE_INT("hw.em.rxd", &em_rxd);
322 TUNABLE_INT("hw.em.txd", &em_txd);
323 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
326 * Kernel trace for characterization of operations
328 #if !defined(KTR_IF_EM)
329 #define KTR_IF_EM KTR_ALL
331 KTR_INFO_MASTER(if_em);
332 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0);
333 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0);
334 #ifdef DEVICE_POLLING
335 KTR_INFO(KTR_IF_EM, if_em, poll_beg, 2, "poll begin", 0);
336 KTR_INFO(KTR_IF_EM, if_em, poll_end, 3, "poll end", 0);
338 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0);
339 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0);
340 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0);
341 #define logif(name) KTR_LOG(if_em_ ## name)
343 /*********************************************************************
344 * Device identification routine
346 * em_probe determines if the driver should be loaded on
347 * adapter based on PCI vendor/device id of the adapter.
349 * return 0 on success, positive on failure
350 *********************************************************************/
353 em_probe(device_t dev)
355 em_vendor_info_t *ent;
357 uint16_t pci_vendor_id = 0;
358 uint16_t pci_device_id = 0;
359 uint16_t pci_subvendor_id = 0;
360 uint16_t pci_subdevice_id = 0;
361 char adapter_name[60];
363 INIT_DEBUGOUT("em_probe: begin");
365 pci_vendor_id = pci_get_vendor(dev);
366 if (pci_vendor_id != EM_VENDOR_ID)
369 pci_device_id = pci_get_device(dev);
370 pci_subvendor_id = pci_get_subvendor(dev);
371 pci_subdevice_id = pci_get_subdevice(dev);
373 ent = em_vendor_info_array;
374 while (ent->vendor_id != 0) {
375 if ((pci_vendor_id == ent->vendor_id) &&
376 (pci_device_id == ent->device_id) &&
378 ((pci_subvendor_id == ent->subvendor_id) ||
379 (ent->subvendor_id == PCI_ANY_ID)) &&
381 ((pci_subdevice_id == ent->subdevice_id) ||
382 (ent->subdevice_id == PCI_ANY_ID))) {
383 snprintf(adapter_name, sizeof(adapter_name),
384 "%s, Version - %s", em_strings[ent->index],
386 device_set_desc_copy(dev, adapter_name);
395 /*********************************************************************
396 * Device initialization routine
398 * The attach entry point is called when the driver is being loaded.
399 * This routine identifies the type of hardware, allocates all resources
400 * and initializes the hardware.
402 * return 0 on success, positive on failure
403 *********************************************************************/
406 em_attach(device_t dev)
408 struct adapter *adapter;
412 INIT_DEBUGOUT("em_attach: begin");
414 adapter = device_get_softc(dev);
416 callout_init(&adapter->timer);
417 callout_init(&adapter->tx_fifo_timer);
420 adapter->osdep.dev = dev;
423 sysctl_ctx_init(&adapter->sysctl_ctx);
424 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx,
425 SYSCTL_STATIC_CHILDREN(_hw),
427 device_get_nameunit(dev),
431 if (adapter->sysctl_tree == NULL) {
432 device_printf(dev, "Unable to create sysctl tree\n");
436 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
437 SYSCTL_CHILDREN(adapter->sysctl_tree),
438 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW,
440 em_sysctl_debug_info, "I", "Debug Information");
442 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
443 SYSCTL_CHILDREN(adapter->sysctl_tree),
444 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW,
446 em_sysctl_stats, "I", "Statistics");
448 /* Determine hardware revision */
449 em_identify_hardware(adapter);
451 /* Set up some sysctls for the tunable interrupt delays */
452 em_add_int_delay_sysctl(adapter, "rx_int_delay",
453 "receive interrupt delay in usecs",
454 &adapter->rx_int_delay,
455 E1000_REG_OFFSET(&adapter->hw, RDTR),
456 em_rx_int_delay_dflt);
457 em_add_int_delay_sysctl(adapter, "tx_int_delay",
458 "transmit interrupt delay in usecs",
459 &adapter->tx_int_delay,
460 E1000_REG_OFFSET(&adapter->hw, TIDV),
461 em_tx_int_delay_dflt);
462 if (adapter->hw.mac_type >= em_82540) {
463 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
464 "receive interrupt delay limit in usecs",
465 &adapter->rx_abs_int_delay,
466 E1000_REG_OFFSET(&adapter->hw, RADV),
467 em_rx_abs_int_delay_dflt);
468 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
469 "transmit interrupt delay limit in usecs",
470 &adapter->tx_abs_int_delay,
471 E1000_REG_OFFSET(&adapter->hw, TADV),
472 em_tx_abs_int_delay_dflt);
473 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
474 SYSCTL_CHILDREN(adapter->sysctl_tree),
475 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
476 adapter, 0, em_sysctl_int_throttle, "I", NULL);
480 * Validate number of transmit and receive descriptors. It
481 * must not exceed hardware maximum, and must be multiple
482 * of EM_DBA_ALIGN (128)
484 if (((em_txd * sizeof(struct em_tx_desc)) % EM_DBA_ALIGN) != 0 ||
485 (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) ||
486 (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) ||
487 (em_txd < EM_MIN_TXD)) {
488 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
489 EM_DEFAULT_TXD, em_txd);
490 adapter->num_tx_desc = EM_DEFAULT_TXD;
492 adapter->num_tx_desc = em_txd;
495 if (((em_rxd * sizeof(struct em_rx_desc)) % EM_DBA_ALIGN) != 0 ||
496 (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) ||
497 (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) ||
498 (em_rxd < EM_MIN_RXD)) {
499 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
500 EM_DEFAULT_RXD, em_rxd);
501 adapter->num_rx_desc = EM_DEFAULT_RXD;
503 adapter->num_rx_desc = em_rxd;
506 adapter->hw.autoneg = DO_AUTO_NEG;
507 adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
508 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
509 adapter->hw.tbi_compatibility_en = TRUE;
510 adapter->rx_buffer_len = EM_RXBUFFER_2048;
512 adapter->hw.phy_init_script = 1;
513 adapter->hw.phy_reset_disable = FALSE;
515 #ifndef EM_MASTER_SLAVE
516 adapter->hw.master_slave = em_ms_hw_default;
518 adapter->hw.master_slave = EM_MASTER_SLAVE;
522 * Set the max frame size assuming standard ethernet
525 adapter->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
527 adapter->hw.min_frame_size =
528 MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN;
531 * This controls when hardware reports transmit completion
534 adapter->hw.report_tx_early = 1;
536 error = em_allocate_pci_resource(dev);
540 /* Initialize eeprom parameters */
541 em_init_eeprom_params(&adapter->hw);
543 tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc),
546 /* Allocate Transmit Descriptor ring */
547 if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_WAITOK)) {
548 device_printf(dev, "Unable to allocate TxDescriptor memory\n");
552 adapter->tx_desc_base = (struct em_tx_desc *) adapter->txdma.dma_vaddr;
554 rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc),
557 /* Allocate Receive Descriptor ring */
558 if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_WAITOK)) {
559 device_printf(dev, "Unable to allocate rx_desc memory\n");
563 adapter->rx_desc_base = (struct em_rx_desc *) adapter->rxdma.dma_vaddr;
565 /* Initialize the hardware */
566 if (em_hardware_init(adapter)) {
567 device_printf(dev, "Unable to initialize the hardware\n");
572 /* Copy the permanent MAC address out of the EEPROM */
573 if (em_read_mac_addr(&adapter->hw) < 0) {
575 "EEPROM read error while reading mac address\n");
580 if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) {
581 device_printf(dev, "Invalid mac address\n");
586 /* Setup OS specific network interface */
587 em_setup_interface(dev, adapter);
589 /* Initialize statistics */
590 em_clear_hw_cntrs(&adapter->hw);
591 em_update_stats_counters(adapter);
592 adapter->hw.get_link_status = 1;
593 em_check_for_link(&adapter->hw);
595 /* Print the link status */
596 if (adapter->link_active == 1) {
597 em_get_speed_and_duplex(&adapter->hw, &adapter->link_speed,
598 &adapter->link_duplex);
599 device_printf(dev, "Speed: %d Mbps, Duplex: %s\n",
601 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half");
603 device_printf(dev, "Speed: N/A, Duplex:N/A\n");
606 /* Indicate SOL/IDER usage */
607 if (em_check_phy_reset_block(&adapter->hw)) {
608 device_printf(dev, "PHY reset is blocked due to "
609 "SOL/IDER session.\n");
612 /* Identify 82544 on PCIX */
613 em_get_bus_info(&adapter->hw);
614 if (adapter->hw.bus_type == em_bus_type_pcix &&
615 adapter->hw.mac_type == em_82544)
616 adapter->pcix_82544 = TRUE;
618 adapter->pcix_82544 = FALSE;
620 error = bus_setup_intr(dev, adapter->res_interrupt, INTR_NETSAFE,
622 &adapter->int_handler_tag,
623 adapter->interface_data.ac_if.if_serializer);
625 device_printf(dev, "Error registering interrupt handler!\n");
626 ether_ifdetach(&adapter->interface_data.ac_if);
630 INIT_DEBUGOUT("em_attach: end");
638 /*********************************************************************
639 * Device removal routine
641 * The detach entry point is called when the driver is being removed.
642 * This routine stops the adapter and deallocates all the resources
643 * that were allocated for driver operation.
645 * return 0 on success, positive on failure
646 *********************************************************************/
649 em_detach(device_t dev)
651 struct adapter *adapter = device_get_softc(dev);
653 INIT_DEBUGOUT("em_detach: begin");
655 if (device_is_attached(dev)) {
656 struct ifnet *ifp = &adapter->interface_data.ac_if;
658 lwkt_serialize_enter(ifp->if_serializer);
659 adapter->in_detach = 1;
661 em_phy_hw_reset(&adapter->hw);
662 bus_teardown_intr(dev, adapter->res_interrupt,
663 adapter->int_handler_tag);
664 lwkt_serialize_exit(ifp->if_serializer);
668 bus_generic_detach(dev);
670 em_free_pci_resource(dev);
672 /* Free Transmit Descriptor ring */
673 if (adapter->tx_desc_base != NULL) {
674 em_dma_free(adapter, &adapter->txdma);
675 adapter->tx_desc_base = NULL;
678 /* Free Receive Descriptor ring */
679 if (adapter->rx_desc_base != NULL) {
680 em_dma_free(adapter, &adapter->rxdma);
681 adapter->rx_desc_base = NULL;
684 /* Free sysctl tree */
685 if (adapter->sysctl_tree != NULL) {
686 adapter->sysctl_tree = NULL;
687 sysctl_ctx_free(&adapter->sysctl_ctx);
693 /*********************************************************************
695 * Shutdown entry point
697 **********************************************************************/
700 em_shutdown(device_t dev)
702 struct adapter *adapter = device_get_softc(dev);
703 struct ifnet *ifp = &adapter->interface_data.ac_if;
705 lwkt_serialize_enter(ifp->if_serializer);
707 lwkt_serialize_exit(ifp->if_serializer);
712 /*********************************************************************
713 * Transmit entry point
715 * em_start is called by the stack to initiate a transmit.
716 * The driver will remain in this routine as long as there are
717 * packets to transmit and transmit resources are available.
718 * In case resources are not available stack is notified and
719 * the packet is requeued.
720 **********************************************************************/
723 em_start(struct ifnet *ifp)
726 struct adapter *adapter = ifp->if_softc;
728 ASSERT_SERIALIZED(ifp->if_serializer);
730 if (!adapter->link_active)
732 while (!ifq_is_empty(&ifp->if_snd)) {
733 m_head = ifq_poll(&ifp->if_snd);
739 if (em_encap(adapter, m_head)) {
740 ifp->if_flags |= IFF_OACTIVE;
743 ifq_dequeue(&ifp->if_snd, m_head);
745 /* Send a copy of the frame to the BPF listener */
746 BPF_MTAP(ifp, m_head);
748 /* Set timeout in case hardware has problems transmitting */
749 ifp->if_timer = EM_TX_TIMEOUT;
753 /*********************************************************************
756 * em_ioctl is called when the user wants to configure the
759 * return 0 on success, positive on failure
760 **********************************************************************/
763 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
765 int max_frame_size, mask, error = 0, reinit = 0;
766 struct ifreq *ifr = (struct ifreq *) data;
767 struct adapter *adapter = ifp->if_softc;
768 uint16_t eeprom_data = 0;
770 ASSERT_SERIALIZED(ifp->if_serializer);
772 if (adapter->in_detach)
777 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
778 switch (adapter->hw.mac_type) {
781 * 82573 only supports jumbo frames
782 * if ASPM is disabled.
784 em_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3,
786 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
787 max_frame_size = ETHER_MAX_LEN;
790 /* Allow Jumbo frames */
794 case em_80003es2lan: /* Limit Jumbo Frame size */
795 max_frame_size = 9234;
798 /* ICH8 does not support jumbo frames */
799 max_frame_size = ETHER_MAX_LEN;
802 max_frame_size = MAX_JUMBO_FRAME_SIZE;
806 max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
809 ifp->if_mtu = ifr->ifr_mtu;
810 adapter->hw.max_frame_size =
811 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
816 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS "
817 "(Set Interface Flags)");
818 if (ifp->if_flags & IFF_UP) {
819 if (!(ifp->if_flags & IFF_RUNNING))
821 em_disable_promisc(adapter);
822 em_set_promisc(adapter);
824 if (ifp->if_flags & IFF_RUNNING)
830 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
831 if (ifp->if_flags & IFF_RUNNING) {
832 em_disable_intr(adapter);
833 em_set_multi(adapter);
834 if (adapter->hw.mac_type == em_82542_rev2_0)
835 em_initialize_receive_unit(adapter);
836 #ifdef DEVICE_POLLING
837 /* Do not enable interrupt if polling(4) is enabled */
838 if ((ifp->if_flags & IFF_POLLING) == 0)
840 em_enable_intr(adapter);
845 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA "
846 "(Get/Set Interface Media)");
847 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
850 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)");
851 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
852 if (mask & IFCAP_HWCSUM) {
853 ifp->if_capenable ^= IFCAP_HWCSUM;
856 if (mask & IFCAP_VLAN_HWTAGGING) {
857 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
860 if (reinit && (ifp->if_flags & IFF_RUNNING))
864 error = ether_ioctl(ifp, command, data);
871 /*********************************************************************
872 * Watchdog entry point
874 * This routine is called whenever hardware quits transmitting.
876 **********************************************************************/
879 em_watchdog(struct ifnet *ifp)
881 struct adapter *adapter = ifp->if_softc;
884 * If we are in this routine because of pause frames, then
885 * don't reset the hardware.
887 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) {
888 ifp->if_timer = EM_TX_TIMEOUT;
893 if (em_check_for_link(&adapter->hw))
895 if_printf(ifp, "watchdog timeout -- resetting\n");
897 ifp->if_flags &= ~IFF_RUNNING;
901 adapter->watchdog_timeouts++;
904 /*********************************************************************
907 * This routine is used in two ways. It is used by the stack as
908 * init entry point in network interface structure. It is also used
909 * by the driver as a hw/sw initialization routine to get to a
912 * return 0 on success, positive on failure
913 **********************************************************************/
918 struct adapter *adapter = arg;
920 struct ifnet *ifp = &adapter->interface_data.ac_if;
922 INIT_DEBUGOUT("em_init: begin");
927 * Packet Buffer Allocation (PBA)
928 * Writing PBA sets the receive portion of the buffer
929 * the remainder is used for the transmit buffer.
931 * Devices before the 82547 had a Packet Buffer of 64K.
932 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
933 * After the 82547 the buffer was reduced to 40K.
934 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
935 * Note: default does not leave enough room for Jumbo Frame >10k.
937 switch (adapter->hw.mac_type) {
939 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
940 if (adapter->hw.max_frame_size > EM_RXBUFFER_8192)
941 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
943 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
945 adapter->tx_fifo_head = 0;
946 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
947 adapter->tx_fifo_size =
948 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
950 case em_80003es2lan: /* 80003es2lan: Total Packet Buffer is 48K */
951 case em_82571: /* 82571: Total Packet Buffer is 48K */
952 case em_82572: /* 82572: Total Packet Buffer is 48K */
953 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
955 case em_82573: /* 82573: Total Packet Buffer is 32K */
956 /* Jumbo frames not supported */
957 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
963 /* Devices before 82547 had a Packet Buffer of 64K. */
964 if(adapter->hw.max_frame_size > EM_RXBUFFER_8192)
965 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
967 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
970 INIT_DEBUGOUT1("em_init: pba=%dK",pba);
971 E1000_WRITE_REG(&adapter->hw, PBA, pba);
973 /* Get the latest mac address, User can use a LAA */
974 bcopy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr,
977 /* Initialize the hardware */
978 if (em_hardware_init(adapter)) {
979 if_printf(ifp, "Unable to initialize the hardware\n");
983 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
984 em_enable_vlans(adapter);
986 /* Prepare transmit descriptors and buffers */
987 if (em_setup_transmit_structures(adapter)) {
988 if_printf(ifp, "Could not setup transmit structures\n");
992 em_initialize_transmit_unit(adapter);
994 /* Setup Multicast table */
995 em_set_multi(adapter);
997 /* Prepare receive descriptors and buffers */
998 if (em_setup_receive_structures(adapter)) {
999 if_printf(ifp, "Could not setup receive structures\n");
1003 em_initialize_receive_unit(adapter);
1005 /* Don't loose promiscuous settings */
1006 em_set_promisc(adapter);
1008 ifp->if_flags |= IFF_RUNNING;
1009 ifp->if_flags &= ~IFF_OACTIVE;
1011 if (adapter->hw.mac_type >= em_82543) {
1012 if (ifp->if_capenable & IFCAP_TXCSUM)
1013 ifp->if_hwassist = EM_CHECKSUM_FEATURES;
1015 ifp->if_hwassist = 0;
1018 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1019 em_clear_hw_cntrs(&adapter->hw);
1021 #ifdef DEVICE_POLLING
1022 /* Do not enable interrupt if polling(4) is enabled */
1023 if (ifp->if_flags & IFF_POLLING)
1024 em_disable_intr(adapter);
1027 em_enable_intr(adapter);
1029 /* Don't reset the phy next time init gets called */
1030 adapter->hw.phy_reset_disable = TRUE;
1033 #ifdef DEVICE_POLLING
1036 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1038 struct adapter *adapter = ifp->if_softc;
1043 ASSERT_SERIALIZED(ifp->if_serializer);
1047 em_disable_intr(adapter);
1049 case POLL_DEREGISTER:
1050 em_enable_intr(adapter);
1052 case POLL_AND_CHECK_STATUS:
1053 reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1054 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1055 callout_stop(&adapter->timer);
1056 adapter->hw.get_link_status = 1;
1057 em_check_for_link(&adapter->hw);
1058 em_print_link_status(adapter);
1059 callout_reset(&adapter->timer, hz, em_local_timer,
1064 if (ifp->if_flags & IFF_RUNNING) {
1065 em_process_receive_interrupts(adapter, count);
1066 em_clean_transmit_interrupts(adapter);
1068 if (!ifq_is_empty(&ifp->if_snd))
1076 #endif /* DEVICE_POLLING */
1078 /*********************************************************************
1080 * Interrupt Service routine
1082 **********************************************************************/
1088 struct adapter *adapter = arg;
1090 ifp = &adapter->interface_data.ac_if;
1093 ASSERT_SERIALIZED(ifp->if_serializer);
1095 reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1096 if ((adapter->hw.mac_type >= em_82571 &&
1097 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1103 if (reg_icr & E1000_ICR_RXO)
1104 adapter->rx_overruns++;
1106 /* Link status change */
1107 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1108 callout_stop(&adapter->timer);
1109 adapter->hw.get_link_status = 1;
1110 em_check_for_link(&adapter->hw);
1111 em_print_link_status(adapter);
1112 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1116 * note: do not attempt to improve efficiency by looping. This
1117 * only results in unnecessary piecemeal collection of received
1118 * packets and unnecessary piecemeal cleanups of the transmit ring.
1120 if (ifp->if_flags & IFF_RUNNING) {
1121 em_process_receive_interrupts(adapter, -1);
1122 em_clean_transmit_interrupts(adapter);
1125 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1130 /*********************************************************************
1132 * Media Ioctl callback
1134 * This routine is called whenever the user queries the status of
1135 * the interface using ifconfig.
1137 **********************************************************************/
1139 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1141 struct adapter * adapter = ifp->if_softc;
1142 u_char fiber_type = IFM_1000_SX;
1144 INIT_DEBUGOUT("em_media_status: begin");
1146 ASSERT_SERIALIZED(ifp->if_serializer);
1148 em_check_for_link(&adapter->hw);
1149 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
1150 if (adapter->link_active == 0) {
1151 em_get_speed_and_duplex(&adapter->hw,
1152 &adapter->link_speed,
1153 &adapter->link_duplex);
1154 adapter->link_active = 1;
1157 if (adapter->link_active == 1) {
1158 adapter->link_speed = 0;
1159 adapter->link_duplex = 0;
1160 adapter->link_active = 0;
1164 ifmr->ifm_status = IFM_AVALID;
1165 ifmr->ifm_active = IFM_ETHER;
1167 if (!adapter->link_active)
1170 ifmr->ifm_status |= IFM_ACTIVE;
1172 if (adapter->hw.media_type == em_media_type_fiber ||
1173 adapter->hw.media_type == em_media_type_internal_serdes) {
1174 if (adapter->hw.mac_type == em_82545)
1175 fiber_type = IFM_1000_LX;
1176 ifmr->ifm_active |= fiber_type | IFM_FDX;
1177 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1179 switch (adapter->link_speed) {
1181 ifmr->ifm_active |= IFM_10_T;
1184 ifmr->ifm_active |= IFM_100_TX;
1187 ifmr->ifm_active |= IFM_1000_T;
1190 if (adapter->link_duplex == FULL_DUPLEX)
1191 ifmr->ifm_active |= IFM_FDX;
1193 ifmr->ifm_active |= IFM_HDX;
1197 /*********************************************************************
1199 * Media Ioctl callback
1201 * This routine is called when the user changes speed/duplex using
1202 * media/mediopt option with ifconfig.
1204 **********************************************************************/
1206 em_media_change(struct ifnet *ifp)
1208 struct adapter * adapter = ifp->if_softc;
1209 struct ifmedia *ifm = &adapter->media;
1211 INIT_DEBUGOUT("em_media_change: begin");
1213 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1216 ASSERT_SERIALIZED(ifp->if_serializer);
1218 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1220 adapter->hw.autoneg = DO_AUTO_NEG;
1221 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1226 adapter->hw.autoneg = DO_AUTO_NEG;
1227 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
1230 adapter->hw.autoneg = FALSE;
1231 adapter->hw.autoneg_advertised = 0;
1232 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1233 adapter->hw.forced_speed_duplex = em_100_full;
1235 adapter->hw.forced_speed_duplex = em_100_half;
1238 adapter->hw.autoneg = FALSE;
1239 adapter->hw.autoneg_advertised = 0;
1240 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1241 adapter->hw.forced_speed_duplex = em_10_full;
1243 adapter->hw.forced_speed_duplex = em_10_half;
1246 if_printf(ifp, "Unsupported media type\n");
1249 * As the speed/duplex settings may have changed we need to
1252 adapter->hw.phy_reset_disable = FALSE;
1260 em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize,
1263 struct em_q *q = arg;
1267 KASSERT(nsegs <= EM_MAX_SCATTER,
1268 ("Too many DMA segments returned when mapping tx packet"));
1270 bcopy(seg, q->segs, nsegs * sizeof(seg[0]));
1273 /*********************************************************************
1275 * This routine maps the mbufs to tx descriptors.
1277 * return 0 on success, positive on failure
1278 **********************************************************************/
1280 em_encap(struct adapter *adapter, struct mbuf *m_head)
1283 uint32_t txd_lower, txd_used = 0, txd_saved = 0;
1287 /* For 82544 Workaround */
1288 DESC_ARRAY desc_array;
1289 uint32_t array_elements;
1292 struct ifvlan *ifv = NULL;
1294 struct em_buffer *tx_buffer = NULL, *tx_buffer_map;
1296 struct em_tx_desc *current_tx_desc = NULL;
1297 struct ifnet *ifp = &adapter->interface_data.ac_if;
1300 * Force a cleanup if number of TX descriptors
1301 * available hits the threshold
1303 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1304 em_clean_transmit_interrupts(adapter);
1305 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1306 adapter->no_tx_desc_avail1++;
1311 * Map the packet for DMA.
1313 tx_buffer_map = &adapter->tx_buffer_area[adapter->next_avail_tx_desc];
1314 map = tx_buffer_map->map;
1315 error = bus_dmamap_load_mbuf(adapter->txtag, map, m_head, em_tx_cb,
1316 &q, BUS_DMA_NOWAIT);
1318 adapter->no_tx_dma_setup++;
1321 KASSERT(q.nsegs != 0, ("em_encap: empty packet"));
1323 if (q.nsegs > adapter->num_tx_desc_avail) {
1324 adapter->no_tx_desc_avail2++;
1329 if (ifp->if_hwassist > 0) {
1330 em_transmit_checksum_setup(adapter, m_head,
1331 &txd_upper, &txd_lower);
1333 txd_upper = txd_lower = 0;
1336 /* Find out if we are in vlan mode */
1337 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1338 m_head->m_pkthdr.rcvif != NULL &&
1339 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1340 ifv = m_head->m_pkthdr.rcvif->if_softc;
1342 i = adapter->next_avail_tx_desc;
1343 if (adapter->pcix_82544) {
1347 for (j = 0; j < q.nsegs; j++) {
1348 /* If adapter is 82544 and on PCIX bus */
1349 if(adapter->pcix_82544) {
1351 address = htole64(q.segs[j].ds_addr);
1353 * Check the Address and Length combination and
1354 * split the data accordingly
1356 array_elements = em_fill_descriptors(address,
1357 htole32(q.segs[j].ds_len),
1359 for (counter = 0; counter < array_elements; counter++) {
1360 if (txd_used == adapter->num_tx_desc_avail) {
1361 adapter->next_avail_tx_desc = txd_saved;
1362 adapter->no_tx_desc_avail2++;
1366 tx_buffer = &adapter->tx_buffer_area[i];
1367 current_tx_desc = &adapter->tx_desc_base[i];
1368 current_tx_desc->buffer_addr = htole64(
1369 desc_array.descriptor[counter].address);
1370 current_tx_desc->lower.data = htole32(
1371 (adapter->txd_cmd | txd_lower |
1372 (uint16_t)desc_array.descriptor[counter].length));
1373 current_tx_desc->upper.data = htole32((txd_upper));
1374 if (++i == adapter->num_tx_desc)
1377 tx_buffer->m_head = NULL;
1381 tx_buffer = &adapter->tx_buffer_area[i];
1382 current_tx_desc = &adapter->tx_desc_base[i];
1384 current_tx_desc->buffer_addr = htole64(q.segs[j].ds_addr);
1385 current_tx_desc->lower.data = htole32(
1386 adapter->txd_cmd | txd_lower | q.segs[j].ds_len);
1387 current_tx_desc->upper.data = htole32(txd_upper);
1389 if (++i == adapter->num_tx_desc)
1392 tx_buffer->m_head = NULL;
1396 adapter->next_avail_tx_desc = i;
1397 if (adapter->pcix_82544)
1398 adapter->num_tx_desc_avail -= txd_used;
1400 adapter->num_tx_desc_avail -= q.nsegs;
1403 /* Set the vlan id */
1404 current_tx_desc->upper.fields.special = htole16(ifv->ifv_tag);
1406 /* Tell hardware to add tag */
1407 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE);
1410 tx_buffer->m_head = m_head;
1411 tx_buffer_map->map = tx_buffer->map;
1412 tx_buffer->map = map;
1413 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1416 * Last Descriptor of Packet needs End Of Packet (EOP)
1418 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP);
1420 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
1421 BUS_DMASYNC_PREWRITE);
1424 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
1425 * that this frame is available to transmit.
1427 if (adapter->hw.mac_type == em_82547 &&
1428 adapter->link_duplex == HALF_DUPLEX) {
1429 em_82547_move_tail_serialized(adapter);
1431 E1000_WRITE_REG(&adapter->hw, TDT, i);
1432 if (adapter->hw.mac_type == em_82547) {
1433 em_82547_update_fifo_head(adapter,
1434 m_head->m_pkthdr.len);
1440 bus_dmamap_unload(adapter->txtag, map);
1444 /*********************************************************************
1446 * 82547 workaround to avoid controller hang in half-duplex environment.
1447 * The workaround is to avoid queuing a large packet that would span
1448 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1449 * in this case. We do that only when FIFO is quiescent.
1451 **********************************************************************/
1453 em_82547_move_tail(void *arg)
1455 struct adapter *adapter = arg;
1456 struct ifnet *ifp = &adapter->interface_data.ac_if;
1458 lwkt_serialize_enter(ifp->if_serializer);
1459 em_82547_move_tail_serialized(adapter);
1460 lwkt_serialize_exit(ifp->if_serializer);
1464 em_82547_move_tail_serialized(struct adapter *adapter)
1468 struct em_tx_desc *tx_desc;
1469 uint16_t length = 0;
1472 hw_tdt = E1000_READ_REG(&adapter->hw, TDT);
1473 sw_tdt = adapter->next_avail_tx_desc;
1475 while (hw_tdt != sw_tdt) {
1476 tx_desc = &adapter->tx_desc_base[hw_tdt];
1477 length += tx_desc->lower.flags.length;
1478 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1479 if(++hw_tdt == adapter->num_tx_desc)
1483 if (em_82547_fifo_workaround(adapter, length)) {
1484 adapter->tx_fifo_wrk_cnt++;
1485 callout_reset(&adapter->tx_fifo_timer, 1,
1486 em_82547_move_tail, adapter);
1489 E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt);
1490 em_82547_update_fifo_head(adapter, length);
1497 em_82547_fifo_workaround(struct adapter *adapter, int len)
1499 int fifo_space, fifo_pkt_len;
1501 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1503 if (adapter->link_duplex == HALF_DUPLEX) {
1504 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1506 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1507 if (em_82547_tx_fifo_reset(adapter))
1518 em_82547_update_fifo_head(struct adapter *adapter, int len)
1520 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1522 /* tx_fifo_head is always 16 byte aligned */
1523 adapter->tx_fifo_head += fifo_pkt_len;
1524 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1525 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1529 em_82547_tx_fifo_reset(struct adapter *adapter)
1533 if ( (E1000_READ_REG(&adapter->hw, TDT) ==
1534 E1000_READ_REG(&adapter->hw, TDH)) &&
1535 (E1000_READ_REG(&adapter->hw, TDFT) ==
1536 E1000_READ_REG(&adapter->hw, TDFH)) &&
1537 (E1000_READ_REG(&adapter->hw, TDFTS) ==
1538 E1000_READ_REG(&adapter->hw, TDFHS)) &&
1539 (E1000_READ_REG(&adapter->hw, TDFPC) == 0)) {
1541 /* Disable TX unit */
1542 tctl = E1000_READ_REG(&adapter->hw, TCTL);
1543 E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN);
1545 /* Reset FIFO pointers */
1546 E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr);
1547 E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr);
1548 E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr);
1549 E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr);
1551 /* Re-enable TX unit */
1552 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
1553 E1000_WRITE_FLUSH(&adapter->hw);
1555 adapter->tx_fifo_head = 0;
1556 adapter->tx_fifo_reset_cnt++;
1565 em_set_promisc(struct adapter *adapter)
1568 struct ifnet *ifp = &adapter->interface_data.ac_if;
1570 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1572 adapter->em_insert_vlan_header = 0;
1573 if (ifp->if_flags & IFF_PROMISC) {
1574 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1575 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1578 * Disable VLAN stripping in promiscous mode.
1579 * This enables bridging of vlan tagged frames to occur
1580 * and also allows vlan tags to be seen in tcpdump.
1582 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1583 em_disable_vlans(adapter);
1584 adapter->em_insert_vlan_header = 1;
1585 } else if (ifp->if_flags & IFF_ALLMULTI) {
1586 reg_rctl |= E1000_RCTL_MPE;
1587 reg_rctl &= ~E1000_RCTL_UPE;
1588 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1593 em_disable_promisc(struct adapter *adapter)
1595 struct ifnet *ifp = &adapter->interface_data.ac_if;
1599 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1601 reg_rctl &= (~E1000_RCTL_UPE);
1602 reg_rctl &= (~E1000_RCTL_MPE);
1603 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1605 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1606 em_enable_vlans(adapter);
1607 adapter->em_insert_vlan_header = 0;
1610 /*********************************************************************
1613 * This routine is called whenever multicast address list is updated.
1615 **********************************************************************/
1618 em_set_multi(struct adapter *adapter)
1620 uint32_t reg_rctl = 0;
1621 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS];
1622 struct ifmultiaddr *ifma;
1624 struct ifnet *ifp = &adapter->interface_data.ac_if;
1626 IOCTL_DEBUGOUT("em_set_multi: begin");
1628 if (adapter->hw.mac_type == em_82542_rev2_0) {
1629 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1630 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1631 em_pci_clear_mwi(&adapter->hw);
1632 reg_rctl |= E1000_RCTL_RST;
1633 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1637 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1638 if (ifma->ifma_addr->sa_family != AF_LINK)
1641 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1644 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1645 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS);
1649 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1650 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1651 reg_rctl |= E1000_RCTL_MPE;
1652 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1654 em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1);
1657 if (adapter->hw.mac_type == em_82542_rev2_0) {
1658 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1659 reg_rctl &= ~E1000_RCTL_RST;
1660 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1662 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1663 em_pci_set_mwi(&adapter->hw);
1667 /*********************************************************************
1670 * This routine checks for link status and updates statistics.
1672 **********************************************************************/
1675 em_local_timer(void *arg)
1678 struct adapter *adapter = arg;
1679 ifp = &adapter->interface_data.ac_if;
1681 lwkt_serialize_enter(ifp->if_serializer);
1683 em_check_for_link(&adapter->hw);
1684 em_print_link_status(adapter);
1685 em_update_stats_counters(adapter);
1686 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING)
1687 em_print_hw_stats(adapter);
1688 em_smartspeed(adapter);
1690 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1692 lwkt_serialize_exit(ifp->if_serializer);
1696 em_print_link_status(struct adapter *adapter)
1698 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
1699 if (adapter->link_active == 0) {
1700 em_get_speed_and_duplex(&adapter->hw,
1701 &adapter->link_speed,
1702 &adapter->link_duplex);
1703 /* Check if we may set SPEED_MODE bit on PCI-E */
1704 if ((adapter->link_speed == SPEED_1000) &&
1705 ((adapter->hw.mac_type == em_82571) ||
1706 (adapter->hw.mac_type == em_82572))) {
1709 #define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
1711 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
1712 tarc0 |= SPEED_MODE_BIT;
1713 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
1715 #undef SPEED_MODE_BIT
1718 if_printf(&adapter->interface_data.ac_if,
1719 "Link is up %d Mbps %s\n",
1720 adapter->link_speed,
1721 adapter->link_duplex == FULL_DUPLEX ?
1722 "Full Duplex" : "Half Duplex");
1724 adapter->link_active = 1;
1725 adapter->smartspeed = 0;
1728 if (adapter->link_active == 1) {
1729 adapter->link_speed = 0;
1730 adapter->link_duplex = 0;
1732 if_printf(&adapter->interface_data.ac_if,
1735 adapter->link_active = 0;
1740 /*********************************************************************
1742 * This routine disables all traffic on the adapter by issuing a
1743 * global reset on the MAC and deallocates TX/RX buffers.
1745 **********************************************************************/
1751 struct adapter * adapter = arg;
1752 ifp = &adapter->interface_data.ac_if;
1754 ASSERT_SERIALIZED(ifp->if_serializer);
1756 INIT_DEBUGOUT("em_stop: begin");
1757 em_disable_intr(adapter);
1758 em_reset_hw(&adapter->hw);
1759 callout_stop(&adapter->timer);
1760 callout_stop(&adapter->tx_fifo_timer);
1761 em_free_transmit_structures(adapter);
1762 em_free_receive_structures(adapter);
1764 /* Tell the stack that the interface is no longer active */
1765 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1769 /*********************************************************************
1771 * Determine hardware revision.
1773 **********************************************************************/
1775 em_identify_hardware(struct adapter * adapter)
1777 device_t dev = adapter->dev;
1779 /* Make sure our PCI config space has the necessary stuff set */
1780 adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1781 if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
1782 (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) {
1783 device_printf(dev, "Memory Access and/or Bus Master bits "
1785 adapter->hw.pci_cmd_word |= (PCIM_CMD_BUSMASTEREN |
1787 pci_write_config(dev, PCIR_COMMAND,
1788 adapter->hw.pci_cmd_word, 2);
1791 /* Save off the information about this board */
1792 adapter->hw.vendor_id = pci_get_vendor(dev);
1793 adapter->hw.device_id = pci_get_device(dev);
1794 adapter->hw.revision_id = pci_get_revid(dev);
1795 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
1796 adapter->hw.subsystem_id = pci_get_subdevice(dev);
1798 /* Identify the MAC */
1799 if (em_set_mac_type(&adapter->hw))
1800 device_printf(dev, "Unknown MAC Type\n");
1802 if (adapter->hw.mac_type == em_82541 ||
1803 adapter->hw.mac_type == em_82541_rev_2 ||
1804 adapter->hw.mac_type == em_82547 ||
1805 adapter->hw.mac_type == em_82547_rev_2)
1806 adapter->hw.phy_init_script = TRUE;
1810 em_allocate_pci_resource(device_t dev)
1812 struct adapter *adapter = device_get_softc(dev);
1816 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1818 if (!(adapter->res_memory)) {
1819 device_printf(dev, "Unable to allocate bus resource: memory\n");
1822 adapter->osdep.mem_bus_space_tag =
1823 rman_get_bustag(adapter->res_memory);
1824 adapter->osdep.mem_bus_space_handle =
1825 rman_get_bushandle(adapter->res_memory);
1826 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
1828 if (adapter->hw.mac_type > em_82543) {
1831 /* Figure our where our IO BAR is ? */
1833 for (i = 0; i < 5; i++) {
1834 val = pci_read_config(dev, rid, 4);
1835 if (val & 0x00000001) {
1836 adapter->io_rid = rid;
1842 adapter->res_ioport = bus_alloc_resource_any(dev,
1843 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1844 if (!(adapter->res_ioport)) {
1845 device_printf(dev, "Unable to allocate bus resource: "
1850 adapter->hw.reg_io_tag = rman_get_bustag(adapter->res_ioport);
1851 adapter->hw.reg_io_handle =
1852 rman_get_bushandle(adapter->res_ioport);
1855 /* For ICH8 we need to find the flash memory */
1856 if (adapter->hw.mac_type == em_ich8lan) {
1859 adapter->flash_mem = bus_alloc_resource_any(dev,
1860 SYS_RES_MEMORY, &rid, RF_ACTIVE);
1861 if (adapter->flash_mem == NULL) {
1862 device_printf(dev, "Unable to allocate bus resource: "
1866 adapter->osdep.flash_bus_space_tag =
1867 rman_get_bustag(adapter->flash_mem);
1868 adapter->osdep.flash_bus_space_handle =
1869 rman_get_bushandle(adapter->flash_mem);
1873 adapter->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1874 &rid, RF_SHAREABLE | RF_ACTIVE);
1875 if (!(adapter->res_interrupt)) {
1876 device_printf(dev, "Unable to allocate bus resource: "
1881 adapter->hw.back = &adapter->osdep;
1887 em_free_pci_resource(device_t dev)
1889 struct adapter *adapter = device_get_softc(dev);
1891 if (adapter->res_interrupt != NULL) {
1892 bus_release_resource(dev, SYS_RES_IRQ, 0,
1893 adapter->res_interrupt);
1895 if (adapter->res_memory != NULL) {
1896 bus_release_resource(dev, SYS_RES_MEMORY, EM_MMBA,
1897 adapter->res_memory);
1900 if (adapter->res_ioport != NULL) {
1901 bus_release_resource(dev, SYS_RES_IOPORT, adapter->io_rid,
1902 adapter->res_ioport);
1905 if (adapter->flash_mem != NULL) {
1906 bus_release_resource(dev, SYS_RES_MEMORY, EM_FLASH,
1907 adapter->flash_mem);
1911 /*********************************************************************
1913 * Initialize the hardware to a configuration as specified by the
1914 * adapter structure. The controller is reset, the EEPROM is
1915 * verified, the MAC address is set, then the shared initialization
1916 * routines are called.
1918 **********************************************************************/
1920 em_hardware_init(struct adapter *adapter)
1922 uint16_t rx_buffer_size;
1924 INIT_DEBUGOUT("em_hardware_init: begin");
1925 /* Issue a global reset */
1926 em_reset_hw(&adapter->hw);
1928 /* When hardware is reset, fifo_head is also reset */
1929 adapter->tx_fifo_head = 0;
1931 /* Make sure we have a good EEPROM before we read from it */
1932 if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
1933 device_printf(adapter->dev,
1934 "The EEPROM Checksum Is Not Valid\n");
1938 if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) {
1939 device_printf(adapter->dev,
1940 "EEPROM read error while reading part number\n");
1944 /* Set up smart power down as default off on newer adapters */
1945 if (!em_smart_pwr_down &&
1946 (adapter->hw.mac_type == em_82571 ||
1947 adapter->hw.mac_type == em_82572)) {
1948 uint16_t phy_tmp = 0;
1950 /* Speed up time to link by disabling smart power down */
1951 em_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
1953 phy_tmp &= ~IGP02E1000_PM_SPD;
1954 em_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
1959 * These parameters control the automatic generation (Tx) and
1960 * response(Rx) to Ethernet PAUSE frames.
1961 * - High water mark should allow for at least two frames to be
1962 * received after sending an XOFF.
1963 * - Low water mark works best when it is very near the high water mark.
1964 * This allows the receiver to restart by sending XON when it has
1965 * drained a bit. Here we use an arbitary value of 1500 which will
1966 * restart after one full frame is pulled from the buffer. There
1967 * could be several smaller frames in the buffer and if so they will
1968 * not trigger the XON until their total number reduces the buffer
1970 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1972 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10);
1974 adapter->hw.fc_high_water =
1975 rx_buffer_size - roundup2(1 * adapter->hw.max_frame_size, 1024);
1976 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500;
1977 if (adapter->hw.mac_type == em_80003es2lan)
1978 adapter->hw.fc_pause_time = 0xFFFF;
1980 adapter->hw.fc_pause_time = 0x1000;
1981 adapter->hw.fc_send_xon = TRUE;
1982 adapter->hw.fc = em_fc_full;
1984 if (em_init_hw(&adapter->hw) < 0) {
1985 device_printf(adapter->dev, "Hardware Initialization Failed");
1989 em_check_for_link(&adapter->hw);
1991 * At the time this code runs copper NICS fail, but fiber
1992 * succeed, however, this causes a problem downstream,
1993 * so for now have fiber NICs just not do this, then
1994 * everything seems to work correctly.
1996 if ((adapter->hw.media_type != em_media_type_fiber &&
1997 adapter->hw.media_type != em_media_type_internal_serdes) &&
1998 (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU))
1999 adapter->link_active = 1;
2001 adapter->link_active = 0;
2003 if (adapter->link_active) {
2004 em_get_speed_and_duplex(&adapter->hw,
2005 &adapter->link_speed,
2006 &adapter->link_duplex);
2008 adapter->link_speed = 0;
2009 adapter->link_duplex = 0;
2015 /*********************************************************************
2017 * Setup networking device structure and register an interface.
2019 **********************************************************************/
2021 em_setup_interface(device_t dev, struct adapter *adapter)
2024 u_char fiber_type = IFM_1000_SX; /* default type */
2025 INIT_DEBUGOUT("em_setup_interface: begin");
2027 ifp = &adapter->interface_data.ac_if;
2028 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2029 ifp->if_mtu = ETHERMTU;
2030 ifp->if_baudrate = 1000000000;
2031 ifp->if_init = em_init;
2032 ifp->if_softc = adapter;
2033 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2034 ifp->if_ioctl = em_ioctl;
2035 ifp->if_start = em_start;
2036 #ifdef DEVICE_POLLING
2037 ifp->if_poll = em_poll;
2039 ifp->if_watchdog = em_watchdog;
2040 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
2041 ifq_set_ready(&ifp->if_snd);
2043 if (adapter->hw.mac_type >= em_82543)
2044 ifp->if_capabilities |= IFCAP_HWCSUM;
2046 ifp->if_capenable = ifp->if_capabilities;
2048 ether_ifattach(ifp, adapter->hw.mac_addr, NULL);
2051 * Tell the upper layer(s) we support long frames.
2053 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2054 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2057 * Specify the media types supported by this adapter and register
2058 * callbacks to update media and link information
2060 ifmedia_init(&adapter->media, IFM_IMASK, em_media_change,
2062 if (adapter->hw.media_type == em_media_type_fiber ||
2063 adapter->hw.media_type == em_media_type_internal_serdes) {
2064 if (adapter->hw.mac_type == em_82545)
2065 fiber_type = IFM_1000_LX;
2066 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
2068 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type,
2071 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2072 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2074 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2076 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2078 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
2080 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2082 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2083 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2086 /*********************************************************************
2088 * Workaround for SmartSpeed on 82541 and 82547 controllers
2090 **********************************************************************/
2092 em_smartspeed(struct adapter *adapter)
2096 if (adapter->link_active || (adapter->hw.phy_type != em_phy_igp) ||
2097 !adapter->hw.autoneg ||
2098 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
2101 if (adapter->smartspeed == 0) {
2103 * If Master/Slave config fault is asserted twice,
2104 * we assume back-to-back.
2106 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2107 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2109 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2110 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2111 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL,
2113 if (phy_tmp & CR_1000T_MS_ENABLE) {
2114 phy_tmp &= ~CR_1000T_MS_ENABLE;
2115 em_write_phy_reg(&adapter->hw,
2116 PHY_1000T_CTRL, phy_tmp);
2117 adapter->smartspeed++;
2118 if (adapter->hw.autoneg &&
2119 !em_phy_setup_autoneg(&adapter->hw) &&
2120 !em_read_phy_reg(&adapter->hw, PHY_CTRL,
2122 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2123 MII_CR_RESTART_AUTO_NEG);
2124 em_write_phy_reg(&adapter->hw,
2130 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2131 /* If still no link, perhaps using 2/3 pair cable */
2132 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2133 phy_tmp |= CR_1000T_MS_ENABLE;
2134 em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2135 if (adapter->hw.autoneg &&
2136 !em_phy_setup_autoneg(&adapter->hw) &&
2137 !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) {
2138 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2139 MII_CR_RESTART_AUTO_NEG);
2140 em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp);
2143 /* Restart process after EM_SMARTSPEED_MAX iterations */
2144 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2145 adapter->smartspeed = 0;
2149 * Manage DMA'able memory.
2152 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2156 *(bus_addr_t*) arg = segs->ds_addr;
2160 em_dma_malloc(struct adapter *adapter, bus_size_t size,
2161 struct em_dma_alloc *dma, int mapflags)
2164 device_t dev = adapter->dev;
2166 r = bus_dma_tag_create(NULL, /* parent */
2167 PAGE_SIZE, 0, /* alignment, bounds */
2168 BUS_SPACE_MAXADDR, /* lowaddr */
2169 BUS_SPACE_MAXADDR, /* highaddr */
2170 NULL, NULL, /* filter, filterarg */
2173 size, /* maxsegsize */
2174 BUS_DMA_ALLOCNOW, /* flags */
2177 device_printf(dev, "em_dma_malloc: bus_dma_tag_create failed; "
2182 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
2183 BUS_DMA_NOWAIT, &dma->dma_map);
2185 device_printf(dev, "em_dma_malloc: bus_dmammem_alloc failed; "
2186 "size %llu, error %d\n", (uintmax_t)size, r);
2190 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
2194 mapflags | BUS_DMA_NOWAIT);
2196 device_printf(dev, "em_dma_malloc: bus_dmamap_load failed; "
2201 dma->dma_size = size;
2205 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2207 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2208 bus_dma_tag_destroy(dma->dma_tag);
2210 dma->dma_map = NULL;
2211 dma->dma_tag = NULL;
2216 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2218 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2219 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2220 bus_dma_tag_destroy(dma->dma_tag);
2223 /*********************************************************************
2225 * Allocate memory for tx_buffer structures. The tx_buffer stores all
2226 * the information needed to transmit a packet on the wire.
2228 **********************************************************************/
2230 em_allocate_transmit_structures(struct adapter * adapter)
2232 adapter->tx_buffer_area = kmalloc(sizeof(struct em_buffer) *
2233 adapter->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO);
2234 if (adapter->tx_buffer_area == NULL) {
2235 device_printf(adapter->dev, "Unable to allocate tx_buffer memory\n");
2242 /*********************************************************************
2244 * Allocate and initialize transmit structures.
2246 **********************************************************************/
2248 em_setup_transmit_structures(struct adapter *adapter)
2250 struct em_buffer *tx_buffer;
2255 * Setup DMA descriptor areas.
2257 size = roundup2(adapter->hw.max_frame_size, MCLBYTES);
2258 if (bus_dma_tag_create(NULL, /* parent */
2259 1, 0, /* alignment, bounds */
2260 BUS_SPACE_MAXADDR, /* lowaddr */
2261 BUS_SPACE_MAXADDR, /* highaddr */
2262 NULL, NULL, /* filter, filterarg */
2264 EM_MAX_SCATTER, /* nsegments */
2265 size, /* maxsegsize */
2266 BUS_DMA_ALLOCNOW, /* flags */
2268 device_printf(adapter->dev, "Unable to allocate TX DMA tag\n");
2272 if (em_allocate_transmit_structures(adapter))
2275 bzero((void *) adapter->tx_desc_base,
2276 (sizeof(struct em_tx_desc)) * adapter->num_tx_desc);
2277 tx_buffer = adapter->tx_buffer_area;
2278 for (i = 0; i < adapter->num_tx_desc; i++) {
2279 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map);
2281 device_printf(adapter->dev,
2282 "Unable to create TX DMA map\n");
2288 adapter->next_avail_tx_desc = 0;
2289 adapter->oldest_used_tx_desc = 0;
2291 /* Set number of descriptors available */
2292 adapter->num_tx_desc_avail = adapter->num_tx_desc;
2294 /* Set checksum context */
2295 adapter->active_checksum_context = OFFLOAD_NONE;
2297 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2298 BUS_DMASYNC_PREWRITE);
2302 em_free_transmit_structures(adapter);
2306 /*********************************************************************
2308 * Enable transmit unit.
2310 **********************************************************************/
2312 em_initialize_transmit_unit(struct adapter * adapter)
2314 uint32_t reg_tctl, reg_tarc;
2315 uint32_t reg_tipg = 0;
2318 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2320 /* Setup the Base and Length of the Tx Descriptor Ring */
2321 bus_addr = adapter->txdma.dma_paddr;
2322 E1000_WRITE_REG(&adapter->hw, TDLEN,
2323 adapter->num_tx_desc * sizeof(struct em_tx_desc));
2324 E1000_WRITE_REG(&adapter->hw, TDBAH, (uint32_t)(bus_addr >> 32));
2325 E1000_WRITE_REG(&adapter->hw, TDBAL, (uint32_t)bus_addr);
2327 /* Setup the HW Tx Head and Tail descriptor pointers */
2328 E1000_WRITE_REG(&adapter->hw, TDT, 0);
2329 E1000_WRITE_REG(&adapter->hw, TDH, 0);
2331 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2332 E1000_READ_REG(&adapter->hw, TDBAL),
2333 E1000_READ_REG(&adapter->hw, TDLEN));
2335 /* Set the default values for the Tx Inter Packet Gap timer */
2336 switch (adapter->hw.mac_type) {
2337 case em_82542_rev2_0:
2338 case em_82542_rev2_1:
2339 reg_tipg = DEFAULT_82542_TIPG_IPGT;
2340 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2341 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2343 case em_80003es2lan:
2344 reg_tipg = DEFAULT_82543_TIPG_IPGR1;
2345 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2348 if (adapter->hw.media_type == em_media_type_fiber ||
2349 adapter->hw.media_type == em_media_type_internal_serdes)
2350 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2352 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2353 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2354 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2357 E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg);
2358 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value);
2359 if (adapter->hw.mac_type >= em_82540)
2360 E1000_WRITE_REG(&adapter->hw, TADV,
2361 adapter->tx_abs_int_delay.value);
2363 /* Do adapter specific tweaks before we enable the transmitter */
2364 if (adapter->hw.mac_type == em_82571 || adapter->hw.mac_type == em_82572) {
2365 reg_tarc = E1000_READ_REG(&adapter->hw, TARC0);
2366 reg_tarc |= (1 << 25);
2367 E1000_WRITE_REG(&adapter->hw, TARC0, reg_tarc);
2368 reg_tarc = E1000_READ_REG(&adapter->hw, TARC1);
2369 reg_tarc |= (1 << 25);
2370 reg_tarc &= ~(1 << 28);
2371 E1000_WRITE_REG(&adapter->hw, TARC1, reg_tarc);
2372 } else if (adapter->hw.mac_type == em_80003es2lan) {
2373 reg_tarc = E1000_READ_REG(&adapter->hw, TARC0);
2375 E1000_WRITE_REG(&adapter->hw, TARC0, reg_tarc);
2376 reg_tarc = E1000_READ_REG(&adapter->hw, TARC1);
2378 E1000_WRITE_REG(&adapter->hw, TARC1, reg_tarc);
2381 /* Program the Transmit Control Register */
2382 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
2383 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2384 if (adapter->hw.mac_type >= em_82571)
2385 reg_tctl |= E1000_TCTL_MULR;
2386 if (adapter->link_duplex == 1)
2387 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2389 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2391 /* This write will effectively turn on the transmit unit */
2392 E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl);
2394 /* Setup Transmit Descriptor Settings for this adapter */
2395 adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS;
2397 if (adapter->tx_int_delay.value > 0)
2398 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2401 /*********************************************************************
2403 * Free all transmit related data structures.
2405 **********************************************************************/
2407 em_free_transmit_structures(struct adapter * adapter)
2409 struct em_buffer *tx_buffer;
2412 INIT_DEBUGOUT("free_transmit_structures: begin");
2414 if (adapter->tx_buffer_area != NULL) {
2415 tx_buffer = adapter->tx_buffer_area;
2416 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
2417 if (tx_buffer->m_head != NULL) {
2418 bus_dmamap_unload(adapter->txtag,
2420 m_freem(tx_buffer->m_head);
2423 if (tx_buffer->map != NULL) {
2424 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
2425 tx_buffer->map = NULL;
2427 tx_buffer->m_head = NULL;
2430 if (adapter->tx_buffer_area != NULL) {
2431 kfree(adapter->tx_buffer_area, M_DEVBUF);
2432 adapter->tx_buffer_area = NULL;
2434 if (adapter->txtag != NULL) {
2435 bus_dma_tag_destroy(adapter->txtag);
2436 adapter->txtag = NULL;
2440 /*********************************************************************
2442 * The offload context needs to be set when we transfer the first
2443 * packet of a particular protocol (TCP/UDP). We change the
2444 * context only if the protocol type changes.
2446 **********************************************************************/
2448 em_transmit_checksum_setup(struct adapter * adapter,
2450 uint32_t *txd_upper,
2451 uint32_t *txd_lower)
2453 struct em_context_desc *TXD;
2454 struct em_buffer *tx_buffer;
2457 if (mp->m_pkthdr.csum_flags) {
2458 if (mp->m_pkthdr.csum_flags & CSUM_TCP) {
2459 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2460 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2461 if (adapter->active_checksum_context == OFFLOAD_TCP_IP)
2464 adapter->active_checksum_context = OFFLOAD_TCP_IP;
2465 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) {
2466 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2467 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2468 if (adapter->active_checksum_context == OFFLOAD_UDP_IP)
2471 adapter->active_checksum_context = OFFLOAD_UDP_IP;
2484 * If we reach this point, the checksum offload context
2485 * needs to be reset.
2487 curr_txd = adapter->next_avail_tx_desc;
2488 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2489 TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd];
2491 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN;
2492 TXD->lower_setup.ip_fields.ipcso =
2493 ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
2494 TXD->lower_setup.ip_fields.ipcse =
2495 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1);
2497 TXD->upper_setup.tcp_fields.tucss =
2498 ETHER_HDR_LEN + sizeof(struct ip);
2499 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2501 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) {
2502 TXD->upper_setup.tcp_fields.tucso =
2503 ETHER_HDR_LEN + sizeof(struct ip) +
2504 offsetof(struct tcphdr, th_sum);
2505 } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) {
2506 TXD->upper_setup.tcp_fields.tucso =
2507 ETHER_HDR_LEN + sizeof(struct ip) +
2508 offsetof(struct udphdr, uh_sum);
2511 TXD->tcp_seg_setup.data = htole32(0);
2512 TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT);
2514 tx_buffer->m_head = NULL;
2516 if (++curr_txd == adapter->num_tx_desc)
2519 adapter->num_tx_desc_avail--;
2520 adapter->next_avail_tx_desc = curr_txd;
2523 /**********************************************************************
2525 * Examine each tx_buffer in the used queue. If the hardware is done
2526 * processing the packet then free associated resources. The
2527 * tx_buffer is put back on the free queue.
2529 **********************************************************************/
2532 em_clean_transmit_interrupts(struct adapter *adapter)
2535 struct em_buffer *tx_buffer;
2536 struct em_tx_desc *tx_desc;
2537 struct ifnet *ifp = &adapter->interface_data.ac_if;
2539 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2542 num_avail = adapter->num_tx_desc_avail;
2543 i = adapter->oldest_used_tx_desc;
2545 tx_buffer = &adapter->tx_buffer_area[i];
2546 tx_desc = &adapter->tx_desc_base[i];
2548 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2549 BUS_DMASYNC_POSTREAD);
2551 while(tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2552 tx_desc->upper.data = 0;
2557 if (tx_buffer->m_head) {
2559 bus_dmamap_sync(adapter->txtag, tx_buffer->map,
2560 BUS_DMASYNC_POSTWRITE);
2561 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2563 m_freem(tx_buffer->m_head);
2564 tx_buffer->m_head = NULL;
2567 if (++i == adapter->num_tx_desc)
2570 tx_buffer = &adapter->tx_buffer_area[i];
2571 tx_desc = &adapter->tx_desc_base[i];
2574 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2575 BUS_DMASYNC_PREWRITE);
2577 adapter->oldest_used_tx_desc = i;
2580 * If we have enough room, clear IFF_OACTIVE to tell the stack
2581 * that it is OK to send packets.
2582 * If there are no pending descriptors, clear the timeout. Otherwise,
2583 * if some descriptors have been freed, restart the timeout.
2585 if (num_avail > EM_TX_CLEANUP_THRESHOLD) {
2586 ifp->if_flags &= ~IFF_OACTIVE;
2587 if (num_avail == adapter->num_tx_desc)
2589 else if (num_avail == adapter->num_tx_desc_avail)
2590 ifp->if_timer = EM_TX_TIMEOUT;
2592 adapter->num_tx_desc_avail = num_avail;
2595 /*********************************************************************
2597 * Get a buffer from system mbuf buffer pool.
2599 **********************************************************************/
2601 em_get_buf(int i, struct adapter *adapter, struct mbuf *nmp, int how)
2603 struct mbuf *mp = nmp;
2604 struct em_buffer *rx_buffer;
2609 ifp = &adapter->interface_data.ac_if;
2612 mp = m_getcl(how, MT_DATA, M_PKTHDR);
2614 adapter->mbuf_cluster_failed++;
2617 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2619 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2620 mp->m_data = mp->m_ext.ext_buf;
2623 if (ifp->if_mtu <= ETHERMTU)
2624 m_adj(mp, ETHER_ALIGN);
2626 rx_buffer = &adapter->rx_buffer_area[i];
2629 * Using memory from the mbuf cluster pool, invoke the
2630 * bus_dma machinery to arrange the memory mapping.
2632 error = bus_dmamap_load(adapter->rxtag, rx_buffer->map,
2633 mtod(mp, void *), mp->m_len,
2634 em_dmamap_cb, &paddr, 0);
2639 rx_buffer->m_head = mp;
2640 adapter->rx_desc_base[i].buffer_addr = htole64(paddr);
2641 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD);
2646 /*********************************************************************
2648 * Allocate memory for rx_buffer structures. Since we use one
2649 * rx_buffer per received packet, the maximum number of rx_buffer's
2650 * that we'll need is equal to the number of receive descriptors
2651 * that we've allocated.
2653 **********************************************************************/
2655 em_allocate_receive_structures(struct adapter *adapter)
2658 struct em_buffer *rx_buffer;
2660 size = adapter->num_rx_desc * sizeof(struct em_buffer);
2661 adapter->rx_buffer_area = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
2663 error = bus_dma_tag_create(NULL, /* parent */
2664 1, 0, /* alignment, bounds */
2665 BUS_SPACE_MAXADDR, /* lowaddr */
2666 BUS_SPACE_MAXADDR, /* highaddr */
2667 NULL, NULL, /* filter, filterarg */
2668 MCLBYTES, /* maxsize */
2670 MCLBYTES, /* maxsegsize */
2671 BUS_DMA_ALLOCNOW, /* flags */
2674 device_printf(adapter->dev, "em_allocate_receive_structures: "
2675 "bus_dma_tag_create failed; error %u\n", error);
2679 rx_buffer = adapter->rx_buffer_area;
2680 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2681 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT,
2684 device_printf(adapter->dev,
2685 "em_allocate_receive_structures: "
2686 "bus_dmamap_create failed; error %u\n",
2692 for (i = 0; i < adapter->num_rx_desc; i++) {
2693 error = em_get_buf(i, adapter, NULL, MB_WAIT);
2695 adapter->rx_buffer_area[i].m_head = NULL;
2696 adapter->rx_desc_base[i].buffer_addr = 0;
2701 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
2702 BUS_DMASYNC_PREWRITE);
2707 bus_dma_tag_destroy(adapter->rxtag);
2709 adapter->rxtag = NULL;
2710 kfree(adapter->rx_buffer_area, M_DEVBUF);
2711 adapter->rx_buffer_area = NULL;
2715 /*********************************************************************
2717 * Allocate and initialize receive structures.
2719 **********************************************************************/
2721 em_setup_receive_structures(struct adapter *adapter)
2723 bzero((void *) adapter->rx_desc_base,
2724 (sizeof(struct em_rx_desc)) * adapter->num_rx_desc);
2726 if (em_allocate_receive_structures(adapter))
2729 /* Setup our descriptor pointers */
2730 adapter->next_rx_desc_to_check = 0;
2734 /*********************************************************************
2736 * Enable receive unit.
2738 **********************************************************************/
2740 em_initialize_receive_unit(struct adapter *adapter)
2743 uint32_t reg_rxcsum;
2747 INIT_DEBUGOUT("em_initialize_receive_unit: begin");
2749 ifp = &adapter->interface_data.ac_if;
2751 /* Make sure receives are disabled while setting up the descriptor ring */
2752 E1000_WRITE_REG(&adapter->hw, RCTL, 0);
2754 /* Set the Receive Delay Timer Register */
2755 E1000_WRITE_REG(&adapter->hw, RDTR,
2756 adapter->rx_int_delay.value | E1000_RDT_FPDB);
2758 if(adapter->hw.mac_type >= em_82540) {
2759 E1000_WRITE_REG(&adapter->hw, RADV,
2760 adapter->rx_abs_int_delay.value);
2762 /* Set the interrupt throttling rate in 256ns increments */
2763 if (em_int_throttle_ceil) {
2764 E1000_WRITE_REG(&adapter->hw, ITR,
2765 1000000000 / 256 / em_int_throttle_ceil);
2767 E1000_WRITE_REG(&adapter->hw, ITR, 0);
2771 /* Setup the Base and Length of the Rx Descriptor Ring */
2772 bus_addr = adapter->rxdma.dma_paddr;
2773 E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc *
2774 sizeof(struct em_rx_desc));
2775 E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32));
2776 E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr);
2778 /* Setup the HW Rx Head and Tail Descriptor Pointers */
2779 E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1);
2780 E1000_WRITE_REG(&adapter->hw, RDH, 0);
2782 /* Setup the Receive Control Register */
2783 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2784 E1000_RCTL_RDMTS_HALF |
2785 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
2787 if (adapter->hw.tbi_compatibility_on == TRUE)
2788 reg_rctl |= E1000_RCTL_SBP;
2790 switch (adapter->rx_buffer_len) {
2792 case EM_RXBUFFER_2048:
2793 reg_rctl |= E1000_RCTL_SZ_2048;
2795 case EM_RXBUFFER_4096:
2796 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2798 case EM_RXBUFFER_8192:
2799 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2801 case EM_RXBUFFER_16384:
2802 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE;
2806 if (ifp->if_mtu > ETHERMTU)
2807 reg_rctl |= E1000_RCTL_LPE;
2809 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
2810 if ((adapter->hw.mac_type >= em_82543) &&
2811 (ifp->if_capenable & IFCAP_RXCSUM)) {
2812 reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
2813 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2814 E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum);
2817 /* Enable Receives */
2818 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
2821 /*********************************************************************
2823 * Free receive related data structures.
2825 **********************************************************************/
2827 em_free_receive_structures(struct adapter *adapter)
2829 struct em_buffer *rx_buffer;
2832 INIT_DEBUGOUT("free_receive_structures: begin");
2834 if (adapter->rx_buffer_area != NULL) {
2835 rx_buffer = adapter->rx_buffer_area;
2836 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2837 if (rx_buffer->map != NULL) {
2838 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2839 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map);
2841 if (rx_buffer->m_head != NULL)
2842 m_freem(rx_buffer->m_head);
2843 rx_buffer->m_head = NULL;
2846 if (adapter->rx_buffer_area != NULL) {
2847 kfree(adapter->rx_buffer_area, M_DEVBUF);
2848 adapter->rx_buffer_area = NULL;
2850 if (adapter->rxtag != NULL) {
2851 bus_dma_tag_destroy(adapter->rxtag);
2852 adapter->rxtag = NULL;
2856 /*********************************************************************
2858 * This routine executes in interrupt context. It replenishes
2859 * the mbufs in the descriptor and sends data which has been
2860 * dma'ed into host memory to upper layer.
2862 * We loop at most count times if count is > 0, or until done if
2865 *********************************************************************/
2867 em_process_receive_interrupts(struct adapter *adapter, int count)
2871 uint8_t accept_frame = 0;
2873 uint16_t len, desc_len, prev_len_adj;
2876 /* Pointer to the receive descriptor being examined. */
2877 struct em_rx_desc *current_desc;
2879 ifp = &adapter->interface_data.ac_if;
2880 i = adapter->next_rx_desc_to_check;
2881 current_desc = &adapter->rx_desc_base[i];
2883 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
2884 BUS_DMASYNC_POSTREAD);
2886 if (!((current_desc->status) & E1000_RXD_STAT_DD))
2889 while ((current_desc->status & E1000_RXD_STAT_DD) && (count != 0)) {
2891 mp = adapter->rx_buffer_area[i].m_head;
2892 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
2893 BUS_DMASYNC_POSTREAD);
2894 bus_dmamap_unload(adapter->rxtag,
2895 adapter->rx_buffer_area[i].map);
2899 desc_len = le16toh(current_desc->length);
2900 if (current_desc->status & E1000_RXD_STAT_EOP) {
2903 if (desc_len < ETHER_CRC_LEN) {
2905 prev_len_adj = ETHER_CRC_LEN - desc_len;
2907 len = desc_len - ETHER_CRC_LEN;
2914 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
2916 uint32_t pkt_len = desc_len;
2918 if (adapter->fmp != NULL)
2919 pkt_len += adapter->fmp->m_pkthdr.len;
2921 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
2923 if (TBI_ACCEPT(&adapter->hw, current_desc->status,
2924 current_desc->errors,
2925 pkt_len, last_byte)) {
2926 em_tbi_adjust_stats(&adapter->hw,
2929 adapter->hw.mac_addr);
2938 if (em_get_buf(i, adapter, NULL, MB_DONTWAIT) == ENOBUFS) {
2939 adapter->dropped_pkts++;
2940 em_get_buf(i, adapter, mp, MB_DONTWAIT);
2941 if (adapter->fmp != NULL)
2942 m_freem(adapter->fmp);
2943 adapter->fmp = NULL;
2944 adapter->lmp = NULL;
2948 /* Assign correct length to the current fragment */
2951 if (adapter->fmp == NULL) {
2952 mp->m_pkthdr.len = len;
2953 adapter->fmp = mp; /* Store the first mbuf */
2956 /* Chain mbuf's together */
2958 * Adjust length of previous mbuf in chain if we
2959 * received less than 4 bytes in the last descriptor.
2961 if (prev_len_adj > 0) {
2962 adapter->lmp->m_len -= prev_len_adj;
2963 adapter->fmp->m_pkthdr.len -= prev_len_adj;
2965 adapter->lmp->m_next = mp;
2966 adapter->lmp = adapter->lmp->m_next;
2967 adapter->fmp->m_pkthdr.len += len;
2971 adapter->fmp->m_pkthdr.rcvif = ifp;
2974 em_receive_checksum(adapter, current_desc,
2976 if (current_desc->status & E1000_RXD_STAT_VP) {
2977 VLAN_INPUT_TAG(adapter->fmp,
2978 (current_desc->special &
2979 E1000_RXD_SPC_VLAN_MASK));
2981 ifp->if_input(ifp, adapter->fmp);
2983 adapter->fmp = NULL;
2984 adapter->lmp = NULL;
2987 adapter->dropped_pkts++;
2988 em_get_buf(i, adapter, mp, MB_DONTWAIT);
2989 if (adapter->fmp != NULL)
2990 m_freem(adapter->fmp);
2991 adapter->fmp = NULL;
2992 adapter->lmp = NULL;
2996 /* Zero out the receive descriptors status */
2997 current_desc->status = 0;
2999 /* Advance our pointers to the next descriptor */
3000 if (++i == adapter->num_rx_desc) {
3002 current_desc = adapter->rx_desc_base;
3008 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
3009 BUS_DMASYNC_PREWRITE);
3011 adapter->next_rx_desc_to_check = i;
3013 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3015 i = adapter->num_rx_desc - 1;
3017 E1000_WRITE_REG(&adapter->hw, RDT, i);
3020 /*********************************************************************
3022 * Verify that the hardware indicated that the checksum is valid.
3023 * Inform the stack about the status of checksum so that stack
3024 * doesn't spend time verifying the checksum.
3026 *********************************************************************/
3028 em_receive_checksum(struct adapter *adapter,
3029 struct em_rx_desc *rx_desc,
3032 /* 82543 or newer only */
3033 if ((adapter->hw.mac_type < em_82543) ||
3034 /* Ignore Checksum bit is set */
3035 (rx_desc->status & E1000_RXD_STAT_IXSM)) {
3036 mp->m_pkthdr.csum_flags = 0;
3040 if (rx_desc->status & E1000_RXD_STAT_IPCS) {
3042 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3043 /* IP Checksum Good */
3044 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
3045 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3047 mp->m_pkthdr.csum_flags = 0;
3051 if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
3053 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3054 mp->m_pkthdr.csum_flags |=
3055 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
3056 mp->m_pkthdr.csum_data = htons(0xffff);
3063 em_enable_vlans(struct adapter *adapter)
3067 E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN);
3069 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3070 ctrl |= E1000_CTRL_VME;
3071 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3075 em_disable_vlans(struct adapter *adapter)
3079 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3080 ctrl &= ~E1000_CTRL_VME;
3081 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3085 * note: we must call bus_enable_intr() prior to enabling the hardware
3086 * interrupt and bus_disable_intr() after disabling the hardware interrupt
3087 * in order to avoid handler execution races from scheduled interrupt
3091 em_enable_intr(struct adapter *adapter)
3093 struct ifnet *ifp = &adapter->interface_data.ac_if;
3095 if ((ifp->if_flags & IFF_POLLING) == 0) {
3096 lwkt_serialize_handler_enable(ifp->if_serializer);
3097 E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK));
3102 em_disable_intr(struct adapter *adapter)
3105 * The first version of 82542 had an errata where when link was
3106 * forced it would stay up even up even if the cable was disconnected.
3107 * Sequence errors were used to detect the disconnect and then the
3108 * driver would unforce the link. This code in the in the ISR. For
3109 * this to work correctly the Sequence error interrupt had to be
3110 * enabled all the time.
3112 if (adapter->hw.mac_type == em_82542_rev2_0) {
3113 E1000_WRITE_REG(&adapter->hw, IMC,
3114 (0xffffffff & ~E1000_IMC_RXSEQ));
3116 E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff);
3119 lwkt_serialize_handler_disable(adapter->interface_data.ac_if.if_serializer);
3123 em_is_valid_ether_addr(uint8_t *addr)
3125 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3127 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN)))
3134 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3136 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2);
3140 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3142 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2);
3146 em_pci_set_mwi(struct em_hw *hw)
3148 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3149 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2);
3153 em_pci_clear_mwi(struct em_hw *hw)
3155 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3156 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2);
3160 em_read_reg_io(struct em_hw *hw, uint32_t offset)
3162 bus_space_write_4(hw->reg_io_tag, hw->reg_io_handle, 0, offset);
3163 return(bus_space_read_4(hw->reg_io_tag, hw->reg_io_handle, 4));
3167 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value)
3169 bus_space_write_4(hw->reg_io_tag, hw->reg_io_handle, 0, offset);
3170 bus_space_write_4(hw->reg_io_tag, hw->reg_io_handle, 4, value);
3173 /*********************************************************************
3174 * 82544 Coexistence issue workaround.
3175 * There are 2 issues.
3176 * 1. Transmit Hang issue.
3177 * To detect this issue, following equation can be used...
3178 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3179 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3182 * To detect this issue, following equation can be used...
3183 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3184 * If SUM[3:0] is in between 9 to c, we will have this issue.
3188 * Make sure we do not have ending address as 1,2,3,4(Hang) or
3191 *************************************************************************/
3193 em_fill_descriptors(uint64_t address, uint32_t length, PDESC_ARRAY desc_array)
3195 /* Since issue is sensitive to length and address.*/
3196 /* Let us first check the address...*/
3197 uint32_t safe_terminator;
3199 desc_array->descriptor[0].address = address;
3200 desc_array->descriptor[0].length = length;
3201 desc_array->elements = 1;
3202 return(desc_array->elements);
3204 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3205 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3206 if (safe_terminator == 0 ||
3207 (safe_terminator > 4 && safe_terminator < 9) ||
3208 (safe_terminator > 0xC && safe_terminator <= 0xF)) {
3209 desc_array->descriptor[0].address = address;
3210 desc_array->descriptor[0].length = length;
3211 desc_array->elements = 1;
3212 return(desc_array->elements);
3215 desc_array->descriptor[0].address = address;
3216 desc_array->descriptor[0].length = length - 4;
3217 desc_array->descriptor[1].address = address + (length - 4);
3218 desc_array->descriptor[1].length = 4;
3219 desc_array->elements = 2;
3220 return(desc_array->elements);
3223 /**********************************************************************
3225 * Update the board statistics counters.
3227 **********************************************************************/
3229 em_update_stats_counters(struct adapter *adapter)
3233 if (adapter->hw.media_type == em_media_type_copper ||
3234 (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
3235 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS);
3236 adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC);
3238 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS);
3239 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC);
3240 adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC);
3241 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL);
3243 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC);
3244 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL);
3245 adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC);
3246 adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC);
3247 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC);
3248 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC);
3249 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC);
3250 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC);
3251 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC);
3252 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC);
3253 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64);
3254 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127);
3255 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255);
3256 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511);
3257 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023);
3258 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522);
3259 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC);
3260 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC);
3261 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC);
3262 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC);
3264 /* For the 64-bit byte counters the low dword must be read first. */
3265 /* Both registers clear on the read of the high dword */
3267 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL);
3268 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH);
3269 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL);
3270 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH);
3272 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC);
3273 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC);
3274 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC);
3275 adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC);
3276 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC);
3278 adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL);
3279 adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH);
3280 adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL);
3281 adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH);
3283 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR);
3284 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT);
3285 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64);
3286 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127);
3287 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255);
3288 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511);
3289 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023);
3290 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522);
3291 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC);
3292 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC);
3294 if (adapter->hw.mac_type >= em_82543) {
3295 adapter->stats.algnerrc +=
3296 E1000_READ_REG(&adapter->hw, ALGNERRC);
3297 adapter->stats.rxerrc +=
3298 E1000_READ_REG(&adapter->hw, RXERRC);
3299 adapter->stats.tncrs +=
3300 E1000_READ_REG(&adapter->hw, TNCRS);
3301 adapter->stats.cexterr +=
3302 E1000_READ_REG(&adapter->hw, CEXTERR);
3303 adapter->stats.tsctc +=
3304 E1000_READ_REG(&adapter->hw, TSCTC);
3305 adapter->stats.tsctfc +=
3306 E1000_READ_REG(&adapter->hw, TSCTFC);
3308 ifp = &adapter->interface_data.ac_if;
3310 /* Fill out the OS statistics structure */
3311 ifp->if_collisions = adapter->stats.colc;
3315 adapter->dropped_pkts +
3316 adapter->stats.rxerrc +
3317 adapter->stats.crcerrs +
3318 adapter->stats.algnerrc +
3319 adapter->stats.ruc + adapter->stats.roc +
3320 adapter->stats.mpc + adapter->stats.cexterr +
3321 adapter->rx_overruns;
3324 ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol +
3325 adapter->watchdog_timeouts;
3329 /**********************************************************************
3331 * This routine is called only when em_display_debug_stats is enabled.
3332 * This routine provides a way to take a look at important statistics
3333 * maintained by the driver and hardware.
3335 **********************************************************************/
3337 em_print_debug_info(struct adapter *adapter)
3339 device_t dev= adapter->dev;
3340 uint8_t *hw_addr = adapter->hw.hw_addr;
3342 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3343 device_printf(dev, "CTRL = 0x%x\n",
3344 E1000_READ_REG(&adapter->hw, CTRL));
3345 device_printf(dev, "RCTL = 0x%x PS=(0x8402)\n",
3346 E1000_READ_REG(&adapter->hw, RCTL));
3347 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk\n",
3348 ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16),
3349 (E1000_READ_REG(&adapter->hw, PBA) & 0xffff));
3350 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3351 adapter->hw.fc_high_water, adapter->hw.fc_low_water);
3352 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3353 E1000_READ_REG(&adapter->hw, TIDV),
3354 E1000_READ_REG(&adapter->hw, TADV));
3355 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3356 E1000_READ_REG(&adapter->hw, RDTR),
3357 E1000_READ_REG(&adapter->hw, RADV));
3358 device_printf(dev, "fifo workaround = %lld, fifo_reset = %lld\n",
3359 (long long)adapter->tx_fifo_wrk_cnt,
3360 (long long)adapter->tx_fifo_reset_cnt);
3361 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3362 E1000_READ_REG(&adapter->hw, TDH),
3363 E1000_READ_REG(&adapter->hw, TDT));
3364 device_printf(dev, "Num Tx descriptors avail = %d\n",
3365 adapter->num_tx_desc_avail);
3366 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3367 adapter->no_tx_desc_avail1);
3368 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3369 adapter->no_tx_desc_avail2);
3370 device_printf(dev, "Std mbuf failed = %ld\n",
3371 adapter->mbuf_alloc_failed);
3372 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3373 adapter->mbuf_cluster_failed);
3374 device_printf(dev, "Driver dropped packets = %ld\n",
3375 adapter->dropped_pkts);
3379 em_print_hw_stats(struct adapter *adapter)
3381 device_t dev= adapter->dev;
3383 device_printf(dev, "Adapter: %p\n", adapter);
3385 device_printf(dev, "Excessive collisions = %lld\n",
3386 (long long)adapter->stats.ecol);
3387 device_printf(dev, "Symbol errors = %lld\n",
3388 (long long)adapter->stats.symerrs);
3389 device_printf(dev, "Sequence errors = %lld\n",
3390 (long long)adapter->stats.sec);
3391 device_printf(dev, "Defer count = %lld\n",
3392 (long long)adapter->stats.dc);
3394 device_printf(dev, "Missed Packets = %lld\n",
3395 (long long)adapter->stats.mpc);
3396 device_printf(dev, "Receive No Buffers = %lld\n",
3397 (long long)adapter->stats.rnbc);
3398 device_printf(dev, "Receive length errors = %lld\n",
3399 (long long)adapter->stats.rlec);
3400 device_printf(dev, "Receive errors = %lld\n",
3401 (long long)adapter->stats.rxerrc);
3402 device_printf(dev, "Crc errors = %lld\n",
3403 (long long)adapter->stats.crcerrs);
3404 device_printf(dev, "Alignment errors = %lld\n",
3405 (long long)adapter->stats.algnerrc);
3406 device_printf(dev, "Carrier extension errors = %lld\n",
3407 (long long)adapter->stats.cexterr);
3408 device_printf(dev, "RX overruns = %lu\n", adapter->rx_overruns);
3409 device_printf(dev, "Watchdog timeouts = %lu\n",
3410 adapter->watchdog_timeouts);
3412 device_printf(dev, "XON Rcvd = %lld\n",
3413 (long long)adapter->stats.xonrxc);
3414 device_printf(dev, "XON Xmtd = %lld\n",
3415 (long long)adapter->stats.xontxc);
3416 device_printf(dev, "XOFF Rcvd = %lld\n",
3417 (long long)adapter->stats.xoffrxc);
3418 device_printf(dev, "XOFF Xmtd = %lld\n",
3419 (long long)adapter->stats.xofftxc);
3421 device_printf(dev, "Good Packets Rcvd = %lld\n",
3422 (long long)adapter->stats.gprc);
3423 device_printf(dev, "Good Packets Xmtd = %lld\n",
3424 (long long)adapter->stats.gptc);
3428 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3432 struct adapter *adapter;
3435 error = sysctl_handle_int(oidp, &result, 0, req);
3437 if (error || !req->newptr)
3441 adapter = (struct adapter *)arg1;
3442 em_print_debug_info(adapter);
3449 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
3453 struct adapter *adapter;
3456 error = sysctl_handle_int(oidp, &result, 0, req);
3458 if (error || !req->newptr)
3462 adapter = (struct adapter *)arg1;
3463 em_print_hw_stats(adapter);
3470 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3472 struct em_int_delay_info *info;
3473 struct adapter *adapter;
3479 info = (struct em_int_delay_info *)arg1;
3480 adapter = info->adapter;
3481 usecs = info->value;
3482 error = sysctl_handle_int(oidp, &usecs, 0, req);
3483 if (error != 0 || req->newptr == NULL)
3485 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535))
3487 info->value = usecs;
3488 ticks = E1000_USECS_TO_TICKS(usecs);
3490 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3491 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
3492 regval = (regval & ~0xffff) | (ticks & 0xffff);
3493 /* Handle a few special cases. */
3494 switch (info->offset) {
3496 case E1000_82542_RDTR:
3497 regval |= E1000_RDT_FPDB;
3500 case E1000_82542_TIDV:
3502 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
3503 /* Don't write 0 into the TIDV register. */
3506 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3509 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
3510 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3515 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
3516 const char *description, struct em_int_delay_info *info,
3517 int offset, int value)
3519 info->adapter = adapter;
3520 info->offset = offset;
3521 info->value = value;
3522 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
3523 SYSCTL_CHILDREN(adapter->sysctl_tree),
3524 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
3525 info, 0, em_sysctl_int_delay, "I", description);
3529 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3531 struct adapter *adapter = (void *)arg1;
3535 throttle = em_int_throttle_ceil;
3536 error = sysctl_handle_int(oidp, &throttle, 0, req);
3537 if (error || req->newptr == NULL)
3539 if (throttle < 0 || throttle > 1000000000 / 256)
3543 * Set the interrupt throttling rate in 256ns increments,
3544 * recalculate sysctl value assignment to get exact frequency.
3546 throttle = 1000000000 / 256 / throttle;
3547 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3548 em_int_throttle_ceil = 1000000000 / 256 / throttle;
3549 E1000_WRITE_REG(&adapter->hw, ITR, throttle);
3550 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3552 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3553 em_int_throttle_ceil = 0;
3554 E1000_WRITE_REG(&adapter->hw, ITR, 0);
3555 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3557 device_printf(adapter->dev, "Interrupt moderation set to %d/sec\n",
3558 em_int_throttle_ceil);