1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.34 2008/07/09 15:51:43 thomas Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
65 #include <sys/interrupt.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
73 #include <net/ethernet.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include "miibus_if.h"
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static int nfe_rxeof(struct nfe_softc *);
117 static int nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_powerup(device_t);
143 static void nfe_mac_reset(struct nfe_softc *);
144 static void nfe_tick(void *);
145 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
146 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
148 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
150 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
152 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
154 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
156 static void nfe_enable_intrs(struct nfe_softc *);
157 static void nfe_disable_intrs(struct nfe_softc *);
159 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
164 static int nfe_debug = 0;
165 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
166 static int nfe_imtime = 0; /* Disable interrupt moderation */
168 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
169 TUNABLE_INT("hw.nfe.imtimer", &nfe_imtime);
170 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
172 #define DPRINTF(sc, fmt, ...) do { \
173 if ((sc)->sc_debug) { \
174 if_printf(&(sc)->arpcom.ac_if, \
179 #define DPRINTFN(sc, lv, fmt, ...) do { \
180 if ((sc)->sc_debug >= (lv)) { \
181 if_printf(&(sc)->arpcom.ac_if, \
186 #else /* !NFE_DEBUG */
188 #define DPRINTF(sc, fmt, ...)
189 #define DPRINTFN(sc, lv, fmt, ...)
191 #endif /* NFE_DEBUG */
195 bus_dma_segment_t *segs;
198 static const struct nfe_dev {
203 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
204 "NVIDIA nForce Fast Ethernet" },
206 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
207 "NVIDIA nForce2 Fast Ethernet" },
209 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
210 "NVIDIA nForce3 Gigabit Ethernet" },
212 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
213 chipset, and possibly also the 400R; it might be both nForce2- and
214 nForce3-based boards can use the same MCPs (= southbridges) */
215 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
216 "NVIDIA nForce3 Gigabit Ethernet" },
218 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
219 "NVIDIA nForce3 Gigabit Ethernet" },
221 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
222 "NVIDIA nForce3 Gigabit Ethernet" },
224 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
225 "NVIDIA nForce3 Gigabit Ethernet" },
227 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
228 "NVIDIA CK804 Gigabit Ethernet" },
230 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
231 "NVIDIA CK804 Gigabit Ethernet" },
233 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
234 "NVIDIA MCP04 Gigabit Ethernet" },
236 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
237 "NVIDIA MCP04 Gigabit Ethernet" },
239 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
240 "NVIDIA MCP51 Gigabit Ethernet" },
242 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
243 "NVIDIA MCP51 Gigabit Ethernet" },
245 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
246 "NVIDIA MCP55 Gigabit Ethernet" },
248 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
249 "NVIDIA MCP55 Gigabit Ethernet" },
251 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
252 "NVIDIA MCP61 Gigabit Ethernet" },
254 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
255 "NVIDIA MCP61 Gigabit Ethernet" },
257 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
258 "NVIDIA MCP61 Gigabit Ethernet" },
260 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
261 "NVIDIA MCP61 Gigabit Ethernet" },
263 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
264 "NVIDIA MCP65 Gigabit Ethernet" },
266 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
267 "NVIDIA MCP65 Gigabit Ethernet" },
269 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
270 "NVIDIA MCP65 Gigabit Ethernet" },
272 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
273 "NVIDIA MCP65 Gigabit Ethernet" },
275 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
276 "NVIDIA MCP67 Gigabit Ethernet" },
278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
279 "NVIDIA MCP67 Gigabit Ethernet" },
281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
282 "NVIDIA MCP67 Gigabit Ethernet" },
284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
285 "NVIDIA MCP67 Gigabit Ethernet" },
287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
288 "NVIDIA MCP73 Gigabit Ethernet" },
290 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
291 "NVIDIA MCP73 Gigabit Ethernet" },
293 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
294 "NVIDIA MCP73 Gigabit Ethernet" },
296 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
297 "NVIDIA MCP73 Gigabit Ethernet" },
299 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
300 "NVIDIA MCP77 Gigabit Ethernet" },
302 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
303 "NVIDIA MCP77 Gigabit Ethernet" },
305 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
306 "NVIDIA MCP77 Gigabit Ethernet" },
308 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
309 "NVIDIA MCP77 Gigabit Ethernet" },
311 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
312 "NVIDIA MCP79 Gigabit Ethernet" },
314 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
315 "NVIDIA MCP79 Gigabit Ethernet" },
317 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
318 "NVIDIA MCP79 Gigabit Ethernet" },
320 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
321 "NVIDIA MCP79 Gigabit Ethernet" },
326 static device_method_t nfe_methods[] = {
327 /* Device interface */
328 DEVMETHOD(device_probe, nfe_probe),
329 DEVMETHOD(device_attach, nfe_attach),
330 DEVMETHOD(device_detach, nfe_detach),
331 DEVMETHOD(device_suspend, nfe_suspend),
332 DEVMETHOD(device_resume, nfe_resume),
333 DEVMETHOD(device_shutdown, nfe_shutdown),
336 DEVMETHOD(bus_print_child, bus_generic_print_child),
337 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
340 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
341 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
342 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
347 static driver_t nfe_driver = {
350 sizeof(struct nfe_softc)
353 static devclass_t nfe_devclass;
355 DECLARE_DUMMY_MODULE(if_nfe);
356 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
357 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
358 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
361 nfe_probe(device_t dev)
363 const struct nfe_dev *n;
366 vid = pci_get_vendor(dev);
367 did = pci_get_device(dev);
368 for (n = nfe_devices; n->desc != NULL; ++n) {
369 if (vid == n->vid && did == n->did) {
370 struct nfe_softc *sc = device_get_softc(dev);
373 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
374 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
375 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
376 sc->sc_caps = NFE_NO_PWRCTL |
379 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
380 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
381 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
382 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
383 sc->sc_caps = NFE_JUMBO_SUP |
388 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
389 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
390 sc->sc_caps = NFE_FIX_EADDR;
392 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
393 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
394 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
395 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
396 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
397 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
398 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
399 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
400 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
401 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
402 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
403 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
404 sc->sc_caps |= NFE_40BIT_ADDR;
406 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
407 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
408 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
409 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
410 sc->sc_caps = NFE_JUMBO_SUP |
416 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
417 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
418 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
419 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
420 sc->sc_caps = NFE_JUMBO_SUP |
423 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
424 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
425 sc->sc_caps = NFE_JUMBO_SUP |
431 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
432 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
433 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
434 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
435 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
436 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
437 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
438 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
439 sc->sc_caps = NFE_40BIT_ADDR |
444 device_set_desc(dev, n->desc);
445 device_set_async_attach(dev, TRUE);
453 nfe_attach(device_t dev)
455 struct nfe_softc *sc = device_get_softc(dev);
456 struct ifnet *ifp = &sc->arpcom.ac_if;
457 uint8_t eaddr[ETHER_ADDR_LEN];
460 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
461 lwkt_serialize_init(&sc->sc_jbuf_serializer);
464 * Initialize sysctl variables
466 sc->sc_rx_ring_count = nfe_rx_ring_count;
467 sc->sc_debug = nfe_debug;
468 if (nfe_imtime < 0) {
469 sc->sc_flags |= NFE_F_DYN_IM;
470 sc->sc_imtime = -nfe_imtime;
472 sc->sc_imtime = nfe_imtime;
474 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
476 sc->sc_mem_rid = PCIR_BAR(0);
478 if (sc->sc_caps & NFE_40BIT_ADDR)
479 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
480 else if (sc->sc_caps & NFE_JUMBO_SUP)
481 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
484 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
487 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
488 irq = pci_read_config(dev, PCIR_INTLINE, 4);
490 device_printf(dev, "chip is in D%d power mode "
491 "-- setting to D0\n", pci_get_powerstate(dev));
493 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
495 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
496 pci_write_config(dev, PCIR_INTLINE, irq, 4);
498 #endif /* !BURN_BRIDGE */
500 /* Enable bus mastering */
501 pci_enable_busmaster(dev);
503 /* Allocate IO memory */
504 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
505 &sc->sc_mem_rid, RF_ACTIVE);
506 if (sc->sc_mem_res == NULL) {
507 device_printf(dev, "cound not allocate io memory\n");
510 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
511 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
515 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
517 RF_SHAREABLE | RF_ACTIVE);
518 if (sc->sc_irq_res == NULL) {
519 device_printf(dev, "could not allocate irq\n");
525 NFE_WRITE(sc, NFE_WOL_CTL, 0);
527 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
530 nfe_get_macaddr(sc, eaddr);
533 * Allocate Tx and Rx rings.
535 error = nfe_alloc_tx_ring(sc, &sc->txq);
537 device_printf(dev, "could not allocate Tx ring\n");
541 error = nfe_alloc_rx_ring(sc, &sc->rxq);
543 device_printf(dev, "could not allocate Rx ring\n");
550 sysctl_ctx_init(&sc->sc_sysctl_ctx);
551 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
552 SYSCTL_STATIC_CHILDREN(_hw),
554 device_get_nameunit(dev),
556 if (sc->sc_sysctl_tree == NULL) {
557 device_printf(dev, "can't add sysctl node\n");
561 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
562 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
563 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
564 sc, 0, nfe_sysctl_imtime, "I",
565 "Interrupt moderation time (usec). "
566 "0 to disable interrupt moderation.");
567 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
568 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
570 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
571 "debug", CTLFLAG_RW, &sc->sc_debug,
572 0, "control debugging printfs");
574 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
577 device_printf(dev, "MII without any phy\n");
582 ifp->if_mtu = ETHERMTU;
583 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
584 ifp->if_ioctl = nfe_ioctl;
585 ifp->if_start = nfe_start;
586 #ifdef DEVICE_POLLING
587 ifp->if_poll = nfe_poll;
589 ifp->if_watchdog = nfe_watchdog;
590 ifp->if_init = nfe_init;
591 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
592 ifq_set_ready(&ifp->if_snd);
594 ifp->if_capabilities = IFCAP_VLAN_MTU;
596 if (sc->sc_caps & NFE_HW_VLAN)
597 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
600 if (sc->sc_caps & NFE_HW_CSUM) {
601 ifp->if_capabilities |= IFCAP_HWCSUM;
602 ifp->if_hwassist = NFE_CSUM_FEATURES;
605 sc->sc_caps &= ~NFE_HW_CSUM;
607 ifp->if_capenable = ifp->if_capabilities;
609 callout_init(&sc->sc_tick_ch);
611 ether_ifattach(ifp, eaddr, NULL);
613 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
614 &sc->sc_ih, ifp->if_serializer);
616 device_printf(dev, "could not setup intr\n");
621 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
622 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
631 nfe_detach(device_t dev)
633 struct nfe_softc *sc = device_get_softc(dev);
635 if (device_is_attached(dev)) {
636 struct ifnet *ifp = &sc->arpcom.ac_if;
638 lwkt_serialize_enter(ifp->if_serializer);
640 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
641 lwkt_serialize_exit(ifp->if_serializer);
646 if (sc->sc_miibus != NULL)
647 device_delete_child(dev, sc->sc_miibus);
648 bus_generic_detach(dev);
650 if (sc->sc_sysctl_tree != NULL)
651 sysctl_ctx_free(&sc->sc_sysctl_ctx);
653 if (sc->sc_irq_res != NULL) {
654 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
658 if (sc->sc_mem_res != NULL) {
659 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
663 nfe_free_tx_ring(sc, &sc->txq);
664 nfe_free_rx_ring(sc, &sc->rxq);
670 nfe_shutdown(device_t dev)
672 struct nfe_softc *sc = device_get_softc(dev);
673 struct ifnet *ifp = &sc->arpcom.ac_if;
675 lwkt_serialize_enter(ifp->if_serializer);
677 lwkt_serialize_exit(ifp->if_serializer);
681 nfe_suspend(device_t dev)
683 struct nfe_softc *sc = device_get_softc(dev);
684 struct ifnet *ifp = &sc->arpcom.ac_if;
686 lwkt_serialize_enter(ifp->if_serializer);
688 lwkt_serialize_exit(ifp->if_serializer);
694 nfe_resume(device_t dev)
696 struct nfe_softc *sc = device_get_softc(dev);
697 struct ifnet *ifp = &sc->arpcom.ac_if;
699 lwkt_serialize_enter(ifp->if_serializer);
700 if (ifp->if_flags & IFF_UP)
702 lwkt_serialize_exit(ifp->if_serializer);
708 nfe_miibus_statchg(device_t dev)
710 struct nfe_softc *sc = device_get_softc(dev);
711 struct mii_data *mii = device_get_softc(sc->sc_miibus);
712 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
714 phy = NFE_READ(sc, NFE_PHY_IFACE);
715 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
717 seed = NFE_READ(sc, NFE_RNDSEED);
718 seed &= ~NFE_SEED_MASK;
720 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
721 phy |= NFE_PHY_HDX; /* half-duplex */
722 misc |= NFE_MISC1_HDX;
725 switch (IFM_SUBTYPE(mii->mii_media_active)) {
726 case IFM_1000_T: /* full-duplex only */
727 link |= NFE_MEDIA_1000T;
728 seed |= NFE_SEED_1000T;
729 phy |= NFE_PHY_1000T;
732 link |= NFE_MEDIA_100TX;
733 seed |= NFE_SEED_100TX;
734 phy |= NFE_PHY_100TX;
737 link |= NFE_MEDIA_10T;
738 seed |= NFE_SEED_10T;
742 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
744 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
745 NFE_WRITE(sc, NFE_MISC1, misc);
746 NFE_WRITE(sc, NFE_LINKSPEED, link);
750 nfe_miibus_readreg(device_t dev, int phy, int reg)
752 struct nfe_softc *sc = device_get_softc(dev);
756 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
758 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
759 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
763 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
765 for (ntries = 0; ntries < 1000; ntries++) {
767 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
770 if (ntries == 1000) {
771 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
775 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
776 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
780 val = NFE_READ(sc, NFE_PHY_DATA);
781 if (val != 0xffffffff && val != 0)
782 sc->mii_phyaddr = phy;
784 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
790 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
792 struct nfe_softc *sc = device_get_softc(dev);
796 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
798 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
799 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
803 NFE_WRITE(sc, NFE_PHY_DATA, val);
804 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
805 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
807 for (ntries = 0; ntries < 1000; ntries++) {
809 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
815 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
819 #ifdef DEVICE_POLLING
822 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
824 struct nfe_softc *sc = ifp->if_softc;
826 ASSERT_SERIALIZED(ifp->if_serializer);
830 nfe_disable_intrs(sc);
833 case POLL_DEREGISTER:
834 nfe_enable_intrs(sc);
837 case POLL_AND_CHECK_STATUS:
840 if (ifp->if_flags & IFF_RUNNING) {
853 struct nfe_softc *sc = arg;
854 struct ifnet *ifp = &sc->arpcom.ac_if;
857 r = NFE_READ(sc, NFE_IRQ_STATUS);
859 return; /* not for us */
860 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
862 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
864 if (r & NFE_IRQ_LINK) {
865 NFE_READ(sc, NFE_PHY_STATUS);
866 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
867 DPRINTF(sc, "link state changed %s\n", "");
870 if (ifp->if_flags & IFF_RUNNING) {
877 ret |= nfe_txeof(sc);
879 if (sc->sc_flags & NFE_F_DYN_IM) {
880 if (ret && (sc->sc_flags & NFE_F_IRQ_TIMER) == 0) {
882 * Assume that using hardware timer could reduce
883 * the interrupt rate.
885 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_IMTIMER);
886 sc->sc_flags |= NFE_F_IRQ_TIMER;
887 } else if (!ret && (sc->sc_flags & NFE_F_IRQ_TIMER)) {
889 * Nothing needs to be processed, fall back to
890 * use TX/RX interrupts.
892 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_NOIMTIMER);
893 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
900 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
902 struct nfe_softc *sc = ifp->if_softc;
903 struct ifreq *ifr = (struct ifreq *)data;
904 struct mii_data *mii;
909 if (((sc->sc_caps & NFE_JUMBO_SUP) &&
910 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
911 ((sc->sc_caps & NFE_JUMBO_SUP) == 0 &&
912 ifr->ifr_mtu > ETHERMTU)) {
914 } else if (ifp->if_mtu != ifr->ifr_mtu) {
915 ifp->if_mtu = ifr->ifr_mtu;
920 if (ifp->if_flags & IFF_UP) {
922 * If only the PROMISC or ALLMULTI flag changes, then
923 * don't do a full re-init of the chip, just update
926 if ((ifp->if_flags & IFF_RUNNING) &&
927 ((ifp->if_flags ^ sc->sc_if_flags) &
928 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
931 if (!(ifp->if_flags & IFF_RUNNING))
935 if (ifp->if_flags & IFF_RUNNING)
938 sc->sc_if_flags = ifp->if_flags;
942 if (ifp->if_flags & IFF_RUNNING)
947 mii = device_get_softc(sc->sc_miibus);
948 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
951 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
952 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
953 ifp->if_capenable ^= mask;
954 if (IFCAP_TXCSUM & ifp->if_capenable)
955 ifp->if_hwassist = NFE_CSUM_FEATURES;
957 ifp->if_hwassist = 0;
959 if (ifp->if_flags & IFF_RUNNING)
964 error = ether_ioctl(ifp, cmd, data);
971 nfe_rxeof(struct nfe_softc *sc)
973 struct ifnet *ifp = &sc->arpcom.ac_if;
974 struct nfe_rx_ring *ring = &sc->rxq;
976 #ifdef ETHER_INPUT_CHAIN
977 struct mbuf_chain chain[MAXCPU];
981 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
983 #ifdef ETHER_INPUT_CHAIN
984 ether_input_chain_init(chain);
988 struct nfe_rx_data *data = &ring->data[ring->cur];
993 if (sc->sc_caps & NFE_40BIT_ADDR) {
994 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
996 flags = le16toh(desc64->flags);
997 len = le16toh(desc64->length) & 0x3fff;
999 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
1001 flags = le16toh(desc32->flags);
1002 len = le16toh(desc32->length) & 0x3fff;
1005 if (flags & NFE_RX_READY)
1010 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1011 if (!(flags & NFE_RX_VALID_V1))
1014 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
1015 flags &= ~NFE_RX_ERROR;
1016 len--; /* fix buffer length */
1019 if (!(flags & NFE_RX_VALID_V2))
1022 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
1023 flags &= ~NFE_RX_ERROR;
1024 len--; /* fix buffer length */
1028 if (flags & NFE_RX_ERROR) {
1035 if (sc->sc_flags & NFE_F_USE_JUMBO)
1036 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1038 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1045 m->m_pkthdr.len = m->m_len = len;
1046 m->m_pkthdr.rcvif = ifp;
1048 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1049 (flags & NFE_RX_CSUMOK)) {
1050 if (flags & NFE_RX_IP_CSUMOK_V2) {
1051 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1056 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1057 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1059 CSUM_FRAG_NOT_CHECKED;
1060 m->m_pkthdr.csum_data = 0xffff;
1065 #ifdef ETHER_INPUT_CHAIN
1067 ether_input_chain2(ifp, m, chain);
1069 ether_input_chain(ifp, m, chain);
1072 ifp->if_input(ifp, m);
1075 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1076 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1080 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1081 #ifdef ETHER_INPUT_CHAIN
1082 ether_input_dispatch(chain);
1089 nfe_txeof(struct nfe_softc *sc)
1091 struct ifnet *ifp = &sc->arpcom.ac_if;
1092 struct nfe_tx_ring *ring = &sc->txq;
1093 struct nfe_tx_data *data = NULL;
1095 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1096 while (ring->next != ring->cur) {
1099 if (sc->sc_caps & NFE_40BIT_ADDR)
1100 flags = le16toh(ring->desc64[ring->next].flags);
1102 flags = le16toh(ring->desc32[ring->next].flags);
1104 if (flags & NFE_TX_VALID)
1107 data = &ring->data[ring->next];
1109 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1110 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1113 if ((flags & NFE_TX_ERROR_V1) != 0) {
1114 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1121 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1124 if ((flags & NFE_TX_ERROR_V2) != 0) {
1125 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1133 if (data->m == NULL) { /* should not get there */
1135 "last fragment bit w/o associated mbuf!\n");
1139 /* last fragment of the mbuf chain transmitted */
1140 bus_dmamap_sync(ring->data_tag, data->map,
1141 BUS_DMASYNC_POSTWRITE);
1142 bus_dmamap_unload(ring->data_tag, data->map);
1149 KKASSERT(ring->queued >= 0);
1150 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1153 if (data != NULL) { /* at least one slot freed */
1154 ifp->if_flags &= ~IFF_OACTIVE;
1162 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1164 struct nfe_dma_ctx ctx;
1165 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1166 struct nfe_tx_data *data, *data_map;
1168 struct nfe_desc64 *desc64 = NULL;
1169 struct nfe_desc32 *desc32 = NULL;
1174 data = &ring->data[ring->cur];
1176 data_map = data; /* Remember who owns the DMA map */
1178 ctx.nsegs = NFE_MAX_SCATTER;
1180 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1181 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1182 if (error && error != EFBIG) {
1183 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1187 if (error) { /* error == EFBIG */
1190 m_new = m_defrag(m0, MB_DONTWAIT);
1191 if (m_new == NULL) {
1192 if_printf(&sc->arpcom.ac_if,
1193 "could not defrag TX mbuf\n");
1200 ctx.nsegs = NFE_MAX_SCATTER;
1202 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1203 nfe_buf_dma_addr, &ctx,
1206 if_printf(&sc->arpcom.ac_if,
1207 "could not map defraged TX mbuf\n");
1214 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1215 bus_dmamap_unload(ring->data_tag, map);
1220 /* setup h/w VLAN tagging */
1221 if (m0->m_flags & M_VLANTAG)
1222 vtag = m0->m_pkthdr.ether_vlantag;
1224 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1225 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1226 flags |= NFE_TX_IP_CSUM;
1227 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1228 flags |= NFE_TX_TCP_CSUM;
1232 * XXX urm. somebody is unaware of how hardware works. You
1233 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1234 * the ring until the entire chain is actually *VALID*. Otherwise
1235 * the hardware may encounter a partially initialized chain that
1236 * is marked as being ready to go when it in fact is not ready to
1240 for (i = 0; i < ctx.nsegs; i++) {
1241 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1242 data = &ring->data[j];
1244 if (sc->sc_caps & NFE_40BIT_ADDR) {
1245 desc64 = &ring->desc64[j];
1246 #if defined(__LP64__)
1247 desc64->physaddr[0] =
1248 htole32(segs[i].ds_addr >> 32);
1250 desc64->physaddr[1] =
1251 htole32(segs[i].ds_addr & 0xffffffff);
1252 desc64->length = htole16(segs[i].ds_len - 1);
1253 desc64->vtag = htole32(vtag);
1254 desc64->flags = htole16(flags);
1256 desc32 = &ring->desc32[j];
1257 desc32->physaddr = htole32(segs[i].ds_addr);
1258 desc32->length = htole16(segs[i].ds_len - 1);
1259 desc32->flags = htole16(flags);
1262 /* csum flags and vtag belong to the first fragment only */
1263 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1267 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1270 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1271 if (sc->sc_caps & NFE_40BIT_ADDR) {
1272 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1274 if (sc->sc_caps & NFE_JUMBO_SUP)
1275 flags = NFE_TX_LASTFRAG_V2;
1277 flags = NFE_TX_LASTFRAG_V1;
1278 desc32->flags |= htole16(flags);
1282 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1283 * whole mess until the first descriptor in the map is flagged.
1285 for (i = ctx.nsegs - 1; i >= 0; --i) {
1286 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1287 if (sc->sc_caps & NFE_40BIT_ADDR) {
1288 desc64 = &ring->desc64[j];
1289 desc64->flags |= htole16(NFE_TX_VALID);
1291 desc32 = &ring->desc32[j];
1292 desc32->flags |= htole16(NFE_TX_VALID);
1295 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1297 /* Exchange DMA map */
1298 data_map->map = data->map;
1302 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1310 nfe_start(struct ifnet *ifp)
1312 struct nfe_softc *sc = ifp->if_softc;
1313 struct nfe_tx_ring *ring = &sc->txq;
1317 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1321 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1325 ETHER_BPF_MTAP(ifp, m0);
1327 if (nfe_encap(sc, ring, m0) != 0) {
1328 ifp->if_flags |= IFF_OACTIVE;
1335 * `m0' may be freed in nfe_encap(), so
1336 * it should not be touched any more.
1339 if (count == 0) /* nothing sent */
1342 /* Sync TX descriptor ring */
1343 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1346 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1349 * Set a timeout in case the chip goes out to lunch.
1355 nfe_watchdog(struct ifnet *ifp)
1357 struct nfe_softc *sc = ifp->if_softc;
1359 if (ifp->if_flags & IFF_RUNNING) {
1360 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1365 if_printf(ifp, "watchdog timeout\n");
1367 nfe_init(ifp->if_softc);
1375 struct nfe_softc *sc = xsc;
1376 struct ifnet *ifp = &sc->arpcom.ac_if;
1382 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
1387 * Switching between jumbo frames and normal frames should
1388 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1390 if (ifp->if_mtu > ETHERMTU) {
1391 sc->sc_flags |= NFE_F_USE_JUMBO;
1392 sc->rxq.bufsz = NFE_JBYTES;
1394 if_printf(ifp, "use jumbo frames\n");
1396 sc->sc_flags &= ~NFE_F_USE_JUMBO;
1397 sc->rxq.bufsz = MCLBYTES;
1399 if_printf(ifp, "use non-jumbo frames\n");
1402 error = nfe_init_tx_ring(sc, &sc->txq);
1408 error = nfe_init_rx_ring(sc, &sc->rxq);
1414 NFE_WRITE(sc, NFE_TX_POLL, 0);
1415 NFE_WRITE(sc, NFE_STATUS, 0);
1417 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1419 if (ifp->if_capenable & IFCAP_RXCSUM)
1420 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1423 * Although the adapter is capable of stripping VLAN tags from received
1424 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1425 * purpose. This will be done in software by our network stack.
1427 if (sc->sc_caps & NFE_HW_VLAN)
1428 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1430 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1432 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1434 if (sc->sc_caps & NFE_HW_VLAN)
1435 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1437 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1439 /* set MAC address */
1440 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1442 /* tell MAC where rings are in memory */
1444 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1446 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1448 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1450 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1452 NFE_WRITE(sc, NFE_RING_SIZE,
1453 (sc->sc_rx_ring_count - 1) << 16 |
1454 (NFE_TX_RING_COUNT - 1));
1456 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1458 /* force MAC to wakeup */
1459 tmp = NFE_READ(sc, NFE_PWR_STATE);
1460 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1462 tmp = NFE_READ(sc, NFE_PWR_STATE);
1463 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1465 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1466 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1467 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1469 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1470 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1472 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1474 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1475 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1477 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1482 nfe_ifmedia_upd(ifp);
1485 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1488 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1490 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1492 #ifdef DEVICE_POLLING
1493 if ((ifp->if_flags & IFF_POLLING))
1494 nfe_disable_intrs(sc);
1497 nfe_enable_intrs(sc);
1499 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1501 ifp->if_flags |= IFF_RUNNING;
1502 ifp->if_flags &= ~IFF_OACTIVE;
1505 * If we had stuff in the tx ring before its all cleaned out now
1506 * so we are not going to get an interrupt, jump-start any pending
1513 nfe_stop(struct nfe_softc *sc)
1515 struct ifnet *ifp = &sc->arpcom.ac_if;
1516 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
1519 callout_stop(&sc->sc_tick_ch);
1522 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1523 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
1525 #define WAITMAX 50000
1530 NFE_WRITE(sc, NFE_TX_CTL, 0);
1531 for (i = 0; i < WAITMAX; ++i) {
1533 if ((NFE_READ(sc, NFE_TX_STATUS) & NFE_TX_STATUS_BUSY) == 0)
1537 if_printf(ifp, "can't stop TX\n");
1543 NFE_WRITE(sc, NFE_RX_CTL, 0);
1544 for (i = 0; i < WAITMAX; ++i) {
1546 if ((NFE_READ(sc, NFE_RX_STATUS) & NFE_RX_STATUS_BUSY) == 0)
1550 if_printf(ifp, "can't stop RX\n");
1555 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
1557 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
1559 /* Disable interrupts */
1560 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1562 /* Reset Tx and Rx rings */
1563 nfe_reset_tx_ring(sc, &sc->txq);
1564 nfe_reset_rx_ring(sc, &sc->rxq);
1568 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1570 int i, j, error, descsize;
1573 if (sc->sc_caps & NFE_40BIT_ADDR) {
1574 desc = (void **)&ring->desc64;
1575 descsize = sizeof(struct nfe_desc64);
1577 desc = (void **)&ring->desc32;
1578 descsize = sizeof(struct nfe_desc32);
1581 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1582 M_DEVBUF, M_WAITOK | M_ZERO);
1583 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1584 M_DEVBUF, M_WAITOK | M_ZERO);
1586 ring->bufsz = MCLBYTES;
1587 ring->cur = ring->next = 0;
1589 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1590 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1592 sc->sc_rx_ring_count * descsize, 1,
1593 sc->sc_rx_ring_count * descsize,
1596 if_printf(&sc->arpcom.ac_if,
1597 "could not create desc RX DMA tag\n");
1601 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1604 if_printf(&sc->arpcom.ac_if,
1605 "could not allocate RX desc DMA memory\n");
1606 bus_dma_tag_destroy(ring->tag);
1611 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1612 sc->sc_rx_ring_count * descsize,
1613 nfe_ring_dma_addr, &ring->physaddr,
1616 if_printf(&sc->arpcom.ac_if,
1617 "could not load RX desc DMA map\n");
1618 bus_dmamem_free(ring->tag, *desc, ring->map);
1619 bus_dma_tag_destroy(ring->tag);
1624 if (sc->sc_caps & NFE_JUMBO_SUP) {
1625 error = nfe_jpool_alloc(sc, ring);
1627 if_printf(&sc->arpcom.ac_if,
1628 "could not allocate jumbo frames\n");
1633 error = bus_dma_tag_create(NULL, 1, 0,
1634 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1636 MCLBYTES, 1, MCLBYTES,
1637 0, &ring->data_tag);
1639 if_printf(&sc->arpcom.ac_if,
1640 "could not create RX mbuf DMA tag\n");
1644 /* Create a spare RX mbuf DMA map */
1645 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1647 if_printf(&sc->arpcom.ac_if,
1648 "could not create spare RX mbuf DMA map\n");
1649 bus_dma_tag_destroy(ring->data_tag);
1650 ring->data_tag = NULL;
1654 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1655 error = bus_dmamap_create(ring->data_tag, 0,
1656 &ring->data[i].map);
1658 if_printf(&sc->arpcom.ac_if,
1659 "could not create %dth RX mbuf DMA mapn", i);
1665 for (j = 0; j < i; ++j)
1666 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1667 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1668 bus_dma_tag_destroy(ring->data_tag);
1669 ring->data_tag = NULL;
1674 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1678 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1679 struct nfe_rx_data *data = &ring->data[i];
1681 if (data->m != NULL) {
1682 if ((sc->sc_flags & NFE_F_USE_JUMBO) == 0)
1683 bus_dmamap_unload(ring->data_tag, data->map);
1688 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1690 ring->cur = ring->next = 0;
1694 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1698 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1701 /* XXX should use a function pointer */
1702 if (sc->sc_flags & NFE_F_USE_JUMBO)
1703 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1705 error = nfe_newbuf_std(sc, ring, i, 1);
1707 if_printf(&sc->arpcom.ac_if,
1708 "could not allocate RX buffer\n");
1712 nfe_set_ready_rxdesc(sc, ring, i);
1714 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1720 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1722 if (ring->data_tag != NULL) {
1723 struct nfe_rx_data *data;
1726 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1727 data = &ring->data[i];
1729 if (data->m != NULL) {
1730 bus_dmamap_unload(ring->data_tag, data->map);
1733 bus_dmamap_destroy(ring->data_tag, data->map);
1735 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1736 bus_dma_tag_destroy(ring->data_tag);
1739 nfe_jpool_free(sc, ring);
1741 if (ring->jbuf != NULL)
1742 kfree(ring->jbuf, M_DEVBUF);
1743 if (ring->data != NULL)
1744 kfree(ring->data, M_DEVBUF);
1746 if (ring->tag != NULL) {
1749 if (sc->sc_caps & NFE_40BIT_ADDR)
1750 desc = ring->desc64;
1752 desc = ring->desc32;
1754 bus_dmamap_unload(ring->tag, ring->map);
1755 bus_dmamem_free(ring->tag, desc, ring->map);
1756 bus_dma_tag_destroy(ring->tag);
1760 static struct nfe_jbuf *
1761 nfe_jalloc(struct nfe_softc *sc)
1763 struct ifnet *ifp = &sc->arpcom.ac_if;
1764 struct nfe_jbuf *jbuf;
1766 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1768 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1770 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1773 if_printf(ifp, "no free jumbo buffer\n");
1776 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1782 nfe_jfree(void *arg)
1784 struct nfe_jbuf *jbuf = arg;
1785 struct nfe_softc *sc = jbuf->sc;
1786 struct nfe_rx_ring *ring = jbuf->ring;
1788 if (&ring->jbuf[jbuf->slot] != jbuf)
1789 panic("%s: free wrong jumbo buffer\n", __func__);
1790 else if (jbuf->inuse == 0)
1791 panic("%s: jumbo buffer already freed\n", __func__);
1793 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1794 atomic_subtract_int(&jbuf->inuse, 1);
1795 if (jbuf->inuse == 0)
1796 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1797 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1803 struct nfe_jbuf *jbuf = arg;
1804 struct nfe_rx_ring *ring = jbuf->ring;
1806 if (&ring->jbuf[jbuf->slot] != jbuf)
1807 panic("%s: ref wrong jumbo buffer\n", __func__);
1808 else if (jbuf->inuse == 0)
1809 panic("%s: jumbo buffer already freed\n", __func__);
1811 atomic_add_int(&jbuf->inuse, 1);
1815 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1817 struct nfe_jbuf *jbuf;
1818 bus_addr_t physaddr;
1823 * Allocate a big chunk of DMA'able memory.
1825 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1826 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1828 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1831 if_printf(&sc->arpcom.ac_if,
1832 "could not create jumbo DMA tag\n");
1836 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1837 BUS_DMA_WAITOK, &ring->jmap);
1839 if_printf(&sc->arpcom.ac_if,
1840 "could not allocate jumbo DMA memory\n");
1841 bus_dma_tag_destroy(ring->jtag);
1846 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1847 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1850 if_printf(&sc->arpcom.ac_if,
1851 "could not load jumbo DMA map\n");
1852 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1853 bus_dma_tag_destroy(ring->jtag);
1858 /* ..and split it into 9KB chunks */
1859 SLIST_INIT(&ring->jfreelist);
1862 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1863 jbuf = &ring->jbuf[i];
1870 jbuf->physaddr = physaddr;
1872 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1875 physaddr += NFE_JBYTES;
1882 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1884 if (ring->jtag != NULL) {
1885 bus_dmamap_unload(ring->jtag, ring->jmap);
1886 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1887 bus_dma_tag_destroy(ring->jtag);
1892 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1894 int i, j, error, descsize;
1897 if (sc->sc_caps & NFE_40BIT_ADDR) {
1898 desc = (void **)&ring->desc64;
1899 descsize = sizeof(struct nfe_desc64);
1901 desc = (void **)&ring->desc32;
1902 descsize = sizeof(struct nfe_desc32);
1906 ring->cur = ring->next = 0;
1908 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1909 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1911 NFE_TX_RING_COUNT * descsize, 1,
1912 NFE_TX_RING_COUNT * descsize,
1915 if_printf(&sc->arpcom.ac_if,
1916 "could not create TX desc DMA map\n");
1920 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1923 if_printf(&sc->arpcom.ac_if,
1924 "could not allocate TX desc DMA memory\n");
1925 bus_dma_tag_destroy(ring->tag);
1930 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1931 NFE_TX_RING_COUNT * descsize,
1932 nfe_ring_dma_addr, &ring->physaddr,
1935 if_printf(&sc->arpcom.ac_if,
1936 "could not load TX desc DMA map\n");
1937 bus_dmamem_free(ring->tag, *desc, ring->map);
1938 bus_dma_tag_destroy(ring->tag);
1943 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1944 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1946 NFE_JBYTES * NFE_MAX_SCATTER,
1947 NFE_MAX_SCATTER, NFE_JBYTES,
1948 0, &ring->data_tag);
1950 if_printf(&sc->arpcom.ac_if,
1951 "could not create TX buf DMA tag\n");
1955 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1956 error = bus_dmamap_create(ring->data_tag, 0,
1957 &ring->data[i].map);
1959 if_printf(&sc->arpcom.ac_if,
1960 "could not create %dth TX buf DMA map\n", i);
1967 for (j = 0; j < i; ++j)
1968 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1969 bus_dma_tag_destroy(ring->data_tag);
1970 ring->data_tag = NULL;
1975 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1979 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1980 struct nfe_tx_data *data = &ring->data[i];
1982 if (sc->sc_caps & NFE_40BIT_ADDR)
1983 ring->desc64[i].flags = 0;
1985 ring->desc32[i].flags = 0;
1987 if (data->m != NULL) {
1988 bus_dmamap_sync(ring->data_tag, data->map,
1989 BUS_DMASYNC_POSTWRITE);
1990 bus_dmamap_unload(ring->data_tag, data->map);
1995 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1998 ring->cur = ring->next = 0;
2002 nfe_init_tx_ring(struct nfe_softc *sc __unused,
2003 struct nfe_tx_ring *ring __unused)
2009 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
2011 if (ring->data_tag != NULL) {
2012 struct nfe_tx_data *data;
2015 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
2016 data = &ring->data[i];
2018 if (data->m != NULL) {
2019 bus_dmamap_unload(ring->data_tag, data->map);
2022 bus_dmamap_destroy(ring->data_tag, data->map);
2025 bus_dma_tag_destroy(ring->data_tag);
2028 if (ring->tag != NULL) {
2031 if (sc->sc_caps & NFE_40BIT_ADDR)
2032 desc = ring->desc64;
2034 desc = ring->desc32;
2036 bus_dmamap_unload(ring->tag, ring->map);
2037 bus_dmamem_free(ring->tag, desc, ring->map);
2038 bus_dma_tag_destroy(ring->tag);
2043 nfe_ifmedia_upd(struct ifnet *ifp)
2045 struct nfe_softc *sc = ifp->if_softc;
2046 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2048 if (mii->mii_instance != 0) {
2049 struct mii_softc *miisc;
2051 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2052 mii_phy_reset(miisc);
2060 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2062 struct nfe_softc *sc = ifp->if_softc;
2063 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2066 ifmr->ifm_status = mii->mii_media_status;
2067 ifmr->ifm_active = mii->mii_media_active;
2071 nfe_setmulti(struct nfe_softc *sc)
2073 struct ifnet *ifp = &sc->arpcom.ac_if;
2074 struct ifmultiaddr *ifma;
2075 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2076 uint32_t filter = NFE_RXFILTER_MAGIC;
2079 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2080 bzero(addr, ETHER_ADDR_LEN);
2081 bzero(mask, ETHER_ADDR_LEN);
2085 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2086 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2088 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2091 if (ifma->ifma_addr->sa_family != AF_LINK)
2094 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2095 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2096 addr[i] &= maddr[i];
2097 mask[i] &= ~maddr[i];
2101 for (i = 0; i < ETHER_ADDR_LEN; i++)
2105 addr[0] |= 0x01; /* make sure multicast bit is set */
2107 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2108 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2109 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2110 addr[5] << 8 | addr[4]);
2111 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2112 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2113 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2114 mask[5] << 8 | mask[4]);
2116 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2117 NFE_WRITE(sc, NFE_RXFILTER, filter);
2121 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2125 lo = NFE_READ(sc, NFE_MACADDR_LO);
2126 hi = NFE_READ(sc, NFE_MACADDR_HI);
2127 if (sc->sc_caps & NFE_FIX_EADDR) {
2128 addr[0] = (lo >> 8) & 0xff;
2129 addr[1] = (lo & 0xff);
2131 addr[2] = (hi >> 24) & 0xff;
2132 addr[3] = (hi >> 16) & 0xff;
2133 addr[4] = (hi >> 8) & 0xff;
2134 addr[5] = (hi & 0xff);
2136 addr[0] = (hi & 0xff);
2137 addr[1] = (hi >> 8) & 0xff;
2138 addr[2] = (hi >> 16) & 0xff;
2139 addr[3] = (hi >> 24) & 0xff;
2141 addr[4] = (lo & 0xff);
2142 addr[5] = (lo >> 8) & 0xff;
2147 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2149 NFE_WRITE(sc, NFE_MACADDR_LO,
2150 addr[5] << 8 | addr[4]);
2151 NFE_WRITE(sc, NFE_MACADDR_HI,
2152 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2158 struct nfe_softc *sc = arg;
2159 struct ifnet *ifp = &sc->arpcom.ac_if;
2160 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2162 lwkt_serialize_enter(ifp->if_serializer);
2165 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2167 lwkt_serialize_exit(ifp->if_serializer);
2171 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2176 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2178 *((uint32_t *)arg) = seg->ds_addr;
2182 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2183 bus_size_t mapsz __unused, int error)
2185 struct nfe_dma_ctx *ctx = arg;
2191 KASSERT(nsegs <= ctx->nsegs,
2192 ("too many segments(%d), should be <= %d\n",
2193 nsegs, ctx->nsegs));
2196 for (i = 0; i < nsegs; ++i)
2197 ctx->segs[i] = segs[i];
2201 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2204 struct nfe_rx_data *data = &ring->data[idx];
2205 struct nfe_dma_ctx ctx;
2206 bus_dma_segment_t seg;
2211 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2214 m->m_len = m->m_pkthdr.len = MCLBYTES;
2218 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2219 m, nfe_buf_dma_addr, &ctx,
2220 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2223 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2227 /* Unload originally mapped mbuf */
2228 bus_dmamap_unload(ring->data_tag, data->map);
2230 /* Swap this DMA map with tmp DMA map */
2232 data->map = ring->data_tmpmap;
2233 ring->data_tmpmap = map;
2235 /* Caller is assumed to have collected the old mbuf */
2238 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2240 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2245 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2248 struct nfe_rx_data *data = &ring->data[idx];
2249 struct nfe_jbuf *jbuf;
2252 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2256 jbuf = nfe_jalloc(sc);
2259 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2260 "-- packet dropped!\n");
2264 m->m_ext.ext_arg = jbuf;
2265 m->m_ext.ext_buf = jbuf->buf;
2266 m->m_ext.ext_free = nfe_jfree;
2267 m->m_ext.ext_ref = nfe_jref;
2268 m->m_ext.ext_size = NFE_JBYTES;
2270 m->m_data = m->m_ext.ext_buf;
2271 m->m_flags |= M_EXT;
2272 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2274 /* Caller is assumed to have collected the old mbuf */
2277 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2279 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2284 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2285 bus_addr_t physaddr)
2287 if (sc->sc_caps & NFE_40BIT_ADDR) {
2288 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2290 #if defined(__LP64__)
2291 desc64->physaddr[0] = htole32(physaddr >> 32);
2293 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2295 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2297 desc32->physaddr = htole32(physaddr);
2302 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2304 if (sc->sc_caps & NFE_40BIT_ADDR) {
2305 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2307 desc64->length = htole16(ring->bufsz);
2308 desc64->flags = htole16(NFE_RX_READY);
2310 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2312 desc32->length = htole16(ring->bufsz);
2313 desc32->flags = htole16(NFE_RX_READY);
2318 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2320 struct nfe_softc *sc = arg1;
2321 struct ifnet *ifp = &sc->arpcom.ac_if;
2325 lwkt_serialize_enter(ifp->if_serializer);
2327 flags = sc->sc_flags & ~NFE_F_DYN_IM;
2329 if (sc->sc_flags & NFE_F_DYN_IM)
2332 error = sysctl_handle_int(oidp, &v, 0, req);
2333 if (error || req->newptr == NULL)
2337 flags |= NFE_F_DYN_IM;
2341 if (v != sc->sc_imtime || (flags ^ sc->sc_flags)) {
2342 int old_imtime = sc->sc_imtime;
2343 uint32_t old_flags = sc->sc_flags;
2346 sc->sc_flags = flags;
2347 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2349 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2351 if (old_imtime * sc->sc_imtime == 0 ||
2352 (old_flags ^ sc->sc_flags)) {
2355 NFE_WRITE(sc, NFE_IMTIMER,
2356 NFE_IMTIME(sc->sc_imtime));
2361 lwkt_serialize_exit(ifp->if_serializer);
2366 nfe_powerup(device_t dev)
2368 struct nfe_softc *sc = device_get_softc(dev);
2373 * Bring MAC and PHY out of low power state
2376 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2378 did = pci_get_device(dev);
2379 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2380 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2381 pci_get_revid(dev) >= 0xa3)
2382 pwr_state |= NFE_PWRUP_REV_A3;
2384 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2388 nfe_mac_reset(struct nfe_softc *sc)
2390 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2391 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2393 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2395 /* Save several registers for later restoration */
2396 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2397 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2398 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2400 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2403 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2406 /* Restore saved registers */
2407 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2408 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2409 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2411 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
2415 nfe_enable_intrs(struct nfe_softc *sc)
2418 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
2419 * It is unclear how wide the timer is. Base programming does
2420 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
2421 * we don't get any interrupt moderation. TX moderation is
2422 * possible by using the timer interrupt instead of TX_DONE.
2424 * It is unclear whether there are other bits that can be
2425 * set to make the NFE device actually do interrupt moderation
2428 * For now set a 128uS interval as a placemark, but don't use
2431 if (sc->sc_imtime == 0)
2432 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
2434 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
2436 /* Enable interrupts */
2437 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
2439 if (sc->sc_irq_enable & NFE_IRQ_TIMER)
2440 sc->sc_flags |= NFE_F_IRQ_TIMER;
2442 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
2446 nfe_disable_intrs(struct nfe_softc *sc)
2448 /* Disable interrupts */
2449 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
2450 sc->sc_flags &= ~NFE_F_IRQ_TIMER;