sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_polling.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 115 #define BGE_MIN_FRAME           60
 116
 117 static const struct bge_type bge_devs[] = {
 118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 119                 "3COM 3C996 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 122                 "Alteon BCM5700 Gigabit Ethernet" },
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 124                 "Alteon BCM5701 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 127                 "Altima AC1000 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 129                 "Altima AC1002 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 131                 "Altima AC9100 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 134                 "Apple BCM5701 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 141                 "Broadcom BCM5702 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 145                 "Broadcom BCM5702 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 149                 "Broadcom BCM5703X Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 151                 "Broadcom BCM5703 Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 159                 "Broadcom BCM5705 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 161                 "Broadcom BCM5705F Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 163                 "Broadcom BCM5705K Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 165                 "Broadcom BCM5705M Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 169                 "Broadcom BCM5714C Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 171                 "Broadcom BCM5714S Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 173                 "Broadcom BCM5715 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 175                 "Broadcom BCM5715S Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 177                 "Broadcom BCM5720 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 179                 "Broadcom BCM5721 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 181                 "Broadcom BCM5722 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 183                 "Broadcom BCM5723 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 215                 "Broadcom BCM5761 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 217                 "Broadcom BCM5761E Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 219                 "Broadcom BCM5761S Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 221                 "Broadcom BCM5761SE Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 223                 "Broadcom BCM5764 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 225                 "Broadcom BCM5780 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 227                 "Broadcom BCM5780S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 229                 "Broadcom BCM5781 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 231                 "Broadcom BCM5782 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 233                 "Broadcom BCM5784 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 235                 "Broadcom BCM5785F Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 237                 "Broadcom BCM5785G Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 239                 "Broadcom BCM5786 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 241                 "Broadcom BCM5787 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 243                 "Broadcom BCM5787F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 245                 "Broadcom BCM5787M Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 247                 "Broadcom BCM5788 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 249                 "Broadcom BCM5789 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 251                 "Broadcom BCM5901 Fast Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 253                 "Broadcom BCM5901A2 Fast Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 255                 "Broadcom BCM5903M Fast Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 257                 "Broadcom BCM5906 Fast Ethernet"},
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 259                 "Broadcom BCM5906M Fast Ethernet"},
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 261                 "Broadcom BCM57760 Gigabit Ethernet"},
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 263                 "Broadcom BCM57780 Gigabit Ethernet"},
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 265                 "Broadcom BCM57788 Gigabit Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 267                 "Broadcom BCM57790 Gigabit Ethernet"},
 268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 269                 "SysKonnect Gigabit Ethernet" },
 270
 271         { 0, 0, NULL }
 272 };
 273
 274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 280
 281 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 282
 283 static int      bge_probe(device_t);
 284 static int      bge_attach(device_t);
 285 static int      bge_detach(device_t);
 286 static void     bge_txeof(struct bge_softc *);
 287 static void     bge_rxeof(struct bge_softc *);
 288
 289 static void     bge_tick(void *);
 290 static void     bge_stats_update(struct bge_softc *);
 291 static void     bge_stats_update_regs(struct bge_softc *);
 292 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 293
 294 #ifdef DEVICE_POLLING
 295 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 296 #endif
 297 static void     bge_intr(void *);
 298 static void     bge_enable_intr(struct bge_softc *);
 299 static void     bge_disable_intr(struct bge_softc *);
 300 static void     bge_start(struct ifnet *);
 301 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 302 static void     bge_init(void *);
 303 static void     bge_stop(struct bge_softc *);
 304 static void     bge_watchdog(struct ifnet *);
 305 static void     bge_shutdown(device_t);
 306 static int      bge_suspend(device_t);
 307 static int      bge_resume(device_t);
 308 static int      bge_ifmedia_upd(struct ifnet *);
 309 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 310
 311 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 312 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 313
 314 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 315 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 316
 317 static void     bge_setmulti(struct bge_softc *);
 318 static void     bge_setpromisc(struct bge_softc *);
 319
 320 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 321 static void     bge_free_jumbo_mem(struct bge_softc *);
 322 static struct bge_jslot
 323                 *bge_jalloc(struct bge_softc *);
 324 static void     bge_jfree(void *);
 325 static void     bge_jref(void *);
 326 static int      bge_newbuf_std(struct bge_softc *, int, int);
 327 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 328 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 329 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 330 static int      bge_init_rx_ring_std(struct bge_softc *);
 331 static void     bge_free_rx_ring_std(struct bge_softc *);
 332 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 333 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 334 static void     bge_free_tx_ring(struct bge_softc *);
 335 static int      bge_init_tx_ring(struct bge_softc *);
 336
 337 static int      bge_chipinit(struct bge_softc *);
 338 static int      bge_blockinit(struct bge_softc *);
 339
 340 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 341 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 342 #ifdef notdef
 343 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 344 #endif
 345 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 346 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 347 static void     bge_writembx(struct bge_softc *, int, int);
 348
 349 static int      bge_miibus_readreg(device_t, int, int);
 350 static int      bge_miibus_writereg(device_t, int, int, int);
 351 static void     bge_miibus_statchg(device_t);
 352 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 353 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 354 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 355
 356 static void     bge_reset(struct bge_softc *);
 357
 358 static int      bge_dma_alloc(struct bge_softc *);
 359 static void     bge_dma_free(struct bge_softc *);
 360 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 361                                     bus_dma_tag_t *, bus_dmamap_t *,
 362                                     void **, bus_addr_t *);
 363 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 364
 365 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 366 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 367 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 368 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 369
 370 static void     bge_coal_change(struct bge_softc *);
 371 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 372 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 373 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 374 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 375 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 376
 377 /*
 378  * Set following tunable to 1 for some IBM blade servers with the DNLK
 379  * switch module. Auto negotiation is broken for those configurations.
 380  */
 381 static int      bge_fake_autoneg = 0;
 382 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 383
 384 /* Interrupt moderation control variables. */
 385 static int      bge_rx_coal_ticks = 100;        /* usec */
 386 static int      bge_tx_coal_ticks = 1023;       /* usec */
 387 static int      bge_rx_max_coal_bds = 80;
 388 static int      bge_tx_max_coal_bds = 128;
 389
 390 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 391 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 392 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 393 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 394
 395 #if !defined(KTR_IF_BGE)
 396 #define KTR_IF_BGE      KTR_ALL
 397 #endif
 398 KTR_INFO_MASTER(if_bge);
 399 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 400 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 401 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 402 #define logif(name)     KTR_LOG(if_bge_ ## name)
 403
 404 static device_method_t bge_methods[] = {
 405         /* Device interface */
 406         DEVMETHOD(device_probe,         bge_probe),
 407         DEVMETHOD(device_attach,        bge_attach),
 408         DEVMETHOD(device_detach,        bge_detach),
 409         DEVMETHOD(device_shutdown,      bge_shutdown),
 410         DEVMETHOD(device_suspend,       bge_suspend),
 411         DEVMETHOD(device_resume,        bge_resume),
 412
 413         /* bus interface */
 414         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 415         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 416
 417         /* MII interface */
 418         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 419         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 420         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 421
 422         { 0, 0 }
 423 };
 424
 425 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 426 static devclass_t bge_devclass;
 427
 428 DECLARE_DUMMY_MODULE(if_bge);
 429 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 430 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 431
 432 static uint32_t
 433 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 434 {
 435         device_t dev = sc->bge_dev;
 436         uint32_t val;
 437
 438         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 439         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 440         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 441         return (val);
 442 }
 443
 444 static void
 445 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 446 {
 447         device_t dev = sc->bge_dev;
 448
 449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 450         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 451         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 452 }
 453
 454 #ifdef notdef
 455 static uint32_t
 456 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 457 {
 458         device_t dev = sc->bge_dev;
 459
 460         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 461         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 462 }
 463 #endif
 464
 465 static void
 466 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 467 {
 468         device_t dev = sc->bge_dev;
 469
 470         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 471         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 472 }
 473
 474 static void
 475 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 476 {
 477         CSR_WRITE_4(sc, off, val);
 478 }
 479
 480 static void
 481 bge_writembx(struct bge_softc *sc, int off, int val)
 482 {
 483         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 484                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 485
 486         CSR_WRITE_4(sc, off, val);
 487 }
 488
 489 static uint8_t
 490 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 491 {
 492         uint32_t access, byte = 0;
 493         int i;
 494
 495         /* Lock. */
 496         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 497         for (i = 0; i < 8000; i++) {
 498                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 499                         break;
 500                 DELAY(20);
 501         }
 502         if (i == 8000)
 503                 return (1);
 504
 505         /* Enable access. */
 506         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 508
 509         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 510         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 511         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 512                 DELAY(10);
 513                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 514                         DELAY(10);
 515                         break;
 516                 }
 517         }
 518
 519         if (i == BGE_TIMEOUT * 10) {
 520                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 521                 return (1);
 522         }
 523
 524         /* Get result. */
 525         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 526
 527         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 528
 529         /* Disable access. */
 530         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 531
 532         /* Unlock. */
 533         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 534         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 535
 536         return (0);
 537 }
 538
 539 /*
 540  * Read a sequence of bytes from NVRAM.
 541  */
 542 static int
 543 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 544 {
 545         int err = 0, i;
 546         uint8_t byte = 0;
 547
 548         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 549                 return (1);
 550
 551         for (i = 0; i < cnt; i++) {
 552                 err = bge_nvram_getbyte(sc, off + i, &byte);
 553                 if (err)
 554                         break;
 555                 *(dest + i) = byte;
 556         }
 557
 558         return (err ? 1 : 0);
 559 }
 560
 561 /*
 562  * Read a byte of data stored in the EEPROM at address 'addr.' The
 563  * BCM570x supports both the traditional bitbang interface and an
 564  * auto access interface for reading the EEPROM. We use the auto
 565  * access method.
 566  */
 567 static uint8_t
 568 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 569 {
 570         int i;
 571         uint32_t byte = 0;
 572
 573         /*
 574          * Enable use of auto EEPROM access so we can avoid
 575          * having to use the bitbang method.
 576          */
 577         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 578
 579         /* Reset the EEPROM, load the clock period. */
 580         CSR_WRITE_4(sc, BGE_EE_ADDR,
 581             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 582         DELAY(20);
 583
 584         /* Issue the read EEPROM command. */
 585         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 586
 587         /* Wait for completion */
 588         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 589                 DELAY(10);
 590                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 591                         break;
 592         }
 593
 594         if (i == BGE_TIMEOUT) {
 595                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 596                 return(1);
 597         }
 598
 599         /* Get result. */
 600         byte = CSR_READ_4(sc, BGE_EE_DATA);
 601
 602         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 603
 604         return(0);
 605 }
 606
 607 /*
 608  * Read a sequence of bytes from the EEPROM.
 609  */
 610 static int
 611 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 612 {
 613         size_t i;
 614         int err;
 615         uint8_t byte;
 616
 617         for (byte = 0, err = 0, i = 0; i < len; i++) {
 618                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 619                 if (err)
 620                         break;
 621                 *(dest + i) = byte;
 622         }
 623
 624         return(err ? 1 : 0);
 625 }
 626
 627 static int
 628 bge_miibus_readreg(device_t dev, int phy, int reg)
 629 {
 630         struct bge_softc *sc = device_get_softc(dev);
 631         struct ifnet *ifp = &sc->arpcom.ac_if;
 632         uint32_t val, autopoll;
 633         int i;
 634
 635         /*
 636          * Broadcom's own driver always assumes the internal
 637          * PHY is at GMII address 1. On some chips, the PHY responds
 638          * to accesses at all addresses, which could cause us to
 639          * bogusly attach the PHY 32 times at probe type. Always
 640          * restricting the lookup to address 1 is simpler than
 641          * trying to figure out which chips revisions should be
 642          * special-cased.
 643          */
 644         if (phy != 1)
 645                 return(0);
 646
 647         /* Reading with autopolling on may trigger PCI errors */
 648         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 649         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 650                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 651                 DELAY(40);
 652         }
 653
 654         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 655             BGE_MIPHY(phy)|BGE_MIREG(reg));
 656
 657         for (i = 0; i < BGE_TIMEOUT; i++) {
 658                 DELAY(10);
 659                 val = CSR_READ_4(sc, BGE_MI_COMM);
 660                 if (!(val & BGE_MICOMM_BUSY))
 661                         break;
 662         }
 663
 664         if (i == BGE_TIMEOUT) {
 665                 if_printf(ifp, "PHY read timed out "
 666                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 667                 val = 0;
 668                 goto done;
 669         }
 670
 671         DELAY(5);
 672         val = CSR_READ_4(sc, BGE_MI_COMM);
 673
 674 done:
 675         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 676                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 677                 DELAY(40);
 678         }
 679
 680         if (val & BGE_MICOMM_READFAIL)
 681                 return(0);
 682
 683         return(val & 0xFFFF);
 684 }
 685
 686 static int
 687 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 688 {
 689         struct bge_softc *sc = device_get_softc(dev);
 690         uint32_t autopoll;
 691         int i;
 692
 693         /*
 694          * See the related comment in bge_miibus_readreg()
 695          */
 696         if (phy != 1)
 697                 return(0);
 698
 699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 701                return(0);
 702
 703         /* Reading with autopolling on may trigger PCI errors */
 704         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 705         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 706                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 707                 DELAY(40);
 708         }
 709
 710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 711             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 712
 713         for (i = 0; i < BGE_TIMEOUT; i++) {
 714                 DELAY(10);
 715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 716                         DELAY(5);
 717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 718                         break;
 719                 }
 720         }
 721
 722         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 723                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 724                 DELAY(40);
 725         }
 726
 727         if (i == BGE_TIMEOUT) {
 728                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 729                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 730                 return(0);
 731         }
 732
 733         return(0);
 734 }
 735
 736 static void
 737 bge_miibus_statchg(device_t dev)
 738 {
 739         struct bge_softc *sc;
 740         struct mii_data *mii;
 741
 742         sc = device_get_softc(dev);
 743         mii = device_get_softc(sc->bge_miibus);
 744
 745         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 746         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 747                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 748         } else {
 749                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 750         }
 751
 752         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 753                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 754         } else {
 755                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 756         }
 757 }
 758
 759 /*
 760  * Memory management for jumbo frames.
 761  */
 762 static int
 763 bge_alloc_jumbo_mem(struct bge_softc *sc)
 764 {
 765         struct ifnet *ifp = &sc->arpcom.ac_if;
 766         struct bge_jslot *entry;
 767         uint8_t *ptr;
 768         bus_addr_t paddr;
 769         int i, error;
 770
 771         /*
 772          * Create tag for jumbo mbufs.
 773          * This is really a bit of a kludge. We allocate a special
 774          * jumbo buffer pool which (thanks to the way our DMA
 775          * memory allocation works) will consist of contiguous
 776          * pages. This means that even though a jumbo buffer might
 777          * be larger than a page size, we don't really need to
 778          * map it into more than one DMA segment. However, the
 779          * default mbuf tag will result in multi-segment mappings,
 780          * so we have to create a special jumbo mbuf tag that
 781          * lets us get away with mapping the jumbo buffers as
 782          * a single segment. I think eventually the driver should
 783          * be changed so that it uses ordinary mbufs and cluster
 784          * buffers, i.e. jumbo frames can span multiple DMA
 785          * descriptors. But that's a project for another day.
 786          */
 787
 788         /*
 789          * Create DMA stuffs for jumbo RX ring.
 790          */
 791         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 792                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 793                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 794                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 795                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 796         if (error) {
 797                 if_printf(ifp, "could not create jumbo RX ring\n");
 798                 return error;
 799         }
 800
 801         /*
 802          * Create DMA stuffs for jumbo buffer block.
 803          */
 804         error = bge_dma_block_alloc(sc, BGE_JMEM,
 805                                     &sc->bge_cdata.bge_jumbo_tag,
 806                                     &sc->bge_cdata.bge_jumbo_map,
 807                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 808                                     &paddr);
 809         if (error) {
 810                 if_printf(ifp, "could not create jumbo buffer\n");
 811                 return error;
 812         }
 813
 814         SLIST_INIT(&sc->bge_jfree_listhead);
 815
 816         /*
 817          * Now divide it up into 9K pieces and save the addresses
 818          * in an array. Note that we play an evil trick here by using
 819          * the first few bytes in the buffer to hold the the address
 820          * of the softc structure for this interface. This is because
 821          * bge_jfree() needs it, but it is called by the mbuf management
 822          * code which will not pass it to us explicitly.
 823          */
 824         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 825                 entry = &sc->bge_cdata.bge_jslots[i];
 826                 entry->bge_sc = sc;
 827                 entry->bge_buf = ptr;
 828                 entry->bge_paddr = paddr;
 829                 entry->bge_inuse = 0;
 830                 entry->bge_slot = i;
 831                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 832
 833                 ptr += BGE_JLEN;
 834                 paddr += BGE_JLEN;
 835         }
 836         return 0;
 837 }
 838
 839 static void
 840 bge_free_jumbo_mem(struct bge_softc *sc)
 841 {
 842         /* Destroy jumbo RX ring. */
 843         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 844                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 845                            sc->bge_ldata.bge_rx_jumbo_ring);
 846
 847         /* Destroy jumbo buffer block. */
 848         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 849                            sc->bge_cdata.bge_jumbo_map,
 850                            sc->bge_ldata.bge_jumbo_buf);
 851 }
 852
 853 /*
 854  * Allocate a jumbo buffer.
 855  */
 856 static struct bge_jslot *
 857 bge_jalloc(struct bge_softc *sc)
 858 {
 859         struct bge_jslot *entry;
 860
 861         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 862         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 863         if (entry) {
 864                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 865                 entry->bge_inuse = 1;
 866         } else {
 867                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 868         }
 869         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 870         return(entry);
 871 }
 872
 873 /*
 874  * Adjust usage count on a jumbo buffer.
 875  */
 876 static void
 877 bge_jref(void *arg)
 878 {
 879         struct bge_jslot *entry = (struct bge_jslot *)arg;
 880         struct bge_softc *sc = entry->bge_sc;
 881
 882         if (sc == NULL)
 883                 panic("bge_jref: can't find softc pointer!");
 884
 885         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 886                 panic("bge_jref: asked to reference buffer "
 887                     "that we don't manage!");
 888         } else if (entry->bge_inuse == 0) {
 889                 panic("bge_jref: buffer already free!");
 890         } else {
 891                 atomic_add_int(&entry->bge_inuse, 1);
 892         }
 893 }
 894
 895 /*
 896  * Release a jumbo buffer.
 897  */
 898 static void
 899 bge_jfree(void *arg)
 900 {
 901         struct bge_jslot *entry = (struct bge_jslot *)arg;
 902         struct bge_softc *sc = entry->bge_sc;
 903
 904         if (sc == NULL)
 905                 panic("bge_jfree: can't find softc pointer!");
 906
 907         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 908                 panic("bge_jfree: asked to free buffer that we don't manage!");
 909         } else if (entry->bge_inuse == 0) {
 910                 panic("bge_jfree: buffer already free!");
 911         } else {
 912                 /*
 913                  * Possible MP race to 0, use the serializer.  The atomic insn
 914                  * is still needed for races against bge_jref().
 915                  */
 916                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 917                 atomic_subtract_int(&entry->bge_inuse, 1);
 918                 if (entry->bge_inuse == 0) {
 919                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 920                                           entry, jslot_link);
 921                 }
 922                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 923         }
 924 }
 925
 926
 927 /*
 928  * Intialize a standard receive ring descriptor.
 929  */
 930 static int
 931 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 932 {
 933         struct mbuf *m_new = NULL;
 934         bus_dma_segment_t seg;
 935         bus_dmamap_t map;
 936         int error, nsegs;
 937
 938         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 939         if (m_new == NULL)
 940                 return ENOBUFS;
 941         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 942
 943         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 944                 m_adj(m_new, ETHER_ALIGN);
 945
 946         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 947                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 948                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 949         if (error) {
 950                 m_freem(m_new);
 951                 return error;
 952         }
 953
 954         if (!init) {
 955                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 956                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 957                                 BUS_DMASYNC_POSTREAD);
 958                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 959                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 960         }
 961
 962         map = sc->bge_cdata.bge_rx_tmpmap;
 963         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 964         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 965
 966         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 967         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 968
 969         bge_setup_rxdesc_std(sc, i);
 970         return 0;
 971 }
 972
 973 static void
 974 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
 975 {
 976         struct bge_rxchain *rc;
 977         struct bge_rx_bd *r;
 978
 979         rc = &sc->bge_cdata.bge_rx_std_chain[i];
 980         r = &sc->bge_ldata.bge_rx_std_ring[i];
 981
 982         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
 983         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
 984         r->bge_len = rc->bge_mbuf->m_len;
 985         r->bge_idx = i;
 986         r->bge_flags = BGE_RXBDFLAG_END;
 987 }
 988
 989 /*
 990  * Initialize a jumbo receive ring descriptor. This allocates
 991  * a jumbo buffer from the pool managed internally by the driver.
 992  */
 993 static int
 994 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
 995 {
 996         struct mbuf *m_new = NULL;
 997         struct bge_jslot *buf;
 998         bus_addr_t paddr;
 999
1000         /* Allocate the mbuf. */
1001         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1002         if (m_new == NULL)
1003                 return ENOBUFS;
1004
1005         /* Allocate the jumbo buffer */
1006         buf = bge_jalloc(sc);
1007         if (buf == NULL) {
1008                 m_freem(m_new);
1009                 return ENOBUFS;
1010         }
1011
1012         /* Attach the buffer to the mbuf. */
1013         m_new->m_ext.ext_arg = buf;
1014         m_new->m_ext.ext_buf = buf->bge_buf;
1015         m_new->m_ext.ext_free = bge_jfree;
1016         m_new->m_ext.ext_ref = bge_jref;
1017         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1018
1019         m_new->m_flags |= M_EXT;
1020
1021         m_new->m_data = m_new->m_ext.ext_buf;
1022         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1023
1024         paddr = buf->bge_paddr;
1025         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1026                 m_adj(m_new, ETHER_ALIGN);
1027                 paddr += ETHER_ALIGN;
1028         }
1029
1030         /* Save necessary information */
1031         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1032         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1033
1034         /* Set up the descriptor. */
1035         bge_setup_rxdesc_jumbo(sc, i);
1036         return 0;
1037 }
1038
1039 static void
1040 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1041 {
1042         struct bge_rx_bd *r;
1043         struct bge_rxchain *rc;
1044
1045         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1046         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1047
1048         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1049         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1050         r->bge_len = rc->bge_mbuf->m_len;
1051         r->bge_idx = i;
1052         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1053 }
1054
1055 static int
1056 bge_init_rx_ring_std(struct bge_softc *sc)
1057 {
1058         int i, error;
1059
1060         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1061                 error = bge_newbuf_std(sc, i, 1);
1062                 if (error)
1063                         return error;
1064         };
1065
1066         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return(0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1079
1080                 if (rc->bge_mbuf != NULL) {
1081                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1082                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1083                         m_freem(rc->bge_mbuf);
1084                         rc->bge_mbuf = NULL;
1085                 }
1086                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1087                     sizeof(struct bge_rx_bd));
1088         }
1089 }
1090
1091 static int
1092 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1093 {
1094         struct bge_rcb *rcb;
1095         int i, error;
1096
1097         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1098                 error = bge_newbuf_jumbo(sc, i, 1);
1099                 if (error)
1100                         return error;
1101         };
1102
1103         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1104
1105         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1106         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1107         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1108
1109         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1110
1111         return(0);
1112 }
1113
1114 static void
1115 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1116 {
1117         int i;
1118
1119         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1120                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1121
1122                 if (rc->bge_mbuf != NULL) {
1123                         m_freem(rc->bge_mbuf);
1124                         rc->bge_mbuf = NULL;
1125                 }
1126                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1127                     sizeof(struct bge_rx_bd));
1128         }
1129 }
1130
1131 static void
1132 bge_free_tx_ring(struct bge_softc *sc)
1133 {
1134         int i;
1135
1136         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1137                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1138                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1139                                           sc->bge_cdata.bge_tx_dmamap[i]);
1140                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1141                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1142                 }
1143                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1144                     sizeof(struct bge_tx_bd));
1145         }
1146 }
1147
1148 static int
1149 bge_init_tx_ring(struct bge_softc *sc)
1150 {
1151         sc->bge_txcnt = 0;
1152         sc->bge_tx_saved_considx = 0;
1153         sc->bge_tx_prodidx = 0;
1154
1155         /* Initialize transmit producer index for host-memory send ring. */
1156         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1157
1158         /* 5700 b2 errata */
1159         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1160                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1161
1162         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1163         /* 5700 b2 errata */
1164         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1165                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1166
1167         return(0);
1168 }
1169
1170 static void
1171 bge_setmulti(struct bge_softc *sc)
1172 {
1173         struct ifnet *ifp;
1174         struct ifmultiaddr *ifma;
1175         uint32_t hashes[4] = { 0, 0, 0, 0 };
1176         int h, i;
1177
1178         ifp = &sc->arpcom.ac_if;
1179
1180         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1181                 for (i = 0; i < 4; i++)
1182                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1183                 return;
1184         }
1185
1186         /* First, zot all the existing filters. */
1187         for (i = 0; i < 4; i++)
1188                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1189
1190         /* Now program new ones. */
1191         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1192                 if (ifma->ifma_addr->sa_family != AF_LINK)
1193                         continue;
1194                 h = ether_crc32_le(
1195                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1196                     ETHER_ADDR_LEN) & 0x7f;
1197                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1198         }
1199
1200         for (i = 0; i < 4; i++)
1201                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1202 }
1203
1204 /*
1205  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1206  * self-test results.
1207  */
1208 static int
1209 bge_chipinit(struct bge_softc *sc)
1210 {
1211         int i;
1212         uint32_t dma_rw_ctl;
1213         uint16_t val;
1214
1215         /* Set endian type before we access any non-PCI registers. */
1216         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1217
1218         /* Clear the MAC control register */
1219         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1220
1221         /*
1222          * Clear the MAC statistics block in the NIC's
1223          * internal memory.
1224          */
1225         for (i = BGE_STATS_BLOCK;
1226             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1227                 BGE_MEMWIN_WRITE(sc, i, 0);
1228
1229         for (i = BGE_STATUS_BLOCK;
1230             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1231                 BGE_MEMWIN_WRITE(sc, i, 0);
1232
1233         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1234                 /*
1235                  * Fix data corruption caused by non-qword write with WB.
1236                  * Fix master abort in PCI mode.
1237                  * Fix PCI latency timer.
1238                  */
1239                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1240                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1241                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1242         }
1243
1244         /* Set up the PCI DMA control register. */
1245         if (sc->bge_flags & BGE_FLAG_PCIE) {
1246                 /* PCI Express */
1247                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1248                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1249                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1250         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1251                 /* PCI-X bus */
1252                 if (BGE_IS_5714_FAMILY(sc)) {
1253                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1254                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1255                         /* XXX magic values, Broadcom-supplied Linux driver */
1256                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1257                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1258                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1259                         } else {
1260                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1261                         }
1262                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1263                         /*
1264                          * The 5704 uses a different encoding of read/write
1265                          * watermarks.
1266                          */
1267                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1268                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1269                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1270                 } else {
1271                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1272                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1273                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1274                             (0x0F);
1275                 }
1276
1277                 /*
1278                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1279                  * for hardware bugs.
1280                  */
1281                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1282                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1283                         uint32_t tmp;
1284
1285                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1286                         if (tmp == 0x6 || tmp == 0x7)
1287                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1288                 }
1289         } else {
1290                 /* Conventional PCI bus */
1291                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1292                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1293                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1294                     (0x0F);
1295         }
1296
1297         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1298             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1299             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1300                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1301         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1302
1303         /*
1304          * Set up general mode register.
1305          */
1306         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1307             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1308             BGE_MODECTL_TX_NO_PHDR_CSUM);
1309
1310         /*
1311          * BCM5701 B5 have a bug causing data corruption when using
1312          * 64-bit DMA reads, which can be terminated early and then
1313          * completed later as 32-bit accesses, in combination with
1314          * certain bridges.
1315          */
1316         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1317             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1318                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1319
1320         /*
1321          * Disable memory write invalidate.  Apparently it is not supported
1322          * properly by these devices.
1323          */
1324         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1325
1326         /* Set the timer prescaler (always 66Mhz) */
1327         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1328
1329         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1330                 DELAY(40);      /* XXX */
1331
1332                 /* Put PHY into ready state */
1333                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1334                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1335                 DELAY(40);
1336         }
1337
1338         return(0);
1339 }
1340
1341 static int
1342 bge_blockinit(struct bge_softc *sc)
1343 {
1344         struct bge_rcb *rcb;
1345         bus_size_t vrcb;
1346         bge_hostaddr taddr;
1347         uint32_t val;
1348         int i;
1349
1350         /*
1351          * Initialize the memory window pointer register so that
1352          * we can access the first 32K of internal NIC RAM. This will
1353          * allow us to set up the TX send ring RCBs and the RX return
1354          * ring RCBs, plus other things which live in NIC memory.
1355          */
1356         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1357
1358         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1359
1360         if (!BGE_IS_5705_PLUS(sc)) {
1361                 /* Configure mbuf memory pool */
1362                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1363                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1364                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1365                 else
1366                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1367
1368                 /* Configure DMA resource pool */
1369                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1370                     BGE_DMA_DESCRIPTORS);
1371                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1372         }
1373
1374         /* Configure mbuf pool watermarks */
1375         if (!BGE_IS_5705_PLUS(sc)) {
1376                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1377                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1378                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1379         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1380                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1381                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1382                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1383         } else {
1384                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1385                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1386                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1387         }
1388
1389         /* Configure DMA resource watermarks */
1390         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1391         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1392
1393         /* Enable buffer manager */
1394         if (!BGE_IS_5705_PLUS(sc)) {
1395                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1396                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1397
1398                 /* Poll for buffer manager start indication */
1399                 for (i = 0; i < BGE_TIMEOUT; i++) {
1400                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1401                                 break;
1402                         DELAY(10);
1403                 }
1404
1405                 if (i == BGE_TIMEOUT) {
1406                         if_printf(&sc->arpcom.ac_if,
1407                                   "buffer manager failed to start\n");
1408                         return(ENXIO);
1409                 }
1410         }
1411
1412         /* Enable flow-through queues */
1413         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1414         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1415
1416         /* Wait until queue initialization is complete */
1417         for (i = 0; i < BGE_TIMEOUT; i++) {
1418                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1419                         break;
1420                 DELAY(10);
1421         }
1422
1423         if (i == BGE_TIMEOUT) {
1424                 if_printf(&sc->arpcom.ac_if,
1425                           "flow-through queue init failed\n");
1426                 return(ENXIO);
1427         }
1428
1429         /* Initialize the standard RX ring control block */
1430         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1431         rcb->bge_hostaddr.bge_addr_lo =
1432             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1433         rcb->bge_hostaddr.bge_addr_hi =
1434             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1435         if (BGE_IS_5705_PLUS(sc))
1436                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1437         else
1438                 rcb->bge_maxlen_flags =
1439                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1440         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1441         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1442         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1443         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1444         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1445
1446         /*
1447          * Initialize the jumbo RX ring control block
1448          * We set the 'ring disabled' bit in the flags
1449          * field until we're actually ready to start
1450          * using this ring (i.e. once we set the MTU
1451          * high enough to require it).
1452          */
1453         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1454                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1455
1456                 rcb->bge_hostaddr.bge_addr_lo =
1457                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1458                 rcb->bge_hostaddr.bge_addr_hi =
1459                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1460                 rcb->bge_maxlen_flags =
1461                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1462                     BGE_RCB_FLAG_RING_DISABLED);
1463                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1464                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1465                     rcb->bge_hostaddr.bge_addr_hi);
1466                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1467                     rcb->bge_hostaddr.bge_addr_lo);
1468                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1469                     rcb->bge_maxlen_flags);
1470                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1471
1472                 /* Set up dummy disabled mini ring RCB */
1473                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1474                 rcb->bge_maxlen_flags =
1475                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1476                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1477                     rcb->bge_maxlen_flags);
1478         }
1479
1480         /*
1481          * Set the BD ring replentish thresholds. The recommended
1482          * values are 1/8th the number of descriptors allocated to
1483          * each ring.
1484          */
1485         if (BGE_IS_5705_PLUS(sc))
1486                 val = 8;
1487         else
1488                 val = BGE_STD_RX_RING_CNT / 8;
1489         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1490         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1491
1492         /*
1493          * Disable all unused send rings by setting the 'ring disabled'
1494          * bit in the flags field of all the TX send ring control blocks.
1495          * These are located in NIC memory.
1496          */
1497         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1498         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1499                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1500                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1501                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1502                 vrcb += sizeof(struct bge_rcb);
1503         }
1504
1505         /* Configure TX RCB 0 (we use only the first ring) */
1506         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1507         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1508         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1509         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1510         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1511             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1512         if (!BGE_IS_5705_PLUS(sc)) {
1513                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1514                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1515         }
1516
1517         /* Disable all unused RX return rings */
1518         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1519         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1520                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1521                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1522                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1523                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1524                     BGE_RCB_FLAG_RING_DISABLED));
1525                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1526                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1527                     (i * (sizeof(uint64_t))), 0);
1528                 vrcb += sizeof(struct bge_rcb);
1529         }
1530
1531         /* Initialize RX ring indexes */
1532         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1533         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1534         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1535
1536         /*
1537          * Set up RX return ring 0
1538          * Note that the NIC address for RX return rings is 0x00000000.
1539          * The return rings live entirely within the host, so the
1540          * nicaddr field in the RCB isn't used.
1541          */
1542         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1543         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1544         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1545         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1546         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1547         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1548             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1549
1550         /* Set random backoff seed for TX */
1551         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1552             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1553             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1554             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1555             BGE_TX_BACKOFF_SEED_MASK);
1556
1557         /* Set inter-packet gap */
1558         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1559
1560         /*
1561          * Specify which ring to use for packets that don't match
1562          * any RX rules.
1563          */
1564         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1565
1566         /*
1567          * Configure number of RX lists. One interrupt distribution
1568          * list, sixteen active lists, one bad frames class.
1569          */
1570         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1571
1572         /* Inialize RX list placement stats mask. */
1573         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1574         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1575
1576         /* Disable host coalescing until we get it set up */
1577         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1578
1579         /* Poll to make sure it's shut down. */
1580         for (i = 0; i < BGE_TIMEOUT; i++) {
1581                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1582                         break;
1583                 DELAY(10);
1584         }
1585
1586         if (i == BGE_TIMEOUT) {
1587                 if_printf(&sc->arpcom.ac_if,
1588                           "host coalescing engine failed to idle\n");
1589                 return(ENXIO);
1590         }
1591
1592         /* Set up host coalescing defaults */
1593         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1594         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1595         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1596         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1597         if (!BGE_IS_5705_PLUS(sc)) {
1598                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1599                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1600         }
1601         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1602         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1603
1604         /* Set up address of statistics block */
1605         if (!BGE_IS_5705_PLUS(sc)) {
1606                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1607                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1608                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1609                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1610
1611                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1612                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1613                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1614         }
1615
1616         /* Set up address of status block */
1617         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1618             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1619         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1620             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1621         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1622         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1623
1624         /* Turn on host coalescing state machine */
1625         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1626
1627         /* Turn on RX BD completion state machine and enable attentions */
1628         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1629             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1630
1631         /* Turn on RX list placement state machine */
1632         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1633
1634         /* Turn on RX list selector state machine. */
1635         if (!BGE_IS_5705_PLUS(sc))
1636                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1637
1638         /* Turn on DMA, clear stats */
1639         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1640             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1641             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1642             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1643             ((sc->bge_flags & BGE_FLAG_TBI) ?
1644              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1645
1646         /* Set misc. local control, enable interrupts on attentions */
1647         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1648
1649 #ifdef notdef
1650         /* Assert GPIO pins for PHY reset */
1651         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1652             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1653         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1654             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1655 #endif
1656
1657         /* Turn on DMA completion state machine */
1658         if (!BGE_IS_5705_PLUS(sc))
1659                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1660
1661         /* Turn on write DMA state machine */
1662         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1663         if (BGE_IS_5755_PLUS(sc)) {
1664                 /* Enable host coalescing bug fix. */
1665                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1666         }
1667         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1668         DELAY(40);
1669
1670         /* Turn on read DMA state machine */
1671         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1672         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1673             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1674             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1675                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1676                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1677                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1678         if (sc->bge_flags & BGE_FLAG_PCIE)
1679                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1680         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1681         DELAY(40);
1682
1683         /* Turn on RX data completion state machine */
1684         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1685
1686         /* Turn on RX BD initiator state machine */
1687         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1688
1689         /* Turn on RX data and RX BD initiator state machine */
1690         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1691
1692         /* Turn on Mbuf cluster free state machine */
1693         if (!BGE_IS_5705_PLUS(sc))
1694                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1695
1696         /* Turn on send BD completion state machine */
1697         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1698
1699         /* Turn on send data completion state machine */
1700         val = BGE_SDCMODE_ENABLE;
1701         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1702                 val |= BGE_SDCMODE_CDELAY;
1703         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1704
1705         /* Turn on send data initiator state machine */
1706         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1707
1708         /* Turn on send BD initiator state machine */
1709         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1710
1711         /* Turn on send BD selector state machine */
1712         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1713
1714         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1715         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1716             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1717
1718         /* ack/clear link change events */
1719         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1720             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1721             BGE_MACSTAT_LINK_CHANGED);
1722         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1723
1724         /* Enable PHY auto polling (for MII/GMII only) */
1725         if (sc->bge_flags & BGE_FLAG_TBI) {
1726                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1727         } else {
1728                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1729                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1730                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1731                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1732                             BGE_EVTENB_MI_INTERRUPT);
1733                 }
1734         }
1735
1736         /*
1737          * Clear any pending link state attention.
1738          * Otherwise some link state change events may be lost until attention
1739          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1740          * It's not necessary on newer BCM chips - perhaps enabling link
1741          * state change attentions implies clearing pending attention.
1742          */
1743         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1744             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1745             BGE_MACSTAT_LINK_CHANGED);
1746
1747         /* Enable link state change attentions. */
1748         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1749
1750         return(0);
1751 }
1752
1753 /*
1754  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1755  * against our list and return its name if we find a match. Note
1756  * that since the Broadcom controller contains VPD support, we
1757  * can get the device name string from the controller itself instead
1758  * of the compiled-in string. This is a little slow, but it guarantees
1759  * we'll always announce the right product name.
1760  */
1761 static int
1762 bge_probe(device_t dev)
1763 {
1764         const struct bge_type *t;
1765         uint16_t product, vendor;
1766
1767         product = pci_get_device(dev);
1768         vendor = pci_get_vendor(dev);
1769
1770         for (t = bge_devs; t->bge_name != NULL; t++) {
1771                 if (vendor == t->bge_vid && product == t->bge_did)
1772                         break;
1773         }
1774         if (t->bge_name == NULL)
1775                 return(ENXIO);
1776
1777         device_set_desc(dev, t->bge_name);
1778         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1779                 struct bge_softc *sc = device_get_softc(dev);
1780                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1781         }
1782         return(0);
1783 }
1784
1785 static int
1786 bge_attach(device_t dev)
1787 {
1788         struct ifnet *ifp;
1789         struct bge_softc *sc;
1790         uint32_t hwcfg = 0;
1791         int error = 0, rid;
1792         uint8_t ether_addr[ETHER_ADDR_LEN];
1793
1794         sc = device_get_softc(dev);
1795         sc->bge_dev = dev;
1796         callout_init(&sc->bge_stat_timer);
1797         lwkt_serialize_init(&sc->bge_jslot_serializer);
1798
1799 #ifndef BURN_BRIDGES
1800         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1801                 uint32_t irq, mem;
1802
1803                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1804                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1805
1806                 device_printf(dev, "chip is in D%d power mode "
1807                     "-- setting to D0\n", pci_get_powerstate(dev));
1808
1809                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1810
1811                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1812                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1813         }
1814 #endif  /* !BURN_BRIDGE */
1815
1816         /*
1817          * Map control/status registers.
1818          */
1819         pci_enable_busmaster(dev);
1820
1821         rid = BGE_PCI_BAR0;
1822         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1823             RF_ACTIVE);
1824
1825         if (sc->bge_res == NULL) {
1826                 device_printf(dev, "couldn't map memory\n");
1827                 return ENXIO;
1828         }
1829
1830         sc->bge_btag = rman_get_bustag(sc->bge_res);
1831         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1832
1833         /* Save various chip information */
1834         sc->bge_chipid =
1835             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1836             BGE_PCIMISCCTL_ASICREV_SHIFT;
1837         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1838                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1839         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1840         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1841
1842         /* Save chipset family. */
1843         switch (sc->bge_asicrev) {
1844         case BGE_ASICREV_BCM5755:
1845         case BGE_ASICREV_BCM5761:
1846         case BGE_ASICREV_BCM5784:
1847         case BGE_ASICREV_BCM5785:
1848         case BGE_ASICREV_BCM5787:
1849         case BGE_ASICREV_BCM57780:
1850             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1851                 BGE_FLAG_5705_PLUS;
1852             break;
1853
1854         case BGE_ASICREV_BCM5700:
1855         case BGE_ASICREV_BCM5701:
1856         case BGE_ASICREV_BCM5703:
1857         case BGE_ASICREV_BCM5704:
1858                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1859                 break;
1860
1861         case BGE_ASICREV_BCM5714_A0:
1862         case BGE_ASICREV_BCM5780:
1863         case BGE_ASICREV_BCM5714:
1864                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1865                 /* Fall through */
1866
1867         case BGE_ASICREV_BCM5750:
1868         case BGE_ASICREV_BCM5752:
1869         case BGE_ASICREV_BCM5906:
1870                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1871                 /* Fall through */
1872
1873         case BGE_ASICREV_BCM5705:
1874                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1875                 break;
1876         }
1877
1878         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1879                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1880
1881         /*
1882          * Set various quirk flags.
1883          */
1884
1885         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1886         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1887             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1888              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1889               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1890             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1891                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1892
1893         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1894             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1895                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1896
1897         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1898             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1899                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1900
1901         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1902                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1903
1904         if (BGE_IS_5705_PLUS(sc)) {
1905                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1906                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1907                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1908                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1909                         uint32_t product = pci_get_device(dev);
1910
1911                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1912                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1913                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1914                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1915                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1916                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1917                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1918                 }
1919         }
1920
1921         /* Allocate interrupt */
1922         rid = 0;
1923
1924         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1925             RF_SHAREABLE | RF_ACTIVE);
1926
1927         if (sc->bge_irq == NULL) {
1928                 device_printf(dev, "couldn't map interrupt\n");
1929                 error = ENXIO;
1930                 goto fail;
1931         }
1932
1933         /*
1934          * Check if this is a PCI-X or PCI Express device.
1935          */
1936         if (BGE_IS_5705_PLUS(sc)) {
1937                 if (pci_is_pcie(dev)) {
1938                         sc->bge_flags |= BGE_FLAG_PCIE;
1939                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1940                 }
1941         } else {
1942                 /*
1943                  * Check if the device is in PCI-X Mode.
1944                  * (This bit is not valid on PCI Express controllers.)
1945                  */
1946                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1947                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1948                         sc->bge_flags |= BGE_FLAG_PCIX;
1949         }
1950
1951         device_printf(dev, "CHIP ID 0x%08x; "
1952                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1953                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1954                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1955                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1956                         "PCI-E" : "PCI"));
1957
1958         /*
1959          * All controllers that are not 5755 or higher have 4GB
1960          * boundary DMA bug.
1961          * Whenever an address crosses a multiple of the 4GB boundary
1962          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
1963          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
1964          * state machine will lockup and cause the device to hang.
1965          */
1966         if (BGE_IS_5755_PLUS(sc) == 0)
1967                 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
1968
1969         /*
1970          * The 40bit DMA bug applies to the 5714/5715 controllers and is
1971          * not actually a MAC controller bug but an issue with the embedded
1972          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
1973          */
1974         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
1975                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
1976
1977         ifp = &sc->arpcom.ac_if;
1978         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1979
1980         /* Try to reset the chip. */
1981         bge_reset(sc);
1982
1983         if (bge_chipinit(sc)) {
1984                 device_printf(dev, "chip initialization failed\n");
1985                 error = ENXIO;
1986                 goto fail;
1987         }
1988
1989         /*
1990          * Get station address
1991          */
1992         error = bge_get_eaddr(sc, ether_addr);
1993         if (error) {
1994                 device_printf(dev, "failed to read station address\n");
1995                 goto fail;
1996         }
1997
1998         /* 5705/5750 limits RX return ring to 512 entries. */
1999         if (BGE_IS_5705_PLUS(sc))
2000                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2001         else
2002                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2003
2004         error = bge_dma_alloc(sc);
2005         if (error)
2006                 goto fail;
2007
2008         /* Set default tuneable values. */
2009         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2010         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2011         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2012         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2013         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2014
2015         /* Set up ifnet structure */
2016         ifp->if_softc = sc;
2017         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2018         ifp->if_ioctl = bge_ioctl;
2019         ifp->if_start = bge_start;
2020 #ifdef DEVICE_POLLING
2021         ifp->if_poll = bge_poll;
2022 #endif
2023         ifp->if_watchdog = bge_watchdog;
2024         ifp->if_init = bge_init;
2025         ifp->if_mtu = ETHERMTU;
2026         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2027         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2028         ifq_set_ready(&ifp->if_snd);
2029
2030         /*
2031          * 5700 B0 chips do not support checksumming correctly due
2032          * to hardware bugs.
2033          */
2034         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2035                 ifp->if_capabilities |= IFCAP_HWCSUM;
2036                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2037         }
2038         ifp->if_capenable = ifp->if_capabilities;
2039
2040         /*
2041          * Figure out what sort of media we have by checking the
2042          * hardware config word in the first 32k of NIC internal memory,
2043          * or fall back to examining the EEPROM if necessary.
2044          * Note: on some BCM5700 cards, this value appears to be unset.
2045          * If that's the case, we have to rely on identifying the NIC
2046          * by its PCI subsystem ID, as we do below for the SysKonnect
2047          * SK-9D41.
2048          */
2049         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2050                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2051         else {
2052                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2053                                     sizeof(hwcfg))) {
2054                         device_printf(dev, "failed to read EEPROM\n");
2055                         error = ENXIO;
2056                         goto fail;
2057                 }
2058                 hwcfg = ntohl(hwcfg);
2059         }
2060
2061         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2062                 sc->bge_flags |= BGE_FLAG_TBI;
2063
2064         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2065         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
2066                 sc->bge_flags |= BGE_FLAG_TBI;
2067
2068         if (sc->bge_flags & BGE_FLAG_TBI) {
2069                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2070                     bge_ifmedia_upd, bge_ifmedia_sts);
2071                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2072                 ifmedia_add(&sc->bge_ifmedia,
2073                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2074                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2075                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2076                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2077         } else {
2078                 /*
2079                  * Do transceiver setup.
2080                  */
2081                 if (mii_phy_probe(dev, &sc->bge_miibus,
2082                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2083                         device_printf(dev, "MII without any PHY!\n");
2084                         error = ENXIO;
2085                         goto fail;
2086                 }
2087         }
2088
2089         /*
2090          * When using the BCM5701 in PCI-X mode, data corruption has
2091          * been observed in the first few bytes of some received packets.
2092          * Aligning the packet buffer in memory eliminates the corruption.
2093          * Unfortunately, this misaligns the packet payloads.  On platforms
2094          * which do not support unaligned accesses, we will realign the
2095          * payloads by copying the received packets.
2096          */
2097         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2098             (sc->bge_flags & BGE_FLAG_PCIX))
2099                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2100
2101         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2102             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2103                 sc->bge_link_upd = bge_bcm5700_link_upd;
2104                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2105         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2106                 sc->bge_link_upd = bge_tbi_link_upd;
2107                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2108         } else {
2109                 sc->bge_link_upd = bge_copper_link_upd;
2110                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2111         }
2112
2113         /*
2114          * Create sysctl nodes.
2115          */
2116         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2117         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2118                                               SYSCTL_STATIC_CHILDREN(_hw),
2119                                               OID_AUTO,
2120                                               device_get_nameunit(dev),
2121                                               CTLFLAG_RD, 0, "");
2122         if (sc->bge_sysctl_tree == NULL) {
2123                 device_printf(dev, "can't add sysctl node\n");
2124                 error = ENXIO;
2125                 goto fail;
2126         }
2127
2128         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2129                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2130                         OID_AUTO, "rx_coal_ticks",
2131                         CTLTYPE_INT | CTLFLAG_RW,
2132                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2133                         "Receive coalescing ticks (usec).");
2134         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2135                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2136                         OID_AUTO, "tx_coal_ticks",
2137                         CTLTYPE_INT | CTLFLAG_RW,
2138                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2139                         "Transmit coalescing ticks (usec).");
2140         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2141                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2142                         OID_AUTO, "rx_max_coal_bds",
2143                         CTLTYPE_INT | CTLFLAG_RW,
2144                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2145                         "Receive max coalesced BD count.");
2146         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2147                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2148                         OID_AUTO, "tx_max_coal_bds",
2149                         CTLTYPE_INT | CTLFLAG_RW,
2150                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2151                         "Transmit max coalesced BD count.");
2152
2153         /*
2154          * Call MI attach routine.
2155          */
2156         ether_ifattach(ifp, ether_addr, NULL);
2157
2158         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2159                                bge_intr, sc, &sc->bge_intrhand,
2160                                ifp->if_serializer);
2161         if (error) {
2162                 ether_ifdetach(ifp);
2163                 device_printf(dev, "couldn't set up irq\n");
2164                 goto fail;
2165         }
2166
2167         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2168         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2169
2170         return(0);
2171 fail:
2172         bge_detach(dev);
2173         return(error);
2174 }
2175
2176 static int
2177 bge_detach(device_t dev)
2178 {
2179         struct bge_softc *sc = device_get_softc(dev);
2180
2181         if (device_is_attached(dev)) {
2182                 struct ifnet *ifp = &sc->arpcom.ac_if;
2183
2184                 lwkt_serialize_enter(ifp->if_serializer);
2185                 bge_stop(sc);
2186                 bge_reset(sc);
2187                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2188                 lwkt_serialize_exit(ifp->if_serializer);
2189
2190                 ether_ifdetach(ifp);
2191         }
2192
2193         if (sc->bge_flags & BGE_FLAG_TBI)
2194                 ifmedia_removeall(&sc->bge_ifmedia);
2195         if (sc->bge_miibus)
2196                 device_delete_child(dev, sc->bge_miibus);
2197         bus_generic_detach(dev);
2198
2199         if (sc->bge_irq != NULL)
2200                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2201
2202         if (sc->bge_res != NULL)
2203                 bus_release_resource(dev, SYS_RES_MEMORY,
2204                     BGE_PCI_BAR0, sc->bge_res);
2205
2206         if (sc->bge_sysctl_tree != NULL)
2207                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2208
2209         bge_dma_free(sc);
2210
2211         return 0;
2212 }
2213
2214 static void
2215 bge_reset(struct bge_softc *sc)
2216 {
2217         device_t dev;
2218         uint32_t cachesize, command, pcistate, reset;
2219         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2220         int i, val = 0;
2221
2222         dev = sc->bge_dev;
2223
2224         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2225             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2226                 if (sc->bge_flags & BGE_FLAG_PCIE)
2227                         write_op = bge_writemem_direct;
2228                 else
2229                         write_op = bge_writemem_ind;
2230         } else {
2231                 write_op = bge_writereg_ind;
2232         }
2233
2234         /* Save some important PCI state. */
2235         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2236         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2237         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2238
2239         pci_write_config(dev, BGE_PCI_MISC_CTL,
2240             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2241             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2242
2243         /* Disable fastboot on controllers that support it. */
2244         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2245             BGE_IS_5755_PLUS(sc)) {
2246                 if (bootverbose)
2247                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2248                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2249         }
2250
2251         /*
2252          * Write the magic number to SRAM at offset 0xB50.
2253          * When firmware finishes its initialization it will
2254          * write ~BGE_MAGIC_NUMBER to the same location.
2255          */
2256         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2257
2258         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2259
2260         /* XXX: Broadcom Linux driver. */
2261         if (sc->bge_flags & BGE_FLAG_PCIE) {
2262                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2263                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2264                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2265                         /* Prevent PCIE link training during global reset */
2266                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2267                         reset |= (1<<29);
2268                 }
2269         }
2270
2271         /*
2272          * Set GPHY Power Down Override to leave GPHY
2273          * powered up in D0 uninitialized.
2274          */
2275         if (BGE_IS_5705_PLUS(sc))
2276                 reset |= 0x04000000;
2277
2278         /* Issue global reset */
2279         write_op(sc, BGE_MISC_CFG, reset);
2280
2281         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2282                 uint32_t status, ctrl;
2283
2284                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2285                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2286                     status | BGE_VCPU_STATUS_DRV_RESET);
2287                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2288                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2289                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2290         }
2291
2292         DELAY(1000);
2293
2294         /* XXX: Broadcom Linux driver. */
2295         if (sc->bge_flags & BGE_FLAG_PCIE) {
2296                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2297                         uint32_t v;
2298
2299                         DELAY(500000); /* wait for link training to complete */
2300                         v = pci_read_config(dev, 0xc4, 4);
2301                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2302                 }
2303                 /*
2304                  * Set PCIE max payload size to 128 bytes and
2305                  * clear error status.
2306                  */
2307                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2308         }
2309
2310         /* Reset some of the PCI state that got zapped by reset */
2311         pci_write_config(dev, BGE_PCI_MISC_CTL,
2312             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2313             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2314         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2315         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2316         write_op(sc, BGE_MISC_CFG, (65 << 1));
2317
2318         /* Enable memory arbiter. */
2319         if (BGE_IS_5714_FAMILY(sc)) {
2320                 uint32_t val;
2321
2322                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2323                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2324         } else {
2325                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2326         }
2327
2328         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2329                 for (i = 0; i < BGE_TIMEOUT; i++) {
2330                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2331                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2332                                 break;
2333                         DELAY(100);
2334                 }
2335                 if (i == BGE_TIMEOUT) {
2336                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2337                         return;
2338                 }
2339         } else {
2340                 /*
2341                  * Poll until we see the 1's complement of the magic number.
2342                  * This indicates that the firmware initialization
2343                  * is complete.
2344                  */
2345                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2346                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2347                         if (val == ~BGE_MAGIC_NUMBER)
2348                                 break;
2349                         DELAY(10);
2350                 }
2351                 if (i == BGE_FIRMWARE_TIMEOUT) {
2352                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2353                                   "timed out, found 0x%08x\n", val);
2354                         return;
2355                 }
2356         }
2357
2358         /*
2359          * XXX Wait for the value of the PCISTATE register to
2360          * return to its original pre-reset state. This is a
2361          * fairly good indicator of reset completion. If we don't
2362          * wait for the reset to fully complete, trying to read
2363          * from the device's non-PCI registers may yield garbage
2364          * results.
2365          */
2366         for (i = 0; i < BGE_TIMEOUT; i++) {
2367                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2368                         break;
2369                 DELAY(10);
2370         }
2371
2372         if (sc->bge_flags & BGE_FLAG_PCIE) {
2373                 reset = bge_readmem_ind(sc, 0x7c00);
2374                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2375         }
2376
2377         /* Fix up byte swapping */
2378         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2379             BGE_MODECTL_BYTESWAP_DATA);
2380
2381         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2382
2383         /*
2384          * The 5704 in TBI mode apparently needs some special
2385          * adjustment to insure the SERDES drive level is set
2386          * to 1.2V.
2387          */
2388         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2389             (sc->bge_flags & BGE_FLAG_TBI)) {
2390                 uint32_t serdescfg;
2391
2392                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2393                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2394                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2395         }
2396
2397         /* XXX: Broadcom Linux driver. */
2398         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2399             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2400                 uint32_t v;
2401
2402                 v = CSR_READ_4(sc, 0x7c00);
2403                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2404         }
2405
2406         DELAY(10000);
2407 }
2408
2409 /*
2410  * Frame reception handling. This is called if there's a frame
2411  * on the receive return list.
2412  *
2413  * Note: we have to be able to handle two possibilities here:
2414  * 1) the frame is from the jumbo recieve ring
2415  * 2) the frame is from the standard receive ring
2416  */
2417
2418 static void
2419 bge_rxeof(struct bge_softc *sc)
2420 {
2421         struct ifnet *ifp;
2422         int stdcnt = 0, jumbocnt = 0;
2423
2424         if (sc->bge_rx_saved_considx ==
2425             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2426                 return;
2427
2428         ifp = &sc->arpcom.ac_if;
2429
2430         while (sc->bge_rx_saved_considx !=
2431                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2432                 struct bge_rx_bd        *cur_rx;
2433                 uint32_t                rxidx;
2434                 struct mbuf             *m = NULL;
2435                 uint16_t                vlan_tag = 0;
2436                 int                     have_tag = 0;
2437
2438                 cur_rx =
2439             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2440
2441                 rxidx = cur_rx->bge_idx;
2442                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2443                 logif(rx_pkt);
2444
2445                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2446                         have_tag = 1;
2447                         vlan_tag = cur_rx->bge_vlan_tag;
2448                 }
2449
2450                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2451                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2452                         jumbocnt++;
2453
2454                         if (rxidx != sc->bge_jumbo) {
2455                                 ifp->if_ierrors++;
2456                                 if_printf(ifp, "sw jumbo index(%d) "
2457                                     "and hw jumbo index(%d) mismatch, drop!\n",
2458                                     sc->bge_jumbo, rxidx);
2459                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2460                                 continue;
2461                         }
2462
2463                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2464                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2465                                 ifp->if_ierrors++;
2466                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2467                                 continue;
2468                         }
2469                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2470                                 ifp->if_ierrors++;
2471                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2472                                 continue;
2473                         }
2474                 } else {
2475                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2476                         stdcnt++;
2477
2478                         if (rxidx != sc->bge_std) {
2479                                 ifp->if_ierrors++;
2480                                 if_printf(ifp, "sw std index(%d) "
2481                                     "and hw std index(%d) mismatch, drop!\n",
2482                                     sc->bge_std, rxidx);
2483                                 bge_setup_rxdesc_std(sc, rxidx);
2484                                 continue;
2485                         }
2486
2487                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2488                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2489                                 ifp->if_ierrors++;
2490                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2491                                 continue;
2492                         }
2493                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2494                                 ifp->if_ierrors++;
2495                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2496                                 continue;
2497                         }
2498                 }
2499
2500                 ifp->if_ipackets++;
2501 #ifndef __i386__
2502                 /*
2503                  * The i386 allows unaligned accesses, but for other
2504                  * platforms we must make sure the payload is aligned.
2505                  */
2506                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2507                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2508                             cur_rx->bge_len);
2509                         m->m_data += ETHER_ALIGN;
2510                 }
2511 #endif
2512                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2513                 m->m_pkthdr.rcvif = ifp;
2514
2515                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2516                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2517                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2518                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2519                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2520                         }
2521                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2522                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2523                                 m->m_pkthdr.csum_data =
2524                                         cur_rx->bge_tcp_udp_csum;
2525                                 m->m_pkthdr.csum_flags |=
2526                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2527                         }
2528                 }
2529
2530                 /*
2531                  * If we received a packet with a vlan tag, pass it
2532                  * to vlan_input() instead of ether_input().
2533                  */
2534                 if (have_tag) {
2535                         m->m_flags |= M_VLANTAG;
2536                         m->m_pkthdr.ether_vlantag = vlan_tag;
2537                         have_tag = vlan_tag = 0;
2538                 }
2539                 ifp->if_input(ifp, m);
2540         }
2541
2542         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2543         if (stdcnt)
2544                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2545         if (jumbocnt)
2546                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2547 }
2548
2549 static void
2550 bge_txeof(struct bge_softc *sc)
2551 {
2552         struct bge_tx_bd *cur_tx = NULL;
2553         struct ifnet *ifp;
2554
2555         if (sc->bge_tx_saved_considx ==
2556             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2557                 return;
2558
2559         ifp = &sc->arpcom.ac_if;
2560
2561         /*
2562          * Go through our tx ring and free mbufs for those
2563          * frames that have been sent.
2564          */
2565         while (sc->bge_tx_saved_considx !=
2566                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2567                 uint32_t idx = 0;
2568
2569                 idx = sc->bge_tx_saved_considx;
2570                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2571                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2572                         ifp->if_opackets++;
2573                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2574                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2575                             sc->bge_cdata.bge_tx_dmamap[idx]);
2576                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2577                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2578                 }
2579                 sc->bge_txcnt--;
2580                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2581                 logif(tx_pkt);
2582         }
2583
2584         if (cur_tx != NULL &&
2585             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2586             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2587                 ifp->if_flags &= ~IFF_OACTIVE;
2588
2589         if (sc->bge_txcnt == 0)
2590                 ifp->if_timer = 0;
2591
2592         if (!ifq_is_empty(&ifp->if_snd))
2593                 if_devstart(ifp);
2594 }
2595
2596 #ifdef DEVICE_POLLING
2597
2598 static void
2599 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2600 {
2601         struct bge_softc *sc = ifp->if_softc;
2602         uint32_t status;
2603
2604         switch(cmd) {
2605         case POLL_REGISTER:
2606                 bge_disable_intr(sc);
2607                 break;
2608         case POLL_DEREGISTER:
2609                 bge_enable_intr(sc);
2610                 break;
2611         case POLL_AND_CHECK_STATUS:
2612                 /*
2613                  * Process link state changes.
2614                  */
2615                 status = CSR_READ_4(sc, BGE_MAC_STS);
2616                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2617                         sc->bge_link_evt = 0;
2618                         sc->bge_link_upd(sc, status);
2619                 }
2620                 /* fall through */
2621         case POLL_ONLY:
2622                 if (ifp->if_flags & IFF_RUNNING) {
2623                         bge_rxeof(sc);
2624                         bge_txeof(sc);
2625                 }
2626                 break;
2627         }
2628 }
2629
2630 #endif
2631
2632 static void
2633 bge_intr(void *xsc)
2634 {
2635         struct bge_softc *sc = xsc;
2636         struct ifnet *ifp = &sc->arpcom.ac_if;
2637         uint32_t status;
2638
2639         logif(intr);
2640
2641         /*
2642          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2643          * disable interrupts by writing nonzero like we used to, since with
2644          * our current organization this just gives complications and
2645          * pessimizations for re-enabling interrupts.  We used to have races
2646          * instead of the necessary complications.  Disabling interrupts
2647          * would just reduce the chance of a status update while we are
2648          * running (by switching to the interrupt-mode coalescence
2649          * parameters), but this chance is already very low so it is more
2650          * efficient to get another interrupt than prevent it.
2651          *
2652          * We do the ack first to ensure another interrupt if there is a
2653          * status update after the ack.  We don't check for the status
2654          * changing later because it is more efficient to get another
2655          * interrupt than prevent it, not quite as above (not checking is
2656          * a smaller optimization than not toggling the interrupt enable,
2657          * since checking doesn't involve PCI accesses and toggling require
2658          * the status check).  So toggling would probably be a pessimization
2659          * even with MSI.  It would only be needed for using a task queue.
2660          */
2661         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2662
2663         /*
2664          * Process link state changes.
2665          */
2666         status = CSR_READ_4(sc, BGE_MAC_STS);
2667         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2668                 sc->bge_link_evt = 0;
2669                 sc->bge_link_upd(sc, status);
2670         }
2671
2672         if (ifp->if_flags & IFF_RUNNING) {
2673                 /* Check RX return ring producer/consumer */
2674                 bge_rxeof(sc);
2675
2676                 /* Check TX ring producer/consumer */
2677                 bge_txeof(sc);
2678         }
2679
2680         if (sc->bge_coal_chg)
2681                 bge_coal_change(sc);
2682 }
2683
2684 static void
2685 bge_tick(void *xsc)
2686 {
2687         struct bge_softc *sc = xsc;
2688         struct ifnet *ifp = &sc->arpcom.ac_if;
2689
2690         lwkt_serialize_enter(ifp->if_serializer);
2691
2692         if (BGE_IS_5705_PLUS(sc))
2693                 bge_stats_update_regs(sc);
2694         else
2695                 bge_stats_update(sc);
2696
2697         if (sc->bge_flags & BGE_FLAG_TBI) {
2698                 /*
2699                  * Since in TBI mode auto-polling can't be used we should poll
2700                  * link status manually. Here we register pending link event
2701                  * and trigger interrupt.
2702                  */
2703                 sc->bge_link_evt++;
2704                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2705         } else if (!sc->bge_link) {
2706                 mii_tick(device_get_softc(sc->bge_miibus));
2707         }
2708
2709         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2710
2711         lwkt_serialize_exit(ifp->if_serializer);
2712 }
2713
2714 static void
2715 bge_stats_update_regs(struct bge_softc *sc)
2716 {
2717         struct ifnet *ifp = &sc->arpcom.ac_if;
2718         struct bge_mac_stats_regs stats;
2719         uint32_t *s;
2720         int i;
2721
2722         s = (uint32_t *)&stats;
2723         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2724                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2725                 s++;
2726         }
2727
2728         ifp->if_collisions +=
2729            (stats.dot3StatsSingleCollisionFrames +
2730            stats.dot3StatsMultipleCollisionFrames +
2731            stats.dot3StatsExcessiveCollisions +
2732            stats.dot3StatsLateCollisions) -
2733            ifp->if_collisions;
2734 }
2735
2736 static void
2737 bge_stats_update(struct bge_softc *sc)
2738 {
2739         struct ifnet *ifp = &sc->arpcom.ac_if;
2740         bus_size_t stats;
2741
2742         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2743
2744 #define READ_STAT(sc, stats, stat)      \
2745         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2746
2747         ifp->if_collisions +=
2748            (READ_STAT(sc, stats,
2749                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2750             READ_STAT(sc, stats,
2751                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2752             READ_STAT(sc, stats,
2753                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2754             READ_STAT(sc, stats,
2755                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2756            ifp->if_collisions;
2757
2758 #undef READ_STAT
2759
2760 #ifdef notdef
2761         ifp->if_collisions +=
2762            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2763            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2764            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2765            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2766            ifp->if_collisions;
2767 #endif
2768 }
2769
2770 /*
2771  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2772  * pointers to descriptors.
2773  */
2774 static int
2775 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2776 {
2777         struct bge_tx_bd *d = NULL;
2778         uint16_t csum_flags = 0;
2779         bus_dma_segment_t segs[BGE_NSEG_NEW];
2780         bus_dmamap_t map;
2781         int error, maxsegs, nsegs, idx, i;
2782         struct mbuf *m_head = *m_head0;
2783
2784         if (m_head->m_pkthdr.csum_flags) {
2785                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2786                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2787                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2788                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2789                 if (m_head->m_flags & M_LASTFRAG)
2790                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2791                 else if (m_head->m_flags & M_FRAG)
2792                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2793         }
2794
2795         idx = *txidx;
2796         map = sc->bge_cdata.bge_tx_dmamap[idx];
2797
2798         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2799         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2800                 ("not enough segments %d", maxsegs));
2801
2802         if (maxsegs > BGE_NSEG_NEW)
2803                 maxsegs = BGE_NSEG_NEW;
2804
2805         /*
2806          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2807          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2808          * but when such padded frames employ the bge IP/TCP checksum
2809          * offload, the hardware checksum assist gives incorrect results
2810          * (possibly from incorporating its own padding into the UDP/TCP
2811          * checksum; who knows).  If we pad such runts with zeros, the
2812          * onboard checksum comes out correct.
2813          */
2814         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2815             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2816                 error = m_devpad(m_head, BGE_MIN_FRAME);
2817                 if (error)
2818                         goto back;
2819         }
2820
2821         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2822                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2823         if (error)
2824                 goto back;
2825
2826         m_head = *m_head0;
2827         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2828
2829         for (i = 0; ; i++) {
2830                 d = &sc->bge_ldata.bge_tx_ring[idx];
2831
2832                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2833                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2834                 d->bge_len = segs[i].ds_len;
2835                 d->bge_flags = csum_flags;
2836
2837                 if (i == nsegs - 1)
2838                         break;
2839                 BGE_INC(idx, BGE_TX_RING_CNT);
2840         }
2841         /* Mark the last segment as end of packet... */
2842         d->bge_flags |= BGE_TXBDFLAG_END;
2843
2844         /* Set vlan tag to the first segment of the packet. */
2845         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2846         if (m_head->m_flags & M_VLANTAG) {
2847                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2848                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2849         } else {
2850                 d->bge_vlan_tag = 0;
2851         }
2852
2853         /*
2854          * Insure that the map for this transmission is placed at
2855          * the array index of the last descriptor in this chain.
2856          */
2857         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2858         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2859         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2860         sc->bge_txcnt += nsegs;
2861
2862         BGE_INC(idx, BGE_TX_RING_CNT);
2863         *txidx = idx;
2864 back:
2865         if (error) {
2866                 m_freem(*m_head0);
2867                 *m_head0 = NULL;
2868         }
2869         return error;
2870 }
2871
2872 /*
2873  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2874  * to the mbuf data regions directly in the transmit descriptors.
2875  */
2876 static void
2877 bge_start(struct ifnet *ifp)
2878 {
2879         struct bge_softc *sc = ifp->if_softc;
2880         struct mbuf *m_head = NULL;
2881         uint32_t prodidx;
2882         int need_trans;
2883
2884         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2885                 return;
2886
2887         prodidx = sc->bge_tx_prodidx;
2888
2889         need_trans = 0;
2890         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2891                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2892                 if (m_head == NULL)
2893                         break;
2894
2895                 /*
2896                  * XXX
2897                  * The code inside the if() block is never reached since we
2898                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2899                  * requests to checksum TCP/UDP in a fragmented packet.
2900                  *
2901                  * XXX
2902                  * safety overkill.  If this is a fragmented packet chain
2903                  * with delayed TCP/UDP checksums, then only encapsulate
2904                  * it if we have enough descriptors to handle the entire
2905                  * chain at once.
2906                  * (paranoia -- may not actually be needed)
2907                  */
2908                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2909                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2910                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2911                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2912                                 ifp->if_flags |= IFF_OACTIVE;
2913                                 ifq_prepend(&ifp->if_snd, m_head);
2914                                 break;
2915                         }
2916                 }
2917
2918                 /*
2919                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2920                  * descriptors of the end of the ring.  Also make
2921                  * sure there are BGE_NSEG_SPARE descriptors for
2922                  * jumbo buffers' defragmentation.
2923                  */
2924                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2925                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2926                         ifp->if_flags |= IFF_OACTIVE;
2927                         ifq_prepend(&ifp->if_snd, m_head);
2928                         break;
2929                 }
2930
2931                 /*
2932                  * Pack the data into the transmit ring. If we
2933                  * don't have room, set the OACTIVE flag and wait
2934                  * for the NIC to drain the ring.
2935                  */
2936                 if (bge_encap(sc, &m_head, &prodidx)) {
2937                         ifp->if_flags |= IFF_OACTIVE;
2938                         ifp->if_oerrors++;
2939                         break;
2940                 }
2941                 need_trans = 1;
2942
2943                 ETHER_BPF_MTAP(ifp, m_head);
2944         }
2945
2946         if (!need_trans)
2947                 return;
2948
2949         /* Transmit */
2950         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2951         /* 5700 b2 errata */
2952         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2953                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2954
2955         sc->bge_tx_prodidx = prodidx;
2956
2957         /*
2958          * Set a timeout in case the chip goes out to lunch.
2959          */
2960         ifp->if_timer = 5;
2961 }
2962
2963 static void
2964 bge_init(void *xsc)
2965 {
2966         struct bge_softc *sc = xsc;
2967         struct ifnet *ifp = &sc->arpcom.ac_if;
2968         uint16_t *m;
2969
2970         ASSERT_SERIALIZED(ifp->if_serializer);
2971
2972         if (ifp->if_flags & IFF_RUNNING)
2973                 return;
2974
2975         /* Cancel pending I/O and flush buffers. */
2976         bge_stop(sc);
2977         bge_reset(sc);
2978         bge_chipinit(sc);
2979
2980         /*
2981          * Init the various state machines, ring
2982          * control blocks and firmware.
2983          */
2984         if (bge_blockinit(sc)) {
2985                 if_printf(ifp, "initialization failure\n");
2986                 bge_stop(sc);
2987                 return;
2988         }
2989
2990         /* Specify MTU. */
2991         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2992             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2993
2994         /* Load our MAC address. */
2995         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2996         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2997         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2998
2999         /* Enable or disable promiscuous mode as needed. */
3000         bge_setpromisc(sc);
3001
3002         /* Program multicast filter. */
3003         bge_setmulti(sc);
3004
3005         /* Init RX ring. */
3006         if (bge_init_rx_ring_std(sc)) {
3007                 if_printf(ifp, "RX ring initialization failed\n");
3008                 bge_stop(sc);
3009                 return;
3010         }
3011
3012         /*
3013          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3014          * memory to insure that the chip has in fact read the first
3015          * entry of the ring.
3016          */
3017         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3018                 uint32_t                v, i;
3019                 for (i = 0; i < 10; i++) {
3020                         DELAY(20);
3021                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3022                         if (v == (MCLBYTES - ETHER_ALIGN))
3023                                 break;
3024                 }
3025                 if (i == 10)
3026                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3027         }
3028
3029         /* Init jumbo RX ring. */
3030         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3031                 if (bge_init_rx_ring_jumbo(sc)) {
3032                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3033                         bge_stop(sc);
3034                         return;
3035                 }
3036         }
3037
3038         /* Init our RX return ring index */
3039         sc->bge_rx_saved_considx = 0;
3040
3041         /* Init TX ring. */
3042         bge_init_tx_ring(sc);
3043
3044         /* Turn on transmitter */
3045         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3046
3047         /* Turn on receiver */
3048         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3049
3050         /* Tell firmware we're alive. */
3051         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3052
3053         /* Enable host interrupts if polling(4) is not enabled. */
3054         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3055 #ifdef DEVICE_POLLING
3056         if (ifp->if_flags & IFF_POLLING)
3057                 bge_disable_intr(sc);
3058         else
3059 #endif
3060         bge_enable_intr(sc);
3061
3062         bge_ifmedia_upd(ifp);
3063
3064         ifp->if_flags |= IFF_RUNNING;
3065         ifp->if_flags &= ~IFF_OACTIVE;
3066
3067         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3068 }
3069
3070 /*
3071  * Set media options.
3072  */
3073 static int
3074 bge_ifmedia_upd(struct ifnet *ifp)
3075 {
3076         struct bge_softc *sc = ifp->if_softc;
3077
3078         /* If this is a 1000baseX NIC, enable the TBI port. */
3079         if (sc->bge_flags & BGE_FLAG_TBI) {
3080                 struct ifmedia *ifm = &sc->bge_ifmedia;
3081
3082                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3083                         return(EINVAL);
3084
3085                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3086                 case IFM_AUTO:
3087                         /*
3088                          * The BCM5704 ASIC appears to have a special
3089                          * mechanism for programming the autoneg
3090                          * advertisement registers in TBI mode.
3091                          */
3092                         if (!bge_fake_autoneg &&
3093                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3094                                 uint32_t sgdig;
3095
3096                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3097                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3098                                 sgdig |= BGE_SGDIGCFG_AUTO |
3099                                          BGE_SGDIGCFG_PAUSE_CAP |
3100                                          BGE_SGDIGCFG_ASYM_PAUSE;
3101                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3102                                             sgdig | BGE_SGDIGCFG_SEND);
3103                                 DELAY(5);
3104                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3105                         }
3106                         break;
3107                 case IFM_1000_SX:
3108                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3109                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3110                                     BGE_MACMODE_HALF_DUPLEX);
3111                         } else {
3112                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3113                                     BGE_MACMODE_HALF_DUPLEX);
3114                         }
3115                         break;
3116                 default:
3117                         return(EINVAL);
3118                 }
3119         } else {
3120                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3121
3122                 sc->bge_link_evt++;
3123                 sc->bge_link = 0;
3124                 if (mii->mii_instance) {
3125                         struct mii_softc *miisc;
3126
3127                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3128                                 mii_phy_reset(miisc);
3129                 }
3130                 mii_mediachg(mii);
3131         }
3132         return(0);
3133 }
3134
3135 /*
3136  * Report current media status.
3137  */
3138 static void
3139 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3140 {
3141         struct bge_softc *sc = ifp->if_softc;
3142
3143         if (sc->bge_flags & BGE_FLAG_TBI) {
3144                 ifmr->ifm_status = IFM_AVALID;
3145                 ifmr->ifm_active = IFM_ETHER;
3146                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3147                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3148                         ifmr->ifm_status |= IFM_ACTIVE;
3149                 } else {
3150                         ifmr->ifm_active |= IFM_NONE;
3151                         return;
3152                 }
3153
3154                 ifmr->ifm_active |= IFM_1000_SX;
3155                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3156                         ifmr->ifm_active |= IFM_HDX;
3157                 else
3158                         ifmr->ifm_active |= IFM_FDX;
3159         } else {
3160                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3161
3162                 mii_pollstat(mii);
3163                 ifmr->ifm_active = mii->mii_media_active;
3164                 ifmr->ifm_status = mii->mii_media_status;
3165         }
3166 }
3167
3168 static int
3169 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3170 {
3171         struct bge_softc *sc = ifp->if_softc;
3172         struct ifreq *ifr = (struct ifreq *)data;
3173         int mask, error = 0;
3174
3175         ASSERT_SERIALIZED(ifp->if_serializer);
3176
3177         switch (command) {
3178         case SIOCSIFMTU:
3179                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3180                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3181                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3182                         error = EINVAL;
3183                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3184                         ifp->if_mtu = ifr->ifr_mtu;
3185                         ifp->if_flags &= ~IFF_RUNNING;
3186                         bge_init(sc);
3187                 }
3188                 break;
3189         case SIOCSIFFLAGS:
3190                 if (ifp->if_flags & IFF_UP) {
3191                         if (ifp->if_flags & IFF_RUNNING) {
3192                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3193
3194                                 /*
3195                                  * If only the state of the PROMISC flag
3196                                  * changed, then just use the 'set promisc
3197                                  * mode' command instead of reinitializing
3198                                  * the entire NIC. Doing a full re-init
3199                                  * means reloading the firmware and waiting
3200                                  * for it to start up, which may take a
3201                                  * second or two.  Similarly for ALLMULTI.
3202                                  */
3203                                 if (mask & IFF_PROMISC)
3204                                         bge_setpromisc(sc);
3205                                 if (mask & IFF_ALLMULTI)
3206                                         bge_setmulti(sc);
3207                         } else {
3208                                 bge_init(sc);
3209                         }
3210                 } else {
3211                         if (ifp->if_flags & IFF_RUNNING)
3212                                 bge_stop(sc);
3213                 }
3214                 sc->bge_if_flags = ifp->if_flags;
3215                 break;
3216         case SIOCADDMULTI:
3217         case SIOCDELMULTI:
3218                 if (ifp->if_flags & IFF_RUNNING)
3219                         bge_setmulti(sc);
3220                 break;
3221         case SIOCSIFMEDIA:
3222         case SIOCGIFMEDIA:
3223                 if (sc->bge_flags & BGE_FLAG_TBI) {
3224                         error = ifmedia_ioctl(ifp, ifr,
3225                             &sc->bge_ifmedia, command);
3226                 } else {
3227                         struct mii_data *mii;
3228
3229                         mii = device_get_softc(sc->bge_miibus);
3230                         error = ifmedia_ioctl(ifp, ifr,
3231                                               &mii->mii_media, command);
3232                 }
3233                 break;
3234         case SIOCSIFCAP:
3235                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3236                 if (mask & IFCAP_HWCSUM) {
3237                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3238                         if (IFCAP_HWCSUM & ifp->if_capenable)
3239                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3240                         else
3241                                 ifp->if_hwassist = 0;
3242                 }
3243                 break;
3244         default:
3245                 error = ether_ioctl(ifp, command, data);
3246                 break;
3247         }
3248         return error;
3249 }
3250
3251 static void
3252 bge_watchdog(struct ifnet *ifp)
3253 {
3254         struct bge_softc *sc = ifp->if_softc;
3255
3256         if_printf(ifp, "watchdog timeout -- resetting\n");
3257
3258         ifp->if_flags &= ~IFF_RUNNING;
3259         bge_init(sc);
3260
3261         ifp->if_oerrors++;
3262
3263         if (!ifq_is_empty(&ifp->if_snd))
3264                 if_devstart(ifp);
3265 }
3266
3267 /*
3268  * Stop the adapter and free any mbufs allocated to the
3269  * RX and TX lists.
3270  */
3271 static void
3272 bge_stop(struct bge_softc *sc)
3273 {
3274         struct ifnet *ifp = &sc->arpcom.ac_if;
3275
3276         ASSERT_SERIALIZED(ifp->if_serializer);
3277
3278         callout_stop(&sc->bge_stat_timer);
3279
3280         /*
3281          * Disable all of the receiver blocks
3282          */
3283         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3284         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3285         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3286         if (!BGE_IS_5705_PLUS(sc))
3287                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3288         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3289         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3290         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3291
3292         /*
3293          * Disable all of the transmit blocks
3294          */
3295         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3296         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3297         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3298         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3299         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3300         if (!BGE_IS_5705_PLUS(sc))
3301                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3302         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3303
3304         /*
3305          * Shut down all of the memory managers and related
3306          * state machines.
3307          */
3308         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3309         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3310         if (!BGE_IS_5705_PLUS(sc))
3311                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3312         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3313         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3314         if (!BGE_IS_5705_PLUS(sc)) {
3315                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3316                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3317         }
3318
3319         /* Disable host interrupts. */
3320         bge_disable_intr(sc);
3321
3322         /*
3323          * Tell firmware we're shutting down.
3324          */
3325         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3326
3327         /* Free the RX lists. */
3328         bge_free_rx_ring_std(sc);
3329
3330         /* Free jumbo RX list. */
3331         if (BGE_IS_JUMBO_CAPABLE(sc))
3332                 bge_free_rx_ring_jumbo(sc);
3333
3334         /* Free TX buffers. */
3335         bge_free_tx_ring(sc);
3336
3337         sc->bge_link = 0;
3338         sc->bge_coal_chg = 0;
3339
3340         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3341
3342         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3343         ifp->if_timer = 0;
3344 }
3345
3346 /*
3347  * Stop all chip I/O so that the kernel's probe routines don't
3348  * get confused by errant DMAs when rebooting.
3349  */
3350 static void
3351 bge_shutdown(device_t dev)
3352 {
3353         struct bge_softc *sc = device_get_softc(dev);
3354         struct ifnet *ifp = &sc->arpcom.ac_if;
3355
3356         lwkt_serialize_enter(ifp->if_serializer);
3357         bge_stop(sc);
3358         bge_reset(sc);
3359         lwkt_serialize_exit(ifp->if_serializer);
3360 }
3361
3362 static int
3363 bge_suspend(device_t dev)
3364 {
3365         struct bge_softc *sc = device_get_softc(dev);
3366         struct ifnet *ifp = &sc->arpcom.ac_if;
3367
3368         lwkt_serialize_enter(ifp->if_serializer);
3369         bge_stop(sc);
3370         lwkt_serialize_exit(ifp->if_serializer);
3371
3372         return 0;
3373 }
3374
3375 static int
3376 bge_resume(device_t dev)
3377 {
3378         struct bge_softc *sc = device_get_softc(dev);
3379         struct ifnet *ifp = &sc->arpcom.ac_if;
3380
3381         lwkt_serialize_enter(ifp->if_serializer);
3382
3383         if (ifp->if_flags & IFF_UP) {
3384                 bge_init(sc);
3385
3386                 if (!ifq_is_empty(&ifp->if_snd))
3387                         if_devstart(ifp);
3388         }
3389
3390         lwkt_serialize_exit(ifp->if_serializer);
3391
3392         return 0;
3393 }
3394
3395 static void
3396 bge_setpromisc(struct bge_softc *sc)
3397 {
3398         struct ifnet *ifp = &sc->arpcom.ac_if;
3399
3400         if (ifp->if_flags & IFF_PROMISC)
3401                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3402         else
3403                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3404 }
3405
3406 static void
3407 bge_dma_free(struct bge_softc *sc)
3408 {
3409         int i;
3410
3411         /* Destroy RX mbuf DMA stuffs. */
3412         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3413                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3414                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3415                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3416                 }
3417                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3418                                    sc->bge_cdata.bge_rx_tmpmap);
3419                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3420         }
3421
3422         /* Destroy TX mbuf DMA stuffs. */
3423         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3424                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3425                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3426                             sc->bge_cdata.bge_tx_dmamap[i]);
3427                 }
3428                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3429         }
3430
3431         /* Destroy standard RX ring */
3432         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3433                            sc->bge_cdata.bge_rx_std_ring_map,
3434                            sc->bge_ldata.bge_rx_std_ring);
3435
3436         if (BGE_IS_JUMBO_CAPABLE(sc))
3437                 bge_free_jumbo_mem(sc);
3438
3439         /* Destroy RX return ring */
3440         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3441                            sc->bge_cdata.bge_rx_return_ring_map,
3442                            sc->bge_ldata.bge_rx_return_ring);
3443
3444         /* Destroy TX ring */
3445         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3446                            sc->bge_cdata.bge_tx_ring_map,
3447                            sc->bge_ldata.bge_tx_ring);
3448
3449         /* Destroy status block */
3450         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3451                            sc->bge_cdata.bge_status_map,
3452                            sc->bge_ldata.bge_status_block);
3453
3454         /* Destroy statistics block */
3455         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3456                            sc->bge_cdata.bge_stats_map,
3457                            sc->bge_ldata.bge_stats);
3458
3459         /* Destroy the parent tag */
3460         if (sc->bge_cdata.bge_parent_tag != NULL)
3461                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3462 }
3463
3464 static int
3465 bge_dma_alloc(struct bge_softc *sc)
3466 {
3467         struct ifnet *ifp = &sc->arpcom.ac_if;
3468         int i, error;
3469         bus_addr_t lowaddr;
3470         bus_size_t boundary;
3471
3472         boundary = 0;
3473         if (sc->bge_flags & BGE_FLAG_BOUNDARY_4G)
3474                 boundary = BGE_DMA_BOUNDARY_4G;
3475
3476         lowaddr = BUS_SPACE_MAXADDR;
3477         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3478                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3479
3480         /*
3481          * Allocate the parent bus DMA tag appropriate for PCI.
3482          */
3483         error = bus_dma_tag_create(NULL, 1, boundary,
3484                                    lowaddr, BUS_SPACE_MAXADDR,
3485                                    NULL, NULL,
3486                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3487                                    BUS_SPACE_MAXSIZE_32BIT,
3488                                    0, &sc->bge_cdata.bge_parent_tag);
3489         if (error) {
3490                 if_printf(ifp, "could not allocate parent dma tag\n");
3491                 return error;
3492         }
3493
3494         /*
3495          * Create DMA tag and maps for RX mbufs.
3496          */
3497         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3498                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3499                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3500                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3501                                    &sc->bge_cdata.bge_rx_mtag);
3502         if (error) {
3503                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3504                 return error;
3505         }
3506
3507         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3508                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3509         if (error) {
3510                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3511                 sc->bge_cdata.bge_rx_mtag = NULL;
3512                 return error;
3513         }
3514
3515         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3516                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3517                                           BUS_DMA_WAITOK,
3518                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3519                 if (error) {
3520                         int j;
3521
3522                         for (j = 0; j < i; ++j) {
3523                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3524                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3525                         }
3526                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3527                         sc->bge_cdata.bge_rx_mtag = NULL;
3528
3529                         if_printf(ifp, "could not create DMA map for RX\n");
3530                         return error;
3531                 }
3532         }
3533
3534         /*
3535          * Create DMA tag and maps for TX mbufs.
3536          */
3537         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3538                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3539                                    NULL, NULL,
3540                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3541                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3542                                    BUS_DMA_ONEBPAGE,
3543                                    &sc->bge_cdata.bge_tx_mtag);
3544         if (error) {
3545                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3546                 return error;
3547         }
3548
3549         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3550                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3551                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3552                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3553                 if (error) {
3554                         int j;
3555
3556                         for (j = 0; j < i; ++j) {
3557                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3558                                         sc->bge_cdata.bge_tx_dmamap[j]);
3559                         }
3560                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3561                         sc->bge_cdata.bge_tx_mtag = NULL;
3562
3563                         if_printf(ifp, "could not create DMA map for TX\n");
3564                         return error;
3565                 }
3566         }
3567
3568         /*
3569          * Create DMA stuffs for standard RX ring.
3570          */
3571         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3572                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3573                                     &sc->bge_cdata.bge_rx_std_ring_map,
3574                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3575                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3576         if (error) {
3577                 if_printf(ifp, "could not create std RX ring\n");
3578                 return error;
3579         }
3580
3581         /*
3582          * Create jumbo buffer pool.
3583          */
3584         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3585                 error = bge_alloc_jumbo_mem(sc);
3586                 if (error) {
3587                         if_printf(ifp, "could not create jumbo buffer pool\n");
3588                         return error;
3589                 }
3590         }
3591
3592         /*
3593          * Create DMA stuffs for RX return ring.
3594          */
3595         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3596                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3597                                     &sc->bge_cdata.bge_rx_return_ring_map,
3598                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3599                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3600         if (error) {
3601                 if_printf(ifp, "could not create RX ret ring\n");
3602                 return error;
3603         }
3604
3605         /*
3606          * Create DMA stuffs for TX ring.
3607          */
3608         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3609                                     &sc->bge_cdata.bge_tx_ring_tag,
3610                                     &sc->bge_cdata.bge_tx_ring_map,
3611                                     (void *)&sc->bge_ldata.bge_tx_ring,
3612                                     &sc->bge_ldata.bge_tx_ring_paddr);
3613         if (error) {
3614                 if_printf(ifp, "could not create TX ring\n");
3615                 return error;
3616         }
3617
3618         /*
3619          * Create DMA stuffs for status block.
3620          */
3621         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3622                                     &sc->bge_cdata.bge_status_tag,
3623                                     &sc->bge_cdata.bge_status_map,
3624                                     (void *)&sc->bge_ldata.bge_status_block,
3625                                     &sc->bge_ldata.bge_status_block_paddr);
3626         if (error) {
3627                 if_printf(ifp, "could not create status block\n");
3628                 return error;
3629         }
3630
3631         /*
3632          * Create DMA stuffs for statistics block.
3633          */
3634         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3635                                     &sc->bge_cdata.bge_stats_tag,
3636                                     &sc->bge_cdata.bge_stats_map,
3637                                     (void *)&sc->bge_ldata.bge_stats,
3638                                     &sc->bge_ldata.bge_stats_paddr);
3639         if (error) {
3640                 if_printf(ifp, "could not create stats block\n");
3641                 return error;
3642         }
3643         return 0;
3644 }
3645
3646 static int
3647 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3648                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3649 {
3650         bus_dmamem_t dmem;
3651         int error;
3652
3653         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3654                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3655                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3656         if (error)
3657                 return error;
3658
3659         *tag = dmem.dmem_tag;
3660         *map = dmem.dmem_map;
3661         *addr = dmem.dmem_addr;
3662         *paddr = dmem.dmem_busaddr;
3663
3664         return 0;
3665 }
3666
3667 static void
3668 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3669 {
3670         if (tag != NULL) {
3671                 bus_dmamap_unload(tag, map);
3672                 bus_dmamem_free(tag, addr, map);
3673                 bus_dma_tag_destroy(tag);
3674         }
3675 }
3676
3677 /*
3678  * Grrr. The link status word in the status block does
3679  * not work correctly on the BCM5700 rev AX and BX chips,
3680  * according to all available information. Hence, we have
3681  * to enable MII interrupts in order to properly obtain
3682  * async link changes. Unfortunately, this also means that
3683  * we have to read the MAC status register to detect link
3684  * changes, thereby adding an additional register access to
3685  * the interrupt handler.
3686  *
3687  * XXX: perhaps link state detection procedure used for
3688  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3689  */
3690 static void
3691 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3692 {
3693         struct ifnet *ifp = &sc->arpcom.ac_if;
3694         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3695
3696         mii_pollstat(mii);
3697
3698         if (!sc->bge_link &&
3699             (mii->mii_media_status & IFM_ACTIVE) &&
3700             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3701                 sc->bge_link++;
3702                 if (bootverbose)
3703                         if_printf(ifp, "link UP\n");
3704         } else if (sc->bge_link &&
3705             (!(mii->mii_media_status & IFM_ACTIVE) ||
3706             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3707                 sc->bge_link = 0;
3708                 if (bootverbose)
3709                         if_printf(ifp, "link DOWN\n");
3710         }
3711
3712         /* Clear the interrupt. */
3713         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3714         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3715         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3716 }
3717
3718 static void
3719 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3720 {
3721         struct ifnet *ifp = &sc->arpcom.ac_if;
3722
3723 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3724
3725         /*
3726          * Sometimes PCS encoding errors are detected in
3727          * TBI mode (on fiber NICs), and for some reason
3728          * the chip will signal them as link changes.
3729          * If we get a link change event, but the 'PCS
3730          * encoding error' bit in the MAC status register
3731          * is set, don't bother doing a link check.
3732          * This avoids spurious "gigabit link up" messages
3733          * that sometimes appear on fiber NICs during
3734          * periods of heavy traffic.
3735          */
3736         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3737                 if (!sc->bge_link) {
3738                         sc->bge_link++;
3739                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3740                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3741                                     BGE_MACMODE_TBI_SEND_CFGS);
3742                         }
3743                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3744
3745                         if (bootverbose)
3746                                 if_printf(ifp, "link UP\n");
3747
3748                         ifp->if_link_state = LINK_STATE_UP;
3749                         if_link_state_change(ifp);
3750                 }
3751         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3752                 if (sc->bge_link) {
3753                         sc->bge_link = 0;
3754
3755                         if (bootverbose)
3756                                 if_printf(ifp, "link DOWN\n");
3757
3758                         ifp->if_link_state = LINK_STATE_DOWN;
3759                         if_link_state_change(ifp);
3760                 }
3761         }
3762
3763 #undef PCS_ENCODE_ERR
3764
3765         /* Clear the attention. */
3766         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3767             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3768             BGE_MACSTAT_LINK_CHANGED);
3769 }
3770
3771 static void
3772 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3773 {
3774         /*
3775          * Check that the AUTOPOLL bit is set before
3776          * processing the event as a real link change.
3777          * Turning AUTOPOLL on and off in the MII read/write
3778          * functions will often trigger a link status
3779          * interrupt for no reason.
3780          */
3781         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3782                 struct ifnet *ifp = &sc->arpcom.ac_if;
3783                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3784
3785                 mii_pollstat(mii);
3786
3787                 if (!sc->bge_link &&
3788                     (mii->mii_media_status & IFM_ACTIVE) &&
3789                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3790                         sc->bge_link++;
3791                         if (bootverbose)
3792                                 if_printf(ifp, "link UP\n");
3793                 } else if (sc->bge_link &&
3794                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3795                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3796                         sc->bge_link = 0;
3797                         if (bootverbose)
3798                                 if_printf(ifp, "link DOWN\n");
3799                 }
3800         }
3801
3802         /* Clear the attention. */
3803         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3804             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3805             BGE_MACSTAT_LINK_CHANGED);
3806 }
3807
3808 static int
3809 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3810 {
3811         struct bge_softc *sc = arg1;
3812
3813         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3814                                    &sc->bge_rx_coal_ticks,
3815                                    BGE_RX_COAL_TICKS_CHG);
3816 }
3817
3818 static int
3819 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3820 {
3821         struct bge_softc *sc = arg1;
3822
3823         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3824                                    &sc->bge_tx_coal_ticks,
3825                                    BGE_TX_COAL_TICKS_CHG);
3826 }
3827
3828 static int
3829 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3830 {
3831         struct bge_softc *sc = arg1;
3832
3833         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3834                                    &sc->bge_rx_max_coal_bds,
3835                                    BGE_RX_MAX_COAL_BDS_CHG);
3836 }
3837
3838 static int
3839 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3840 {
3841         struct bge_softc *sc = arg1;
3842
3843         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3844                                    &sc->bge_tx_max_coal_bds,
3845                                    BGE_TX_MAX_COAL_BDS_CHG);
3846 }
3847
3848 static int
3849 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3850                     uint32_t coal_chg_mask)
3851 {
3852         struct bge_softc *sc = arg1;
3853         struct ifnet *ifp = &sc->arpcom.ac_if;
3854         int error = 0, v;
3855
3856         lwkt_serialize_enter(ifp->if_serializer);
3857
3858         v = *coal;
3859         error = sysctl_handle_int(oidp, &v, 0, req);
3860         if (!error && req->newptr != NULL) {
3861                 if (v < 0) {
3862                         error = EINVAL;
3863                 } else {
3864                         *coal = v;
3865                         sc->bge_coal_chg |= coal_chg_mask;
3866                 }
3867         }
3868
3869         lwkt_serialize_exit(ifp->if_serializer);
3870         return error;
3871 }
3872
3873 static void
3874 bge_coal_change(struct bge_softc *sc)
3875 {
3876         struct ifnet *ifp = &sc->arpcom.ac_if;
3877         uint32_t val;
3878
3879         ASSERT_SERIALIZED(ifp->if_serializer);
3880
3881         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3882                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3883                             sc->bge_rx_coal_ticks);
3884                 DELAY(10);
3885                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3886
3887                 if (bootverbose) {
3888                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3889                                   sc->bge_rx_coal_ticks);
3890                 }
3891         }
3892
3893         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3894                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3895                             sc->bge_tx_coal_ticks);
3896                 DELAY(10);
3897                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3898
3899                 if (bootverbose) {
3900                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3901                                   sc->bge_tx_coal_ticks);
3902                 }
3903         }
3904
3905         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3906                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3907                             sc->bge_rx_max_coal_bds);
3908                 DELAY(10);
3909                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3910
3911                 if (bootverbose) {
3912                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3913                                   sc->bge_rx_max_coal_bds);
3914                 }
3915         }
3916
3917         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3918                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3919                             sc->bge_tx_max_coal_bds);
3920                 DELAY(10);
3921                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3922
3923                 if (bootverbose) {
3924                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3925                                   sc->bge_tx_max_coal_bds);
3926                 }
3927         }
3928
3929         sc->bge_coal_chg = 0;
3930 }
3931
3932 static void
3933 bge_enable_intr(struct bge_softc *sc)
3934 {
3935         struct ifnet *ifp = &sc->arpcom.ac_if;
3936
3937         lwkt_serialize_handler_enable(ifp->if_serializer);
3938
3939         /*
3940          * Enable interrupt.
3941          */
3942         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3943
3944         /*
3945          * Unmask the interrupt when we stop polling.
3946          */
3947         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3948
3949         /*
3950          * Trigger another interrupt, since above writing
3951          * to interrupt mailbox0 may acknowledge pending
3952          * interrupt.
3953          */
3954         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3955 }
3956
3957 static void
3958 bge_disable_intr(struct bge_softc *sc)
3959 {
3960         struct ifnet *ifp = &sc->arpcom.ac_if;
3961
3962         /*
3963          * Mask the interrupt when we start polling.
3964          */
3965         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3966
3967         /*
3968          * Acknowledge possible asserted interrupt.
3969          */
3970         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3971
3972         lwkt_serialize_handler_disable(ifp->if_serializer);
3973 }
3974
3975 static int
3976 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
3977 {
3978         uint32_t mac_addr;
3979         int ret = 1;
3980
3981         mac_addr = bge_readmem_ind(sc, 0x0c14);
3982         if ((mac_addr >> 16) == 0x484b) {
3983                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3984                 ether_addr[1] = (uint8_t)mac_addr;
3985                 mac_addr = bge_readmem_ind(sc, 0x0c18);
3986                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3987                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3988                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3989                 ether_addr[5] = (uint8_t)mac_addr;
3990                 ret = 0;
3991         }
3992         return ret;
3993 }
3994
3995 static int
3996 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
3997 {
3998         int mac_offset = BGE_EE_MAC_OFFSET;
3999
4000         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4001                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4002
4003         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4004 }
4005
4006 static int
4007 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4008 {
4009         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4010                 return 1;
4011
4012         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4013                                ETHER_ADDR_LEN);
4014 }
4015
4016 static int
4017 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4018 {
4019         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4020                 /* NOTE: Order is critical */
4021                 bge_get_eaddr_mem,
4022                 bge_get_eaddr_nvram,
4023                 bge_get_eaddr_eeprom,
4024                 NULL
4025         };
4026         const bge_eaddr_fcn_t *func;
4027
4028         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4029                 if ((*func)(sc, eaddr) == 0)
4030                         break;
4031         }
4032         return (*func == NULL ? ENXIO : 0);
4033 }