2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.28 2006/03/28 22:18:59 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/mpipe.h>
40 #include <sys/devicestat.h>
43 #include <bus/pci/pcivar.h>
44 #include <machine/bus.h>
49 static void cyrix_timing(struct ata_device *, int, int);
50 static void promise_timing(struct ata_device *, int, int);
51 static void hpt_timing(struct ata_device *, int, int);
52 static int hpt_cable80(struct ata_device *);
55 #define ATAPI_DEVICE(atadev) \
56 ((atadev->unit == ATA_MASTER && \
57 atadev->channel->devices & ATA_ATAPI_MASTER) || \
58 (atadev->unit == ATA_SLAVE && \
59 atadev->channel->devices & ATA_ATAPI_SLAVE))
61 int ata_dma_debug = 0;
64 ata_dmaalloc(struct ata_device *atadev, int flags)
66 struct ata_channel *ch = atadev->channel;
68 if (atadev->dmastate.dmatab != NULL)
71 KKASSERT(ch->dma_mpipe.max_count != 0);
72 if (flags & M_RNOWAIT)
73 atadev->dmastate.dmatab = mpipe_alloc_nowait(&ch->dma_mpipe);
75 atadev->dmastate.dmatab = mpipe_alloc_waitok(&ch->dma_mpipe);
77 if (atadev->dmastate.dmatab != NULL) {
78 KKASSERT(((uintptr_t)atadev->dmastate.dmatab & PAGE_MASK) == 0);
85 ata_dmafree(struct ata_device *atadev)
87 struct ata_channel *ch = atadev->channel;
89 if (atadev->dmastate.dmatab) {
90 mpipe_free(&ch->dma_mpipe, atadev->dmastate.dmatab);
91 atadev->dmastate.dmatab = NULL;
96 ata_dmafreetags(struct ata_channel *ch)
101 ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
107 ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
109 device_t parent = device_get_parent(atadev->channel->dev);
110 int chiptype = atadev->channel->chiptype;
111 int chiprev = pci_get_revid(parent);
112 int channel = atadev->channel->unit;
113 int device = ATA_DEV(atadev->unit);
114 int devno = (channel << 1) + device;
117 /* set our most pessimistic default mode */
118 atadev->mode = ATA_PIO;
120 if (!atadev->channel->r_bmio)
123 /* if simplex controller, only allow DMA on primary channel */
125 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
126 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
127 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
128 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
129 ATA_BMSTAT_DMA_SIMPLEX) {
130 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
135 /* DMA engine address alignment is usually 1 word (2 bytes) */
136 atadev->channel->alignment = 0x1;
139 if (udmamode > 2 && !atadev->param->hwres_cblid) {
140 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
146 case 0x27df8086: /* Intel ICH7 ATA */
147 case 0x27c48086: /* Intel ICH7M SATA */
148 case 0x266f8086: /* Intel ICH6 ATA */
149 case 0x26528086: /* Intel ICH6R/RW SATA */
150 case 0x26518086: /* Intel ICH6/W SATA */
151 case 0x24db8086: /* Intel ICH5 */
152 case 0x24d18086: /* Intel ICH5 SATA */
153 case 0x24ca8086: /* Intel ICH4 mobile */
154 case 0x24cb8086: /* Intel ICH4 */
155 case 0x248a8086: /* Intel ICH3 mobile */
156 case 0x248b8086: /* Intel ICH3 */
157 case 0x244a8086: /* Intel ICH2 mobile */
158 case 0x244b8086: /* Intel ICH2 */
160 int32_t mask48, new48;
163 word54 = pci_read_config(parent, 0x54, 2);
164 if (word54 & (0x10 << devno)) {
165 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
166 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
168 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
169 (error) ? "failed" : "success");
171 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
172 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
173 pci_write_config(parent, 0x48,
174 (pci_read_config(parent, 0x48, 4) &
175 ~mask48) | new48, 4);
176 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
177 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
182 /* make sure eventual ATA100 mode from the BIOS is disabled */
183 pci_write_config(parent, 0x54,
184 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
187 case 0x24118086: /* Intel ICH */
188 case 0x76018086: /* Intel ICH */
190 int32_t mask48, new48;
193 word54 = pci_read_config(parent, 0x54, 2);
194 if (word54 & (0x10 << devno)) {
195 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
196 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
198 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
199 (error) ? "failed" : "success");
201 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
202 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
203 pci_write_config(parent, 0x48,
204 (pci_read_config(parent, 0x48, 4) &
205 ~mask48) | new48, 4);
206 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
207 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
212 /* make sure eventual ATA66 mode from the BIOS is disabled */
213 pci_write_config(parent, 0x54,
214 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
217 case 0x71118086: /* Intel PIIX4 */
218 case 0x84CA8086: /* Intel PIIX4 */
219 case 0x71998086: /* Intel PIIX4e */
220 case 0x24218086: /* Intel ICH0 */
222 int32_t mask48, new48;
224 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
225 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
227 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
228 (error) ? "failed" : "success");
230 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
231 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
232 pci_write_config(parent, 0x48,
233 (pci_read_config(parent, 0x48, 4) &
234 ~mask48) | new48, 4);
235 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
239 /* make sure eventual ATA33 mode from the BIOS is disabled */
240 pci_write_config(parent, 0x48,
241 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
244 case 0x70108086: /* Intel PIIX3 */
245 if (wdmamode >= 2 && apiomode >= 4) {
246 int32_t mask40, new40, mask44, new44;
248 /* if SITRE not set doit for both channels */
249 if (!((pci_read_config(parent,0x40,4)>>(channel<<8))&0x4000)) {
250 new40 = pci_read_config(parent, 0x40, 4);
251 new44 = pci_read_config(parent, 0x44, 4);
252 if (!(new40 & 0x00004000)) {
253 new44 &= ~0x0000000f;
254 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
256 if (!(new40 & 0x40000000)) {
257 new44 &= ~0x000000f0;
258 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
261 pci_write_config(parent, 0x40, new40, 4);
262 pci_write_config(parent, 0x44, new44, 4);
264 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
265 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
267 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
268 (error) ? "failed" : "success");
270 if (device == ATA_MASTER) {
288 pci_write_config(parent, 0x40,
289 (pci_read_config(parent, 0x40, 4) & ~mask40)|
291 pci_write_config(parent, 0x44,
292 (pci_read_config(parent, 0x44, 4) & ~mask44)|
294 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
298 /* we could set PIO mode timings, but we assume the BIOS did that */
301 case 0x12308086: /* Intel PIIX */
302 if (wdmamode >= 2 && apiomode >= 4) {
305 word40 = pci_read_config(parent, 0x40, 4);
306 word40 >>= channel * 16;
308 /* Check for timing config usable for DMA on controller */
309 if (!((word40 & 0x3300) == 0x2300 &&
310 ((word40 >> (device ? 4 : 0)) & 1) == 1))
313 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
314 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
316 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
317 (error) ? "failed" : "success");
319 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
325 case 0x522910b9: /* AcerLabs Aladdin IV/V */
326 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
327 if (chiprev < 0xc2 &&
328 atadev->channel->devices & ATA_ATAPI_MASTER &&
329 atadev->channel->devices & ATA_ATAPI_SLAVE) {
330 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
333 #if !defined(NO_ATANG)
334 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
336 if (udmamode >= 5 && chiprev >= 0xc4) {
337 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
338 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
340 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
341 (error) ? "failed" : "success");
343 int32_t word54 = pci_read_config(parent, 0x54, 4);
345 pci_write_config(parent, 0x4b,
346 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
347 word54 &= ~(0x000f000f << (devno << 2));
348 word54 |= (0x000f0005 << (devno << 2));
349 pci_write_config(parent, 0x54, word54, 4);
350 pci_write_config(parent, 0x53,
351 pci_read_config(parent, 0x53, 1) | 0x03, 1);
352 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
356 if (udmamode >= 4 && chiprev >= 0xc2) {
357 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
358 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
360 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
361 (error) ? "failed" : "success");
363 int32_t word54 = pci_read_config(parent, 0x54, 4);
365 pci_write_config(parent, 0x4b,
366 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
367 word54 &= ~(0x000f000f << (devno << 2));
368 word54 |= (0x00080005 << (devno << 2));
369 pci_write_config(parent, 0x54, word54, 4);
370 pci_write_config(parent, 0x53,
371 pci_read_config(parent, 0x53, 1) | 0x03, 1);
372 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
376 if (udmamode >= 2 && chiprev >= 0x20) {
377 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
378 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
380 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
381 (error) ? "failed" : "success");
383 int32_t word54 = pci_read_config(parent, 0x54, 4);
385 word54 &= ~(0x000f000f << (devno << 2));
386 word54 |= (0x000a0005 << (devno << 2));
387 pci_write_config(parent, 0x54, word54, 4);
388 pci_write_config(parent, 0x53,
389 pci_read_config(parent, 0x53, 1) | 0x03, 1);
390 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
391 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
396 /* make sure eventual UDMA mode from the BIOS is disabled */
397 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
398 ~(0x0008 << (devno << 2)), 2);
400 if (wdmamode >= 2 && apiomode >= 4) {
401 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
402 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
404 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
405 (error) ? "failed" : "success");
407 pci_write_config(parent, 0x53,
408 pci_read_config(parent, 0x53, 1) | 0x03, 1);
409 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
410 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
414 pci_write_config(parent, 0x53,
415 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
416 #if !defined(NO_ATANG)
417 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
419 ATA_C_F_SETXFER, ATA_WAIT_READY);
421 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
422 (error) ? "failed" : "success",
423 (apiomode >= 0) ? apiomode : 0);
425 int32_t word54 = pci_read_config(parent, 0x54, 4);
428 switch(ATA_PIO0 + apiomode) {
429 case ATA_PIO0: timing = 0x006d0003; break;
430 case ATA_PIO1: timing = 0x00580002; break;
431 case ATA_PIO2: timing = 0x00440001; break;
432 case ATA_PIO3: timing = 0x00330001; break;
433 case ATA_PIO4: timing = 0x00310001; break;
434 default: timing = 0x006d0003; break;
436 pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
437 word54 &= ~(0x000f000f << (devno << 2));
438 word54 |= (0x00000004 << (devno << 2));
439 pci_write_config(parent, 0x54, word54, 4);
440 atadev->mode = ATA_PIO0 + apiomode;
446 case 0x31491106: /* VIA 8237 SATA part */
448 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
450 ATA_C_F_SETXFER, ATA_WAIT_READY);
452 ata_prtdev(atadev, "%s setting UDMA%d on VIA chip\n",
453 (error) ? "failed" : "success", udmamode);
455 ata_dmacreate(atadev, apiomode, ATA_UDMA + udmamode);
459 /* we could set PIO mode timings, but we assume the BIOS did that */
462 case 0x01bc10de: /* NVIDIA nForce1 */
463 case 0x006510de: /* NVIDIA nForce2 */
464 case 0x00d510de: /* NVIDIA nForce3 */
465 case 0x00e310de: /* NVIDIA nForce3 PRO S1 */
466 case 0x00e510de: /* NVIDIA nForce3 PRO */
467 case 0x74691022: /* AMD 8111 */
468 case 0x74411022: /* AMD 768 */
469 case 0x74111022: /* AMD 766 */
470 case 0x74091022: /* AMD 756 */
471 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
473 int via_modes[][7] = {
474 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
475 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
476 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
477 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
478 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
483 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
484 ata_find_dev(parent, 0x31771106, 0) || /* 8235 */
485 ata_find_dev(parent, 0x31491106, 0)) { /* 8237 */
486 udmamode = imin(udmamode, 6);
487 reg_val = via_modes[3];
489 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
490 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
491 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
492 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
493 udmamode = imin(udmamode, 5);
494 reg_val = via_modes[2];
496 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
497 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
498 udmamode = imin(udmamode, 4);
499 reg_val = via_modes[1];
501 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
502 udmamode = imin(udmamode, 2);
503 reg_val = via_modes[1];
505 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
506 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
507 udmamode = imin(udmamode, 2);
508 reg_val = via_modes[0];
510 else if (chiptype == 0x74691022 || /* AMD 8111 */
511 chiptype == 0x74411022 || /* AMD 768 */
512 chiptype == 0x74111022) { /* AMD 766 */
513 udmamode = imin(udmamode, 5);
514 reg_val = via_modes[4];
517 else if (chiptype == 0x74091022) { /* AMD 756 */
518 udmamode = imin(udmamode, 4);
519 reg_val = via_modes[4];
522 else if (chiptype == 0x01bc10de) { /* nForce1 */
523 udmamode = imin(udmamode, 5);
524 reg_val = via_modes[4];
525 #if !defined(NO_ATANG)
530 else if (chiptype == 0x006510de || /* nForce2 */
531 chiptype == 0x00d510de || /* nForce3 */
532 chiptype == 0x00e310de || /* nForce3 PRO S1 */
533 chiptype == 0x00e510de) { /* nForce3 PRO */
534 udmamode = imin(udmamode, 6);
535 reg_val = via_modes[4];
536 #if !defined(NO_ATANG)
547 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
548 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
550 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
551 (error) ? "failed" : "success", chip);
553 pci_write_config(parent, reg_off, reg_val[6], 1);
554 pci_write_config(parent, reg_off - 8, 0x20, 1);
555 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
560 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
561 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
563 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
564 (error) ? "failed" : "success", chip);
566 pci_write_config(parent, reg_off, reg_val[5], 1);
567 pci_write_config(parent, reg_off - 8, 0x20, 1);
568 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
573 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
574 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
576 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
577 (error) ? "failed" : "success", chip);
579 pci_write_config(parent, reg_off, reg_val[4], 1);
580 pci_write_config(parent, reg_off - 8, 0x20, 1);
581 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
586 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
587 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
589 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
590 (error) ? "failed" : "success", chip);
592 pci_write_config(parent, reg_off, reg_val[2], 1);
593 pci_write_config(parent, reg_off - 8, 0x20, 1);
594 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
598 if (wdmamode >= 2 && apiomode >= 4) {
599 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
600 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
602 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
603 (error) ? "failed" : "success", chip);
605 pci_write_config(parent, reg_off, 0x0b, 1);
606 pci_write_config(parent, reg_off - 8, 0x20, 1);
607 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
611 pci_write_config(parent, reg_off, 0x8b, 1);
614 pci_write_config(parent, reg_off - 8, 0xa8, 1);
617 pci_write_config(parent, reg_off - 8, 0x65, 1);
620 pci_write_config(parent, reg_off - 8, 0x42, 1);
623 pci_write_config(parent, reg_off - 8, 0x22, 1);
626 pci_write_config(parent, reg_off - 8, 0x20, 1);
632 case 0x55131039: /* SiS 5591 */
633 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
634 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
635 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
636 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
637 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
638 ata_find_dev(parent, 0x06461039, 0) || /* SiS 645DX */
639 ata_find_dev(parent, 0x06481039, 0) || /* SiS 648 */
640 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
641 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
642 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
643 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
644 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
645 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
646 ata_find_dev(parent, 0x07461039, 0) || /* SiS 746 */
647 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
648 int8_t reg = 0x40 + (devno << 1);
649 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
652 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
653 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
655 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
656 (error) ? "failed" : "success");
658 pci_write_config(parent, reg, val | 0x8000, 2);
659 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
664 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
665 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
667 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
668 (error) ? "failed" : "success");
670 pci_write_config(parent, reg, val | 0x9000, 2);
671 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
676 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
677 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
679 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
680 (error) ? "failed" : "success");
682 pci_write_config(parent, reg, val | 0xb000, 2);
683 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
687 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
688 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
689 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
690 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
691 int8_t reg = 0x40 + (devno << 1);
692 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
695 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
696 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
698 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
699 (error) ? "failed" : "success");
701 pci_write_config(parent, reg, val | 0x9000, 2);
702 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
707 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
708 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
710 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
711 (error) ? "failed" : "success");
713 pci_write_config(parent, reg, val | 0xa000, 2);
714 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
718 } else if (udmamode >= 2 && chiprev > 0xc1) {
719 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
720 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
722 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
723 (error) ? "failed" : "success");
725 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
726 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
730 if (wdmamode >=2 && apiomode >= 4) {
731 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
732 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
734 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
735 (error) ? "failed" : "success");
737 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
738 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
742 /* we could set PIO mode timings, but we assume the BIOS did that */
745 case 0x35121095: /* SiI 3512 SATA controller */
746 /* EXPERIMENTAL! Works with FN85 AMD 64 3200+ motherboard */
748 case 0x31241095: /* SiI 3124 SATA controller */
749 case 0x31141095: /* SiI 3114 SATA controller */
750 case 0x31121095: /* SiI 3112 SATA controller */
751 case 0x06801095: /* SiI 0680 ATA133 controller */
753 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
754 u_int8_t uval = pci_read_config(parent, ureg, 1);
755 u_int8_t mreg = channel ? 0x84 : 0x80;
756 u_int8_t mask = device ? 0x30 : 0x03;
757 u_int8_t mode = pci_read_config(parent, mreg, 1);
759 /* enable UDMA mode */
760 pci_write_config(parent, mreg,
761 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
763 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
764 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
766 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
767 (error) ? "failed" : "success");
769 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x01, 1);
770 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
775 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
776 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
778 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
779 (error) ? "failed" : "success");
781 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x02, 1);
782 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
787 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
788 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
790 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
791 (error) ? "failed" : "success");
793 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x03, 1);
794 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
799 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
800 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
802 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
803 (error) ? "failed" : "success");
805 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x07, 1);
806 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
811 /* disable UDMA mode and enable WDMA mode */
812 pci_write_config(parent, mreg,
813 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
814 if (wdmamode >= 2 && apiomode >= 4) {
815 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
816 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
818 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
819 (error) ? "failed" : "success");
821 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
822 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
827 /* restore PIO mode */
828 pci_write_config(parent, mreg, mode, 1);
830 /* we could set PIO mode timings, but we assume the BIOS did that */
833 case 0x06491095: /* CMD 649 ATA100 controller */
837 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
838 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
840 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
841 (error) ? "failed" : "success");
843 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
844 umode &= ~(device ? 0xca : 0x35);
845 umode |= (device ? 0x0a : 0x05);
846 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
847 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
853 case 0x06481095: /* CMD 648 ATA66 controller */
857 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
858 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
860 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
861 (error) ? "failed" : "success");
863 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
864 umode &= ~(device ? 0xca : 0x35);
865 umode |= (device ? 0x4a : 0x15);
866 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
867 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
874 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
875 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
877 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
878 (error) ? "failed" : "success");
880 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
881 umode &= ~(device ? 0xca : 0x35);
882 umode |= (device ? 0x42 : 0x11);
883 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
884 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
888 /* make sure eventual UDMA mode from the BIOS is disabled */
889 pci_write_config(parent, channel ? 0x7b : 0x73,
890 pci_read_config(parent, channel ? 0x7b : 0x73, 1)&
891 #if !defined(NO_ATANG)
892 ~(device ? 0xca : 0x53), 1);
894 ~(device ? 0xca : 0x35), 1);
898 case 0x06461095: /* CMD 646 ATA controller */
899 if (wdmamode >= 2 && apiomode >= 4) {
900 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
901 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
903 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
904 error ? "failed" : "success");
906 int32_t offset = (devno < 3) ? (devno << 1) : 7;
908 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
909 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
913 /* we could set PIO mode timings, but we assume the BIOS did that */
916 case 0xc6931080: /* Cypress 82c693 ATA controller */
917 if (wdmamode >= 2 && apiomode >= 4) {
918 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
919 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
921 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
922 error ? "failed" : "success");
924 pci_write_config(atadev->channel->dev,
925 channel ? 0x4e:0x4c, 0x2020, 2);
926 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
930 /* we could set PIO mode timings, but we assume the BIOS did that */
933 case 0x01021078: /* Cyrix 5530 ATA33 controller */
934 atadev->channel->alignment = 0xf; /* DMA engine requires 16 byte alignment */
936 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
937 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
939 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
940 (error) ? "failed" : "success");
942 cyrix_timing(atadev, devno, ATA_UDMA2);
943 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
947 if (wdmamode >= 2 && apiomode >= 4) {
948 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
949 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
951 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
952 (error) ? "failed" : "success");
954 cyrix_timing(atadev, devno, ATA_WDMA2);
955 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
959 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
960 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
963 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
964 (error) ? "failed" : "success",
965 ata_mode2str(ATA_PIO0 + apiomode));
966 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
967 atadev->mode = ATA_PIO0 + apiomode;
970 #if !defined(NO_ATANG)
971 case 0x02131166: /* ServerWorks CSB6 ATA 100 controller (chan 0+1) */
973 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
974 #if !defined(NO_ATANG)
975 if (udmamode >= 5 && (chiptype == 0x02131166 ||
976 (chiptype == 0x02121166 &&
979 if (udmamode >= 5 && chiprev >= 0x92) {
981 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
982 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
984 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
985 (error) ? "failed" : "success");
989 pci_write_config(parent, 0x54,
990 pci_read_config(parent, 0x54, 1) |
992 reg56 = pci_read_config(parent, 0x56, 2);
993 reg56 &= ~(0xf << (devno * 4));
994 reg56 |= (0x5 << (devno * 4));
995 pci_write_config(parent, 0x56, reg56, 2);
996 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1000 #if !defined(NO_ATANG)
1002 case 0x02171166: /* Server Works CSB6 ATA 66 controller chan 2 */
1004 if (udmamode >= 4) {
1005 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1006 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1008 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
1009 (error) ? "failed" : "success");
1013 pci_write_config(parent, 0x54,
1014 pci_read_config(parent, 0x54, 1) |
1015 (0x01 << devno), 1);
1016 reg56 = pci_read_config(parent, 0x56, 2);
1017 reg56 &= ~(0xf << (devno * 4));
1018 reg56 |= (0x4 << (devno * 4));
1019 pci_write_config(parent, 0x56, reg56, 2);
1020 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1026 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
1027 if (udmamode >= 2) {
1028 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1029 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1031 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
1032 (error) ? "failed" : "success");
1036 pci_write_config(parent, 0x54,
1037 pci_read_config(parent, 0x54, 1) |
1038 (0x01 << devno), 1);
1039 reg56 = pci_read_config(parent, 0x56, 2);
1040 reg56 &= ~(0xf << (devno * 4));
1041 reg56 |= (0x2 << (devno * 4));
1042 pci_write_config(parent, 0x56, reg56, 2);
1043 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1047 if (wdmamode >= 2 && apiomode >= 4) {
1048 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1049 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1051 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
1052 (error) ? "failed" : "success");
1054 int offset = devno ^ 0x01; /* (chan*2) + (dev==ATA_MASTER)*/
1055 int word44 = pci_read_config(parent, 0x44, 4);
1057 pci_write_config(parent, 0x54,
1058 pci_read_config(parent, 0x54, 1) &
1059 ~(0x01 << devno), 1);
1060 word44 &= ~(0xff << (offset << 8));
1061 word44 |= (0x20 << (offset << 8));
1062 pci_write_config(parent, 0x44, 0x20, 4);
1063 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1067 /* we could set PIO mode timings, but we assume the BIOS did that */
1070 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
1071 case 0x5275105a: /* Promise TX2 ATA133 controllers */
1072 case 0x6269105a: /* Promise TX2 ATA133 controllers */
1073 case 0x7275105a: /* Promise TX2 ATA133 controllers */
1074 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1075 if (udmamode >= 6 &&
1076 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1077 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1078 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1080 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
1081 (error) ? "failed" : "success");
1083 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1089 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
1090 case 0x6268105a: /* Promise TX2 ATA100 controllers */
1091 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1092 if (udmamode >= 5 &&
1093 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1094 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1095 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1097 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1098 (error) ? "failed" : "success");
1100 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1104 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1105 if (udmamode >= 4 &&
1106 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1107 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1108 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1110 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1111 (error) ? "failed" : "success");
1113 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1117 if (udmamode >= 2) {
1118 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1119 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1121 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
1122 (error) ? "failed" : "success");
1124 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1128 if (wdmamode >= 2 && apiomode >= 4) {
1129 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1130 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1132 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1133 (error) ? "failed" : "success");
1135 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1141 case 0x0d30105a: /* Promise OEM ATA100 controllers */
1142 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
1143 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 &&
1144 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1145 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1146 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1148 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1149 (error) ? "failed" : "success");
1151 promise_timing(atadev, devno, ATA_UDMA5);
1152 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1158 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1159 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1160 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 &&
1161 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1162 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1163 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1165 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1166 (error) ? "failed" : "success");
1168 promise_timing(atadev, devno, ATA_UDMA4);
1169 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1175 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1176 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1177 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1178 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1180 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1181 (error) ? "failed" : "success");
1183 promise_timing(atadev, devno, ATA_UDMA2);
1184 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1188 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1189 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1190 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1192 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1193 (error) ? "failed" : "success");
1195 promise_timing(atadev, devno, ATA_WDMA2);
1196 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1200 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1201 ATA_PIO0 + apiomode,
1202 ATA_C_F_SETXFER, ATA_WAIT_READY);
1204 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1205 (error) ? "failed" : "success",
1206 (apiomode >= 0) ? apiomode : 0);
1207 promise_timing(atadev, devno, ATA_PIO0 + apiomode);
1208 atadev->mode = ATA_PIO0 + apiomode;
1211 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1212 case 0x00051103: /* HighPoint HPT372 controllers */
1213 case 0x00081103: /* HighPoint HPT374 controllers */
1214 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
1215 ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1216 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1217 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1218 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1219 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1221 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1222 (error) ? "failed" : "success");
1224 hpt_timing(atadev, devno, ATA_UDMA6);
1225 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1229 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
1230 ((chiptype == 0x00041103 && chiprev >= 0x03) ||
1231 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1232 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1233 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1234 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1236 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1237 (error) ? "failed" : "success");
1239 hpt_timing(atadev, devno, ATA_UDMA5);
1240 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1244 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
1245 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1246 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1248 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1249 (error) ? "failed" : "success");
1251 hpt_timing(atadev, devno, ATA_UDMA4);
1252 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1256 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1257 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1258 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1260 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1261 (error) ? "failed" : "success");
1263 hpt_timing(atadev, devno, ATA_UDMA2);
1264 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1268 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1269 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1270 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1272 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1273 (error) ? "failed" : "success");
1275 hpt_timing(atadev, devno, ATA_WDMA2);
1276 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1280 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1281 ATA_PIO0 + apiomode,
1282 ATA_C_F_SETXFER, ATA_WAIT_READY);
1284 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1285 (error) ? "failed" : "success",
1286 (apiomode >= 0) ? apiomode : 0);
1287 hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
1288 atadev->mode = ATA_PIO0 + apiomode;
1291 case 0x000116ca: /* Cenatek Rocket Drive controller */
1292 if (wdmamode >= 0 &&
1293 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1294 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
1295 ata_dmacreate(atadev, apiomode, ATA_DMA);
1297 atadev->mode = ATA_PIO;
1300 default: /* unknown controller chip */
1301 /* better not try generic DMA on ATAPI devices it almost never works */
1302 if (ATAPI_DEVICE(atadev))
1305 /* if controller says its setup for DMA take the easy way out */
1306 /* the downside is we dont know what DMA mode we are in */
1307 if ((udmamode >= 0 || wdmamode >= 2) &&
1308 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1309 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
1310 ata_dmacreate(atadev, apiomode, ATA_DMA);
1314 /* well, we have no support for this, but try anyways */
1315 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
1316 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1317 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1319 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1320 (error) ? "failed" : "success");
1322 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1327 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1328 ATA_C_F_SETXFER, ATA_WAIT_READY);
1330 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1331 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1333 atadev->mode = ATA_PIO0 + apiomode;
1336 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1337 atadev->mode = ATA_PIO;
1342 ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
1344 struct ata_channel *ch = atadev->channel;
1345 struct ata_dmastate *ds = &atadev->dmastate;
1346 u_int32_t dma_count, dma_base;
1349 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1350 ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
1355 ata_prtdev(atadev, "zero length DMA transfer attempted\n");
1359 dma_base = vtophys(data);
1360 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1365 ds->dmatab[i].base = dma_base;
1366 ds->dmatab[i].count = (dma_count & 0xffff);
1368 if (i >= ATA_DMA_ENTRIES) {
1369 ata_prtdev(atadev, "too many segments in DMA table\n");
1372 dma_base = vtophys(data);
1373 dma_count = imin(count, PAGE_SIZE);
1374 data += imin(count, PAGE_SIZE);
1375 count -= imin(count, PAGE_SIZE);
1377 ds->dmatab[i].base = dma_base;
1378 ds->dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1383 ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
1385 struct ata_channel *ch = atadev->channel;
1386 struct ata_dmastate *ds = &atadev->dmastate;
1388 ch->flags |= ATA_DMA_ACTIVE;
1389 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(ds->dmatab));
1390 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1391 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1392 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1393 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1394 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1395 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1400 ata_dmadone(struct ata_device *atadev)
1402 struct ata_channel *ch;
1403 struct ata_dmastate *ds;
1406 ch = atadev->channel;
1407 ds = &atadev->dmastate;
1409 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1410 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1411 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1412 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1413 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1414 ch->flags &= ~ATA_DMA_ACTIVE;
1416 return error & ATA_BMSTAT_MASK;
1420 ata_dmastatus(struct ata_channel *ch)
1422 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1426 cyrix_timing(struct ata_device *atadev, int devno, int mode)
1428 u_int32_t reg20 = 0x0000e132;
1429 u_int32_t reg24 = 0x00017771;
1432 case ATA_PIO0: reg20 = 0x0000e132; break;
1433 case ATA_PIO1: reg20 = 0x00018121; break;
1434 case ATA_PIO2: reg20 = 0x00024020; break;
1435 case ATA_PIO3: reg20 = 0x00032010; break;
1436 case ATA_PIO4: reg20 = 0x00040010; break;
1437 case ATA_WDMA2: reg24 = 0x00002020; break;
1438 case ATA_UDMA2: reg24 = 0x00911030; break;
1440 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
1441 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
1445 promise_timing(struct ata_device *atadev, int devno, int mode)
1447 u_int32_t timing = 0;
1448 /* XXX: Endianess */
1449 struct promise_timing {
1451 u_int8_t prefetch:1;
1462 u_int8_t reserved:8;
1463 } *t = (struct promise_timing*)&timing;
1465 t->iordy = 1; t->iordyp = 1;
1466 if (mode >= ATA_DMA) {
1467 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1470 switch (atadev->channel->chiptype) {
1471 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1474 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1475 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1476 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1477 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1478 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1479 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1480 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1484 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1485 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1486 case 0x0d30105a: /* Promise OEM ATA 100 */
1489 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1490 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1491 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1492 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1493 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1494 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1495 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1496 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1497 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1501 pci_write_config(device_get_parent(atadev->channel->dev),
1502 0x60 + (devno<<2), timing, 4);
1506 hpt_timing(struct ata_device *atadev, int devno, int mode)
1508 device_t parent = device_get_parent(atadev->channel->dev);
1509 u_int32_t chiptype = atadev->channel->chiptype;
1510 int chiprev = pci_get_revid(parent);
1513 if (chiptype == 0x00081103 && chiprev >= 0x07) {
1514 switch (mode) { /* HPT374 */
1515 case ATA_PIO0: timing = 0x0ac1f48a; break;
1516 case ATA_PIO1: timing = 0x0ac1f465; break;
1517 case ATA_PIO2: timing = 0x0a81f454; break;
1518 case ATA_PIO3: timing = 0x0a81f443; break;
1519 case ATA_PIO4: timing = 0x0a81f442; break;
1520 case ATA_WDMA2: timing = 0x22808242; break;
1521 case ATA_UDMA2: timing = 0x120c8242; break;
1522 case ATA_UDMA4: timing = 0x12ac8242; break;
1523 case ATA_UDMA5: timing = 0x12848242; break;
1524 case ATA_UDMA6: timing = 0x12808242; break;
1525 default: timing = 0x0d029d5e;
1528 else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1529 (chiptype == 0x00051103 && chiprev >= 0x01)) {
1530 switch (mode) { /* HPT372 */
1531 case ATA_PIO0: timing = 0x0d029d5e; break;
1532 case ATA_PIO1: timing = 0x0d029d26; break;
1533 case ATA_PIO2: timing = 0x0c829ca6; break;
1534 case ATA_PIO3: timing = 0x0c829c84; break;
1535 case ATA_PIO4: timing = 0x0c829c62; break;
1536 case ATA_WDMA2: timing = 0x2c829262; break;
1537 case ATA_UDMA2: timing = 0x1c91dc62; break;
1538 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1539 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1540 case ATA_UDMA6: timing = 0x1c81dc62; break;
1541 default: timing = 0x0d029d5e;
1544 else if (chiptype == 0x00041103 && chiprev >= 0x03) {
1545 switch (mode) { /* HPT370 */
1546 case ATA_PIO0: timing = 0x06914e57; break;
1547 case ATA_PIO1: timing = 0x06914e43; break;
1548 case ATA_PIO2: timing = 0x06514e33; break;
1549 case ATA_PIO3: timing = 0x06514e22; break;
1550 case ATA_PIO4: timing = 0x06514e21; break;
1551 case ATA_WDMA2: timing = 0x26514e21; break;
1552 case ATA_UDMA2: timing = 0x16494e31; break;
1553 case ATA_UDMA4: timing = 0x16454e31; break;
1554 case ATA_UDMA5: timing = 0x16454e31; break;
1555 default: timing = 0x06514e57;
1557 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1559 else { /* HPT36[68] */
1560 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1561 case 0x85: /* 25Mhz */
1563 case ATA_PIO0: timing = 0x40d08585; break;
1564 case ATA_PIO1: timing = 0x40d08572; break;
1565 case ATA_PIO2: timing = 0x40ca8542; break;
1566 case ATA_PIO3: timing = 0x40ca8532; break;
1567 case ATA_PIO4: timing = 0x40ca8521; break;
1568 case ATA_WDMA2: timing = 0x20ca8521; break;
1569 case ATA_UDMA2: timing = 0x10cf8521; break;
1570 case ATA_UDMA4: timing = 0x10c98521; break;
1571 default: timing = 0x01208585;
1575 case 0xa7: /* 33MHz */
1577 case ATA_PIO0: timing = 0x40d0a7aa; break;
1578 case ATA_PIO1: timing = 0x40d0a7a3; break;
1579 case ATA_PIO2: timing = 0x40d0a753; break;
1580 case ATA_PIO3: timing = 0x40c8a742; break;
1581 case ATA_PIO4: timing = 0x40c8a731; break;
1582 case ATA_WDMA2: timing = 0x20c8a731; break;
1583 case ATA_UDMA2: timing = 0x10caa731; break;
1584 case ATA_UDMA4: timing = 0x10c9a731; break;
1585 default: timing = 0x0120a7a7;
1588 case 0xd9: /* 40Mhz */
1590 case ATA_PIO0: timing = 0x4018d9d9; break;
1591 case ATA_PIO1: timing = 0x4010d9c7; break;
1592 case ATA_PIO2: timing = 0x4010d997; break;
1593 case ATA_PIO3: timing = 0x4010d974; break;
1594 case ATA_PIO4: timing = 0x4008d963; break;
1595 case ATA_WDMA2: timing = 0x2008d943; break;
1596 case ATA_UDMA2: timing = 0x100bd943; break;
1597 case ATA_UDMA4: timing = 0x100fd943; break;
1598 default: timing = 0x0120d9d9;
1602 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1606 hpt_cable80(struct ata_device *atadev)
1608 device_t parent = device_get_parent(atadev->channel->dev);
1609 u_int8_t reg, val, res;
1611 if (atadev->channel->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1612 reg = atadev->channel->unit ? 0x57 : 0x53;
1613 val = pci_read_config(parent, reg, 1);
1614 pci_write_config(parent, reg, val | 0x80, 1);
1618 val = pci_read_config(parent, reg, 1);
1619 pci_write_config(parent, reg, val & 0xfe, 1);
1621 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x01 : 0x02);
1622 pci_write_config(parent, reg, val, 1);