bge: Improve TX performance on certain low end chips
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 /*
37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38  * 
39  * Written by Bill Paul <wpaul@windriver.com>
40  * Senior Engineer, Wind River Systems
41  */
42
43 /*
44  * The Broadcom BCM5700 is based on technology originally developed by
45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49  * frames, highly configurable RX filtering, and 16 RX and TX queues
50  * (which, along with RX filter rules, can be used for QOS applications).
51  * Other features, such as TCP segmentation, may be available as part
52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53  * firmware images can be stored in hardware and need not be compiled
54  * into the driver.
55  *
56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58  * 
59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61  * does not support external SSRAM.
62  *
63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
64  * brand name, which is functionally similar but lacks PCI-X support.
65  *
66  * Without external SSRAM, you can only have at most 4 TX rings,
67  * and the use of the mini RX ring is disabled. This seems to imply
68  * that these features are simply not available on the BCM5701. As a
69  * result, this driver does not implement any support for the mini RX
70  * ring.
71  */
72
73 #include "opt_polling.h"
74
75 #include <sys/param.h>
76 #include <sys/bus.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
79 #include <sys/ktr.h>
80 #include <sys/interrupt.h>
81 #include <sys/mbuf.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
84 #include <sys/rman.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
89
90 #include <net/bpf.h>
91 #include <net/ethernet.h>
92 #include <net/if.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99 #include <net/vlan/if_vlan_ether.h>
100
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
103 #include <dev/netif/mii_layer/brgphyreg.h>
104
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
108
109 #include <dev/netif/bge/if_bgereg.h>
110
111 /* "device miibus" required.  See GENERIC if you get errors here. */
112 #include "miibus_if.h"
113
114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
115 #define BGE_MIN_FRAME           60
116
117 static const struct bge_type bge_devs[] = {
118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119                 "3COM 3C996 Gigabit Ethernet" },
120
121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
122                 "Alteon BCM5700 Gigabit Ethernet" },
123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124                 "Alteon BCM5701 Gigabit Ethernet" },
125
126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127                 "Altima AC1000 Gigabit Ethernet" },
128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129                 "Altima AC1002 Gigabit Ethernet" },
130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131                 "Altima AC9100 Gigabit Ethernet" },
132
133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134                 "Apple BCM5701 Gigabit Ethernet" },
135
136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
137                 "Broadcom BCM5700 Gigabit Ethernet" },
138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
139                 "Broadcom BCM5701 Gigabit Ethernet" },
140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141                 "Broadcom BCM5702 Gigabit Ethernet" },
142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
143                 "Broadcom BCM5702X Gigabit Ethernet" },
144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145                 "Broadcom BCM5702 Gigabit Ethernet" },
146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147                 "Broadcom BCM5703 Gigabit Ethernet" },
148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149                 "Broadcom BCM5703X Gigabit Ethernet" },
150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151                 "Broadcom BCM5703 Gigabit Ethernet" },
152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
159                 "Broadcom BCM5705 Gigabit Ethernet" },
160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161                 "Broadcom BCM5705F Gigabit Ethernet" },
162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163                 "Broadcom BCM5705K Gigabit Ethernet" },
164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
165                 "Broadcom BCM5705M Gigabit Ethernet" },
166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
167                 "Broadcom BCM5705M Gigabit Ethernet" },
168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
169                 "Broadcom BCM5714C Gigabit Ethernet" },
170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171                 "Broadcom BCM5714S Gigabit Ethernet" },
172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173                 "Broadcom BCM5715 Gigabit Ethernet" },
174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175                 "Broadcom BCM5715S Gigabit Ethernet" },
176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177                 "Broadcom BCM5720 Gigabit Ethernet" },
178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179                 "Broadcom BCM5721 Gigabit Ethernet" },
180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181                 "Broadcom BCM5722 Gigabit Ethernet" },
182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183                 "Broadcom BCM5723 Gigabit Ethernet" },
184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185                 "Broadcom BCM5750 Gigabit Ethernet" },
186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187                 "Broadcom BCM5750M Gigabit Ethernet" },
188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189                 "Broadcom BCM5751 Gigabit Ethernet" },
190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191                 "Broadcom BCM5751F Gigabit Ethernet" },
192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193                 "Broadcom BCM5751M Gigabit Ethernet" },
194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195                 "Broadcom BCM5752 Gigabit Ethernet" },
196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197                 "Broadcom BCM5752M Gigabit Ethernet" },
198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199                 "Broadcom BCM5753 Gigabit Ethernet" },
200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201                 "Broadcom BCM5753F Gigabit Ethernet" },
202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203                 "Broadcom BCM5753M Gigabit Ethernet" },
204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205                 "Broadcom BCM5754 Gigabit Ethernet" },
206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207                 "Broadcom BCM5754M Gigabit Ethernet" },
208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209                 "Broadcom BCM5755 Gigabit Ethernet" },
210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211                 "Broadcom BCM5755M Gigabit Ethernet" },
212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213                 "Broadcom BCM5756 Gigabit Ethernet" },
214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215                 "Broadcom BCM5761 Gigabit Ethernet" },
216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217                 "Broadcom BCM5761E Gigabit Ethernet" },
218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219                 "Broadcom BCM5761S Gigabit Ethernet" },
220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221                 "Broadcom BCM5761SE Gigabit Ethernet" },
222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223                 "Broadcom BCM5764 Gigabit Ethernet" },
224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225                 "Broadcom BCM5780 Gigabit Ethernet" },
226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227                 "Broadcom BCM5780S Gigabit Ethernet" },
228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229                 "Broadcom BCM5781 Gigabit Ethernet" },
230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
231                 "Broadcom BCM5782 Gigabit Ethernet" },
232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233                 "Broadcom BCM5784 Gigabit Ethernet" },
234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235                 "Broadcom BCM5785F Gigabit Ethernet" },
236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237                 "Broadcom BCM5785G Gigabit Ethernet" },
238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239                 "Broadcom BCM5786 Gigabit Ethernet" },
240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241                 "Broadcom BCM5787 Gigabit Ethernet" },
242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243                 "Broadcom BCM5787F Gigabit Ethernet" },
244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245                 "Broadcom BCM5787M Gigabit Ethernet" },
246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
247                 "Broadcom BCM5788 Gigabit Ethernet" },
248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249                 "Broadcom BCM5789 Gigabit Ethernet" },
250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251                 "Broadcom BCM5901 Fast Ethernet" },
252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253                 "Broadcom BCM5901A2 Fast Ethernet" },
254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255                 "Broadcom BCM5903M Fast Ethernet" },
256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257                 "Broadcom BCM5906 Fast Ethernet"},
258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259                 "Broadcom BCM5906M Fast Ethernet"},
260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261                 "Broadcom BCM57760 Gigabit Ethernet"},
262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263                 "Broadcom BCM57780 Gigabit Ethernet"},
264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265                 "Broadcom BCM57788 Gigabit Ethernet"},
266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267                 "Broadcom BCM57790 Gigabit Ethernet"},
268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
269                 "SysKonnect Gigabit Ethernet" },
270
271         { 0, 0, NULL }
272 };
273
274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
280
281 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
282
283 static int      bge_probe(device_t);
284 static int      bge_attach(device_t);
285 static int      bge_detach(device_t);
286 static void     bge_txeof(struct bge_softc *);
287 static void     bge_rxeof(struct bge_softc *);
288
289 static void     bge_tick(void *);
290 static void     bge_stats_update(struct bge_softc *);
291 static void     bge_stats_update_regs(struct bge_softc *);
292 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
293
294 #ifdef DEVICE_POLLING
295 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
296 #endif
297 static void     bge_intr(void *);
298 static void     bge_enable_intr(struct bge_softc *);
299 static void     bge_disable_intr(struct bge_softc *);
300 static void     bge_start(struct ifnet *);
301 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
302 static void     bge_init(void *);
303 static void     bge_stop(struct bge_softc *);
304 static void     bge_watchdog(struct ifnet *);
305 static void     bge_shutdown(device_t);
306 static int      bge_suspend(device_t);
307 static int      bge_resume(device_t);
308 static int      bge_ifmedia_upd(struct ifnet *);
309 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
310
311 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
312 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
313
314 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
315 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
316
317 static void     bge_setmulti(struct bge_softc *);
318 static void     bge_setpromisc(struct bge_softc *);
319
320 static int      bge_alloc_jumbo_mem(struct bge_softc *);
321 static void     bge_free_jumbo_mem(struct bge_softc *);
322 static struct bge_jslot
323                 *bge_jalloc(struct bge_softc *);
324 static void     bge_jfree(void *);
325 static void     bge_jref(void *);
326 static int      bge_newbuf_std(struct bge_softc *, int, int);
327 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
328 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
329 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
330 static int      bge_init_rx_ring_std(struct bge_softc *);
331 static void     bge_free_rx_ring_std(struct bge_softc *);
332 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
333 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
334 static void     bge_free_tx_ring(struct bge_softc *);
335 static int      bge_init_tx_ring(struct bge_softc *);
336
337 static int      bge_chipinit(struct bge_softc *);
338 static int      bge_blockinit(struct bge_softc *);
339
340 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
341 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
342 #ifdef notdef
343 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
344 #endif
345 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
346 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
347 static void     bge_writembx(struct bge_softc *, int, int);
348
349 static int      bge_miibus_readreg(device_t, int, int);
350 static int      bge_miibus_writereg(device_t, int, int, int);
351 static void     bge_miibus_statchg(device_t);
352 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
353 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
354 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
355
356 static void     bge_reset(struct bge_softc *);
357
358 static int      bge_dma_alloc(struct bge_softc *);
359 static void     bge_dma_free(struct bge_softc *);
360 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
361                                     bus_dma_tag_t *, bus_dmamap_t *,
362                                     void **, bus_addr_t *);
363 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
364
365 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
366 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
367 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
368 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
369
370 static void     bge_coal_change(struct bge_softc *);
371 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
372 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
373 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
374 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
375 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
376
377 /*
378  * Set following tunable to 1 for some IBM blade servers with the DNLK
379  * switch module. Auto negotiation is broken for those configurations.
380  */
381 static int      bge_fake_autoneg = 0;
382 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
383
384 /* Interrupt moderation control variables. */
385 static int      bge_rx_coal_ticks = 100;        /* usec */
386 static int      bge_tx_coal_ticks = 1023;       /* usec */
387 static int      bge_rx_max_coal_bds = 80;
388 static int      bge_tx_max_coal_bds = 128;
389
390 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
391 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
392 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
393 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
394
395 #if !defined(KTR_IF_BGE)
396 #define KTR_IF_BGE      KTR_ALL
397 #endif
398 KTR_INFO_MASTER(if_bge);
399 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
400 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
401 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
402 #define logif(name)     KTR_LOG(if_bge_ ## name)
403
404 static device_method_t bge_methods[] = {
405         /* Device interface */
406         DEVMETHOD(device_probe,         bge_probe),
407         DEVMETHOD(device_attach,        bge_attach),
408         DEVMETHOD(device_detach,        bge_detach),
409         DEVMETHOD(device_shutdown,      bge_shutdown),
410         DEVMETHOD(device_suspend,       bge_suspend),
411         DEVMETHOD(device_resume,        bge_resume),
412
413         /* bus interface */
414         DEVMETHOD(bus_print_child,      bus_generic_print_child),
415         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
416
417         /* MII interface */
418         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
419         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
420         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
421
422         { 0, 0 }
423 };
424
425 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
426 static devclass_t bge_devclass;
427
428 DECLARE_DUMMY_MODULE(if_bge);
429 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
430 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
431
432 static uint32_t
433 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
434 {
435         device_t dev = sc->bge_dev;
436         uint32_t val;
437
438         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
439         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
440         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
441         return (val);
442 }
443
444 static void
445 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
446 {
447         device_t dev = sc->bge_dev;
448
449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
450         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
451         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
452 }
453
454 #ifdef notdef
455 static uint32_t
456 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
457 {
458         device_t dev = sc->bge_dev;
459
460         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
461         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
462 }
463 #endif
464
465 static void
466 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
467 {
468         device_t dev = sc->bge_dev;
469
470         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
471         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
472 }
473
474 static void
475 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
476 {
477         CSR_WRITE_4(sc, off, val);
478 }
479
480 static void
481 bge_writembx(struct bge_softc *sc, int off, int val)
482 {
483         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
484                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
485
486         CSR_WRITE_4(sc, off, val);
487 }
488
489 static uint8_t
490 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
491 {
492         uint32_t access, byte = 0;
493         int i;
494
495         /* Lock. */
496         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
497         for (i = 0; i < 8000; i++) {
498                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
499                         break;
500                 DELAY(20);
501         }
502         if (i == 8000)
503                 return (1);
504
505         /* Enable access. */
506         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
508
509         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
510         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
511         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
512                 DELAY(10);
513                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
514                         DELAY(10);
515                         break;
516                 }
517         }
518
519         if (i == BGE_TIMEOUT * 10) {
520                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
521                 return (1);
522         }
523
524         /* Get result. */
525         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
526
527         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
528
529         /* Disable access. */
530         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
531
532         /* Unlock. */
533         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
534         CSR_READ_4(sc, BGE_NVRAM_SWARB);
535
536         return (0);
537 }
538
539 /*
540  * Read a sequence of bytes from NVRAM.
541  */
542 static int
543 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
544 {
545         int err = 0, i;
546         uint8_t byte = 0;
547
548         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
549                 return (1);
550
551         for (i = 0; i < cnt; i++) {
552                 err = bge_nvram_getbyte(sc, off + i, &byte);
553                 if (err)
554                         break;
555                 *(dest + i) = byte;
556         }
557
558         return (err ? 1 : 0);
559 }
560
561 /*
562  * Read a byte of data stored in the EEPROM at address 'addr.' The
563  * BCM570x supports both the traditional bitbang interface and an
564  * auto access interface for reading the EEPROM. We use the auto
565  * access method.
566  */
567 static uint8_t
568 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
569 {
570         int i;
571         uint32_t byte = 0;
572
573         /*
574          * Enable use of auto EEPROM access so we can avoid
575          * having to use the bitbang method.
576          */
577         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
578
579         /* Reset the EEPROM, load the clock period. */
580         CSR_WRITE_4(sc, BGE_EE_ADDR,
581             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
582         DELAY(20);
583
584         /* Issue the read EEPROM command. */
585         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
586
587         /* Wait for completion */
588         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
589                 DELAY(10);
590                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
591                         break;
592         }
593
594         if (i == BGE_TIMEOUT) {
595                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
596                 return(1);
597         }
598
599         /* Get result. */
600         byte = CSR_READ_4(sc, BGE_EE_DATA);
601
602         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
603
604         return(0);
605 }
606
607 /*
608  * Read a sequence of bytes from the EEPROM.
609  */
610 static int
611 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
612 {
613         size_t i;
614         int err;
615         uint8_t byte;
616
617         for (byte = 0, err = 0, i = 0; i < len; i++) {
618                 err = bge_eeprom_getbyte(sc, off + i, &byte);
619                 if (err)
620                         break;
621                 *(dest + i) = byte;
622         }
623
624         return(err ? 1 : 0);
625 }
626
627 static int
628 bge_miibus_readreg(device_t dev, int phy, int reg)
629 {
630         struct bge_softc *sc = device_get_softc(dev);
631         struct ifnet *ifp = &sc->arpcom.ac_if;
632         uint32_t val, autopoll;
633         int i;
634
635         /*
636          * Broadcom's own driver always assumes the internal
637          * PHY is at GMII address 1. On some chips, the PHY responds
638          * to accesses at all addresses, which could cause us to
639          * bogusly attach the PHY 32 times at probe type. Always
640          * restricting the lookup to address 1 is simpler than
641          * trying to figure out which chips revisions should be
642          * special-cased.
643          */
644         if (phy != 1)
645                 return(0);
646
647         /* Reading with autopolling on may trigger PCI errors */
648         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
649         if (autopoll & BGE_MIMODE_AUTOPOLL) {
650                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
651                 DELAY(40);
652         }
653
654         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
655             BGE_MIPHY(phy)|BGE_MIREG(reg));
656
657         for (i = 0; i < BGE_TIMEOUT; i++) {
658                 DELAY(10);
659                 val = CSR_READ_4(sc, BGE_MI_COMM);
660                 if (!(val & BGE_MICOMM_BUSY))
661                         break;
662         }
663
664         if (i == BGE_TIMEOUT) {
665                 if_printf(ifp, "PHY read timed out "
666                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
667                 val = 0;
668                 goto done;
669         }
670
671         DELAY(5);
672         val = CSR_READ_4(sc, BGE_MI_COMM);
673
674 done:
675         if (autopoll & BGE_MIMODE_AUTOPOLL) {
676                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
677                 DELAY(40);
678         }
679
680         if (val & BGE_MICOMM_READFAIL)
681                 return(0);
682
683         return(val & 0xFFFF);
684 }
685
686 static int
687 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
688 {
689         struct bge_softc *sc = device_get_softc(dev);
690         uint32_t autopoll;
691         int i;
692
693         /*
694          * See the related comment in bge_miibus_readreg()
695          */
696         if (phy != 1)
697                 return(0);
698
699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
701                return(0);
702
703         /* Reading with autopolling on may trigger PCI errors */
704         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
705         if (autopoll & BGE_MIMODE_AUTOPOLL) {
706                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
707                 DELAY(40);
708         }
709
710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
711             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
712
713         for (i = 0; i < BGE_TIMEOUT; i++) {
714                 DELAY(10);
715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
716                         DELAY(5);
717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
718                         break;
719                 }
720         }
721
722         if (autopoll & BGE_MIMODE_AUTOPOLL) {
723                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
724                 DELAY(40);
725         }
726
727         if (i == BGE_TIMEOUT) {
728                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
729                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
730                 return(0);
731         }
732
733         return(0);
734 }
735
736 static void
737 bge_miibus_statchg(device_t dev)
738 {
739         struct bge_softc *sc;
740         struct mii_data *mii;
741
742         sc = device_get_softc(dev);
743         mii = device_get_softc(sc->bge_miibus);
744
745         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
746         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
747                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
748         } else {
749                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
750         }
751
752         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
753                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
754         } else {
755                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
756         }
757 }
758
759 /*
760  * Memory management for jumbo frames.
761  */
762 static int
763 bge_alloc_jumbo_mem(struct bge_softc *sc)
764 {
765         struct ifnet *ifp = &sc->arpcom.ac_if;
766         struct bge_jslot *entry;
767         uint8_t *ptr;
768         bus_addr_t paddr;
769         int i, error;
770
771         /*
772          * Create tag for jumbo mbufs.
773          * This is really a bit of a kludge. We allocate a special
774          * jumbo buffer pool which (thanks to the way our DMA
775          * memory allocation works) will consist of contiguous
776          * pages. This means that even though a jumbo buffer might
777          * be larger than a page size, we don't really need to
778          * map it into more than one DMA segment. However, the
779          * default mbuf tag will result in multi-segment mappings,
780          * so we have to create a special jumbo mbuf tag that
781          * lets us get away with mapping the jumbo buffers as
782          * a single segment. I think eventually the driver should
783          * be changed so that it uses ordinary mbufs and cluster
784          * buffers, i.e. jumbo frames can span multiple DMA
785          * descriptors. But that's a project for another day.
786          */
787
788         /*
789          * Create DMA stuffs for jumbo RX ring.
790          */
791         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
792                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
793                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
794                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
795                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
796         if (error) {
797                 if_printf(ifp, "could not create jumbo RX ring\n");
798                 return error;
799         }
800
801         /*
802          * Create DMA stuffs for jumbo buffer block.
803          */
804         error = bge_dma_block_alloc(sc, BGE_JMEM,
805                                     &sc->bge_cdata.bge_jumbo_tag,
806                                     &sc->bge_cdata.bge_jumbo_map,
807                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
808                                     &paddr);
809         if (error) {
810                 if_printf(ifp, "could not create jumbo buffer\n");
811                 return error;
812         }
813
814         SLIST_INIT(&sc->bge_jfree_listhead);
815
816         /*
817          * Now divide it up into 9K pieces and save the addresses
818          * in an array. Note that we play an evil trick here by using
819          * the first few bytes in the buffer to hold the the address
820          * of the softc structure for this interface. This is because
821          * bge_jfree() needs it, but it is called by the mbuf management
822          * code which will not pass it to us explicitly.
823          */
824         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
825                 entry = &sc->bge_cdata.bge_jslots[i];
826                 entry->bge_sc = sc;
827                 entry->bge_buf = ptr;
828                 entry->bge_paddr = paddr;
829                 entry->bge_inuse = 0;
830                 entry->bge_slot = i;
831                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
832
833                 ptr += BGE_JLEN;
834                 paddr += BGE_JLEN;
835         }
836         return 0;
837 }
838
839 static void
840 bge_free_jumbo_mem(struct bge_softc *sc)
841 {
842         /* Destroy jumbo RX ring. */
843         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
844                            sc->bge_cdata.bge_rx_jumbo_ring_map,
845                            sc->bge_ldata.bge_rx_jumbo_ring);
846
847         /* Destroy jumbo buffer block. */
848         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
849                            sc->bge_cdata.bge_jumbo_map,
850                            sc->bge_ldata.bge_jumbo_buf);
851 }
852
853 /*
854  * Allocate a jumbo buffer.
855  */
856 static struct bge_jslot *
857 bge_jalloc(struct bge_softc *sc)
858 {
859         struct bge_jslot *entry;
860
861         lwkt_serialize_enter(&sc->bge_jslot_serializer);
862         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
863         if (entry) {
864                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
865                 entry->bge_inuse = 1;
866         } else {
867                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
868         }
869         lwkt_serialize_exit(&sc->bge_jslot_serializer);
870         return(entry);
871 }
872
873 /*
874  * Adjust usage count on a jumbo buffer.
875  */
876 static void
877 bge_jref(void *arg)
878 {
879         struct bge_jslot *entry = (struct bge_jslot *)arg;
880         struct bge_softc *sc = entry->bge_sc;
881
882         if (sc == NULL)
883                 panic("bge_jref: can't find softc pointer!");
884
885         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
886                 panic("bge_jref: asked to reference buffer "
887                     "that we don't manage!");
888         } else if (entry->bge_inuse == 0) {
889                 panic("bge_jref: buffer already free!");
890         } else {
891                 atomic_add_int(&entry->bge_inuse, 1);
892         }
893 }
894
895 /*
896  * Release a jumbo buffer.
897  */
898 static void
899 bge_jfree(void *arg)
900 {
901         struct bge_jslot *entry = (struct bge_jslot *)arg;
902         struct bge_softc *sc = entry->bge_sc;
903
904         if (sc == NULL)
905                 panic("bge_jfree: can't find softc pointer!");
906
907         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
908                 panic("bge_jfree: asked to free buffer that we don't manage!");
909         } else if (entry->bge_inuse == 0) {
910                 panic("bge_jfree: buffer already free!");
911         } else {
912                 /*
913                  * Possible MP race to 0, use the serializer.  The atomic insn
914                  * is still needed for races against bge_jref().
915                  */
916                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
917                 atomic_subtract_int(&entry->bge_inuse, 1);
918                 if (entry->bge_inuse == 0) {
919                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
920                                           entry, jslot_link);
921                 }
922                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
923         }
924 }
925
926
927 /*
928  * Intialize a standard receive ring descriptor.
929  */
930 static int
931 bge_newbuf_std(struct bge_softc *sc, int i, int init)
932 {
933         struct mbuf *m_new = NULL;
934         bus_dma_segment_t seg;
935         bus_dmamap_t map;
936         int error, nsegs;
937
938         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
939         if (m_new == NULL)
940                 return ENOBUFS;
941         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
942
943         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
944                 m_adj(m_new, ETHER_ALIGN);
945
946         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
947                         sc->bge_cdata.bge_rx_tmpmap, m_new,
948                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
949         if (error) {
950                 m_freem(m_new);
951                 return error;
952         }
953
954         if (!init) {
955                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
956                                 sc->bge_cdata.bge_rx_std_dmamap[i],
957                                 BUS_DMASYNC_POSTREAD);
958                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
959                         sc->bge_cdata.bge_rx_std_dmamap[i]);
960         }
961
962         map = sc->bge_cdata.bge_rx_tmpmap;
963         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
964         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
965
966         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
967         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
968
969         bge_setup_rxdesc_std(sc, i);
970         return 0;
971 }
972
973 static void
974 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
975 {
976         struct bge_rxchain *rc;
977         struct bge_rx_bd *r;
978
979         rc = &sc->bge_cdata.bge_rx_std_chain[i];
980         r = &sc->bge_ldata.bge_rx_std_ring[i];
981
982         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
983         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
984         r->bge_len = rc->bge_mbuf->m_len;
985         r->bge_idx = i;
986         r->bge_flags = BGE_RXBDFLAG_END;
987 }
988
989 /*
990  * Initialize a jumbo receive ring descriptor. This allocates
991  * a jumbo buffer from the pool managed internally by the driver.
992  */
993 static int
994 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
995 {
996         struct mbuf *m_new = NULL;
997         struct bge_jslot *buf;
998         bus_addr_t paddr;
999
1000         /* Allocate the mbuf. */
1001         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1002         if (m_new == NULL)
1003                 return ENOBUFS;
1004
1005         /* Allocate the jumbo buffer */
1006         buf = bge_jalloc(sc);
1007         if (buf == NULL) {
1008                 m_freem(m_new);
1009                 return ENOBUFS;
1010         }
1011
1012         /* Attach the buffer to the mbuf. */
1013         m_new->m_ext.ext_arg = buf;
1014         m_new->m_ext.ext_buf = buf->bge_buf;
1015         m_new->m_ext.ext_free = bge_jfree;
1016         m_new->m_ext.ext_ref = bge_jref;
1017         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1018
1019         m_new->m_flags |= M_EXT;
1020
1021         m_new->m_data = m_new->m_ext.ext_buf;
1022         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1023
1024         paddr = buf->bge_paddr;
1025         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1026                 m_adj(m_new, ETHER_ALIGN);
1027                 paddr += ETHER_ALIGN;
1028         }
1029
1030         /* Save necessary information */
1031         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1032         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1033
1034         /* Set up the descriptor. */
1035         bge_setup_rxdesc_jumbo(sc, i);
1036         return 0;
1037 }
1038
1039 static void
1040 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1041 {
1042         struct bge_rx_bd *r;
1043         struct bge_rxchain *rc;
1044
1045         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1046         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1047
1048         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1049         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1050         r->bge_len = rc->bge_mbuf->m_len;
1051         r->bge_idx = i;
1052         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1053 }
1054
1055 static int
1056 bge_init_rx_ring_std(struct bge_softc *sc)
1057 {
1058         int i, error;
1059
1060         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1061                 error = bge_newbuf_std(sc, i, 1);
1062                 if (error)
1063                         return error;
1064         };
1065
1066         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return(0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1079
1080                 if (rc->bge_mbuf != NULL) {
1081                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1082                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1083                         m_freem(rc->bge_mbuf);
1084                         rc->bge_mbuf = NULL;
1085                 }
1086                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1087                     sizeof(struct bge_rx_bd));
1088         }
1089 }
1090
1091 static int
1092 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1093 {
1094         struct bge_rcb *rcb;
1095         int i, error;
1096
1097         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1098                 error = bge_newbuf_jumbo(sc, i, 1);
1099                 if (error)
1100                         return error;
1101         };
1102
1103         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1104
1105         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1106         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1107         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1108
1109         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1110
1111         return(0);
1112 }
1113
1114 static void
1115 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1116 {
1117         int i;
1118
1119         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1120                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1121
1122                 if (rc->bge_mbuf != NULL) {
1123                         m_freem(rc->bge_mbuf);
1124                         rc->bge_mbuf = NULL;
1125                 }
1126                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1127                     sizeof(struct bge_rx_bd));
1128         }
1129 }
1130
1131 static void
1132 bge_free_tx_ring(struct bge_softc *sc)
1133 {
1134         int i;
1135
1136         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1137                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1138                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1139                                           sc->bge_cdata.bge_tx_dmamap[i]);
1140                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1141                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1142                 }
1143                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1144                     sizeof(struct bge_tx_bd));
1145         }
1146 }
1147
1148 static int
1149 bge_init_tx_ring(struct bge_softc *sc)
1150 {
1151         sc->bge_txcnt = 0;
1152         sc->bge_tx_saved_considx = 0;
1153         sc->bge_tx_prodidx = 0;
1154
1155         /* Initialize transmit producer index for host-memory send ring. */
1156         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1157
1158         /* 5700 b2 errata */
1159         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1160                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1161
1162         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1163         /* 5700 b2 errata */
1164         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1165                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1166
1167         return(0);
1168 }
1169
1170 static void
1171 bge_setmulti(struct bge_softc *sc)
1172 {
1173         struct ifnet *ifp;
1174         struct ifmultiaddr *ifma;
1175         uint32_t hashes[4] = { 0, 0, 0, 0 };
1176         int h, i;
1177
1178         ifp = &sc->arpcom.ac_if;
1179
1180         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1181                 for (i = 0; i < 4; i++)
1182                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1183                 return;
1184         }
1185
1186         /* First, zot all the existing filters. */
1187         for (i = 0; i < 4; i++)
1188                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1189
1190         /* Now program new ones. */
1191         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1192                 if (ifma->ifma_addr->sa_family != AF_LINK)
1193                         continue;
1194                 h = ether_crc32_le(
1195                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1196                     ETHER_ADDR_LEN) & 0x7f;
1197                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1198         }
1199
1200         for (i = 0; i < 4; i++)
1201                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1202 }
1203
1204 /*
1205  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1206  * self-test results.
1207  */
1208 static int
1209 bge_chipinit(struct bge_softc *sc)
1210 {
1211         int i;
1212         uint32_t dma_rw_ctl;
1213         uint16_t val;
1214
1215         /* Set endian type before we access any non-PCI registers. */
1216         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1217
1218         /* Clear the MAC control register */
1219         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1220
1221         /*
1222          * Clear the MAC statistics block in the NIC's
1223          * internal memory.
1224          */
1225         for (i = BGE_STATS_BLOCK;
1226             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1227                 BGE_MEMWIN_WRITE(sc, i, 0);
1228
1229         for (i = BGE_STATUS_BLOCK;
1230             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1231                 BGE_MEMWIN_WRITE(sc, i, 0);
1232
1233         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1234                 /*
1235                  * Fix data corruption caused by non-qword write with WB.
1236                  * Fix master abort in PCI mode.
1237                  * Fix PCI latency timer.
1238                  */
1239                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1240                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1241                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1242         }
1243
1244         /* Set up the PCI DMA control register. */
1245         if (sc->bge_flags & BGE_FLAG_PCIE) {
1246                 /* PCI Express */
1247                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1248                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1249                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1250         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1251                 /* PCI-X bus */
1252                 if (BGE_IS_5714_FAMILY(sc)) {
1253                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1254                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1255                         /* XXX magic values, Broadcom-supplied Linux driver */
1256                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1257                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | 
1258                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1259                         } else {
1260                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1261                         }
1262                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1263                         /*
1264                          * In the BCM5703, the DMA read watermark should
1265                          * be set to less than or equal to the maximum
1266                          * memory read byte count of the PCI-X command
1267                          * register.
1268                          */
1269                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1270                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1271                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1272                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1273                         /*
1274                          * The 5704 uses a different encoding of read/write
1275                          * watermarks.
1276                          */
1277                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1278                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1279                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1280                 } else {
1281                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1282                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1283                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1284                             (0x0F);
1285                 }
1286
1287                 /*
1288                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1289                  * for hardware bugs.
1290                  */
1291                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1292                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1293                         uint32_t tmp;
1294
1295                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1296                         if (tmp == 0x6 || tmp == 0x7)
1297                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1298                 }
1299         } else {
1300                 /* Conventional PCI bus */
1301                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1302                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1303                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1304                     (0x0F);
1305         }
1306
1307         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1308             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1309             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1310                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1311         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1312
1313         /*
1314          * Set up general mode register.
1315          */
1316         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1317             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1318             BGE_MODECTL_TX_NO_PHDR_CSUM);
1319
1320         /*
1321          * BCM5701 B5 have a bug causing data corruption when using
1322          * 64-bit DMA reads, which can be terminated early and then
1323          * completed later as 32-bit accesses, in combination with
1324          * certain bridges.
1325          */
1326         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1327             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1328                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1329
1330         /*
1331          * Disable memory write invalidate.  Apparently it is not supported
1332          * properly by these devices.
1333          */
1334         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1335
1336         /* Set the timer prescaler (always 66Mhz) */
1337         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1338
1339         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1340                 DELAY(40);      /* XXX */
1341
1342                 /* Put PHY into ready state */
1343                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1344                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1345                 DELAY(40);
1346         }
1347
1348         return(0);
1349 }
1350
1351 static int
1352 bge_blockinit(struct bge_softc *sc)
1353 {
1354         struct bge_rcb *rcb;
1355         bus_size_t vrcb;
1356         bge_hostaddr taddr;
1357         uint32_t val;
1358         int i;
1359
1360         /*
1361          * Initialize the memory window pointer register so that
1362          * we can access the first 32K of internal NIC RAM. This will
1363          * allow us to set up the TX send ring RCBs and the RX return
1364          * ring RCBs, plus other things which live in NIC memory.
1365          */
1366         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1367
1368         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1369
1370         if (!BGE_IS_5705_PLUS(sc)) {
1371                 /* Configure mbuf memory pool */
1372                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1373                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1374                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1375                 else
1376                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1377
1378                 /* Configure DMA resource pool */
1379                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1380                     BGE_DMA_DESCRIPTORS);
1381                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1382         }
1383
1384         /* Configure mbuf pool watermarks */
1385         if (!BGE_IS_5705_PLUS(sc)) {
1386                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1387                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1388                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1389         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1390                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1391                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1392                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1393         } else {
1394                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1395                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1396                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1397         }
1398
1399         /* Configure DMA resource watermarks */
1400         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1401         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1402
1403         /* Enable buffer manager */
1404         if (!BGE_IS_5705_PLUS(sc)) {
1405                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1406                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1407
1408                 /* Poll for buffer manager start indication */
1409                 for (i = 0; i < BGE_TIMEOUT; i++) {
1410                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1411                                 break;
1412                         DELAY(10);
1413                 }
1414
1415                 if (i == BGE_TIMEOUT) {
1416                         if_printf(&sc->arpcom.ac_if,
1417                                   "buffer manager failed to start\n");
1418                         return(ENXIO);
1419                 }
1420         }
1421
1422         /* Enable flow-through queues */
1423         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1424         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1425
1426         /* Wait until queue initialization is complete */
1427         for (i = 0; i < BGE_TIMEOUT; i++) {
1428                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1429                         break;
1430                 DELAY(10);
1431         }
1432
1433         if (i == BGE_TIMEOUT) {
1434                 if_printf(&sc->arpcom.ac_if,
1435                           "flow-through queue init failed\n");
1436                 return(ENXIO);
1437         }
1438
1439         /* Initialize the standard RX ring control block */
1440         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1441         rcb->bge_hostaddr.bge_addr_lo =
1442             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1443         rcb->bge_hostaddr.bge_addr_hi =
1444             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1445         if (BGE_IS_5705_PLUS(sc))
1446                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1447         else
1448                 rcb->bge_maxlen_flags =
1449                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1450         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1451         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1452         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1453         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1454         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1455
1456         /*
1457          * Initialize the jumbo RX ring control block
1458          * We set the 'ring disabled' bit in the flags
1459          * field until we're actually ready to start
1460          * using this ring (i.e. once we set the MTU
1461          * high enough to require it).
1462          */
1463         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1464                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1465
1466                 rcb->bge_hostaddr.bge_addr_lo =
1467                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1468                 rcb->bge_hostaddr.bge_addr_hi =
1469                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1470                 rcb->bge_maxlen_flags =
1471                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1472                     BGE_RCB_FLAG_RING_DISABLED);
1473                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1474                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1475                     rcb->bge_hostaddr.bge_addr_hi);
1476                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1477                     rcb->bge_hostaddr.bge_addr_lo);
1478                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1479                     rcb->bge_maxlen_flags);
1480                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1481
1482                 /* Set up dummy disabled mini ring RCB */
1483                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1484                 rcb->bge_maxlen_flags =
1485                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1486                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1487                     rcb->bge_maxlen_flags);
1488         }
1489
1490         /*
1491          * Set the BD ring replentish thresholds. The recommended
1492          * values are 1/8th the number of descriptors allocated to
1493          * each ring.
1494          */
1495         if (BGE_IS_5705_PLUS(sc))
1496                 val = 8;
1497         else
1498                 val = BGE_STD_RX_RING_CNT / 8;
1499         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1500         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1501
1502         /*
1503          * Disable all unused send rings by setting the 'ring disabled'
1504          * bit in the flags field of all the TX send ring control blocks.
1505          * These are located in NIC memory.
1506          */
1507         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1508         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1509                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1510                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1511                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1512                 vrcb += sizeof(struct bge_rcb);
1513         }
1514
1515         /* Configure TX RCB 0 (we use only the first ring) */
1516         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1517         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1518         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1519         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1520         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1521             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1522         if (!BGE_IS_5705_PLUS(sc)) {
1523                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1524                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1525         }
1526
1527         /* Disable all unused RX return rings */
1528         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1529         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1530                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1531                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1532                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1533                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1534                     BGE_RCB_FLAG_RING_DISABLED));
1535                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1536                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1537                     (i * (sizeof(uint64_t))), 0);
1538                 vrcb += sizeof(struct bge_rcb);
1539         }
1540
1541         /* Initialize RX ring indexes */
1542         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1543         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1544         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1545
1546         /*
1547          * Set up RX return ring 0
1548          * Note that the NIC address for RX return rings is 0x00000000.
1549          * The return rings live entirely within the host, so the
1550          * nicaddr field in the RCB isn't used.
1551          */
1552         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1553         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1554         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1555         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1556         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1557         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1558             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1559
1560         /* Set random backoff seed for TX */
1561         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1562             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1563             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1564             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1565             BGE_TX_BACKOFF_SEED_MASK);
1566
1567         /* Set inter-packet gap */
1568         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1569
1570         /*
1571          * Specify which ring to use for packets that don't match
1572          * any RX rules.
1573          */
1574         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1575
1576         /*
1577          * Configure number of RX lists. One interrupt distribution
1578          * list, sixteen active lists, one bad frames class.
1579          */
1580         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1581
1582         /* Inialize RX list placement stats mask. */
1583         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1584         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1585
1586         /* Disable host coalescing until we get it set up */
1587         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1588
1589         /* Poll to make sure it's shut down. */
1590         for (i = 0; i < BGE_TIMEOUT; i++) {
1591                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1592                         break;
1593                 DELAY(10);
1594         }
1595
1596         if (i == BGE_TIMEOUT) {
1597                 if_printf(&sc->arpcom.ac_if,
1598                           "host coalescing engine failed to idle\n");
1599                 return(ENXIO);
1600         }
1601
1602         /* Set up host coalescing defaults */
1603         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1604         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1605         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1606         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1607         if (!BGE_IS_5705_PLUS(sc)) {
1608                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1609                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1610         }
1611         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1612         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1613
1614         /* Set up address of statistics block */
1615         if (!BGE_IS_5705_PLUS(sc)) {
1616                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1617                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1618                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1619                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1620
1621                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1622                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1623                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1624         }
1625
1626         /* Set up address of status block */
1627         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1628             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1629         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1630             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1631         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1632         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1633
1634         /*
1635          * Set up status block partail update size.
1636          *
1637          * Because only single TX ring, RX produce ring and Rx return ring
1638          * are used, ask device to update only minimum part of status block
1639          * except for BCM5700 AX/BX, whose status block partial update size
1640          * can't be configured.
1641          */
1642         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1643             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1644                 /* XXX Actually reserved on BCM5700 AX/BX */
1645                 val = BGE_STATBLKSZ_FULL;
1646         } else {
1647                 val = BGE_STATBLKSZ_32BYTE;
1648         }
1649
1650         /* Turn on host coalescing state machine */
1651         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1652
1653         /* Turn on RX BD completion state machine and enable attentions */
1654         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1655             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1656
1657         /* Turn on RX list placement state machine */
1658         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1659
1660         /* Turn on RX list selector state machine. */
1661         if (!BGE_IS_5705_PLUS(sc))
1662                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1663
1664         /* Turn on DMA, clear stats */
1665         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1666             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1667             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1668             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1669             ((sc->bge_flags & BGE_FLAG_TBI) ?
1670              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1671
1672         /* Set misc. local control, enable interrupts on attentions */
1673         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1674
1675 #ifdef notdef
1676         /* Assert GPIO pins for PHY reset */
1677         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1678             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1679         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1680             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1681 #endif
1682
1683         /* Turn on DMA completion state machine */
1684         if (!BGE_IS_5705_PLUS(sc))
1685                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1686
1687         /* Turn on write DMA state machine */
1688         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1689         if (BGE_IS_5755_PLUS(sc)) {
1690                 /* Enable host coalescing bug fix. */
1691                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1692         }
1693         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1694         DELAY(40);
1695
1696         /* Turn on read DMA state machine */
1697         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1698         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1699             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1700             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1701                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1702                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1703                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1704         if (sc->bge_flags & BGE_FLAG_PCIE)
1705                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1706         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1707         DELAY(40);
1708
1709         /* Turn on RX data completion state machine */
1710         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1711
1712         /* Turn on RX BD initiator state machine */
1713         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1714
1715         /* Turn on RX data and RX BD initiator state machine */
1716         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1717
1718         /* Turn on Mbuf cluster free state machine */
1719         if (!BGE_IS_5705_PLUS(sc))
1720                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1721
1722         /* Turn on send BD completion state machine */
1723         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1724
1725         /* Turn on send data completion state machine */
1726         val = BGE_SDCMODE_ENABLE;
1727         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1728                 val |= BGE_SDCMODE_CDELAY; 
1729         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1730
1731         /* Turn on send data initiator state machine */
1732         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1733
1734         /* Turn on send BD initiator state machine */
1735         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1736
1737         /* Turn on send BD selector state machine */
1738         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1739
1740         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1741         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1742             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1743
1744         /* ack/clear link change events */
1745         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1746             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1747             BGE_MACSTAT_LINK_CHANGED);
1748         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1749
1750         /* Enable PHY auto polling (for MII/GMII only) */
1751         if (sc->bge_flags & BGE_FLAG_TBI) {
1752                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1753         } else {
1754                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1755                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1756                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1757                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1758                             BGE_EVTENB_MI_INTERRUPT);
1759                 }
1760         }
1761
1762         /*
1763          * Clear any pending link state attention.
1764          * Otherwise some link state change events may be lost until attention
1765          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1766          * It's not necessary on newer BCM chips - perhaps enabling link
1767          * state change attentions implies clearing pending attention.
1768          */
1769         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1770             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1771             BGE_MACSTAT_LINK_CHANGED);
1772
1773         /* Enable link state change attentions. */
1774         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1775
1776         return(0);
1777 }
1778
1779 /*
1780  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1781  * against our list and return its name if we find a match. Note
1782  * that since the Broadcom controller contains VPD support, we
1783  * can get the device name string from the controller itself instead
1784  * of the compiled-in string. This is a little slow, but it guarantees
1785  * we'll always announce the right product name.
1786  */
1787 static int
1788 bge_probe(device_t dev)
1789 {
1790         const struct bge_type *t;
1791         uint16_t product, vendor;
1792
1793         product = pci_get_device(dev);
1794         vendor = pci_get_vendor(dev);
1795
1796         for (t = bge_devs; t->bge_name != NULL; t++) {
1797                 if (vendor == t->bge_vid && product == t->bge_did)
1798                         break;
1799         }
1800         if (t->bge_name == NULL)
1801                 return(ENXIO);
1802
1803         device_set_desc(dev, t->bge_name);
1804         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1805                 struct bge_softc *sc = device_get_softc(dev);
1806                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1807         }
1808         return(0);
1809 }
1810
1811 static int
1812 bge_attach(device_t dev)
1813 {
1814         struct ifnet *ifp;
1815         struct bge_softc *sc;
1816         uint32_t hwcfg = 0;
1817         int error = 0, rid;
1818         uint8_t ether_addr[ETHER_ADDR_LEN];
1819
1820         sc = device_get_softc(dev);
1821         sc->bge_dev = dev;
1822         callout_init(&sc->bge_stat_timer);
1823         lwkt_serialize_init(&sc->bge_jslot_serializer);
1824
1825 #ifndef BURN_BRIDGES
1826         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1827                 uint32_t irq, mem;
1828
1829                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1830                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1831
1832                 device_printf(dev, "chip is in D%d power mode "
1833                     "-- setting to D0\n", pci_get_powerstate(dev));
1834
1835                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1836
1837                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1838                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1839         }
1840 #endif  /* !BURN_BRIDGE */
1841
1842         /*
1843          * Map control/status registers.
1844          */
1845         pci_enable_busmaster(dev);
1846
1847         rid = BGE_PCI_BAR0;
1848         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1849             RF_ACTIVE);
1850
1851         if (sc->bge_res == NULL) {
1852                 device_printf(dev, "couldn't map memory\n");
1853                 return ENXIO;
1854         }
1855
1856         sc->bge_btag = rman_get_bustag(sc->bge_res);
1857         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1858
1859         /* Save various chip information */
1860         sc->bge_chipid =
1861             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1862             BGE_PCIMISCCTL_ASICREV_SHIFT;
1863         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1864                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1865         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1866         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1867
1868         /* Save chipset family. */
1869         switch (sc->bge_asicrev) {
1870         case BGE_ASICREV_BCM5755:
1871         case BGE_ASICREV_BCM5761:
1872         case BGE_ASICREV_BCM5784:
1873         case BGE_ASICREV_BCM5785:
1874         case BGE_ASICREV_BCM5787:
1875         case BGE_ASICREV_BCM57780:
1876             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1877                 BGE_FLAG_5705_PLUS;
1878             break;
1879
1880         case BGE_ASICREV_BCM5700:
1881         case BGE_ASICREV_BCM5701:
1882         case BGE_ASICREV_BCM5703:
1883         case BGE_ASICREV_BCM5704:
1884                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1885                 break;
1886
1887         case BGE_ASICREV_BCM5714_A0:
1888         case BGE_ASICREV_BCM5780:
1889         case BGE_ASICREV_BCM5714:
1890                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1891                 /* Fall through */
1892
1893         case BGE_ASICREV_BCM5750:
1894         case BGE_ASICREV_BCM5752:
1895         case BGE_ASICREV_BCM5906:
1896                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1897                 /* Fall through */
1898
1899         case BGE_ASICREV_BCM5705:
1900                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1901                 break;
1902         }
1903
1904         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1905                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1906
1907         /*
1908          * Set various quirk flags.
1909          */
1910
1911         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1912         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1913             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1914              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1915               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1916             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1917                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1918
1919         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1920             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1921                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1922
1923         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1924             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1925                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1926
1927         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1928                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1929
1930         if (BGE_IS_5705_PLUS(sc)) {
1931                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1932                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1933                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1934                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1935                         uint32_t product = pci_get_device(dev);
1936
1937                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1938                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1939                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1940                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1941                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1942                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1943                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1944                 }
1945         }
1946
1947         /* Allocate interrupt */
1948         rid = 0;
1949
1950         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1951             RF_SHAREABLE | RF_ACTIVE);
1952
1953         if (sc->bge_irq == NULL) {
1954                 device_printf(dev, "couldn't map interrupt\n");
1955                 error = ENXIO;
1956                 goto fail;
1957         }
1958
1959         /*
1960          * Check if this is a PCI-X or PCI Express device.
1961          */
1962         if (BGE_IS_5705_PLUS(sc)) {
1963                 if (pci_is_pcie(dev)) {
1964                         sc->bge_flags |= BGE_FLAG_PCIE;
1965                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1966                 }
1967         } else {
1968                 /*
1969                  * Check if the device is in PCI-X Mode.
1970                  * (This bit is not valid on PCI Express controllers.)
1971                  */
1972                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1973                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
1974                         sc->bge_flags |= BGE_FLAG_PCIX;
1975                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
1976                 }
1977         }
1978
1979         device_printf(dev, "CHIP ID 0x%08x; "
1980                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1981                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1982                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1983                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1984                         "PCI-E" : "PCI"));
1985
1986         /*
1987          * All controllers that are not 5755 or higher have 4GB
1988          * boundary DMA bug.
1989          * Whenever an address crosses a multiple of the 4GB boundary
1990          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
1991          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
1992          * state machine will lockup and cause the device to hang.
1993          */
1994         if (BGE_IS_5755_PLUS(sc) == 0)
1995                 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
1996
1997         /*
1998          * The 40bit DMA bug applies to the 5714/5715 controllers and is
1999          * not actually a MAC controller bug but an issue with the embedded
2000          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2001          */
2002         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2003                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2004
2005         ifp = &sc->arpcom.ac_if;
2006         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2007
2008         /* Try to reset the chip. */
2009         bge_reset(sc);
2010
2011         if (bge_chipinit(sc)) {
2012                 device_printf(dev, "chip initialization failed\n");
2013                 error = ENXIO;
2014                 goto fail;
2015         }
2016
2017         /*
2018          * Get station address
2019          */
2020         error = bge_get_eaddr(sc, ether_addr);
2021         if (error) {
2022                 device_printf(dev, "failed to read station address\n");
2023                 goto fail;
2024         }
2025
2026         /* 5705/5750 limits RX return ring to 512 entries. */
2027         if (BGE_IS_5705_PLUS(sc))
2028                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2029         else
2030                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2031
2032         error = bge_dma_alloc(sc);
2033         if (error)
2034                 goto fail;
2035
2036         /* Set default tuneable values. */
2037         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2038         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2039         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2040         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2041         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2042
2043         /* Set up ifnet structure */
2044         ifp->if_softc = sc;
2045         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2046         ifp->if_ioctl = bge_ioctl;
2047         ifp->if_start = bge_start;
2048 #ifdef DEVICE_POLLING
2049         ifp->if_poll = bge_poll;
2050 #endif
2051         ifp->if_watchdog = bge_watchdog;
2052         ifp->if_init = bge_init;
2053         ifp->if_mtu = ETHERMTU;
2054         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2055         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2056         ifq_set_ready(&ifp->if_snd);
2057
2058         /*
2059          * 5700 B0 chips do not support checksumming correctly due
2060          * to hardware bugs.
2061          */
2062         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2063                 ifp->if_capabilities |= IFCAP_HWCSUM;
2064                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2065         }
2066         ifp->if_capenable = ifp->if_capabilities;
2067
2068         /*
2069          * Figure out what sort of media we have by checking the
2070          * hardware config word in the first 32k of NIC internal memory,
2071          * or fall back to examining the EEPROM if necessary.
2072          * Note: on some BCM5700 cards, this value appears to be unset.
2073          * If that's the case, we have to rely on identifying the NIC
2074          * by its PCI subsystem ID, as we do below for the SysKonnect
2075          * SK-9D41.
2076          */
2077         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2078                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2079         else {
2080                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2081                                     sizeof(hwcfg))) {
2082                         device_printf(dev, "failed to read EEPROM\n");
2083                         error = ENXIO;
2084                         goto fail;
2085                 }
2086                 hwcfg = ntohl(hwcfg);
2087         }
2088
2089         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2090                 sc->bge_flags |= BGE_FLAG_TBI;
2091
2092         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2093         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
2094                 sc->bge_flags |= BGE_FLAG_TBI;
2095
2096         if (sc->bge_flags & BGE_FLAG_TBI) {
2097                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2098                     bge_ifmedia_upd, bge_ifmedia_sts);
2099                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2100                 ifmedia_add(&sc->bge_ifmedia,
2101                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2102                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2103                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2104                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2105         } else {
2106                 /*
2107                  * Do transceiver setup.
2108                  */
2109                 if (mii_phy_probe(dev, &sc->bge_miibus,
2110                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2111                         device_printf(dev, "MII without any PHY!\n");
2112                         error = ENXIO;
2113                         goto fail;
2114                 }
2115         }
2116
2117         /*
2118          * When using the BCM5701 in PCI-X mode, data corruption has
2119          * been observed in the first few bytes of some received packets.
2120          * Aligning the packet buffer in memory eliminates the corruption.
2121          * Unfortunately, this misaligns the packet payloads.  On platforms
2122          * which do not support unaligned accesses, we will realign the
2123          * payloads by copying the received packets.
2124          */
2125         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2126             (sc->bge_flags & BGE_FLAG_PCIX))
2127                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2128
2129         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2130             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2131                 sc->bge_link_upd = bge_bcm5700_link_upd;
2132                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2133         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2134                 sc->bge_link_upd = bge_tbi_link_upd;
2135                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2136         } else {
2137                 sc->bge_link_upd = bge_copper_link_upd;
2138                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2139         }
2140
2141         /*
2142          * Create sysctl nodes.
2143          */
2144         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2145         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2146                                               SYSCTL_STATIC_CHILDREN(_hw),
2147                                               OID_AUTO,
2148                                               device_get_nameunit(dev),
2149                                               CTLFLAG_RD, 0, "");
2150         if (sc->bge_sysctl_tree == NULL) {
2151                 device_printf(dev, "can't add sysctl node\n");
2152                 error = ENXIO;
2153                 goto fail;
2154         }
2155
2156         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2157                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2158                         OID_AUTO, "rx_coal_ticks",
2159                         CTLTYPE_INT | CTLFLAG_RW,
2160                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2161                         "Receive coalescing ticks (usec).");
2162         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2163                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2164                         OID_AUTO, "tx_coal_ticks",
2165                         CTLTYPE_INT | CTLFLAG_RW,
2166                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2167                         "Transmit coalescing ticks (usec).");
2168         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2169                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2170                         OID_AUTO, "rx_max_coal_bds",
2171                         CTLTYPE_INT | CTLFLAG_RW,
2172                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2173                         "Receive max coalesced BD count.");
2174         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2175                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2176                         OID_AUTO, "tx_max_coal_bds",
2177                         CTLTYPE_INT | CTLFLAG_RW,
2178                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2179                         "Transmit max coalesced BD count.");
2180
2181         if (sc->bge_flags & BGE_FLAG_PCIE) {
2182                 /*
2183                  * A common design characteristic for many Broadcom
2184                  * client controllers is that they only support a
2185                  * single outstanding DMA read operation on the PCIe
2186                  * bus. This means that it will take twice as long to
2187                  * fetch a TX frame that is split into header and
2188                  * payload buffers as it does to fetch a single,
2189                  * contiguous TX frame (2 reads vs. 1 read). For these
2190                  * controllers, coalescing buffers to reduce the number
2191                  * of memory reads is effective way to get maximum
2192                  * performance(about 940Mbps).  Without collapsing TX
2193                  * buffers the maximum TCP bulk transfer performance
2194                  * is about 850Mbps. However forcing coalescing mbufs
2195                  * consumes a lot of CPU cycles, so leave it off by
2196                  * default.
2197                  */
2198                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2199                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2200                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2201                                &sc->bge_force_defrag, 0,
2202                                "Force defragment on TX path");
2203         }
2204
2205         /*
2206          * Call MI attach routine.
2207          */
2208         ether_ifattach(ifp, ether_addr, NULL);
2209
2210         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2211                                bge_intr, sc, &sc->bge_intrhand, 
2212                                ifp->if_serializer);
2213         if (error) {
2214                 ether_ifdetach(ifp);
2215                 device_printf(dev, "couldn't set up irq\n");
2216                 goto fail;
2217         }
2218
2219         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2220         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2221
2222         return(0);
2223 fail:
2224         bge_detach(dev);
2225         return(error);
2226 }
2227
2228 static int
2229 bge_detach(device_t dev)
2230 {
2231         struct bge_softc *sc = device_get_softc(dev);
2232
2233         if (device_is_attached(dev)) {
2234                 struct ifnet *ifp = &sc->arpcom.ac_if;
2235
2236                 lwkt_serialize_enter(ifp->if_serializer);
2237                 bge_stop(sc);
2238                 bge_reset(sc);
2239                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2240                 lwkt_serialize_exit(ifp->if_serializer);
2241
2242                 ether_ifdetach(ifp);
2243         }
2244
2245         if (sc->bge_flags & BGE_FLAG_TBI)
2246                 ifmedia_removeall(&sc->bge_ifmedia);
2247         if (sc->bge_miibus)
2248                 device_delete_child(dev, sc->bge_miibus);
2249         bus_generic_detach(dev);
2250
2251         if (sc->bge_irq != NULL)
2252                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2253
2254         if (sc->bge_res != NULL)
2255                 bus_release_resource(dev, SYS_RES_MEMORY,
2256                     BGE_PCI_BAR0, sc->bge_res);
2257
2258         if (sc->bge_sysctl_tree != NULL)
2259                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2260
2261         bge_dma_free(sc);
2262
2263         return 0;
2264 }
2265
2266 static void
2267 bge_reset(struct bge_softc *sc)
2268 {
2269         device_t dev;
2270         uint32_t cachesize, command, pcistate, reset;
2271         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2272         int i, val = 0;
2273
2274         dev = sc->bge_dev;
2275
2276         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2277             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2278                 if (sc->bge_flags & BGE_FLAG_PCIE)
2279                         write_op = bge_writemem_direct;
2280                 else
2281                         write_op = bge_writemem_ind;
2282         } else {
2283                 write_op = bge_writereg_ind;
2284         }
2285
2286         /* Save some important PCI state. */
2287         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2288         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2289         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2290
2291         pci_write_config(dev, BGE_PCI_MISC_CTL,
2292             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2293             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2294
2295         /* Disable fastboot on controllers that support it. */
2296         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2297             BGE_IS_5755_PLUS(sc)) {
2298                 if (bootverbose)
2299                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2300                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2301         }
2302
2303         /*
2304          * Write the magic number to SRAM at offset 0xB50.
2305          * When firmware finishes its initialization it will
2306          * write ~BGE_MAGIC_NUMBER to the same location.
2307          */
2308         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2309
2310         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2311
2312         /* XXX: Broadcom Linux driver. */
2313         if (sc->bge_flags & BGE_FLAG_PCIE) {
2314                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2315                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2316                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2317                         /* Prevent PCIE link training during global reset */
2318                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2319                         reset |= (1<<29);
2320                 }
2321         }
2322
2323         /* 
2324          * Set GPHY Power Down Override to leave GPHY
2325          * powered up in D0 uninitialized.
2326          */
2327         if (BGE_IS_5705_PLUS(sc))
2328                 reset |= 0x04000000;
2329
2330         /* Issue global reset */
2331         write_op(sc, BGE_MISC_CFG, reset);
2332
2333         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2334                 uint32_t status, ctrl;
2335
2336                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2337                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2338                     status | BGE_VCPU_STATUS_DRV_RESET);
2339                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2340                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2341                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2342         }
2343
2344         DELAY(1000);
2345
2346         /* XXX: Broadcom Linux driver. */
2347         if (sc->bge_flags & BGE_FLAG_PCIE) {
2348                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2349                         uint32_t v;
2350
2351                         DELAY(500000); /* wait for link training to complete */
2352                         v = pci_read_config(dev, 0xc4, 4);
2353                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2354                 }
2355                 /*
2356                  * Set PCIE max payload size to 128 bytes and
2357                  * clear error status.
2358                  */
2359                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2360         }
2361
2362         /* Reset some of the PCI state that got zapped by reset */
2363         pci_write_config(dev, BGE_PCI_MISC_CTL,
2364             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2365             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2366         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2367         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2368         write_op(sc, BGE_MISC_CFG, (65 << 1));
2369
2370         /*
2371          * Disable PCI-X relaxed ordering to ensure status block update
2372          * comes first then packet buffer DMA. Otherwise driver may
2373          * read stale status block.
2374          */
2375         if (sc->bge_flags & BGE_FLAG_PCIX) {
2376                 uint16_t devctl;
2377
2378                 devctl = pci_read_config(dev,
2379                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2380                 devctl &= ~PCIXM_COMMAND_ERO;
2381                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2382                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2383                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2384                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2385                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2386                             PCIXM_COMMAND_MAX_READ);
2387                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2388                 }
2389                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2390                     devctl, 2);
2391         }
2392
2393         /* Enable memory arbiter. */
2394         if (BGE_IS_5714_FAMILY(sc)) {
2395                 uint32_t val;
2396
2397                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2398                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2399         } else {
2400                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2401         }
2402
2403         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2404                 for (i = 0; i < BGE_TIMEOUT; i++) {
2405                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2406                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2407                                 break;
2408                         DELAY(100);
2409                 }
2410                 if (i == BGE_TIMEOUT) {
2411                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2412                         return;
2413                 }
2414         } else {
2415                 /*
2416                  * Poll until we see the 1's complement of the magic number.
2417                  * This indicates that the firmware initialization
2418                  * is complete.
2419                  */
2420                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2421                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2422                         if (val == ~BGE_MAGIC_NUMBER)
2423                                 break;
2424                         DELAY(10);
2425                 }
2426                 if (i == BGE_FIRMWARE_TIMEOUT) {
2427                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2428                                   "timed out, found 0x%08x\n", val);
2429                         return;
2430                 }
2431         }
2432
2433         /*
2434          * XXX Wait for the value of the PCISTATE register to
2435          * return to its original pre-reset state. This is a
2436          * fairly good indicator of reset completion. If we don't
2437          * wait for the reset to fully complete, trying to read
2438          * from the device's non-PCI registers may yield garbage
2439          * results.
2440          */
2441         for (i = 0; i < BGE_TIMEOUT; i++) {
2442                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2443                         break;
2444                 DELAY(10);
2445         }
2446
2447         if (sc->bge_flags & BGE_FLAG_PCIE) {
2448                 reset = bge_readmem_ind(sc, 0x7c00);
2449                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2450         }
2451
2452         /* Fix up byte swapping */
2453         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2454             BGE_MODECTL_BYTESWAP_DATA);
2455
2456         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2457
2458         /*
2459          * The 5704 in TBI mode apparently needs some special
2460          * adjustment to insure the SERDES drive level is set
2461          * to 1.2V.
2462          */
2463         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2464             (sc->bge_flags & BGE_FLAG_TBI)) {
2465                 uint32_t serdescfg;
2466
2467                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2468                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2469                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2470         }
2471
2472         /* XXX: Broadcom Linux driver. */
2473         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2474             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2475                 uint32_t v;
2476
2477                 v = CSR_READ_4(sc, 0x7c00);
2478                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2479         }
2480
2481         DELAY(10000);
2482 }
2483
2484 /*
2485  * Frame reception handling. This is called if there's a frame
2486  * on the receive return list.
2487  *
2488  * Note: we have to be able to handle two possibilities here:
2489  * 1) the frame is from the jumbo recieve ring
2490  * 2) the frame is from the standard receive ring
2491  */
2492
2493 static void
2494 bge_rxeof(struct bge_softc *sc)
2495 {
2496         struct ifnet *ifp;
2497         int stdcnt = 0, jumbocnt = 0;
2498
2499         if (sc->bge_rx_saved_considx ==
2500             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2501                 return;
2502
2503         ifp = &sc->arpcom.ac_if;
2504
2505         while (sc->bge_rx_saved_considx !=
2506                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2507                 struct bge_rx_bd        *cur_rx;
2508                 uint32_t                rxidx;
2509                 struct mbuf             *m = NULL;
2510                 uint16_t                vlan_tag = 0;
2511                 int                     have_tag = 0;
2512
2513                 cur_rx =
2514             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2515
2516                 rxidx = cur_rx->bge_idx;
2517                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2518                 logif(rx_pkt);
2519
2520                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2521                         have_tag = 1;
2522                         vlan_tag = cur_rx->bge_vlan_tag;
2523                 }
2524
2525                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2526                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2527                         jumbocnt++;
2528
2529                         if (rxidx != sc->bge_jumbo) {
2530                                 ifp->if_ierrors++;
2531                                 if_printf(ifp, "sw jumbo index(%d) "
2532                                     "and hw jumbo index(%d) mismatch, drop!\n",
2533                                     sc->bge_jumbo, rxidx);
2534                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2535                                 continue;
2536                         }
2537
2538                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2539                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2540                                 ifp->if_ierrors++;
2541                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2542                                 continue;
2543                         }
2544                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2545                                 ifp->if_ierrors++;
2546                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2547                                 continue;
2548                         }
2549                 } else {
2550                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2551                         stdcnt++;
2552
2553                         if (rxidx != sc->bge_std) {
2554                                 ifp->if_ierrors++;
2555                                 if_printf(ifp, "sw std index(%d) "
2556                                     "and hw std index(%d) mismatch, drop!\n",
2557                                     sc->bge_std, rxidx);
2558                                 bge_setup_rxdesc_std(sc, rxidx);
2559                                 continue;
2560                         }
2561
2562                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2563                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2564                                 ifp->if_ierrors++;
2565                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2566                                 continue;
2567                         }
2568                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2569                                 ifp->if_ierrors++;
2570                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2571                                 continue;
2572                         }
2573                 }
2574
2575                 ifp->if_ipackets++;
2576 #if !defined(__i386__) && !defined(__x86_64__)
2577                 /*
2578                  * The x86 allows unaligned accesses, but for other
2579                  * platforms we must make sure the payload is aligned.
2580                  */
2581                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2582                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2583                             cur_rx->bge_len);
2584                         m->m_data += ETHER_ALIGN;
2585                 }
2586 #endif
2587                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2588                 m->m_pkthdr.rcvif = ifp;
2589
2590                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2591                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2592                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2593                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2594                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2595                         }
2596                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2597                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2598                                 m->m_pkthdr.csum_data =
2599                                         cur_rx->bge_tcp_udp_csum;
2600                                 m->m_pkthdr.csum_flags |=
2601                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2602                         }
2603                 }
2604
2605                 /*
2606                  * If we received a packet with a vlan tag, pass it
2607                  * to vlan_input() instead of ether_input().
2608                  */
2609                 if (have_tag) {
2610                         m->m_flags |= M_VLANTAG;
2611                         m->m_pkthdr.ether_vlantag = vlan_tag;
2612                         have_tag = vlan_tag = 0;
2613                 }
2614                 ifp->if_input(ifp, m);
2615         }
2616
2617         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2618         if (stdcnt)
2619                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2620         if (jumbocnt)
2621                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2622 }
2623
2624 static void
2625 bge_txeof(struct bge_softc *sc)
2626 {
2627         struct bge_tx_bd *cur_tx = NULL;
2628         struct ifnet *ifp;
2629
2630         if (sc->bge_tx_saved_considx ==
2631             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2632                 return;
2633
2634         ifp = &sc->arpcom.ac_if;
2635
2636         /*
2637          * Go through our tx ring and free mbufs for those
2638          * frames that have been sent.
2639          */
2640         while (sc->bge_tx_saved_considx !=
2641                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2642                 uint32_t idx = 0;
2643
2644                 idx = sc->bge_tx_saved_considx;
2645                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2646                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2647                         ifp->if_opackets++;
2648                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2649                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2650                             sc->bge_cdata.bge_tx_dmamap[idx]);
2651                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2652                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2653                 }
2654                 sc->bge_txcnt--;
2655                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2656                 logif(tx_pkt);
2657         }
2658
2659         if (cur_tx != NULL &&
2660             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2661             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2662                 ifp->if_flags &= ~IFF_OACTIVE;
2663
2664         if (sc->bge_txcnt == 0)
2665                 ifp->if_timer = 0;
2666
2667         if (!ifq_is_empty(&ifp->if_snd))
2668                 if_devstart(ifp);
2669 }
2670
2671 #ifdef DEVICE_POLLING
2672
2673 static void
2674 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2675 {
2676         struct bge_softc *sc = ifp->if_softc;
2677         uint32_t status;
2678
2679         switch(cmd) {
2680         case POLL_REGISTER:
2681                 bge_disable_intr(sc);
2682                 break;
2683         case POLL_DEREGISTER:
2684                 bge_enable_intr(sc);
2685                 break;
2686         case POLL_AND_CHECK_STATUS:
2687                 /*
2688                  * Process link state changes.
2689                  */
2690                 status = CSR_READ_4(sc, BGE_MAC_STS);
2691                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2692                         sc->bge_link_evt = 0;
2693                         sc->bge_link_upd(sc, status);
2694                 }
2695                 /* fall through */
2696         case POLL_ONLY:
2697                 if (ifp->if_flags & IFF_RUNNING) {
2698                         bge_rxeof(sc);
2699                         bge_txeof(sc);
2700                 }
2701                 break;
2702         }
2703 }
2704
2705 #endif
2706
2707 static void
2708 bge_intr(void *xsc)
2709 {
2710         struct bge_softc *sc = xsc;
2711         struct ifnet *ifp = &sc->arpcom.ac_if;
2712         uint32_t status;
2713
2714         logif(intr);
2715
2716         /*
2717          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2718          * disable interrupts by writing nonzero like we used to, since with
2719          * our current organization this just gives complications and
2720          * pessimizations for re-enabling interrupts.  We used to have races
2721          * instead of the necessary complications.  Disabling interrupts
2722          * would just reduce the chance of a status update while we are
2723          * running (by switching to the interrupt-mode coalescence
2724          * parameters), but this chance is already very low so it is more
2725          * efficient to get another interrupt than prevent it.
2726          *
2727          * We do the ack first to ensure another interrupt if there is a
2728          * status update after the ack.  We don't check for the status
2729          * changing later because it is more efficient to get another
2730          * interrupt than prevent it, not quite as above (not checking is
2731          * a smaller optimization than not toggling the interrupt enable,
2732          * since checking doesn't involve PCI accesses and toggling require
2733          * the status check).  So toggling would probably be a pessimization
2734          * even with MSI.  It would only be needed for using a task queue.
2735          */
2736         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2737
2738         /*
2739          * Process link state changes.
2740          */
2741         status = CSR_READ_4(sc, BGE_MAC_STS);
2742         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2743                 sc->bge_link_evt = 0;
2744                 sc->bge_link_upd(sc, status);
2745         }
2746
2747         if (ifp->if_flags & IFF_RUNNING) {
2748                 /* Check RX return ring producer/consumer */
2749                 bge_rxeof(sc);
2750
2751                 /* Check TX ring producer/consumer */
2752                 bge_txeof(sc);
2753         }
2754
2755         if (sc->bge_coal_chg)
2756                 bge_coal_change(sc);
2757 }
2758
2759 static void
2760 bge_tick(void *xsc)
2761 {
2762         struct bge_softc *sc = xsc;
2763         struct ifnet *ifp = &sc->arpcom.ac_if;
2764
2765         lwkt_serialize_enter(ifp->if_serializer);
2766
2767         if (BGE_IS_5705_PLUS(sc))
2768                 bge_stats_update_regs(sc);
2769         else
2770                 bge_stats_update(sc);
2771
2772         if (sc->bge_flags & BGE_FLAG_TBI) {
2773                 /*
2774                  * Since in TBI mode auto-polling can't be used we should poll
2775                  * link status manually. Here we register pending link event
2776                  * and trigger interrupt.
2777                  */
2778                 sc->bge_link_evt++;
2779                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2780         } else if (!sc->bge_link) {
2781                 mii_tick(device_get_softc(sc->bge_miibus));
2782         }
2783
2784         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2785
2786         lwkt_serialize_exit(ifp->if_serializer);
2787 }
2788
2789 static void
2790 bge_stats_update_regs(struct bge_softc *sc)
2791 {
2792         struct ifnet *ifp = &sc->arpcom.ac_if;
2793         struct bge_mac_stats_regs stats;
2794         uint32_t *s;
2795         int i;
2796
2797         s = (uint32_t *)&stats;
2798         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2799                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2800                 s++;
2801         }
2802
2803         ifp->if_collisions +=
2804            (stats.dot3StatsSingleCollisionFrames +
2805            stats.dot3StatsMultipleCollisionFrames +
2806            stats.dot3StatsExcessiveCollisions +
2807            stats.dot3StatsLateCollisions) -
2808            ifp->if_collisions;
2809 }
2810
2811 static void
2812 bge_stats_update(struct bge_softc *sc)
2813 {
2814         struct ifnet *ifp = &sc->arpcom.ac_if;
2815         bus_size_t stats;
2816
2817         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2818
2819 #define READ_STAT(sc, stats, stat)      \
2820         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2821
2822         ifp->if_collisions +=
2823            (READ_STAT(sc, stats,
2824                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2825             READ_STAT(sc, stats,
2826                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2827             READ_STAT(sc, stats,
2828                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2829             READ_STAT(sc, stats,
2830                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2831            ifp->if_collisions;
2832
2833 #undef READ_STAT
2834
2835 #ifdef notdef
2836         ifp->if_collisions +=
2837            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2838            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2839            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2840            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2841            ifp->if_collisions;
2842 #endif
2843 }
2844
2845 /*
2846  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2847  * pointers to descriptors.
2848  */
2849 static int
2850 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2851 {
2852         struct bge_tx_bd *d = NULL;
2853         uint16_t csum_flags = 0;
2854         bus_dma_segment_t segs[BGE_NSEG_NEW];
2855         bus_dmamap_t map;
2856         int error, maxsegs, nsegs, idx, i;
2857         struct mbuf *m_head = *m_head0;
2858
2859         if (m_head->m_pkthdr.csum_flags) {
2860                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2861                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2862                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2863                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2864                 if (m_head->m_flags & M_LASTFRAG)
2865                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2866                 else if (m_head->m_flags & M_FRAG)
2867                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2868         }
2869
2870         idx = *txidx;
2871         map = sc->bge_cdata.bge_tx_dmamap[idx];
2872
2873         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2874         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2875                 ("not enough segments %d", maxsegs));
2876
2877         if (maxsegs > BGE_NSEG_NEW)
2878                 maxsegs = BGE_NSEG_NEW;
2879
2880         /*
2881          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2882          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2883          * but when such padded frames employ the bge IP/TCP checksum
2884          * offload, the hardware checksum assist gives incorrect results
2885          * (possibly from incorporating its own padding into the UDP/TCP
2886          * checksum; who knows).  If we pad such runts with zeros, the
2887          * onboard checksum comes out correct.
2888          */
2889         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2890             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2891                 error = m_devpad(m_head, BGE_MIN_FRAME);
2892                 if (error)
2893                         goto back;
2894         }
2895
2896         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
2897             m_head->m_next != NULL) {
2898                 struct mbuf *m_new;
2899
2900                 /*
2901                  * Forcefully defragment mbuf chain to overcome hardware
2902                  * limitation which only support a single outstanding
2903                  * DMA read operation.  If it fails, keep moving on using
2904                  * the original mbuf chain.
2905                  */
2906                 m_new = m_defrag(m_head, MB_DONTWAIT);
2907                 if (m_new != NULL)
2908                         *m_head0 = m_head = m_new;
2909         }
2910
2911         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2912                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2913         if (error)
2914                 goto back;
2915
2916         m_head = *m_head0;
2917         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2918
2919         for (i = 0; ; i++) {
2920                 d = &sc->bge_ldata.bge_tx_ring[idx];
2921
2922                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2923                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2924                 d->bge_len = segs[i].ds_len;
2925                 d->bge_flags = csum_flags;
2926
2927                 if (i == nsegs - 1)
2928                         break;
2929                 BGE_INC(idx, BGE_TX_RING_CNT);
2930         }
2931         /* Mark the last segment as end of packet... */
2932         d->bge_flags |= BGE_TXBDFLAG_END;
2933
2934         /* Set vlan tag to the first segment of the packet. */
2935         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2936         if (m_head->m_flags & M_VLANTAG) {
2937                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2938                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2939         } else {
2940                 d->bge_vlan_tag = 0;
2941         }
2942
2943         /*
2944          * Insure that the map for this transmission is placed at
2945          * the array index of the last descriptor in this chain.
2946          */
2947         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2948         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2949         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2950         sc->bge_txcnt += nsegs;
2951
2952         BGE_INC(idx, BGE_TX_RING_CNT);
2953         *txidx = idx;
2954 back:
2955         if (error) {
2956                 m_freem(*m_head0);
2957                 *m_head0 = NULL;
2958         }
2959         return error;
2960 }
2961
2962 /*
2963  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2964  * to the mbuf data regions directly in the transmit descriptors.
2965  */
2966 static void
2967 bge_start(struct ifnet *ifp)
2968 {
2969         struct bge_softc *sc = ifp->if_softc;
2970         struct mbuf *m_head = NULL;
2971         uint32_t prodidx;
2972         int need_trans;
2973
2974         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2975                 return;
2976
2977         prodidx = sc->bge_tx_prodidx;
2978
2979         need_trans = 0;
2980         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2981                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2982                 if (m_head == NULL)
2983                         break;
2984
2985                 /*
2986                  * XXX
2987                  * The code inside the if() block is never reached since we
2988                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2989                  * requests to checksum TCP/UDP in a fragmented packet.
2990                  * 
2991                  * XXX
2992                  * safety overkill.  If this is a fragmented packet chain
2993                  * with delayed TCP/UDP checksums, then only encapsulate
2994                  * it if we have enough descriptors to handle the entire
2995                  * chain at once.
2996                  * (paranoia -- may not actually be needed)
2997                  */
2998                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2999                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3000                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3001                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3002                                 ifp->if_flags |= IFF_OACTIVE;
3003                                 ifq_prepend(&ifp->if_snd, m_head);
3004                                 break;
3005                         }
3006                 }
3007
3008                 /*
3009                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3010                  * descriptors of the end of the ring.  Also make
3011                  * sure there are BGE_NSEG_SPARE descriptors for
3012                  * jumbo buffers' defragmentation.
3013                  */
3014                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3015                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3016                         ifp->if_flags |= IFF_OACTIVE;
3017                         ifq_prepend(&ifp->if_snd, m_head);
3018                         break;
3019                 }
3020
3021                 /*
3022                  * Pack the data into the transmit ring. If we
3023                  * don't have room, set the OACTIVE flag and wait
3024                  * for the NIC to drain the ring.
3025                  */
3026                 if (bge_encap(sc, &m_head, &prodidx)) {
3027                         ifp->if_flags |= IFF_OACTIVE;
3028                         ifp->if_oerrors++;
3029                         break;
3030                 }
3031                 need_trans = 1;
3032
3033                 ETHER_BPF_MTAP(ifp, m_head);
3034         }
3035
3036         if (!need_trans)
3037                 return;
3038
3039         /* Transmit */
3040         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3041         /* 5700 b2 errata */
3042         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3043                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3044
3045         sc->bge_tx_prodidx = prodidx;
3046
3047         /*
3048          * Set a timeout in case the chip goes out to lunch.
3049          */
3050         ifp->if_timer = 5;
3051 }
3052
3053 static void
3054 bge_init(void *xsc)
3055 {
3056         struct bge_softc *sc = xsc;
3057         struct ifnet *ifp = &sc->arpcom.ac_if;
3058         uint16_t *m;
3059
3060         ASSERT_SERIALIZED(ifp->if_serializer);
3061
3062         if (ifp->if_flags & IFF_RUNNING)
3063                 return;
3064
3065         /* Cancel pending I/O and flush buffers. */
3066         bge_stop(sc);
3067         bge_reset(sc);
3068         bge_chipinit(sc);
3069
3070         /*
3071          * Init the various state machines, ring
3072          * control blocks and firmware.
3073          */
3074         if (bge_blockinit(sc)) {
3075                 if_printf(ifp, "initialization failure\n");
3076                 bge_stop(sc);
3077                 return;
3078         }
3079
3080         /* Specify MTU. */
3081         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3082             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3083
3084         /* Load our MAC address. */
3085         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3086         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3087         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3088
3089         /* Enable or disable promiscuous mode as needed. */
3090         bge_setpromisc(sc);
3091
3092         /* Program multicast filter. */
3093         bge_setmulti(sc);
3094
3095         /* Init RX ring. */
3096         if (bge_init_rx_ring_std(sc)) {
3097                 if_printf(ifp, "RX ring initialization failed\n");
3098                 bge_stop(sc);
3099                 return;
3100         }
3101
3102         /*
3103          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3104          * memory to insure that the chip has in fact read the first
3105          * entry of the ring.
3106          */
3107         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3108                 uint32_t                v, i;
3109                 for (i = 0; i < 10; i++) {
3110                         DELAY(20);
3111                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3112                         if (v == (MCLBYTES - ETHER_ALIGN))
3113                                 break;
3114                 }
3115                 if (i == 10)
3116                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3117         }
3118
3119         /* Init jumbo RX ring. */
3120         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3121                 if (bge_init_rx_ring_jumbo(sc)) {
3122                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3123                         bge_stop(sc);
3124                         return;
3125                 }
3126         }
3127
3128         /* Init our RX return ring index */
3129         sc->bge_rx_saved_considx = 0;
3130
3131         /* Init TX ring. */
3132         bge_init_tx_ring(sc);
3133
3134         /* Turn on transmitter */
3135         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3136
3137         /* Turn on receiver */
3138         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3139
3140         /* Tell firmware we're alive. */
3141         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3142
3143         /* Enable host interrupts if polling(4) is not enabled. */
3144         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3145 #ifdef DEVICE_POLLING
3146         if (ifp->if_flags & IFF_POLLING)
3147                 bge_disable_intr(sc);
3148         else
3149 #endif
3150         bge_enable_intr(sc);
3151
3152         bge_ifmedia_upd(ifp);
3153
3154         ifp->if_flags |= IFF_RUNNING;
3155         ifp->if_flags &= ~IFF_OACTIVE;
3156
3157         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3158 }
3159
3160 /*
3161  * Set media options.
3162  */
3163 static int
3164 bge_ifmedia_upd(struct ifnet *ifp)
3165 {
3166         struct bge_softc *sc = ifp->if_softc;
3167
3168         /* If this is a 1000baseX NIC, enable the TBI port. */
3169         if (sc->bge_flags & BGE_FLAG_TBI) {
3170                 struct ifmedia *ifm = &sc->bge_ifmedia;
3171
3172                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3173                         return(EINVAL);
3174
3175                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3176                 case IFM_AUTO:
3177                         /*
3178                          * The BCM5704 ASIC appears to have a special
3179                          * mechanism for programming the autoneg
3180                          * advertisement registers in TBI mode.
3181                          */
3182                         if (!bge_fake_autoneg &&
3183                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3184                                 uint32_t sgdig;
3185
3186                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3187                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3188                                 sgdig |= BGE_SGDIGCFG_AUTO |
3189                                          BGE_SGDIGCFG_PAUSE_CAP |
3190                                          BGE_SGDIGCFG_ASYM_PAUSE;
3191                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3192                                             sgdig | BGE_SGDIGCFG_SEND);
3193                                 DELAY(5);
3194                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3195                         }
3196                         break;
3197                 case IFM_1000_SX:
3198                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3199                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3200                                     BGE_MACMODE_HALF_DUPLEX);
3201                         } else {
3202                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3203                                     BGE_MACMODE_HALF_DUPLEX);
3204                         }
3205                         break;
3206                 default:
3207                         return(EINVAL);
3208                 }
3209         } else {
3210                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3211
3212                 sc->bge_link_evt++;
3213                 sc->bge_link = 0;
3214                 if (mii->mii_instance) {
3215                         struct mii_softc *miisc;
3216
3217                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3218                                 mii_phy_reset(miisc);
3219                 }
3220                 mii_mediachg(mii);
3221         }
3222         return(0);
3223 }
3224
3225 /*
3226  * Report current media status.
3227  */
3228 static void
3229 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3230 {
3231         struct bge_softc *sc = ifp->if_softc;
3232
3233         if (sc->bge_flags & BGE_FLAG_TBI) {
3234                 ifmr->ifm_status = IFM_AVALID;
3235                 ifmr->ifm_active = IFM_ETHER;
3236                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3237                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3238                         ifmr->ifm_status |= IFM_ACTIVE;
3239                 } else {
3240                         ifmr->ifm_active |= IFM_NONE;
3241                         return;
3242                 }
3243
3244                 ifmr->ifm_active |= IFM_1000_SX;
3245                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3246                         ifmr->ifm_active |= IFM_HDX;    
3247                 else
3248                         ifmr->ifm_active |= IFM_FDX;
3249         } else {
3250                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3251
3252                 mii_pollstat(mii);
3253                 ifmr->ifm_active = mii->mii_media_active;
3254                 ifmr->ifm_status = mii->mii_media_status;
3255         }
3256 }
3257
3258 static int
3259 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3260 {
3261         struct bge_softc *sc = ifp->if_softc;
3262         struct ifreq *ifr = (struct ifreq *)data;
3263         int mask, error = 0;
3264
3265         ASSERT_SERIALIZED(ifp->if_serializer);
3266
3267         switch (command) {
3268         case SIOCSIFMTU:
3269                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3270                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3271                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3272                         error = EINVAL;
3273                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3274                         ifp->if_mtu = ifr->ifr_mtu;
3275                         ifp->if_flags &= ~IFF_RUNNING;
3276                         bge_init(sc);
3277                 }
3278                 break;
3279         case SIOCSIFFLAGS:
3280                 if (ifp->if_flags & IFF_UP) {
3281                         if (ifp->if_flags & IFF_RUNNING) {
3282                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3283
3284                                 /*
3285                                  * If only the state of the PROMISC flag
3286                                  * changed, then just use the 'set promisc
3287                                  * mode' command instead of reinitializing
3288                                  * the entire NIC. Doing a full re-init
3289                                  * means reloading the firmware and waiting
3290                                  * for it to start up, which may take a
3291                                  * second or two.  Similarly for ALLMULTI.
3292                                  */
3293                                 if (mask & IFF_PROMISC)
3294                                         bge_setpromisc(sc);
3295                                 if (mask & IFF_ALLMULTI)
3296                                         bge_setmulti(sc);
3297                         } else {
3298                                 bge_init(sc);
3299                         }
3300                 } else {
3301                         if (ifp->if_flags & IFF_RUNNING)
3302                                 bge_stop(sc);
3303                 }
3304                 sc->bge_if_flags = ifp->if_flags;
3305                 break;
3306         case SIOCADDMULTI:
3307         case SIOCDELMULTI:
3308                 if (ifp->if_flags & IFF_RUNNING)
3309                         bge_setmulti(sc);
3310                 break;
3311         case SIOCSIFMEDIA:
3312         case SIOCGIFMEDIA:
3313                 if (sc->bge_flags & BGE_FLAG_TBI) {
3314                         error = ifmedia_ioctl(ifp, ifr,
3315                             &sc->bge_ifmedia, command);
3316                 } else {
3317                         struct mii_data *mii;
3318
3319                         mii = device_get_softc(sc->bge_miibus);
3320                         error = ifmedia_ioctl(ifp, ifr,
3321                                               &mii->mii_media, command);
3322                 }
3323                 break;
3324         case SIOCSIFCAP:
3325                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3326                 if (mask & IFCAP_HWCSUM) {
3327                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3328                         if (IFCAP_HWCSUM & ifp->if_capenable)
3329                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3330                         else
3331                                 ifp->if_hwassist = 0;
3332                 }
3333                 break;
3334         default:
3335                 error = ether_ioctl(ifp, command, data);
3336                 break;
3337         }
3338         return error;
3339 }
3340
3341 static void
3342 bge_watchdog(struct ifnet *ifp)
3343 {
3344         struct bge_softc *sc = ifp->if_softc;
3345
3346         if_printf(ifp, "watchdog timeout -- resetting\n");
3347
3348         ifp->if_flags &= ~IFF_RUNNING;
3349         bge_init(sc);
3350
3351         ifp->if_oerrors++;
3352
3353         if (!ifq_is_empty(&ifp->if_snd))
3354                 if_devstart(ifp);
3355 }
3356
3357 /*
3358  * Stop the adapter and free any mbufs allocated to the
3359  * RX and TX lists.
3360  */
3361 static void
3362 bge_stop(struct bge_softc *sc)
3363 {
3364         struct ifnet *ifp = &sc->arpcom.ac_if;
3365
3366         ASSERT_SERIALIZED(ifp->if_serializer);
3367
3368         callout_stop(&sc->bge_stat_timer);
3369
3370         /*
3371          * Disable all of the receiver blocks
3372          */
3373         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3374         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3375         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3376         if (!BGE_IS_5705_PLUS(sc))
3377                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3378         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3379         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3380         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3381
3382         /*
3383          * Disable all of the transmit blocks
3384          */
3385         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3386         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3387         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3388         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3389         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3390         if (!BGE_IS_5705_PLUS(sc))
3391                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3392         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3393
3394         /*
3395          * Shut down all of the memory managers and related
3396          * state machines.
3397          */
3398         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3399         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3400         if (!BGE_IS_5705_PLUS(sc))
3401                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3402         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3403         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3404         if (!BGE_IS_5705_PLUS(sc)) {
3405                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3406                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3407         }
3408
3409         /* Disable host interrupts. */
3410         bge_disable_intr(sc);
3411
3412         /*
3413          * Tell firmware we're shutting down.
3414          */
3415         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3416
3417         /* Free the RX lists. */
3418         bge_free_rx_ring_std(sc);
3419
3420         /* Free jumbo RX list. */
3421         if (BGE_IS_JUMBO_CAPABLE(sc))
3422                 bge_free_rx_ring_jumbo(sc);
3423
3424         /* Free TX buffers. */
3425         bge_free_tx_ring(sc);
3426
3427         sc->bge_link = 0;
3428         sc->bge_coal_chg = 0;
3429
3430         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3431
3432         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3433         ifp->if_timer = 0;
3434 }
3435
3436 /*
3437  * Stop all chip I/O so that the kernel's probe routines don't
3438  * get confused by errant DMAs when rebooting.
3439  */
3440 static void
3441 bge_shutdown(device_t dev)
3442 {
3443         struct bge_softc *sc = device_get_softc(dev);
3444         struct ifnet *ifp = &sc->arpcom.ac_if;
3445
3446         lwkt_serialize_enter(ifp->if_serializer);
3447         bge_stop(sc);
3448         bge_reset(sc);
3449         lwkt_serialize_exit(ifp->if_serializer);
3450 }
3451
3452 static int
3453 bge_suspend(device_t dev)
3454 {
3455         struct bge_softc *sc = device_get_softc(dev);
3456         struct ifnet *ifp = &sc->arpcom.ac_if;
3457
3458         lwkt_serialize_enter(ifp->if_serializer);
3459         bge_stop(sc);
3460         lwkt_serialize_exit(ifp->if_serializer);
3461
3462         return 0;
3463 }
3464
3465 static int
3466 bge_resume(device_t dev)
3467 {
3468         struct bge_softc *sc = device_get_softc(dev);
3469         struct ifnet *ifp = &sc->arpcom.ac_if;
3470
3471         lwkt_serialize_enter(ifp->if_serializer);
3472
3473         if (ifp->if_flags & IFF_UP) {
3474                 bge_init(sc);
3475
3476                 if (!ifq_is_empty(&ifp->if_snd))
3477                         if_devstart(ifp);
3478         }
3479
3480         lwkt_serialize_exit(ifp->if_serializer);
3481
3482         return 0;
3483 }
3484
3485 static void
3486 bge_setpromisc(struct bge_softc *sc)
3487 {
3488         struct ifnet *ifp = &sc->arpcom.ac_if;
3489
3490         if (ifp->if_flags & IFF_PROMISC)
3491                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3492         else
3493                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3494 }
3495
3496 static void
3497 bge_dma_free(struct bge_softc *sc)
3498 {
3499         int i;
3500
3501         /* Destroy RX mbuf DMA stuffs. */
3502         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3503                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3504                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3505                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3506                 }
3507                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3508                                    sc->bge_cdata.bge_rx_tmpmap);
3509                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3510         }
3511
3512         /* Destroy TX mbuf DMA stuffs. */
3513         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3514                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3515                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3516                             sc->bge_cdata.bge_tx_dmamap[i]);
3517                 }
3518                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3519         }
3520
3521         /* Destroy standard RX ring */
3522         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3523                            sc->bge_cdata.bge_rx_std_ring_map,
3524                            sc->bge_ldata.bge_rx_std_ring);
3525
3526         if (BGE_IS_JUMBO_CAPABLE(sc))
3527                 bge_free_jumbo_mem(sc);
3528
3529         /* Destroy RX return ring */
3530         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3531                            sc->bge_cdata.bge_rx_return_ring_map,
3532                            sc->bge_ldata.bge_rx_return_ring);
3533
3534         /* Destroy TX ring */
3535         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3536                            sc->bge_cdata.bge_tx_ring_map,
3537                            sc->bge_ldata.bge_tx_ring);
3538
3539         /* Destroy status block */
3540         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3541                            sc->bge_cdata.bge_status_map,
3542                            sc->bge_ldata.bge_status_block);
3543
3544         /* Destroy statistics block */
3545         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3546                            sc->bge_cdata.bge_stats_map,
3547                            sc->bge_ldata.bge_stats);
3548
3549         /* Destroy the parent tag */
3550         if (sc->bge_cdata.bge_parent_tag != NULL)
3551                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3552 }
3553
3554 static int
3555 bge_dma_alloc(struct bge_softc *sc)
3556 {
3557         struct ifnet *ifp = &sc->arpcom.ac_if;
3558         int i, error;
3559         bus_addr_t lowaddr;
3560         bus_size_t boundary;
3561
3562         boundary = 0;
3563         if (sc->bge_flags & BGE_FLAG_BOUNDARY_4G)
3564                 boundary = BGE_DMA_BOUNDARY_4G;
3565
3566         lowaddr = BUS_SPACE_MAXADDR;
3567         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3568                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3569
3570         /*
3571          * Allocate the parent bus DMA tag appropriate for PCI.
3572          */
3573         error = bus_dma_tag_create(NULL, 1, boundary,
3574                                    lowaddr, BUS_SPACE_MAXADDR,
3575                                    NULL, NULL,
3576                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3577                                    BUS_SPACE_MAXSIZE_32BIT,
3578                                    0, &sc->bge_cdata.bge_parent_tag);
3579         if (error) {
3580                 if_printf(ifp, "could not allocate parent dma tag\n");
3581                 return error;
3582         }
3583
3584         /*
3585          * Create DMA tag and maps for RX mbufs.
3586          */
3587         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3588                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3589                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3590                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3591                                    &sc->bge_cdata.bge_rx_mtag);
3592         if (error) {
3593                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3594                 return error;
3595         }
3596
3597         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3598                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3599         if (error) {
3600                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3601                 sc->bge_cdata.bge_rx_mtag = NULL;
3602                 return error;
3603         }
3604
3605         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3606                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3607                                           BUS_DMA_WAITOK,
3608                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3609                 if (error) {
3610                         int j;
3611
3612                         for (j = 0; j < i; ++j) {
3613                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3614                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3615                         }
3616                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3617                         sc->bge_cdata.bge_rx_mtag = NULL;
3618
3619                         if_printf(ifp, "could not create DMA map for RX\n");
3620                         return error;
3621                 }
3622         }
3623
3624         /*
3625          * Create DMA tag and maps for TX mbufs.
3626          */
3627         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3628                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3629                                    NULL, NULL,
3630                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3631                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3632                                    BUS_DMA_ONEBPAGE,
3633                                    &sc->bge_cdata.bge_tx_mtag);
3634         if (error) {
3635                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3636                 return error;
3637         }
3638
3639         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3640                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3641                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3642                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3643                 if (error) {
3644                         int j;
3645
3646                         for (j = 0; j < i; ++j) {
3647                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3648                                         sc->bge_cdata.bge_tx_dmamap[j]);
3649                         }
3650                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3651                         sc->bge_cdata.bge_tx_mtag = NULL;
3652
3653                         if_printf(ifp, "could not create DMA map for TX\n");
3654                         return error;
3655                 }
3656         }
3657
3658         /*
3659          * Create DMA stuffs for standard RX ring.
3660          */
3661         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3662                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3663                                     &sc->bge_cdata.bge_rx_std_ring_map,
3664                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3665                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3666         if (error) {
3667                 if_printf(ifp, "could not create std RX ring\n");
3668                 return error;
3669         }
3670
3671         /*
3672          * Create jumbo buffer pool.
3673          */
3674         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3675                 error = bge_alloc_jumbo_mem(sc);
3676                 if (error) {
3677                         if_printf(ifp, "could not create jumbo buffer pool\n");
3678                         return error;
3679                 }
3680         }
3681
3682         /*
3683          * Create DMA stuffs for RX return ring.
3684          */
3685         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3686                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3687                                     &sc->bge_cdata.bge_rx_return_ring_map,
3688                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3689                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3690         if (error) {
3691                 if_printf(ifp, "could not create RX ret ring\n");
3692                 return error;
3693         }
3694
3695         /*
3696          * Create DMA stuffs for TX ring.
3697          */
3698         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3699                                     &sc->bge_cdata.bge_tx_ring_tag,
3700                                     &sc->bge_cdata.bge_tx_ring_map,
3701                                     (void *)&sc->bge_ldata.bge_tx_ring,
3702                                     &sc->bge_ldata.bge_tx_ring_paddr);
3703         if (error) {
3704                 if_printf(ifp, "could not create TX ring\n");
3705                 return error;
3706         }
3707
3708         /*
3709          * Create DMA stuffs for status block.
3710          */
3711         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3712                                     &sc->bge_cdata.bge_status_tag,
3713                                     &sc->bge_cdata.bge_status_map,
3714                                     (void *)&sc->bge_ldata.bge_status_block,
3715                                     &sc->bge_ldata.bge_status_block_paddr);
3716         if (error) {
3717                 if_printf(ifp, "could not create status block\n");
3718                 return error;
3719         }
3720
3721         /*
3722          * Create DMA stuffs for statistics block.
3723          */
3724         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3725                                     &sc->bge_cdata.bge_stats_tag,
3726                                     &sc->bge_cdata.bge_stats_map,
3727                                     (void *)&sc->bge_ldata.bge_stats,
3728                                     &sc->bge_ldata.bge_stats_paddr);
3729         if (error) {
3730                 if_printf(ifp, "could not create stats block\n");
3731                 return error;
3732         }
3733         return 0;
3734 }
3735
3736 static int
3737 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3738                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3739 {
3740         bus_dmamem_t dmem;
3741         int error;
3742
3743         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3744                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3745                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3746         if (error)
3747                 return error;
3748
3749         *tag = dmem.dmem_tag;
3750         *map = dmem.dmem_map;
3751         *addr = dmem.dmem_addr;
3752         *paddr = dmem.dmem_busaddr;
3753
3754         return 0;
3755 }
3756
3757 static void
3758 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3759 {
3760         if (tag != NULL) {
3761                 bus_dmamap_unload(tag, map);
3762                 bus_dmamem_free(tag, addr, map);
3763                 bus_dma_tag_destroy(tag);
3764         }
3765 }
3766
3767 /*
3768  * Grrr. The link status word in the status block does
3769  * not work correctly on the BCM5700 rev AX and BX chips,
3770  * according to all available information. Hence, we have
3771  * to enable MII interrupts in order to properly obtain
3772  * async link changes. Unfortunately, this also means that
3773  * we have to read the MAC status register to detect link
3774  * changes, thereby adding an additional register access to
3775  * the interrupt handler.
3776  *
3777  * XXX: perhaps link state detection procedure used for
3778  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3779  */
3780 static void
3781 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3782 {
3783         struct ifnet *ifp = &sc->arpcom.ac_if;
3784         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3785
3786         mii_pollstat(mii);
3787
3788         if (!sc->bge_link &&
3789             (mii->mii_media_status & IFM_ACTIVE) &&
3790             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3791                 sc->bge_link++;
3792                 if (bootverbose)
3793                         if_printf(ifp, "link UP\n");
3794         } else if (sc->bge_link &&
3795             (!(mii->mii_media_status & IFM_ACTIVE) ||
3796             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3797                 sc->bge_link = 0;
3798                 if (bootverbose)
3799                         if_printf(ifp, "link DOWN\n");
3800         }
3801
3802         /* Clear the interrupt. */
3803         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3804         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3805         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3806 }
3807
3808 static void
3809 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3810 {
3811         struct ifnet *ifp = &sc->arpcom.ac_if;
3812
3813 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3814
3815         /*
3816          * Sometimes PCS encoding errors are detected in
3817          * TBI mode (on fiber NICs), and for some reason
3818          * the chip will signal them as link changes.
3819          * If we get a link change event, but the 'PCS
3820          * encoding error' bit in the MAC status register
3821          * is set, don't bother doing a link check.
3822          * This avoids spurious "gigabit link up" messages
3823          * that sometimes appear on fiber NICs during
3824          * periods of heavy traffic.
3825          */
3826         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3827                 if (!sc->bge_link) {
3828                         sc->bge_link++;
3829                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3830                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3831                                     BGE_MACMODE_TBI_SEND_CFGS);
3832                         }
3833                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3834
3835                         if (bootverbose)
3836                                 if_printf(ifp, "link UP\n");
3837
3838                         ifp->if_link_state = LINK_STATE_UP;
3839                         if_link_state_change(ifp);
3840                 }
3841         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3842                 if (sc->bge_link) {
3843                         sc->bge_link = 0;
3844
3845                         if (bootverbose)
3846                                 if_printf(ifp, "link DOWN\n");
3847
3848                         ifp->if_link_state = LINK_STATE_DOWN;
3849                         if_link_state_change(ifp);
3850                 }
3851         }
3852
3853 #undef PCS_ENCODE_ERR
3854
3855         /* Clear the attention. */
3856         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3857             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3858             BGE_MACSTAT_LINK_CHANGED);
3859 }
3860
3861 static void
3862 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3863 {
3864         /*
3865          * Check that the AUTOPOLL bit is set before
3866          * processing the event as a real link change.
3867          * Turning AUTOPOLL on and off in the MII read/write
3868          * functions will often trigger a link status
3869          * interrupt for no reason.
3870          */
3871         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3872                 struct ifnet *ifp = &sc->arpcom.ac_if;
3873                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3874
3875                 mii_pollstat(mii);
3876
3877                 if (!sc->bge_link &&
3878                     (mii->mii_media_status & IFM_ACTIVE) &&
3879                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3880                         sc->bge_link++;
3881                         if (bootverbose)
3882                                 if_printf(ifp, "link UP\n");
3883                 } else if (sc->bge_link &&
3884                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3885                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3886                         sc->bge_link = 0;
3887                         if (bootverbose)
3888                                 if_printf(ifp, "link DOWN\n");
3889                 }
3890         }
3891
3892         /* Clear the attention. */
3893         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3894             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3895             BGE_MACSTAT_LINK_CHANGED);
3896 }
3897
3898 static int
3899 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3900 {
3901         struct bge_softc *sc = arg1;
3902
3903         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3904                                    &sc->bge_rx_coal_ticks,
3905                                    BGE_RX_COAL_TICKS_CHG);
3906 }
3907
3908 static int
3909 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3910 {
3911         struct bge_softc *sc = arg1;
3912
3913         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3914                                    &sc->bge_tx_coal_ticks,
3915                                    BGE_TX_COAL_TICKS_CHG);
3916 }
3917
3918 static int
3919 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3920 {
3921         struct bge_softc *sc = arg1;
3922
3923         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3924                                    &sc->bge_rx_max_coal_bds,
3925                                    BGE_RX_MAX_COAL_BDS_CHG);
3926 }
3927
3928 static int
3929 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3930 {
3931         struct bge_softc *sc = arg1;
3932
3933         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3934                                    &sc->bge_tx_max_coal_bds,
3935                                    BGE_TX_MAX_COAL_BDS_CHG);
3936 }
3937
3938 static int
3939 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3940                     uint32_t coal_chg_mask)
3941 {
3942         struct bge_softc *sc = arg1;
3943         struct ifnet *ifp = &sc->arpcom.ac_if;
3944         int error = 0, v;
3945
3946         lwkt_serialize_enter(ifp->if_serializer);
3947
3948         v = *coal;
3949         error = sysctl_handle_int(oidp, &v, 0, req);
3950         if (!error && req->newptr != NULL) {
3951                 if (v < 0) {
3952                         error = EINVAL;
3953                 } else {
3954                         *coal = v;
3955                         sc->bge_coal_chg |= coal_chg_mask;
3956                 }
3957         }
3958
3959         lwkt_serialize_exit(ifp->if_serializer);
3960         return error;
3961 }
3962
3963 static void
3964 bge_coal_change(struct bge_softc *sc)
3965 {
3966         struct ifnet *ifp = &sc->arpcom.ac_if;
3967         uint32_t val;
3968