4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
21 * This code is derived from software contributed to The DragonFly Project
22 * by Matthew Dillon <dillon@backplane.com>
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
34 * 3. Neither the name of The DragonFly Project nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific, prior written permission.
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
56 static int ahci_vt8251_attach(device_t);
57 static int ahci_ati_sb600_attach(device_t);
58 static int ahci_nvidia_mcp_attach(device_t);
59 static int ahci_pci_attach(device_t);
60 static int ahci_pci_detach(device_t);
62 static const struct ahci_device ahci_devices[] = {
63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA,
66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
74 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
83 static const struct ahci_pciid ahci_msi_blacklist[] = {
84 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, -1 },
85 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_AHCI, -1 },
87 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, -1 },
88 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, -1 },
90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa1 },
91 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa1 },
92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa1 },
93 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa1 },
94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa1 },
95 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa1 },
96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa1 },
97 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa1 },
99 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa2 },
100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa2 },
101 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa2 },
102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa2 },
103 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa2 },
104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa2 },
105 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa2 },
106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa2 }
109 static int ahci_msi_enable = 1;
110 TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable);
113 * Match during probe and attach. The device does not yet have a softc.
115 const struct ahci_device *
116 ahci_lookup_device(device_t dev)
118 const struct ahci_device *ad;
119 u_int16_t vendor = pci_get_vendor(dev);
120 u_int16_t product = pci_get_device(dev);
121 u_int8_t class = pci_get_class(dev);
122 u_int8_t subclass = pci_get_subclass(dev);
123 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
127 * Generally speaking if the pci device does not identify as
130 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
131 progif == PCIP_STORAGE_SATA_AHCI_1_0) {
137 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
138 if (ad->ad_vendor == vendor && ad->ad_product == product)
143 * Last ad is the default match if the PCI device matches SATA.
151 * Attach functions. They all eventually fall through to ahci_pci_attach().
154 ahci_vt8251_attach(device_t dev)
156 struct ahci_softc *sc = device_get_softc(dev);
158 sc->sc_flags |= AHCI_F_NO_NCQ;
159 return (ahci_pci_attach(dev));
163 ahci_ati_sb600_attach(device_t dev)
165 struct ahci_softc *sc = device_get_softc(dev);
167 u_int8_t subclass = pci_get_subclass(dev);
170 if (subclass == PCIS_STORAGE_IDE) {
171 revid = pci_read_config(dev, PCIR_REVID, 1);
172 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
173 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
174 magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
175 pci_write_config(dev, PCIR_REVID,
176 (PCIC_STORAGE << 24) |
177 (PCIS_STORAGE_SATA << 16) |
178 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
180 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
183 sc->sc_flags |= AHCI_F_IGN_FR;
184 return (ahci_pci_attach(dev));
188 ahci_nvidia_mcp_attach(device_t dev)
190 struct ahci_softc *sc = device_get_softc(dev);
192 sc->sc_flags |= AHCI_F_IGN_FR;
193 return (ahci_pci_attach(dev));
197 ahci_pci_attach(device_t dev)
199 struct ahci_softc *sc = device_get_softc(dev);
200 struct ahci_port *ap;
203 u_int32_t cap, pi, reg;
206 int i, error, msi_enable, rev;
207 const char *revision;
209 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
210 device_printf(dev, "BIOS disabled PCI interrupt, "
212 pci_write_config(dev, PCIR_COMMAND,
213 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
219 * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
222 msi_enable = ahci_msi_enable;
224 vid = pci_get_vendor(dev);
225 did = pci_get_device(dev);
226 rev = pci_get_revid(dev);
227 for (i = 0; i < NELEM(ahci_msi_blacklist); ++i) {
228 const struct ahci_pciid *id = &ahci_msi_blacklist[i];
230 if (vid == id->ahci_vid && did == id->ahci_did) {
231 if (id->ahci_rev < 0 || id->ahci_rev == rev) {
238 sc->sc_irq_type = pci_alloc_1intr(dev, msi_enable,
239 &sc->sc_rid_irq, &irq_flags);
241 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
243 if (sc->sc_irq == NULL) {
244 device_printf(dev, "unable to map interrupt\n");
245 ahci_pci_detach(dev);
250 * When mapping the register window store the tag and handle
251 * separately so we can use the tag with per-port bus handle
254 sc->sc_rid_regs = PCIR_BAR(5);
255 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
256 &sc->sc_rid_regs, RF_ACTIVE);
257 if (sc->sc_regs == NULL) {
258 device_printf(dev, "unable to map registers\n");
259 ahci_pci_detach(dev);
262 sc->sc_iot = rman_get_bustag(sc->sc_regs);
263 sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
266 * Initialize the chipset and then set the interrupt vector up
268 error = ahci_init(sc);
270 ahci_pci_detach(dev);
275 * Get the AHCI capabilities and max number of concurrent
276 * command tags and set up the DMA tags.
278 cap = ahci_read(sc, AHCI_REG_CAP);
279 if (sc->sc_flags & AHCI_F_NO_NCQ)
280 cap &= ~AHCI_REG_CAP_SNCQ;
284 * We assume at least 4 commands.
286 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
287 if (sc->sc_ncmds < 4) {
288 device_printf(dev, "NCS must probe a value >= 4\n");
289 ahci_pci_detach(dev);
293 addr = (cap & AHCI_REG_CAP_S64A) ?
294 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
297 * DMA tags for allocation of DMA memory buffers, lists, and so
298 * forth. These are typically per-port.
301 error += bus_dma_tag_create(
302 NULL, /* parent tag */
304 PAGE_SIZE, /* boundary */
306 BUS_SPACE_MAXADDR, /* hiaddr */
308 NULL, /* filterarg */
309 sizeof(struct ahci_rfis), /* [max]size */
311 sizeof(struct ahci_rfis), /* maxsegsz */
313 &sc->sc_tag_rfis); /* return tag */
315 error += bus_dma_tag_create(
316 NULL, /* parent tag */
318 4096 * 1024, /* boundary */
320 BUS_SPACE_MAXADDR, /* hiaddr */
322 NULL, /* filterarg */
323 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
325 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
327 &sc->sc_tag_cmdh); /* return tag */
330 * NOTE: ahci_cmd_table is sized to a power of 2
332 error += bus_dma_tag_create(
333 NULL, /* parent tag */
334 sizeof(struct ahci_cmd_table), /* alignment */
335 4096 * 1024, /* boundary */
337 BUS_SPACE_MAXADDR, /* hiaddr */
339 NULL, /* filterarg */
340 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
342 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
344 &sc->sc_tag_cmdt); /* return tag */
347 * The data tag is used for later dmamaps and not immediately
350 error += bus_dma_tag_create(
351 NULL, /* parent tag */
355 BUS_SPACE_MAXADDR, /* hiaddr */
357 NULL, /* filterarg */
358 4096 * 1024, /* maxiosize */
359 AHCI_MAX_PRDT, /* maxsegs */
360 65536, /* maxsegsz */
362 &sc->sc_tag_data); /* return tag */
365 device_printf(dev, "unable to create dma tags\n");
366 ahci_pci_detach(dev);
370 switch (cap & AHCI_REG_CAP_ISS) {
371 case AHCI_REG_CAP_ISS_G1:
374 case AHCI_REG_CAP_ISS_G2:
377 case AHCI_REG_CAP_ISS_G3:
385 /* check the revision */
386 reg = ahci_read(sc, AHCI_REG_VS);
388 case AHCI_REG_VS_0_95:
389 revision = "AHCI 0.95";
391 case AHCI_REG_VS_1_0:
392 revision = "AHCI 1.0";
394 case AHCI_REG_VS_1_1:
395 revision = "AHCI 1.1";
397 case AHCI_REG_VS_1_2:
398 revision = "AHCI 1.2";
400 case AHCI_REG_VS_1_3:
401 revision = "AHCI 1.3";
403 case AHCI_REG_VS_1_4:
404 revision = "AHCI 1.4";
406 case AHCI_REG_VS_1_5:
407 revision = "AHCI 1.5"; /* future will catch up to us */
410 device_printf(sc->sc_dev,
411 "Warning: Unknown AHCI revision 0x%08x\n", reg);
412 revision = "AHCI <unknown>";
417 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n",
420 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
422 pi = ahci_read(sc, AHCI_REG_PI);
423 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
427 /* Naive coalescing support - enable for all ports. */
428 if (cap & AHCI_REG_CAP_CCCS) {
429 u_int16_t ccc_timeout = 20;
430 u_int8_t ccc_numcomplete = 12;
433 /* disable coalescing during reconfiguration. */
434 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
435 ccc_ctl &= ~0x00000001;
436 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
438 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
439 if (pi & sc->sc_ccc_mask) {
440 /* A conflict with the implemented port list? */
441 printf("%s: coalescing interrupt/implemented port list "
442 "conflict, PI: %08x, ccc_mask: %08x\n",
443 DEVNAME(sc), pi, sc->sc_ccc_mask);
448 /* ahci_port_start will enable each port when it starts. */
449 sc->sc_ccc_ports = pi;
450 sc->sc_ccc_ports_cur = 0;
452 /* program thresholds and enable overall coalescing. */
453 ccc_ctl &= ~0xffffff00;
454 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
455 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
456 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
457 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
462 * Allocate per-port resources
464 * Ignore attach errors, leave the port intact for
465 * rescan and continue the loop.
467 * All ports are attached in parallel but the CAM scan-bus
468 * is held up until all ports are attached so we get a deterministic
471 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
472 if ((pi & (1 << i)) == 0) {
473 /* dont allocate stuff if the port isnt implemented */
476 error = ahci_port_alloc(sc, i);
480 * Setup the interrupt vector and enable interrupts. Note that
481 * since the irq may be shared we do not set it up until we are
485 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
487 &sc->sc_irq_handle, NULL);
491 device_printf(dev, "unable to install interrupt\n");
492 ahci_pci_detach(dev);
497 * Before marking the sc as good, which allows the interrupt
498 * subsystem to operate on the ports, wait for all the port threads
499 * to get past their initial pre-probe init. Otherwise an interrupt
500 * may try to process the port before it has been initialized.
502 for (i = 0; i < AHCI_MAX_PORTS; i++) {
503 if ((ap = sc->sc_ports[i]) != NULL) {
504 while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
505 tsleep(&ap->ap_signal, 0, "ahprb1", hz);
510 * Master interrupt enable, and call ahci_intr() in case we race
511 * our AHCI_F_INT_GOOD flag.
514 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
515 sc->sc_flags |= AHCI_F_INT_GOOD;
520 * All ports are probing in parallel. Wait for them to finish
521 * and then issue the cam attachment and bus scan serially so
522 * the 'da' assignments are deterministic.
524 for (i = 0; i < AHCI_MAX_PORTS; i++) {
525 if ((ap = sc->sc_ports[i]) != NULL) {
526 while (ap->ap_signal & AP_SIGF_INIT)
527 tsleep(&ap->ap_signal, 0, "ahprb2", hz);
528 ahci_os_lock_port(ap);
529 if (ahci_cam_attach(ap) == 0) {
530 ahci_cam_changed(ap, NULL, -1);
531 ahci_os_unlock_port(ap);
532 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
533 tsleep(&ap->ap_flags, 0, "ahprb2", hz);
536 ahci_os_unlock_port(ap);
545 * Device unload / detachment
548 ahci_pci_detach(device_t dev)
550 struct ahci_softc *sc = device_get_softc(dev);
551 struct ahci_port *ap;
555 * Disable the controller and de-register the interrupt, if any.
557 * XXX interlock last interrupt?
559 sc->sc_flags &= ~AHCI_F_INT_GOOD;
561 ahci_write(sc, AHCI_REG_GHC, 0);
563 if (sc->sc_irq_handle) {
564 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
565 sc->sc_irq_handle = NULL;
569 * Free port structures and DMA memory
571 for (i = 0; i < AHCI_MAX_PORTS; i++) {
572 ap = sc->sc_ports[i];
575 ahci_port_free(sc, i);
580 * Clean up the bus space
583 bus_release_resource(dev, SYS_RES_IRQ,
584 sc->sc_rid_irq, sc->sc_irq);
588 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI)
589 pci_release_msi(dev);
592 bus_release_resource(dev, SYS_RES_MEMORY,
593 sc->sc_rid_regs, sc->sc_regs);
597 if (sc->sc_tag_rfis) {
598 bus_dma_tag_destroy(sc->sc_tag_rfis);
599 sc->sc_tag_rfis = NULL;
601 if (sc->sc_tag_cmdh) {
602 bus_dma_tag_destroy(sc->sc_tag_cmdh);
603 sc->sc_tag_cmdh = NULL;
605 if (sc->sc_tag_cmdt) {
606 bus_dma_tag_destroy(sc->sc_tag_cmdt);
607 sc->sc_tag_cmdt = NULL;
609 if (sc->sc_tag_data) {
610 bus_dma_tag_destroy(sc->sc_tag_data);
611 sc->sc_tag_data = NULL;