2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
36 * $DragonFly: src/sys/platform/pc32/isa/npx.c,v 1.38 2006/12/23 00:27:03 swildner Exp $
40 #include "opt_debug_npx.h"
41 #include "opt_math_emulate.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/module.h>
49 #include <sys/sysctl.h>
53 #include <sys/syslog.h>
55 #include <sys/signalvar.h>
56 #include <sys/thread2.h>
59 #include <machine/asmacros.h>
61 #include <machine/cputypes.h>
62 #include <machine/frame.h>
63 #include <machine/ipl.h>
64 #include <machine/md_var.h>
65 #include <machine/pcb.h>
66 #include <machine/psl.h>
68 #include <machine/clock.h>
70 #include <machine/specialreg.h>
71 #include <machine/segments.h>
72 #include <machine/globaldata.h>
75 #include <machine_base/icu/icu.h>
76 #include <machine_base/isa/intr_machdep.h>
77 #include <bus/isa/i386/isa.h>
81 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
84 /* Configuration flags. */
85 #define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
86 #define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
87 #define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
88 #define NPX_PREFER_EMULATOR (1 << 3)
92 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
93 #define fnclex() __asm("fnclex")
94 #define fninit() __asm("fninit")
95 #define fnop() __asm("fnop")
96 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
97 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
98 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
99 #define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
100 #define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
101 #ifndef CPU_DISABLE_SSE
102 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
103 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
105 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
106 : : "n" (CR0_TS) : "ax")
107 #define stop_emulating() __asm("clts")
109 #else /* not __GNUC__ */
111 void fldcw (caddr_t addr);
115 void fnsave (caddr_t addr);
116 void fnstcw (caddr_t addr);
117 void fnstsw (caddr_t addr);
118 void fp_divide_by_0 (void);
119 void frstor (caddr_t addr);
120 #ifndef CPU_DISABLE_SSE
121 void fxsave (caddr_t addr);
122 void fxrstor (caddr_t addr);
124 void start_emulating (void);
125 void stop_emulating (void);
127 #endif /* __GNUC__ */
129 #ifndef CPU_DISABLE_SSE
130 #define GET_FPU_EXSW_PTR(td) \
132 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
133 &(td)->td_savefpu->sv_87.sv_ex_sw)
134 #else /* CPU_DISABLE_SSE */
135 #define GET_FPU_EXSW_PTR(td) \
136 (&(td)->td_savefpu->sv_87.sv_ex_sw)
137 #endif /* CPU_DISABLE_SSE */
139 typedef u_char bool_t;
140 #ifndef CPU_DISABLE_SSE
141 static void fpu_clean_state(void);
145 static int npx_attach (device_t dev);
146 void npx_intr (void *);
147 static int npx_probe (device_t dev);
148 static int npx_probe1 (device_t dev);
149 static void fpusave (union savefpu *);
150 static void fpurstor (union savefpu *);
152 int hw_float; /* XXX currently just alias for npx_exists */
154 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
155 CTLFLAG_RD, &hw_float, 0,
156 "Floatingpoint instructions executed in hardware");
157 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
159 SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
160 "MMX/XMM optimized bcopy/copyin/copyout support");
164 static u_int npx0_imask;
165 static struct gate_descriptor npx_idt_probeintr;
166 static int npx_intrno;
167 static volatile u_int npx_intrs_while_probing;
168 static volatile u_int npx_traps_while_probing;
171 static bool_t npx_ex16;
172 static bool_t npx_exists;
173 static bool_t npx_irq13;
174 static int npx_irq; /* irq number */
178 * Special interrupt handlers. Someday intr0-intr15 will be used to count
179 * interrupts. We'll still need a special exception 16 handler. The busy
180 * latch stuff in probeintr() can be moved to npxprobe().
186 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
187 " __XSTRING(CNAME(probeintr)) ": \n\
189 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
191 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
192 outb %al,$0xa0 # IO_ICU2 \n\
193 outb %al,$0x20 # IO_ICU1 \n\
195 outb %al,$0xf0 # clear BUSY# latch \n\
204 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
205 " __XSTRING(CNAME(probetrap)) ": \n\
207 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
214 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
215 * whether the device exists or not (XXX should be elsewhere). Set flags
216 * to tell npxattach() what to do. Modify device struct if npx doesn't
217 * need to use interrupts. Return 1 if device exists.
220 npx_probe(device_t dev)
224 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
226 return npx_probe1(dev);
232 u_char save_icu1_mask;
233 u_char save_icu2_mask;
234 struct gate_descriptor save_idt_npxintr;
235 struct gate_descriptor save_idt_npxtrap;
237 * This routine is now just a wrapper for npxprobe1(), to install
238 * special npx interrupt and trap handlers, to enable npx interrupts
239 * and to disable other interrupts. Someday isa_configure() will
240 * install suitable handlers and run with interrupts enabled so we
241 * won't need to do so much here.
243 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
245 npx_intrno = IDT_OFFSET + npx_irq;
246 save_eflags = read_eflags();
248 save_icu1_mask = inb(IO_ICU1 + 1);
249 save_icu2_mask = inb(IO_ICU2 + 1);
250 save_idt_npxintr = idt[npx_intrno];
251 save_idt_npxtrap = idt[16];
252 outb(IO_ICU1 + 1, ~(1 << ICU_IRQ_SLAVE));
253 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
254 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
255 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
256 npx_idt_probeintr = idt[npx_intrno];
258 result = npx_probe1(dev);
260 outb(IO_ICU1 + 1, save_icu1_mask);
261 outb(IO_ICU2 + 1, save_icu2_mask);
262 idt[npx_intrno] = save_idt_npxintr;
263 idt[16] = save_idt_npxtrap;
264 write_eflags(save_eflags);
271 npx_probe1(device_t dev)
279 * Partially reset the coprocessor, if any. Some BIOS's don't reset
280 * it after a warm boot.
282 outb(0xf1, 0); /* full reset on some systems, NOP on others */
283 outb(0xf0, 0); /* clear BUSY# latch */
285 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
286 * instructions. We must set the CR0_MP bit and use the CR0_TS
287 * bit to control the trap, because setting the CR0_EM bit does
288 * not cause WAIT instructions to trap. It's important to trap
289 * WAIT instructions - otherwise the "wait" variants of no-wait
290 * control instructions would degenerate to the "no-wait" variants
291 * after FP context switches but work correctly otherwise. It's
292 * particularly important to trap WAITs when there is no NPX -
293 * otherwise the "wait" variants would always degenerate.
295 * Try setting CR0_NE to get correct error reporting on 486DX's.
296 * Setting it should fail or do nothing on lesser processors.
298 load_cr0(rcr0() | CR0_MP | CR0_NE);
300 * But don't trap while we're probing.
304 * Finish resetting the coprocessor, if any. If there is an error
305 * pending, then we may get a bogus IRQ13, but probeintr() will handle
306 * it OK. Bogus halts have never been observed, but we enabled
307 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
313 * Exception 16 MUST work for SMP.
316 npx_ex16 = hw_float = npx_exists = 1;
317 device_set_desc(dev, "math processor");
321 device_set_desc(dev, "math processor");
324 * Don't use fwait here because it might hang.
325 * Don't use fnop here because it usually hangs if there is no FPU.
327 DELAY(1000); /* wait for any IRQ13 */
329 if (npx_intrs_while_probing != 0)
330 kprintf("fninit caused %u bogus npx interrupt(s)\n",
331 npx_intrs_while_probing);
332 if (npx_traps_while_probing != 0)
333 kprintf("fninit caused %u bogus npx trap(s)\n",
334 npx_traps_while_probing);
337 * Check for a status of mostly zero.
341 if ((status & 0xb8ff) == 0) {
343 * Good, now check for a proper control word.
347 if ((control & 0x1f3f) == 0x033f) {
348 hw_float = npx_exists = 1;
350 * We have an npx, now divide by 0 to see if exception
353 control &= ~(1 << 2); /* enable divide by 0 trap */
355 npx_traps_while_probing = npx_intrs_while_probing = 0;
357 if (npx_traps_while_probing != 0) {
359 * Good, exception 16 works.
364 if (npx_intrs_while_probing != 0) {
369 * Bad, we are stuck with IRQ13.
373 * npxattach would be too late to set npx0_imask
375 npx0_imask |= (1 << npx_irq);
378 * We allocate these resources permanently,
379 * so there is no need to keep track of them.
382 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
383 &rid, IO_NPX, IO_NPX,
384 IO_NPXSIZE, RF_ACTIVE);
386 panic("npx: can't get ports");
388 r = bus_alloc_resource(dev, SYS_RES_IRQ,
389 &rid, npx_irq, npx_irq,
392 panic("npx: can't get IRQ");
393 BUS_SETUP_INTR(device_get_parent(dev),
395 npx_intr, 0, &intr, NULL);
397 panic("npx: can't create intr");
402 * Worse, even IRQ13 is broken. Use emulator.
407 * Probe failed, but we want to get to npxattach to initialize the
408 * emulator and say that it has been installed. XXX handle devices
409 * that aren't really devices better.
416 * Attach routine - announce which it is, and wire into system
419 npx_attach(device_t dev)
423 if (resource_int_value("npx", 0, "flags", &flags) != 0)
427 device_printf(dev, "flags 0x%x ", flags);
429 device_printf(dev, "using IRQ 13 interface\n");
431 #if defined(MATH_EMULATE)
433 if (!(flags & NPX_PREFER_EMULATOR))
434 device_printf(dev, "INT 16 interface\n");
436 device_printf(dev, "FPU exists, but flags request "
438 hw_float = npx_exists = 0;
440 } else if (npx_exists) {
441 device_printf(dev, "error reporting broken; using 387 emulator\n");
442 hw_float = npx_exists = 0;
444 device_printf(dev, "387 emulator\n");
447 device_printf(dev, "INT 16 interface\n");
448 if (flags & NPX_PREFER_EMULATOR) {
449 device_printf(dev, "emulator requested, but none compiled "
450 "into kernel, using FPU\n");
453 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
456 npxinit(__INITIAL_NPXCW__);
458 #if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
460 * The asm_mmx_*() routines actually use XMM as well, so only
461 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
463 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
464 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
465 (cpu_feature & CPUID_SSE2) &&
466 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
468 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
469 bcopy_vector = (void **)asm_xmm_bcopy;
470 ovbcopy_vector = (void **)asm_xmm_bcopy;
471 memcpy_vector = (void **)asm_xmm_memcpy;
472 kprintf("Using XMM optimized bcopy/copyin/copyout\n");
474 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
477 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
478 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
480 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
481 bcopy_vector = (void **)asm_mmx_bcopy;
482 ovbcopy_vector = (void **)asm_mmx_bcopy;
483 memcpy_vector = (void **)asm_mmx_memcpy;
484 kprintf("Using MMX optimized bcopy/copyin/copyout\n");
486 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
492 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
493 timezero("i586_bzero()", i586_bzero) <
494 timezero("bzero()", bzero) * 4 / 5) {
495 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
496 bcopy_vector = i586_bcopy;
497 ovbcopy_vector = i586_bcopy;
499 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
500 bzero_vector = i586_bzero;
501 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
502 copyin_vector = i586_copyin;
503 copyout_vector = i586_copyout;
507 return (0); /* XXX unused */
511 * Initialize the floating point unit.
514 npxinit(u_short control)
516 static union savefpu dummy;
521 * fninit has the same h/w bugs as fnsave. Use the detoxified
522 * fnsave to throw away any junk in the fpu. npxsave() initializes
523 * the fpu and sets npxthread = NULL as important side effects.
529 fpusave(curthread->td_savefpu);
530 mdcpu->gd_npxthread = NULL;
536 * Free coprocessor (if we have it).
541 if (curthread == mdcpu->gd_npxthread)
542 npxsave(curthread->td_savefpu);
545 u_int masked_exceptions;
548 curthread->td_savefpu->sv_87.sv_env.en_cw
549 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
551 * Log exceptions that would have trapped with the old
552 * control word (overflow, divide by 0, and invalid operand).
554 if (masked_exceptions & 0x0d)
556 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
557 curproc->p_pid, curproc->p_comm, masked_exceptions);
563 * The following mechanism is used to ensure that the FPE_... value
564 * that is passed as a trapcode to the signal handler of the user
565 * process does not have more than one bit set.
567 * Multiple bits may be set if the user process modifies the control
568 * word while a status word bit is already set. While this is a sign
569 * of bad coding, we have no choise than to narrow them down to one
570 * bit, since we must not send a trapcode that is not exactly one of
573 * The mechanism has a static table with 127 entries. Each combination
574 * of the 7 FPU status word exception bits directly translates to a
575 * position in this table, where a single FPE_... value is stored.
576 * This FPE_... value stored there is considered the "most important"
577 * of the exception bits and will be sent as the signal code. The
578 * precedence of the bits is based upon Intel Document "Numerical
579 * Applications", Chapter "Special Computational Situations".
581 * The macro to choose one of these values does these steps: 1) Throw
582 * away status word bits that cannot be masked. 2) Throw away the bits
583 * currently masked in the control word, assuming the user isn't
584 * interested in them anymore. 3) Reinsert status word bit 7 (stack
585 * fault) if it is set, which cannot be masked but must be presered.
586 * 4) Use the remaining bits to point into the trapcode table.
588 * The 6 maskable bits in order of their preference, as stated in the
589 * above referenced Intel manual:
590 * 1 Invalid operation (FP_X_INV)
593 * 1c Operand of unsupported format
595 * 2 QNaN operand (not an exception, irrelavant here)
596 * 3 Any other invalid-operation not mentioned above or zero divide
597 * (FP_X_INV, FP_X_DZ)
598 * 4 Denormal operand (FP_X_DNML)
599 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
600 * 6 Inexact result (FP_X_IMP)
602 static char fpetable[128] = {
604 FPE_FLTINV, /* 1 - INV */
605 FPE_FLTUND, /* 2 - DNML */
606 FPE_FLTINV, /* 3 - INV | DNML */
607 FPE_FLTDIV, /* 4 - DZ */
608 FPE_FLTINV, /* 5 - INV | DZ */
609 FPE_FLTDIV, /* 6 - DNML | DZ */
610 FPE_FLTINV, /* 7 - INV | DNML | DZ */
611 FPE_FLTOVF, /* 8 - OFL */
612 FPE_FLTINV, /* 9 - INV | OFL */
613 FPE_FLTUND, /* A - DNML | OFL */
614 FPE_FLTINV, /* B - INV | DNML | OFL */
615 FPE_FLTDIV, /* C - DZ | OFL */
616 FPE_FLTINV, /* D - INV | DZ | OFL */
617 FPE_FLTDIV, /* E - DNML | DZ | OFL */
618 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
619 FPE_FLTUND, /* 10 - UFL */
620 FPE_FLTINV, /* 11 - INV | UFL */
621 FPE_FLTUND, /* 12 - DNML | UFL */
622 FPE_FLTINV, /* 13 - INV | DNML | UFL */
623 FPE_FLTDIV, /* 14 - DZ | UFL */
624 FPE_FLTINV, /* 15 - INV | DZ | UFL */
625 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
626 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
627 FPE_FLTOVF, /* 18 - OFL | UFL */
628 FPE_FLTINV, /* 19 - INV | OFL | UFL */
629 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
630 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
631 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
632 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
633 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
634 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
635 FPE_FLTRES, /* 20 - IMP */
636 FPE_FLTINV, /* 21 - INV | IMP */
637 FPE_FLTUND, /* 22 - DNML | IMP */
638 FPE_FLTINV, /* 23 - INV | DNML | IMP */
639 FPE_FLTDIV, /* 24 - DZ | IMP */
640 FPE_FLTINV, /* 25 - INV | DZ | IMP */
641 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
642 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
643 FPE_FLTOVF, /* 28 - OFL | IMP */
644 FPE_FLTINV, /* 29 - INV | OFL | IMP */
645 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
646 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
647 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
648 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
649 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
650 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
651 FPE_FLTUND, /* 30 - UFL | IMP */
652 FPE_FLTINV, /* 31 - INV | UFL | IMP */
653 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
654 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
655 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
656 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
657 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
658 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
659 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
660 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
661 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
662 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
663 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
664 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
665 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
666 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
667 FPE_FLTSUB, /* 40 - STK */
668 FPE_FLTSUB, /* 41 - INV | STK */
669 FPE_FLTUND, /* 42 - DNML | STK */
670 FPE_FLTSUB, /* 43 - INV | DNML | STK */
671 FPE_FLTDIV, /* 44 - DZ | STK */
672 FPE_FLTSUB, /* 45 - INV | DZ | STK */
673 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
674 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
675 FPE_FLTOVF, /* 48 - OFL | STK */
676 FPE_FLTSUB, /* 49 - INV | OFL | STK */
677 FPE_FLTUND, /* 4A - DNML | OFL | STK */
678 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
679 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
680 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
681 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
682 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
683 FPE_FLTUND, /* 50 - UFL | STK */
684 FPE_FLTSUB, /* 51 - INV | UFL | STK */
685 FPE_FLTUND, /* 52 - DNML | UFL | STK */
686 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
687 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
688 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
689 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
690 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
691 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
692 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
693 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
694 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
695 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
696 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
697 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
698 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
699 FPE_FLTRES, /* 60 - IMP | STK */
700 FPE_FLTSUB, /* 61 - INV | IMP | STK */
701 FPE_FLTUND, /* 62 - DNML | IMP | STK */
702 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
703 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
704 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
705 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
706 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
707 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
708 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
709 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
710 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
711 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
712 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
713 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
714 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
715 FPE_FLTUND, /* 70 - UFL | IMP | STK */
716 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
717 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
718 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
719 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
720 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
721 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
722 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
723 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
724 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
725 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
726 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
727 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
728 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
729 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
730 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
734 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
736 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
737 * depend on longjmp() restoring a usable state. Restoring the state
738 * or examining it might fail if we didn't clear exceptions.
740 * The error code chosen will be one of the FPE_... macros. It will be
741 * sent as the second argument to old BSD-style signal handlers and as
742 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
744 * XXX the FP state is not preserved across signal handlers. So signal
745 * handlers cannot afford to do FP unless they preserve the state or
746 * longjmp() out. Both preserving the state and longjmp()ing may be
747 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
748 * solution for signals other than SIGFPE.
750 * The MP lock is not held on entry (see i386/i386/exception.s) and
751 * should not be held on exit. Interrupts are enabled. We must enter
752 * a critical section to stabilize the FP system and prevent an interrupt
753 * or preemption from changing the FP state out from under us.
756 npx_intr(void *dummy)
760 struct intrframe *frame;
766 * This exception can only occur with CR0_TS clear, otherwise we
767 * would get a DNA exception. However, since interrupts were
768 * enabled a preemption could have sneaked in and used the FP system
769 * before we entered our critical section. If that occured, the
770 * TS bit will be set and npxthread will be NULL.
772 if (npx_exists && (rcr0() & CR0_TS)) {
773 KASSERT(mdcpu->gd_npxthread == NULL, ("gd_npxthread was %p with TS set!", mdcpu->gd_npxthread));
778 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
780 kprintf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
781 mdcpu->gd_npxthread, curthread, npx_exists);
782 panic("npxintr from nowhere");
784 if (mdcpu->gd_npxthread != curthread) {
786 kprintf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
787 mdcpu->gd_npxthread, curthread, npx_exists);
788 panic("npxintr from non-current process");
791 exstat = GET_FPU_EXSW_PTR(curthread);
800 * Pass exception to process.
802 frame = (struct intrframe *)&dummy; /* XXX */
803 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
805 * Interrupt is essentially a trap, so we can afford to call
806 * the SIGFPE handler (if any) as soon as the interrupt
809 * XXX little or nothing is gained from this, and plenty is
810 * lost - the interrupt frame has to contain the trap frame
811 * (this is otherwise only necessary for the rescheduling trap
812 * in doreti, and the frame for that could easily be set up
813 * just before it is used).
815 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
817 * Encode the appropriate code for detailed information on
821 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
822 trapsignal(curproc, SIGFPE, code);
825 * Nested interrupt. These losers occur when:
826 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
827 * o immediately after an fnsave or frstor of an
829 * o a couple of 386 instructions after
830 * "fstpl _memvar" causes a stack overflow.
831 * These are especially nasty when combined with a
833 * o an IRQ13 occurs at the same time as another higher-
834 * priority interrupt.
836 * Treat them like a true async interrupt.
838 ksignal(curproc, SIGFPE);
845 * Implement the device not available (DNA) exception. gd_npxthread had
846 * better be NULL. Restore the current thread's FP state and set gd_npxthread
849 * Interrupts are enabled and preemption can occur. Enter a critical
850 * section to stabilize the FP state.
859 if (mdcpu->gd_npxthread != NULL) {
860 kprintf("npxdna: npxthread = %p, curthread = %p\n",
861 mdcpu->gd_npxthread, curthread);
865 * The setting of gd_npxthread and the call to fpurstor() must not
866 * be preempted by an interrupt thread or we will take an npxdna
867 * trap and potentially save our current fpstate (which is garbage)
868 * and then restore the garbage rather then the originally saved
874 * Record new context early in case frstor causes an IRQ13.
876 mdcpu->gd_npxthread = curthread;
877 exstat = GET_FPU_EXSW_PTR(curthread);
880 * The following frstor may cause an IRQ13 when the state being
881 * restored has a pending error. The error will appear to have been
882 * triggered by the current (npx) user instruction even when that
883 * instruction is a no-wait instruction that should not trigger an
884 * error (e.g., fnclex). On at least one 486 system all of the
885 * no-wait instructions are broken the same as frstor, so our
886 * treatment does not amplify the breakage. On at least one
887 * 386/Cyrix 387 system, fnclex works correctly while frstor and
888 * fnsave are broken, so our treatment breaks fnclex if it is the
889 * first FPU instruction after a context switch.
891 fpurstor(curthread->td_savefpu);
898 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
899 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
900 * any IRQ13 to be handled immediately, and then ignore it. This routine is
901 * often called at splhigh so it must not use many system services. In
902 * particular, it's much easier to install a special handler than to
903 * guarantee that it's safe to use npxintr() and its supporting code.
905 * WARNING! This call is made during a switch and the MP lock will be
906 * setup for the new target thread rather then the current thread, so we
907 * cannot do anything here that depends on the *_mplock() functions as
908 * we may trip over their assertions.
910 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
911 * kernel will always assume that the FP state is 'safe' (will not cause
912 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
913 * setup a custom save area before actually using the FP unit, but it will
914 * not bother calling fninit. This greatly improves kernel performance when
915 * it wishes to use the FP unit.
918 npxsave(union savefpu *addr)
920 #if defined(SMP) || !defined(CPU_DISABLE_SSE)
925 mdcpu->gd_npxthread = NULL;
930 #else /* !SMP and CPU_DISABLE_SSE */
934 u_char old_icu1_mask;
935 u_char old_icu2_mask;
936 struct gate_descriptor save_idt_npxintr;
939 save_eflags = read_eflags();
941 old_icu1_mask = inb(IO_ICU1 + 1);
942 old_icu2_mask = inb(IO_ICU2 + 1);
943 save_idt_npxintr = idt[npx_intrno];
944 outb(IO_ICU1 + 1, old_icu1_mask & ~((1 << ICU_IRQ_SLAVE) | npx0_imask));
945 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
946 idt[npx_intrno] = npx_idt_probeintr;
952 mdcpu->gd_npxthread = NULL;
954 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
955 icu2_mask = inb(IO_ICU2 + 1);
957 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
959 (icu2_mask & ~(npx0_imask >> 8))
960 | (old_icu2_mask & (npx0_imask >> 8)));
961 idt[npx_intrno] = save_idt_npxintr;
962 write_eflags(save_eflags); /* back to usual state */
968 fpusave(union savefpu *addr)
970 #ifndef CPU_DISABLE_SSE
978 #ifndef CPU_DISABLE_SSE
980 * On AuthenticAMD processors, the fxrstor instruction does not restore
981 * the x87's stored last instruction pointer, last data pointer, and last
982 * opcode values, except in the rare case in which the exception summary
983 * (ES) bit in the x87 status word is set to 1.
985 * In order to avoid leaking this information across processes, we clean
986 * these values by performing a dummy load before executing fxrstor().
988 static double dummy_variable = 0.0;
990 fpu_clean_state(void)
995 * Clear the ES bit in the x87 status word if it is currently
996 * set, in order to avoid causing a fault in the upcoming load.
1003 * Load the dummy variable into the x87 stack. This mangles
1004 * the x87 stack, but we don't care since we're about to call
1007 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
1009 #endif /* CPU_DISABLE_SSE */
1012 fpurstor(union savefpu *addr)
1014 #ifndef CPU_DISABLE_SSE
1027 * Because npx is a static device that always exists under nexus,
1028 * and is not scanned by the nexus device, we need an identify
1029 * function to install the device.
1031 static device_method_t npx_methods[] = {
1032 /* Device interface */
1033 DEVMETHOD(device_identify, bus_generic_identify),
1034 DEVMETHOD(device_probe, npx_probe),
1035 DEVMETHOD(device_attach, npx_attach),
1036 DEVMETHOD(device_detach, bus_generic_detach),
1037 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1038 DEVMETHOD(device_suspend, bus_generic_suspend),
1039 DEVMETHOD(device_resume, bus_generic_resume),
1044 static driver_t npx_driver = {
1050 static devclass_t npx_devclass;
1053 * We prefer to attach to the root nexus so that the usual case (exception 16)
1054 * doesn't describe the processor as being `on isa'.
1056 DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);