2 * Copyright (c) 2005, 2006
3 * Damien Bergamini <damien.bergamini@free.fr>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: src/sys/dev/ral/rt2560reg.h,v 1.1 2006/03/05 20:36:56 damien Exp $
18 * $DragonFly: src/sys/dev/netif/ral/rt2560reg.h,v 1.3 2007/02/05 15:19:04 sephe Exp $
21 #define RT2560_DEFAULT_RSSI_CORR 0x79
22 #define RT2560_NOISE_FLOOR -95
24 #define RT2560_TX_RING_COUNT 48
25 #define RT2560_ATIM_RING_COUNT 4
26 #define RT2560_PRIO_RING_COUNT 16
27 #define RT2560_BEACON_RING_COUNT 1
28 #define RT2560_RX_RING_COUNT 32
30 #define RT2560_TX_DESC_SIZE (sizeof (struct rt2560_tx_desc))
31 #define RT2560_RX_DESC_SIZE (sizeof (struct rt2560_rx_desc))
33 #define RT2560_MAX_SCATTER 1
36 * Control and status registers.
38 #define RT2560_CSR0 0x0000 /* ASIC version number */
39 #define RT2560_CSR1 0x0004 /* System control */
40 #define RT2560_CSR3 0x000c /* STA MAC address 0 */
41 #define RT2560_CSR4 0x0010 /* STA MAC address 1 */
42 #define RT2560_CSR5 0x0014 /* BSSID 0 */
43 #define RT2560_CSR6 0x0018 /* BSSID 1 */
44 #define RT2560_CSR7 0x001c /* Interrupt source */
45 #define RT2560_CSR8 0x0020 /* Interrupt mask */
46 #define RT2560_CSR9 0x0024 /* Maximum frame length */
47 #define RT2560_SECCSR0 0x0028 /* WEP control */
48 #define RT2560_CSR11 0x002c /* Back-off control */
49 #define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */
50 #define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */
51 #define RT2560_CSR14 0x0038 /* Synchronization control */
52 #define RT2560_CSR15 0x003c /* Synchronization status */
53 #define RT2560_CSR16 0x0040 /* TSF timer 0 */
54 #define RT2560_CSR17 0x0044 /* TSF timer 1 */
55 #define RT2560_CSR18 0x0048 /* IFS timer 0 */
56 #define RT2560_CSR19 0x004c /* IFS timer 1 */
57 #define RT2560_CSR20 0x0050 /* WAKEUP timer */
58 #define RT2560_CSR21 0x0054 /* EEPROM control */
59 #define RT2560_CSR22 0x0058 /* CFP control */
60 #define RT2560_TXCSR0 0x0060 /* TX control */
61 #define RT2560_TXCSR1 0x0064 /* TX configuration */
62 #define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */
63 #define RT2560_TXCSR3 0x006c /* TX ring base address */
64 #define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */
65 #define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */
66 #define RT2560_TXCSR6 0x0078 /* Beacon base address */
67 #define RT2560_TXCSR7 0x007c /* AutoResponder control */
68 #define RT2560_RXCSR0 0x0080 /* RX control */
69 #define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */
70 #define RT2560_RXCSR2 0x0088 /* RX ring base address */
71 #define RT2560_PCICSR 0x008c /* PCI control */
72 #define RT2560_RXCSR3 0x0090 /* BBP ID 0 */
73 #define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */
74 #define RT2560_TXCSR8 0x0098 /* CCK TX BBP */
75 #define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */
76 #define RT2560_CNT0 0x00a0 /* FCS error counter */
77 #define RT2560_CNT1 0x00ac /* PLCP error counter */
78 #define RT2560_CNT2 0x00b0 /* Long error counter */
79 #define RT2560_CNT3 0x00b8 /* CCA false alarm counter */
80 #define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */
81 #define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */
82 #define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */
83 #define RT2560_PSCSR0 0x00c8 /* Power state transition time */
84 #define RT2560_PSCSR1 0x00cc /* Power state transition time */
85 #define RT2560_PSCSR2 0x00d0 /* Power state transition time */
86 #define RT2560_PSCSR3 0x00d4 /* Power state transition time */
87 #define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */
88 #define RT2560_TIMECSR 0x00dc /* Timer control */
89 #define RT2560_MACCSR0 0x00e0 /* MAC configuration */
90 #define RT2560_MACCSR1 0x00e4 /* MAC configuration */
91 #define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */
92 #define RT2560_BCNCSR 0x00ec /* Beacon interval control */
93 #define RT2560_BBPCSR 0x00f0 /* BBP serial control */
94 #define RT2560_RFCSR 0x00f4 /* RF serial control */
95 #define RT2560_LEDCSR 0x00f8 /* LED control */
96 #define RT2560_SECCSR3 0x00fc /* XXX not documented */
97 #define RT2560_DMACSR0 0x0100 /* Current RX ring address */
98 #define RT2560_DMACSR1 0x0104 /* Current Tx ring address */
99 #define RT2560_DMACSR2 0x0104 /* Current Priority ring address */
100 #define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */
101 #define RT2560_TXACKCSR0 0x0110 /* XXX not documented */
102 #define RT2560_GPIOCSR 0x0120 /* */
103 #define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */
104 #define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */
105 #define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */
106 #define RT2560_BCNOCSR 0x0130 /* Beacon time offset */
107 #define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */
108 #define RT2560_TESTCSR 0x0138 /* Test Mode Select */
109 #define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */
110 #define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */
111 #define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */
112 #define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */
113 #define RT2560_ARTCSR0 0x014c /* ACK/CTS padload consume time
116 #define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time
119 #define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time
122 #define RT2560_SECCSR1 0x0158 /* WEP control */
123 #define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */
126 /* possible flags for register RXCSR0 */
127 #define RT2560_DISABLE_RX (1 << 0)
128 #define RT2560_DROP_CRC_ERROR (1 << 1)
129 #define RT2560_DROP_PHY_ERROR (1 << 2)
130 #define RT2560_DROP_CTL (1 << 3)
131 #define RT2560_DROP_NOT_TO_ME (1 << 4)
132 #define RT2560_DROP_TODS (1 << 5)
133 #define RT2560_DROP_VERSION_ERROR (1 << 6)
135 /* possible flags for register CSR1 */
136 #define RT2560_RESET_ASIC (1 << 0)
137 #define RT2560_RESET_BBP (1 << 1)
138 #define RT2560_HOST_READY (1 << 2)
140 /* possible flags for register CSR14 */
141 #define RT2560_ENABLE_TSF (1 << 0)
142 #define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1)
143 #define RT2560_ENABLE_TBCN (1 << 3)
144 #define RT2560_ENABLE_BEACON_GENERATOR (1 << 6)
146 /* possible flags for register CSR21 */
147 #define RT2560_C (1 << 1)
148 #define RT2560_S (1 << 2)
149 #define RT2560_D (1 << 3)
150 #define RT2560_Q (1 << 4)
151 #define RT2560_93C46 (1 << 5)
153 #define RT2560_SHIFT_D 3
154 #define RT2560_SHIFT_Q 4
156 /* possible flags for register TXCSR0 */
157 #define RT2560_KICK_TX (1 << 0)
158 #define RT2560_KICK_ATIM (1 << 1)
159 #define RT2560_KICK_PRIO (1 << 2)
160 #define RT2560_ABORT_TX (1 << 3)
162 /* possible flags for register SECCSR0 */
163 #define RT2560_KICK_DECRYPT (1 << 0)
165 /* possible flags for register SECCSR1 */
166 #define RT2560_KICK_ENCRYPT (1 << 0)
168 /* possible flags for register CSR7 */
169 #define RT2560_BEACON_EXPIRE 0x00000001
170 #define RT2560_WAKEUP_EXPIRE 0x00000002
171 #define RT2560_ATIM_EXPIRE 0x00000004
172 #define RT2560_TX_DONE 0x00000008
173 #define RT2560_ATIM_DONE 0x00000010
174 #define RT2560_PRIO_DONE 0x00000020
175 #define RT2560_RX_DONE 0x00000040
176 #define RT2560_DECRYPTION_DONE 0x00000080
177 #define RT2560_ENCRYPTION_DONE 0x00000100
179 #define RT2560_INTR_MASK \
180 (~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \
181 RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE | \
182 RT2560_ENCRYPTION_DONE))
185 struct rt2560_tx_desc {
187 #define RT2560_TX_BUSY (1 << 0)
188 #define RT2560_TX_VALID (1 << 1)
190 #define RT2560_TX_RESULT_MASK 0x0000001c
191 #define RT2560_TX_SUCCESS (0 << 2)
192 #define RT2560_TX_SUCCESS_RETRY (1 << 2)
193 #define RT2560_TX_FAIL_RETRY (2 << 2)
194 #define RT2560_TX_FAIL_INVALID (3 << 2)
195 #define RT2560_TX_FAIL_OTHER (4 << 2)
197 #define RT2560_TX_MORE_FRAG (1 << 8)
198 #define RT2560_TX_ACK (1 << 9)
199 #define RT2560_TX_TIMESTAMP (1 << 10)
200 #define RT2560_TX_OFDM (1 << 11)
201 #define RT2560_TX_CIPHER_BUSY (1 << 12)
203 #define RT2560_TX_IFS_MASK 0x00006000
204 #define RT2560_TX_IFS_BACKOFF (0 << 13)
205 #define RT2560_TX_IFS_SIFS (1 << 13)
206 #define RT2560_TX_IFS_NEWBACKOFF (2 << 13)
207 #define RT2560_TX_IFS_NONE (3 << 13)
209 #define RT2560_TX_LONG_RETRY (1 << 15)
211 #define RT2560_TX_CIPHER_MASK 0xe0000000
212 #define RT2560_TX_CIPHER_NONE (0 << 29)
213 #define RT2560_TX_CIPHER_WEP40 (1 << 29)
214 #define RT2560_TX_CIPHER_WEP104 (2 << 29)
215 #define RT2560_TX_CIPHER_TKIP (3 << 29)
216 #define RT2560_TX_CIPHER_AES (4 << 29)
220 #define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12)
221 #define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8)
222 #define RT2560_AIFSN(x) (((x) & 0x3) << 6)
223 #define RT2560_IVOFFSET(x) (((x) & 0x3f))
227 uint8_t plcp_service;
228 #define RT2560_PLCP_LENGEXT 0x80
230 uint8_t plcp_length_lo;
231 uint8_t plcp_length_hi;
234 uint8_t key[IEEE80211_KEYBUF_SIZE];
235 uint32_t reserved2[2];
239 struct rt2560_rx_desc {
241 #define RT2560_RX_BUSY (1 << 0)
242 #define RT2560_RX_CRC_ERROR (1 << 5)
243 #define RT2560_RX_OFDM (1 << 6)
244 #define RT2560_RX_PHY_ERROR (1 << 7)
245 #define RT2560_RX_CIPHER_BUSY (1 << 8)
246 #define RT2560_RX_ICV_ERROR (1 << 9)
248 #define RT2560_RX_CIPHER_MASK 0xe0000000
249 #define RT2560_RX_CIPHER_NONE (0 << 29)
250 #define RT2560_RX_CIPHER_WEP40 (1 << 29)
251 #define RT2560_RX_CIPHER_WEP104 (2 << 29)
252 #define RT2560_RX_CIPHER_TKIP (3 << 29)
253 #define RT2560_RX_CIPHER_AES (4 << 29)
258 uint8_t ta[IEEE80211_ADDR_LEN];
261 uint8_t key[IEEE80211_KEYBUF_SIZE];
262 uint32_t reserved[2];
270 #define RT2560_RF1_AUTOTUNE 0x08000
271 #define RT2560_RF3_AUTOTUNE 0x00040
273 #define RT2560_BBP_BUSY (1 << 15)
274 #define RT2560_BBP_WRITE (1 << 16)
275 #define RT2560_RF_20BIT (20 << 24)
276 #define RT2560_RF_BUSY (1 << 31)
278 #define RT2560_RF_2522 0x00
279 #define RT2560_RF_2523 0x01
280 #define RT2560_RF_2524 0x02
281 #define RT2560_RF_2525 0x03
282 #define RT2560_RF_2525E 0x04
283 #define RT2560_RF_2526 0x05
285 #define RT2560_RF_5222 0x10
287 #define RT2560_BBP_VERSION 0
288 #define RT2560_BBP_TX 2
289 #define RT2560_BBP_RX 14
291 #define RT2560_BBP_ANTA 0x00
292 #define RT2560_BBP_DIVERSITY 0x01
293 #define RT2560_BBP_ANTB 0x02
294 #define RT2560_BBP_ANTMASK 0x03
295 #define RT2560_BBP_FLIPIQ 0x04
297 #define RT2560_LED_MODE_DEFAULT 0
298 #define RT2560_LED_MODE_TXRX_ACTIVITY 1
299 #define RT2560_LED_MODE_SINGLE 2
300 #define RT2560_LED_MODE_ASUS 3
302 #define RT2560_JAPAN_FILTER 0x8
304 #define RT2560_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
306 #define RT2560_EEPROM_CONFIG0 16
307 #define RT2560_EEPROM_BBP_BASE 19
308 #define RT2560_EEPROM_TXPOWER 35
309 #define RT2560_EEPROM_CALIBRATE 62
312 * control and status registers access macros
314 #define RAL_READ(sc, reg) \
315 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
317 #define RAL_WRITE(sc, reg, val) \
318 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
321 * EEPROM access macro
323 #define RT2560_EEPROM_CTL(sc, val) do { \
324 RAL_WRITE((sc), RT2560_CSR21, (val)); \
325 DELAY(RT2560_EEPROM_DELAY); \
326 } while (/* CONSTCOND */0)
329 * Default values for MAC registers; values taken from the reference driver.
331 #define RT2560_DEF_MAC \
332 { RT2560_PSCSR0, 0x00020002 }, \
333 { RT2560_PSCSR1, 0x00000002 }, \
334 { RT2560_PSCSR2, 0x00020002 }, \
335 { RT2560_PSCSR3, 0x00000002 }, \
336 { RT2560_TIMECSR, 0x00003f21 }, \
337 { RT2560_CSR9, 0x00000780 }, \
338 { RT2560_CSR11, 0x07041483 }, \
339 { RT2560_CNT3, 0x00000000 }, \
340 { RT2560_TXCSR1, 0x07614562 }, \
341 { RT2560_TXCSR8, 0x8c8d8b8a }, \
342 { RT2560_ARTCSR0, 0x7038140a }, \
343 { RT2560_ARTCSR1, 0x1d21252d }, \
344 { RT2560_ARTCSR2, 0x1919191d }, \
345 { RT2560_RXCSR0, 0xffffffff }, \
346 { RT2560_RXCSR3, 0xb3aab3af }, \
347 { RT2560_PCICSR, 0x000003b8 }, \
348 { RT2560_PWRCSR0, 0x3f3b3100 }, \
349 { RT2560_GPIOCSR, 0x0000ff00 }, \
350 { RT2560_TESTCSR, 0x000000f0 }, \
351 { RT2560_PWRCSR1, 0x000001ff }, \
352 { RT2560_MACCSR0, 0x00213223 }, \
353 { RT2560_MACCSR1, 0x00235518 }, \
354 { RT2560_RLPWCSR, 0x00000040 }, \
355 { RT2560_RALINKCSR, 0x9a009a11 }, \
356 { RT2560_CSR7, 0xffffffff }, \
357 { RT2560_BBPCSR1, 0x82188200 }, \
358 { RT2560_TXACKCSR0, 0x00000020 }, \
359 { RT2560_SECCSR3, 0x0000e78f }
362 * Default values for BBP registers; values taken from the reference driver.
364 #define RT2560_DEF_BBP \
399 * Default values for RF register R2 indexed by channel numbers; values taken
400 * from the reference driver.
402 #define RT2560_RF2522_R2 \
404 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \
405 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \
408 #define RT2560_RF2523_R2 \
410 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
411 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
414 #define RT2560_RF2524_R2 \
416 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
417 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
420 #define RT2560_RF2525_R2 \
422 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \
423 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \
426 #define RT2560_RF2525_HI_R2 \
428 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \
429 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \
432 #define RT2560_RF2525E_R2 \
434 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \
435 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \
438 #define RT2560_RF2526_HI_R2 \
440 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \
441 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \
444 #define RT2560_RF2526_R2 \
446 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \
447 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \
451 * For dual-band RF, RF registers R1 and R4 also depend on channel number;
452 * values taken from the reference driver.
454 #define RT2560_RF5222 \
455 { 1, 0x08808, 0x0044d, 0x00282 }, \
456 { 2, 0x08808, 0x0044e, 0x00282 }, \
457 { 3, 0x08808, 0x0044f, 0x00282 }, \
458 { 4, 0x08808, 0x00460, 0x00282 }, \
459 { 5, 0x08808, 0x00461, 0x00282 }, \
460 { 6, 0x08808, 0x00462, 0x00282 }, \
461 { 7, 0x08808, 0x00463, 0x00282 }, \
462 { 8, 0x08808, 0x00464, 0x00282 }, \
463 { 9, 0x08808, 0x00465, 0x00282 }, \
464 { 10, 0x08808, 0x00466, 0x00282 }, \
465 { 11, 0x08808, 0x00467, 0x00282 }, \
466 { 12, 0x08808, 0x00468, 0x00282 }, \
467 { 13, 0x08808, 0x00469, 0x00282 }, \
468 { 14, 0x08808, 0x0046b, 0x00286 }, \
470 { 36, 0x08804, 0x06225, 0x00287 }, \
471 { 40, 0x08804, 0x06226, 0x00287 }, \
472 { 44, 0x08804, 0x06227, 0x00287 }, \
473 { 48, 0x08804, 0x06228, 0x00287 }, \
474 { 52, 0x08804, 0x06229, 0x00287 }, \
475 { 56, 0x08804, 0x0622a, 0x00287 }, \
476 { 60, 0x08804, 0x0622b, 0x00287 }, \
477 { 64, 0x08804, 0x0622c, 0x00287 }, \
479 { 100, 0x08804, 0x02200, 0x00283 }, \
480 { 104, 0x08804, 0x02201, 0x00283 }, \
481 { 108, 0x08804, 0x02202, 0x00283 }, \
482 { 112, 0x08804, 0x02203, 0x00283 }, \
483 { 116, 0x08804, 0x02204, 0x00283 }, \
484 { 120, 0x08804, 0x02205, 0x00283 }, \
485 { 124, 0x08804, 0x02206, 0x00283 }, \
486 { 128, 0x08804, 0x02207, 0x00283 }, \
487 { 132, 0x08804, 0x02208, 0x00283 }, \
488 { 136, 0x08804, 0x02209, 0x00283 }, \
489 { 140, 0x08804, 0x0220a, 0x00283 }, \
491 { 149, 0x08808, 0x02429, 0x00281 }, \
492 { 153, 0x08808, 0x0242b, 0x00281 }, \
493 { 157, 0x08808, 0x0242d, 0x00281 }, \
494 { 161, 0x08808, 0x0242f, 0x00281 }