2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved.
3 * Copyright (c) 2008 Jordan Gordeev.
5 * This code is derived from software contributed to The DragonFly Project
6 * by Matthew Dillon <dillon@backplane.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * Copyright (c) 1990 The Regents of the University of California.
36 * All rights reserved.
38 * This code is derived from software contributed to Berkeley by
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by the University of
52 * California, Berkeley and its contributors.
53 * 4. Neither the name of the University nor the names of its contributors
54 * may be used to endorse or promote products derived from this software
55 * without specific prior written permission.
57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $
70 * $DragonFly: src/sys/platform/pc64/amd64/swtch.s,v 1.3 2008/08/29 17:07:10 dillon Exp $
73 //#include "use_npx.h"
75 #include <sys/rtprio.h>
77 #include <machine/asmacros.h>
78 #include <machine/segments.h>
80 #include <machine/pmap.h>
82 #include <machine_base/apic/apicreg.h>
84 #include <machine/lock.h>
86 #define CHECKNZ(expr, scratch_reg) \
87 movq expr, scratch_reg; testq scratch_reg, scratch_reg; jnz 7f; int $3; 7:
92 #define MPLOCKED lock ;
101 #if defined(SWTCH_OPTIM_STATS)
102 .globl swtch_optim_stats, tlb_flush_count
103 swtch_optim_stats: .long 0 /* number of _swtch_optims */
104 tlb_flush_count: .long 0
111 * cpu_heavy_switch(struct thread *next_thread)
113 * Switch from the current thread to a new thread. This entry
114 * is normally called via the thread->td_switch function, and will
115 * only be called when the current thread is a heavy weight process.
117 * Some instructions have been reordered to reduce pipeline stalls.
119 * YYY disable interrupts once giant is removed.
121 ENTRY(cpu_heavy_switch)
123 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15).
125 movq PCPU(curthread),%rcx
126 /* On top of the stack is the return adress. */
127 movq (%rsp),%rax /* (reorder optimization) */
128 movq TD_PCB(%rcx),%rdx /* RDX = PCB */
129 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */
130 movq %rbx,PCB_RBX(%rdx)
131 movq %rsp,PCB_RSP(%rdx)
132 movq %rbp,PCB_RBP(%rdx)
133 movq %r12,PCB_R12(%rdx)
134 movq %r13,PCB_R13(%rdx)
135 movq %r14,PCB_R14(%rdx)
136 movq %r15,PCB_R15(%rdx)
138 movq %rcx,%rbx /* RBX = curthread */
139 movq TD_LWP(%rcx),%rcx
140 movl PCPU(cpuid), %eax
141 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */
142 MPLOCKED btrl %eax, VM_PMAP+PM_ACTIVE(%rcx)
145 * Push the LWKT switch restore function, which resumes a heavy
146 * weight process. Note that the LWKT switcher is based on
147 * TD_SP, while the heavy weight process switcher is based on
148 * PCB_RSP. TD_SP is usually two ints pushed relative to
149 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore.
152 movq $cpu_heavy_restore, %rax
154 movq %rsp,TD_SP(%rbx)
158 * Save debug regs if necessary
160 movb PCB_FLAGS(%edx),%al
162 jz 1f /* no, skip over */
163 movl %dr7,%eax /* yes, do the save */
164 movl %eax,PCB_DR7(%edx)
165 andl $0x0000fc00, %eax /* disable all watchpoints */
168 movl %eax,PCB_DR6(%edx)
170 movl %eax,PCB_DR3(%edx)
172 movl %eax,PCB_DR2(%edx)
174 movl %eax,PCB_DR1(%edx)
176 movl %eax,PCB_DR0(%edx)
183 * Save the FP state if we have used the FP. Note that calling
184 * npxsave will NULL out PCPU(npxthread).
186 cmpl %ebx,PCPU(npxthread)
188 pushl TD_SAVEFPU(%ebx)
189 call npxsave /* do it in a big C function */
190 addl $4,%esp /* EAX, ECX, EDX trashed */
193 #endif /* NNPX > 0 */
196 * Switch to the next thread, which was passed as an argument
197 * to cpu_heavy_switch(). The argument is in %rdi.
198 * Set the current thread, load the stack pointer,
199 * and 'ret' into the switch-restore function.
201 * The switch restore function expects the new thread to be in %rax
202 * and the old one to be in %rbx.
204 * There is a one-instruction window where curthread is the new
205 * thread but %rsp still points to the old thread's stack, but
206 * we are protected by a critical section so it is ok.
208 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */
209 movq %rax,PCPU(curthread)
210 movq TD_SP(%rax),%rsp
215 * cpu_exit_switch(struct thread *next)
217 * The switch function is changed to this when a thread is going away
218 * for good. We have to ensure that the MMU state is not cached, and
219 * we don't bother saving the existing thread state before switching.
221 * At this point we are in a critical section and this cpu owns the
222 * thread's token, which serves as an interlock until the switchout is
225 ENTRY(cpu_exit_switch)
227 * Get us out of the vmspace
233 /* JG no increment of statistics counters? see cpu_heavy_restore */
238 orq $(PG_RW|PG_V), %rcx
244 movq PCPU(curthread),%rbx
247 * If this is a process/lwp, deactivate the pmap after we've
250 movq TD_LWP(%rbx),%rcx
253 movl PCPU(cpuid), %eax
254 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */
255 MPLOCKED btrl %eax, VM_PMAP+PM_ACTIVE(%rcx)
258 * Switch to the next thread. RET into the restore function, which
259 * expects the new thread in RAX and the old in RBX.
261 * There is a one-instruction window where curthread is the new
262 * thread but %rsp still points to the old thread's stack, but
263 * we are protected by a critical section so it is ok.
266 movq %rax,PCPU(curthread)
267 movq TD_SP(%rax),%rsp
272 * cpu_heavy_restore() (current thread in %rax on entry)
274 * Restore the thread after an LWKT switch. This entry is normally
275 * called via the LWKT switch restore function, which was pulled
276 * off the thread stack and jumped to.
278 * This entry is only called if the thread was previously saved
279 * using cpu_heavy_switch() (the heavy weight process thread switcher),
280 * or when a new process is initially scheduled. The first thing we
281 * do is clear the TDF_RUNNING bit in the old thread and set it in the
284 * NOTE: The lwp may be in any state, not necessarily LSRUN, because
285 * a preemption switch may interrupt the process and then return via
288 * YYY theoretically we do not have to restore everything here, a lot
289 * of this junk can wait until we return to usermode. But for now
290 * we restore everything.
292 * YYY the PCB crap is really crap, it makes startup a bitch because
293 * we can't switch away.
295 * YYY note: spl check is done in mi_switch when it splx()'s.
298 ENTRY(cpu_heavy_restore)
300 movq TD_PCB(%rax),%rdx /* RDX = PCB */
301 movq TD_LWP(%rax),%rcx
303 #if defined(SWTCH_OPTIM_STATS)
304 incl _swtch_optim_stats
307 * Tell the pmap that our cpu is using the VMSPACE now. We cannot
308 * safely test/reload %cr3 until after we have set the bit in the
309 * pmap (remember, we do not hold the MP lock in the switch code).
311 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */
312 movl PCPU(cpuid), %esi
313 MPLOCKED btsl %esi, VM_PMAP+PM_ACTIVE(%rcx)
316 * Restore the MMU address space. If it is the same as the last
317 * thread we don't have to invalidate the tlb (i.e. reload cr3).
318 * YYY which naturally also means that the PM_ACTIVE bit had better
319 * already have been set before we set it above, check? YYY
323 movq PCB_CR3(%rdx),%rcx
326 #if defined(SWTCH_OPTIM_STATS)
327 decl _swtch_optim_stats
328 incl _tlb_flush_count
333 movq PCB_CR3(%rdx),%rcx
334 orq $(PG_RW|PG_U|PG_V), %rcx
342 * Clear TDF_RUNNING flag in old thread only after cleaning up
343 * %cr3. The target thread is already protected by being TDF_RUNQ
344 * so setting TDF_RUNNING isn't as big a deal.
346 andl $~TDF_RUNNING,TD_FLAGS(%rbx)
347 orl $TDF_RUNNING,TD_FLAGS(%rax)
350 * Deal with the PCB extension, restore the private tss
352 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */
353 /* JG cheaper than "movq $1,%rbx", right? */
354 /* JG what's that magic value $1? */
355 movl $1,%ebx /* maybe mark use of a private tss */
362 * Going back to the common_tss. We may need to update TSS_ESP0
363 * which sets the top of the supervisor stack when entering from
364 * usermode. The PCB is at the top of the stack but we need another
365 * 16 bytes to take vm86 into account.
369 movl %ebx, PCPU(common_tss) + TSS_ESP0
371 cmpl $0,PCPU(private_tss) /* don't have to reload if */
372 je 3f /* already using the common TSS */
375 subl %ebx,%ebx /* unmark use of private tss */
378 * Get the address of the common TSS descriptor for the ltr.
379 * There is no way to get the address of a segment-accessed variable
380 * so we store a self-referential pointer at the base of the per-cpu
381 * data area and add the appropriate offset.
384 movq $gd_common_tssd, %rdi
385 /* JG name for "%gs:0"? */
389 * Move the correct TSS descriptor into the GDT slot, then reload
394 movl %ebx,PCPU(private_tss) /* mark/unmark private tss */
395 movq PCPU(tss_gdt), %rbx /* entry in GDT */
398 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */
404 * Restore the user %gs and %fs
406 movq PCB_FSBASE(%rdx),%r9
407 cmpq PCPU(user_fs),%r9
410 movq %r9,PCPU(user_fs)
411 movl $MSR_FSBASE,%ecx
412 movl PCB_FSBASE(%r10),%eax
413 movl PCB_FSBASE+4(%r10),%edx
417 movq PCB_GSBASE(%rdx),%r9
418 cmpq PCPU(user_gs),%r9
421 movq %r9,PCPU(user_gs)
422 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */
423 movl PCB_GSBASE(%r10),%eax
424 movl PCB_GSBASE+4(%r10),%edx
430 * Restore general registers.
432 movq PCB_RBX(%rdx), %rbx
433 movq PCB_RSP(%rdx), %rsp
434 movq PCB_RBP(%rdx), %rbp
435 movq PCB_R12(%rdx), %r12
436 movq PCB_R13(%rdx), %r13
437 movq PCB_R14(%rdx), %r14
438 movq PCB_R15(%rdx), %r15
439 movq PCB_RIP(%rdx), %rax
444 * Restore the user LDT if we have one
446 cmpl $0, PCB_USERLDT(%edx)
448 movl _default_ldt,%eax
449 cmpl PCPU(currentldt),%eax
452 movl %eax,PCPU(currentldt)
461 * Restore the user TLS if we have one
470 * Restore the DEBUG register state if necessary.
472 movb PCB_FLAGS(%edx),%al
474 jz 1f /* no, skip over */
475 movl PCB_DR6(%edx),%eax /* yes, do the restore */
477 movl PCB_DR3(%edx),%eax
479 movl PCB_DR2(%edx),%eax
481 movl PCB_DR1(%edx),%eax
483 movl PCB_DR0(%edx),%eax
485 movl %dr7,%eax /* load dr7 so as not to disturb */
486 andl $0x0000fc00,%eax /* reserved bits */
488 movl PCB_DR7(%edx),%ebx
489 andl $~0x0000fc00,%ebx
500 * savectx(struct pcb *pcb)
502 * Update pcb, saving current processor state.
506 /* JG use %rdi instead of %rcx everywhere? */
509 /* caller's return address - child won't execute this routine */
511 movq %rax,PCB_RIP(%rcx)
516 movq $0x000ffffffffff000, %rcx
521 movq %rax,PCB_CR3(%rcx)
523 movq %rbx,PCB_RBX(%rcx)
524 movq %rsp,PCB_RSP(%rcx)
525 movq %rbp,PCB_RBP(%rcx)
526 movq %r12,PCB_R12(%rcx)
527 movq %r13,PCB_R13(%rcx)
528 movq %r14,PCB_R14(%rcx)
529 movq %r15,PCB_R15(%rcx)
534 * If npxthread == NULL, then the npx h/w state is irrelevant and the
535 * state had better already be in the pcb. This is true for forks
536 * but not for dumps (the old book-keeping with FP flags in the pcb
537 * always lost for dumps because the dump pcb has 0 flags).
539 * If npxthread != NULL, then we have to save the npx h/w state to
540 * npxthread's pcb and copy it to the requested pcb, or save to the
541 * requested pcb and reload. Copying is easier because we would
542 * have to handle h/w bugs for reloading. We used to lose the
543 * parent's npx state for forks by forgetting to reload.
545 movl PCPU(npxthread),%eax
549 pushl %ecx /* target pcb */
550 movl TD_SAVEFPU(%eax),%eax /* originating savefpu area */
560 pushl $PCB_SAVEFPU_SIZE
561 leal PCB_SAVEFPU(%ecx),%ecx
566 #endif /* NNPX > 0 */
574 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution)
576 * Don't bother setting up any regs other than %rbp so backtraces
577 * don't die. This restore function is used to bootstrap into the
578 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for
581 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3.
583 * If we are an AP we have to call ap_init() before jumping to
584 * cpu_idle(). ap_init() will synchronize with the BP and finish
585 * setting up various ncpu-dependant globaldata fields. This may
586 * happen on UP as well as SMP if we happen to be simulating multiple
589 ENTRY(cpu_idle_restore)
596 orq $(PG_RW|PG_V), %rcx
601 andl $~TDF_RUNNING,TD_FLAGS(%rbx)
602 orl $TDF_RUNNING,TD_FLAGS(%rax)
610 * ap_init can decide to enable interrupts early, but otherwise, or if
611 * we are UP, do it here.
617 * cpu_kthread_restore() (current thread is %rax on entry) (one-time execution)
619 * Don't bother setting up any regs other then %rbp so backtraces
620 * don't die. This restore function is used to bootstrap into an
621 * LWKT based kernel thread only. cpu_lwkt_switch() will be used
624 * Since all of our context is on the stack we are reentrant and
625 * we can release our critical section and enable interrupts early.
627 ENTRY(cpu_kthread_restore)
630 movq TD_PCB(%rax),%rdx
631 /* JG "movq $0, %rbp"? "xorq %rbp, %rbp"? */
633 orq $(PG_RW|PG_V), %rcx
638 /* rax and rbx come from the switchout code */
639 andl $~TDF_RUNNING,TD_FLAGS(%rbx)
640 orl $TDF_RUNNING,TD_FLAGS(%rax)
641 subl $TDPRI_CRIT,TD_PRI(%rax)
642 movq PCB_R12(%rdx),%rdi /* argument to RBX function */
643 movq PCB_RBX(%rdx),%rax /* thread function */
644 /* note: top of stack return address inherited by function */
649 * cpu_lwkt_switch(struct thread *)
651 * Standard LWKT switching function. Only non-scratch registers are
652 * saved and we don't bother with the MMU state or anything else.
654 * This function is always called while in a critical section.
656 * There is a one-instruction window where curthread is the new
657 * thread but %rsp still points to the old thread's stack, but
658 * we are protected by a critical section so it is ok.
662 ENTRY(cpu_lwkt_switch)
663 pushq %rbp /* JG note: GDB hacked to locate ebp relative to td_sp */
664 /* JG we've got more registers on AMD64 */
666 movq PCPU(curthread),%rbx
676 * Save the FP state if we have used the FP. Note that calling
677 * npxsave will NULL out PCPU(npxthread).
679 * We have to deal with the FP state for LWKT threads in case they
680 * happen to get preempted or block while doing an optimized
681 * bzero/bcopy/memcpy.
683 cmpl %ebx,PCPU(npxthread)
685 pushl TD_SAVEFPU(%ebx)
686 call npxsave /* do it in a big C function */
687 addl $4,%esp /* EAX, ECX, EDX trashed */
689 #endif /* NNPX > 0 */
692 movq %rdi,%rax /* switch to this thread */
693 pushq $cpu_lwkt_restore
694 movq %rsp,TD_SP(%rbx)
695 movq %rax,PCPU(curthread)
696 movq TD_SP(%rax),%rsp
699 * %rax contains new thread, %rbx contains old thread.
705 * cpu_lwkt_restore() (current thread in %rax on entry)
707 * Standard LWKT restore function. This function is always called
708 * while in a critical section.
710 * Warning: due to preemption the restore function can be used to
711 * 'return' to the original thread. Interrupt disablement must be
712 * protected through the switch so we cannot run splz here.
714 * YYY we theoretically do not need to load KPML4phys into cr3, but if
715 * so we need a way to detect when the PTD we are using is being
716 * deleted due to a process exiting.
718 ENTRY(cpu_lwkt_restore)
720 movq common_lvl4_phys,%rcx /* YYY borrow but beware desched/cpuchg/exit */
723 orq $(PG_RW|PG_V), %rcx
735 andl $~TDF_RUNNING,TD_FLAGS(%rbx)
736 orl $TDF_RUNNING,TD_FLAGS(%rax)