kernel/printcpuinfo(): Sync feature bit descriptions with FreeBSD.
[dragonfly.git] / sys / platform / pc32 / i386 / identcpu.c
1 /*-
2  * Copyright (c) 1992 Terrence R. Lambert.
3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4  * Copyright (c) 1997 KATO Takenori.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to Berkeley by
8  * William Jolitz.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *      This product includes software developed by the University of
21  *      California, Berkeley and its contributors.
22  * 4. Neither the name of the University nor the names of its contributors
23  *    may be used to endorse or promote products derived from this software
24  *    without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39  * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.206 2009/11/12 10:59:00 nyan
40  */
41 #include "opt_cpu.h"
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/sysctl.h>
47 #include <sys/lock.h>
48
49 #include <machine/asmacros.h>
50 #include <machine/clock.h>
51 #include <machine/cputypes.h>
52 #include <machine/segments.h>
53 #include <machine/specialreg.h>
54 #include <machine/md_var.h>
55 #include <machine/intr_machdep.h>
56
57 #define IDENTBLUE_CYRIX486      0
58 #define IDENTBLUE_IBMCPU        1
59 #define IDENTBLUE_CYRIXM2       2
60
61 /* XXX - should be in header file: */
62 void printcpuinfo(void);
63 void finishidentcpu(void);
64 void earlysetcpuclass(void);
65 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
66 void    enable_K5_wt_alloc(void);
67 void    enable_K6_wt_alloc(void);
68 void    enable_K6_2_wt_alloc(void);
69 #endif
70 void panicifcpuunsupported(void);
71
72 static void identifycyrix(void);
73 static void init_exthigh(void);
74 static u_int find_cpu_vendor_id(void);
75 static void print_AMD_info(void);
76 static void print_INTEL_info(void);
77 static void print_INTEL_TLB(u_int data);
78 static void print_AMD_assoc(int i);
79 static void print_transmeta_info(void);
80 static void print_via_padlock_info(void);
81
82 int     cpu_class;
83 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
84 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
85 char machine[] = MACHINE;
86 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
87     machine, 0, "Machine class");
88
89 static char cpu_model[128];
90 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
91     cpu_model, 0, "Machine model");
92
93 static int hw_clockrate;
94 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
95     &hw_clockrate, 0, "CPU instruction clock rate");
96
97 static char cpu_brand[48];
98
99 #define MAX_ADDITIONAL_INFO     16
100
101 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
102 static u_int additional_cpu_info_count;
103
104 #define MAX_BRAND_INDEX 8
105
106 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
107         NULL,                   /* No brand */
108         "Intel Celeron",
109         "Intel Pentium III",
110         "Intel Pentium III Xeon",
111         NULL,
112         NULL,
113         NULL,
114         NULL,
115         "Intel Pentium 4"
116 };
117
118 static struct {
119         char    *cpu_name;
120         int     cpu_class;
121 } i386_cpus[] = {
122         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
123         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
124         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
125         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
126         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
127         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
128         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
129         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
130         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
131         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
132         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
133         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
134         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
135         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
136         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
137         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
138         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
139 };
140
141 static struct {
142         char    *vendor;
143         u_int   vendor_id;
144 } cpu_vendors[] = {
145         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
146         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
147         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
148         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
149         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
150         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
151         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
152         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
153         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
154         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
155 #if 0
156         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
157         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
158 #endif
159 };
160
161 #ifdef foo
162 static int cpu_cores;
163 static int cpu_logical;
164 #endif
165
166 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
167 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
168 #endif
169
170 static void
171 init_exthigh(void)
172 {
173         static int done = 0;
174         u_int regs[4];
175
176         if (done == 0) {
177                 if (cpu_high > 0 &&
178                     (cpu_vendor_id == CPU_VENDOR_INTEL ||
179                     cpu_vendor_id == CPU_VENDOR_AMD ||
180                     cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
181                     cpu_vendor_id == CPU_VENDOR_CENTAUR ||
182                     cpu_vendor_id == CPU_VENDOR_NSC)) {
183                         do_cpuid(0x80000000, regs);
184                         if (regs[0] >= 0x80000000)
185                                 cpu_exthigh = regs[0];
186                 }
187
188                 done = 1;
189         }
190 }
191
192 void
193 printcpuinfo(void)
194 {
195         u_int regs[4], i;
196         char *brand;
197
198         cpu_class = i386_cpus[cpu].cpu_class;
199         kprintf("CPU: ");
200         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
201
202         /* Check for extended CPUID information and a processor name. */
203         init_exthigh();
204         if (cpu_exthigh >= 0x80000004) {
205                 brand = cpu_brand;
206                 for (i = 0x80000002; i < 0x80000005; i++) {
207                         do_cpuid(i, regs);
208                         memcpy(brand, regs, sizeof(regs));
209                         brand += sizeof(regs);
210                 }
211         }
212
213         if (cpu_vendor_id == CPU_VENDOR_INTEL) {
214                 if ((cpu_id & 0xf00) > 0x300) {
215                         u_int brand_index;
216
217                         cpu_model[0] = '\0';
218
219                         switch (cpu_id & 0x3000) {
220                         case 0x1000:
221                                 strcpy(cpu_model, "Overdrive ");
222                                 break;
223                         case 0x2000:
224                                 strcpy(cpu_model, "Dual ");
225                                 break;
226                         }
227
228                         switch (cpu_id & 0xf00) {
229                         case 0x400:
230                                 strcat(cpu_model, "i486 ");
231                                 /* Check the particular flavor of 486 */
232                                 switch (cpu_id & 0xf0) {
233                                 case 0x00:
234                                 case 0x10:
235                                         strcat(cpu_model, "DX");
236                                         break;
237                                 case 0x20:
238                                         strcat(cpu_model, "SX");
239                                         break;
240                                 case 0x30:
241                                         strcat(cpu_model, "DX2");
242                                         break;
243                                 case 0x40:
244                                         strcat(cpu_model, "SL");
245                                         break;
246                                 case 0x50:
247                                         strcat(cpu_model, "SX2");
248                                         break;
249                                 case 0x70:
250                                         strcat(cpu_model,
251                                             "DX2 Write-Back Enhanced");
252                                         break;
253                                 case 0x80:
254                                         strcat(cpu_model, "DX4");
255                                         break;
256                                 }
257                                 break;
258                         case 0x500:
259                                 /* Check the particular flavor of 586 */
260                                 strcat(cpu_model, "Pentium");
261                                 switch (cpu_id & 0xf0) {
262                                 case 0x00:
263                                         strcat(cpu_model, " A-step");
264                                         break;
265                                 case 0x10:
266                                         strcat(cpu_model, "/P5");
267                                         break;
268                                 case 0x20:
269                                         strcat(cpu_model, "/P54C");
270                                         break;
271                                 case 0x30:
272                                         strcat(cpu_model, "/P24T");
273                                         break;
274                                 case 0x40:
275                                         strcat(cpu_model, "/P55C");
276                                         break;
277                                 case 0x70:
278                                         strcat(cpu_model, "/P54C");
279                                         break;
280                                 case 0x80:
281                                         strcat(cpu_model, "/P55C (quarter-micron)");
282                                         break;
283                                 default:
284                                         /* nothing */
285                                         break;
286                                 }
287 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
288                                 /*
289                                  * XXX - If/when Intel fixes the bug, this
290                                  * should also check the version of the
291                                  * CPU, not just that it's a Pentium.
292                                  */
293                                 has_f00f_bug = 1;
294 #endif
295                                 break;
296                         case 0x600:
297                                 /* Check the particular flavor of 686 */
298                                 switch (cpu_id & 0xf0) {
299                                 case 0x00:
300                                         strcat(cpu_model, "Pentium Pro A-step");
301                                         break;
302                                 case 0x10:
303                                         strcat(cpu_model, "Pentium Pro");
304                                         break;
305                                 case 0x30:
306                                 case 0x50:
307                                 case 0x60:
308                                         strcat(cpu_model,
309                                 "Pentium II/Pentium II Xeon/Celeron");
310                                         cpu = CPU_PII;
311                                         break;
312                                 case 0x70:
313                                 case 0x80:
314                                 case 0xa0:
315                                 case 0xb0:
316                                         strcat(cpu_model,
317                                         "Pentium III/Pentium III Xeon/Celeron");
318                                         cpu = CPU_PIII;
319                                         break;
320                                 default:
321                                         strcat(cpu_model, "Unknown 80686");
322                                         break;
323                                 }
324                                 break;
325                         case 0xf00:
326                                 strcat(cpu_model, "Pentium 4");
327                                 cpu = CPU_P4;
328                                 break;
329                         default:
330                                 strcat(cpu_model, "unknown");
331                                 break;
332                         }
333
334                         /*
335                          * If we didn't get a brand name from the extended
336                          * CPUID, try to look it up in the brand table.
337                          */
338                         if (cpu_high > 0 && *cpu_brand == '\0') {
339                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
340                                 if (brand_index <= MAX_BRAND_INDEX &&
341                                     cpu_brandtable[brand_index] != NULL)
342                                         strcpy(cpu_brand,
343                                             cpu_brandtable[brand_index]);
344                         }
345                 }
346         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
347                 /*
348                  * Values taken from AMD Processor Recognition
349                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
350                  * (also describes ``Features'' encodings.
351                  */
352                 strcpy(cpu_model, "AMD ");
353                 switch (cpu_id & 0xFF0) {
354                 case 0x410:
355                         strcat(cpu_model, "Standard Am486DX");
356                         break;
357                 case 0x430:
358                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
359                         break;
360                 case 0x470:
361                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
362                         break;
363                 case 0x480:
364                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
365                         break;
366                 case 0x490:
367                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
368                         break;
369                 case 0x4E0:
370                         strcat(cpu_model, "Am5x86 Write-Through");
371                         break;
372                 case 0x4F0:
373                         strcat(cpu_model, "Am5x86 Write-Back");
374                         break;
375                 case 0x500:
376                         strcat(cpu_model, "K5 model 0");
377                         tsc_is_broken = 1;
378                         break;
379                 case 0x510:
380                         strcat(cpu_model, "K5 model 1");
381                         break;
382                 case 0x520:
383                         strcat(cpu_model, "K5 PR166 (model 2)");
384                         break;
385                 case 0x530:
386                         strcat(cpu_model, "K5 PR200 (model 3)");
387                         break;
388                 case 0x560:
389                         strcat(cpu_model, "K6");
390                         break;
391                 case 0x570:
392                         strcat(cpu_model, "K6 266 (model 1)");
393                         break;
394                 case 0x580:
395                         strcat(cpu_model, "K6-2");
396                         break;
397                 case 0x590:
398                         strcat(cpu_model, "K6-III");
399                         break;
400                 case 0x5a0:
401                         strcat(cpu_model, "Geode LX");
402                         /*
403                          * Make sure the TSC runs through suspension,
404                          * otherwise we can't use it as timecounter
405                          */
406                         wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
407                         break;
408                 default:
409                         strcat(cpu_model, "Unknown");
410                         break;
411                 }
412 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
413                 if ((cpu_id & 0xf00) == 0x500) {
414                         if (((cpu_id & 0x0f0) > 0)
415                             && ((cpu_id & 0x0f0) < 0x60)
416                             && ((cpu_id & 0x00f) > 3))
417                                 enable_K5_wt_alloc();
418                         else if (((cpu_id & 0x0f0) > 0x80)
419                                  || (((cpu_id & 0x0f0) == 0x80)
420                                      && (cpu_id & 0x00f) > 0x07))
421                                 enable_K6_2_wt_alloc();
422                         else if ((cpu_id & 0x0f0) > 0x50)
423                                 enable_K6_wt_alloc();
424                 }
425 #endif
426         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
427                 strcpy(cpu_model, "Cyrix ");
428                 switch (cpu_id & 0xff0) {
429                 case 0x440:
430                         strcat(cpu_model, "MediaGX");
431                         break;
432                 case 0x520:
433                         strcat(cpu_model, "6x86");
434                         break;
435                 case 0x540:
436                         cpu_class = CPUCLASS_586;
437                         strcat(cpu_model, "GXm");
438                         break;
439                 case 0x600:
440                         strcat(cpu_model, "6x86MX");
441                         break;
442                 default:
443                         /*
444                          * Even though CPU supports the cpuid
445                          * instruction, it can be disabled.
446                          * Therefore, this routine supports all Cyrix
447                          * CPUs.
448                          */
449                         switch (cyrix_did & 0xf0) {
450                         case 0x00:
451                                 switch (cyrix_did & 0x0f) {
452                                 case 0x00:
453                                         strcat(cpu_model, "486SLC");
454                                         break;
455                                 case 0x01:
456                                         strcat(cpu_model, "486DLC");
457                                         break;
458                                 case 0x02:
459                                         strcat(cpu_model, "486SLC2");
460                                         break;
461                                 case 0x03:
462                                         strcat(cpu_model, "486DLC2");
463                                         break;
464                                 case 0x04:
465                                         strcat(cpu_model, "486SRx");
466                                         break;
467                                 case 0x05:
468                                         strcat(cpu_model, "486DRx");
469                                         break;
470                                 case 0x06:
471                                         strcat(cpu_model, "486SRx2");
472                                         break;
473                                 case 0x07:
474                                         strcat(cpu_model, "486DRx2");
475                                         break;
476                                 case 0x08:
477                                         strcat(cpu_model, "486SRu");
478                                         break;
479                                 case 0x09:
480                                         strcat(cpu_model, "486DRu");
481                                         break;
482                                 case 0x0a:
483                                         strcat(cpu_model, "486SRu2");
484                                         break;
485                                 case 0x0b:
486                                         strcat(cpu_model, "486DRu2");
487                                         break;
488                                 default:
489                                         strcat(cpu_model, "Unknown");
490                                         break;
491                                 }
492                                 break;
493                         case 0x10:
494                                 switch (cyrix_did & 0x0f) {
495                                 case 0x00:
496                                         strcat(cpu_model, "486S");
497                                         break;
498                                 case 0x01:
499                                         strcat(cpu_model, "486S2");
500                                         break;
501                                 case 0x02:
502                                         strcat(cpu_model, "486Se");
503                                         break;
504                                 case 0x03:
505                                         strcat(cpu_model, "486S2e");
506                                         break;
507                                 case 0x0a:
508                                         strcat(cpu_model, "486DX");
509                                         break;
510                                 case 0x0b:
511                                         strcat(cpu_model, "486DX2");
512                                         break;
513                                 case 0x0f:
514                                         strcat(cpu_model, "486DX4");
515                                         break;
516                                 default:
517                                         strcat(cpu_model, "Unknown");
518                                         break;
519                                 }
520                                 break;
521                         case 0x20:
522                                 if ((cyrix_did & 0x0f) < 8)
523                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
524                                 else
525                                         strcat(cpu_model, "5x86");
526                                 break;
527                         case 0x30:
528                                 strcat(cpu_model, "6x86");
529                                 break;
530                         case 0x40:
531                                 if ((cyrix_did & 0xf000) == 0x3000) {
532                                         cpu_class = CPUCLASS_586;
533                                         strcat(cpu_model, "GXm");
534                                 } else
535                                         strcat(cpu_model, "MediaGX");
536                                 break;
537                         case 0x50:
538                                 strcat(cpu_model, "6x86MX");
539                                 break;
540                         case 0xf0:
541                                 switch (cyrix_did & 0x0f) {
542                                 case 0x0d:
543                                         strcat(cpu_model, "Overdrive CPU");
544                                         break;
545                                 case 0x0e:
546                                         strcpy(cpu_model, "Texas Instruments 486SXL");
547                                         break;
548                                 case 0x0f:
549                                         strcat(cpu_model, "486SLC/DLC");
550                                         break;
551                                 default:
552                                         strcat(cpu_model, "Unknown");
553                                         break;
554                                 }
555                                 break;
556                         default:
557                                 strcat(cpu_model, "Unknown");
558                                 break;
559                         }
560                         break;
561                 }
562         } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
563                 strcpy(cpu_model, "Rise ");
564                 switch (cpu_id & 0xff0) {
565                 case 0x500:
566                         strcat(cpu_model, "mP6");
567                         break;
568                 default:
569                         strcat(cpu_model, "Unknown");
570                 }
571         } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
572                 switch (cpu_id & 0xff0) {
573                 case 0x540:
574                         strcpy(cpu_model, "IDT WinChip C6");
575                         tsc_is_broken = 1;
576                         break;
577                 case 0x580:
578                         strcpy(cpu_model, "IDT WinChip 2");
579                         break;
580                 case 0x660:
581                         strcpy(cpu_model, "VIA C3 Samuel");
582                         break;
583                 case 0x670:
584                         if (cpu_id & 0x8)
585                                 strcpy(cpu_model, "VIA C3 Ezra");
586                         else
587                                 strcpy(cpu_model, "VIA C3 Samuel 2");
588                         break;
589                 case 0x680:
590                         strcpy(cpu_model, "VIA C3 Ezra-T");
591                         break;
592                 case 0x690:
593                         strcpy(cpu_model, "VIA C3 Nehemiah");
594                         break;
595                 case 0x6a0:
596                 case 0x6d0:
597                         strcpy(cpu_model, "VIA C7 Esther");
598                         break;
599                 case 0x6f0:
600                         strcpy(cpu_model, "VIA Nano");
601                         break;
602                 default:
603                         strcpy(cpu_model, "VIA/IDT Unknown");
604                 }
605         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
606                 strcpy(cpu_model, "Blue Lightning CPU");
607         } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
608                 switch (cpu_id & 0xfff) {
609                 case 0x540:
610                         strcpy(cpu_model, "Geode SC1100");
611                         cpu = CPU_GEODE1100;
612                         tsc_is_broken = 1;
613                         break;
614                 default:
615                         strcpy(cpu_model, "Geode/NSC unknown");
616                         break;
617                 }
618         }
619
620         /*
621          * Replace cpu_model with cpu_brand minus leading spaces if
622          * we have one.
623          */
624         brand = cpu_brand;
625         while (*brand == ' ')
626                 ++brand;
627         if (*brand != '\0')
628                 strcpy(cpu_model, brand);
629
630         kprintf("%s (", cpu_model);
631         switch(cpu_class) {
632         case CPUCLASS_286:
633                 kprintf("286");
634                 break;
635         case CPUCLASS_386:
636                 kprintf("386");
637                 break;
638 #if defined(I486_CPU)
639         case CPUCLASS_486:
640                 kprintf("486");
641                 /* bzero_vector = i486_bzero; */
642                 break;
643 #endif
644 #if defined(I586_CPU)
645         case CPUCLASS_586:
646                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
647                 kprintf("%jd.%02d-MHz ",
648                        (intmax_t)(tsc_frequency + 4999) / 1000000,
649                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
650                 kprintf("586");
651                 break;
652 #endif
653 #if defined(I686_CPU)
654         case CPUCLASS_686:
655                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
656                 kprintf("%jd.%02d-MHz ",
657                        (intmax_t)(tsc_frequency + 4999) / 1000000,
658                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
659                 kprintf("686");
660                 break;
661 #endif
662         default:
663                 kprintf("Unknown");     /* will panic below... */
664         }
665         kprintf("-class CPU)\n");
666         if(*cpu_vendor)
667                 kprintf("  Origin = \"%s\"",cpu_vendor);
668         if(cpu_id)
669                 kprintf("  Id = 0x%x", cpu_id);
670
671         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
672             cpu_vendor_id == CPU_VENDOR_AMD ||
673             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
674             cpu_vendor_id == CPU_VENDOR_RISE ||
675             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
676             cpu_vendor_id == CPU_VENDOR_NSC ||
677                 (cpu_vendor_id == CPU_VENDOR_CYRIX &&
678                  ((cpu_id & 0xf00) > 0x500))) {
679                 kprintf("  Stepping = %u", cpu_id & 0xf);
680                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
681                         kprintf("  DIR=0x%04x", cyrix_did);
682                 if (cpu_high > 0) {
683                         u_int cmp = 1, htt = 1;
684
685                         /*
686                          * Here we should probably set up flags indicating
687                          * whether or not various features are available.
688                          * The interesting ones are probably VME, PSE, PAE,
689                          * and PGE.  The code already assumes without bothering
690                          * to check that all CPUs >= Pentium have a TSC and
691                          * MSRs.
692                          */
693                         kprintf("\n  Features=0x%b", cpu_feature,
694                         "\020"
695                         "\001FPU"       /* Integral FPU */
696                         "\002VME"       /* Extended VM86 mode support */
697                         "\003DE"        /* Debugging Extensions (CR4.DE) */
698                         "\004PSE"       /* 4MByte page tables */
699                         "\005TSC"       /* Timestamp counter */
700                         "\006MSR"       /* Machine specific registers */
701                         "\007PAE"       /* Physical address extension */
702                         "\010MCE"       /* Machine Check support */
703                         "\011CX8"       /* CMPEXCH8 instruction */
704                         "\012APIC"      /* SMP local APIC */
705                         "\013oldMTRR"   /* Previous implementation of MTRR */
706                         "\014SEP"       /* Fast System Call */
707                         "\015MTRR"      /* Memory Type Range Registers */
708                         "\016PGE"       /* PG_G (global bit) support */
709                         "\017MCA"       /* Machine Check Architecture */
710                         "\020CMOV"      /* CMOV instruction */
711                         "\021PAT"       /* Page attributes table */
712                         "\022PSE36"     /* 36 bit address space support */
713                         "\023PN"        /* Processor Serial number */
714                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
715                         "\025<b20>"
716                         "\026DTS"       /* Debug Trace Store */
717                         "\027ACPI"      /* ACPI support */
718                         "\030MMX"       /* MMX instructions */
719                         "\031FXSR"      /* FXSAVE/FXRSTOR */
720                         "\032SSE"       /* Streaming SIMD Extensions */
721                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
722                         "\034SS"        /* Self snoop */
723                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
724                         "\036TM"        /* Thermal Monitor clock slowdown */
725                         "\037IA64"      /* CPU can execute IA64 instructions */
726                         "\040PBE"       /* Pending Break Enable */
727                         );
728
729                         if (cpu_feature2 != 0) {
730                                 kprintf("\n  Features2=0x%b", cpu_feature2,
731                                 "\020"
732                                 "\001SSE3"      /* SSE3 */
733                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
734                                 "\003DTES64"    /* 64-bit Debug Trace */
735                                 "\004MON"       /* MONITOR/MWAIT Instructions */
736                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
737                                 "\006VMX"       /* Virtual Machine Extensions */
738                                 "\007SMX"       /* Safer Mode Extensions */
739                                 "\010EST"       /* Enhanced SpeedStep */
740                                 "\011TM2"       /* Thermal Monitor 2 */
741                                 "\012SSSE3"     /* SSSE3 */
742                                 "\013CNXT-ID"   /* L1 context ID available */
743                                 "\014<b11>"
744                                 "\015FMA"       /* Fused Multiply Add */
745                                 "\016CX16"      /* CMPXCHG16B Instruction */
746                                 "\017xTPR"      /* Send Task Priority Messages */
747                                 "\020PDCM"      /* Perf/Debug Capability MSR */
748                                 "\021<b16>"
749                                 "\022PCID"      /* Process-context Identifiers */
750                                 "\023DCA"       /* Direct Cache Access */
751                                 "\024SSE4.1"    /* SSE 4.1 */
752                                 "\025SSE4.2"    /* SSE 4.2 */
753                                 "\026x2APIC"    /* xAPIC Extensions */
754                                 "\027MOVBE"     /* MOVBE Instruction */
755                                 "\030POPCNT"    /* POPCNT Instruction */
756                                 "\031TSCDLT"    /* TSC-Deadline Timer */
757                                 "\032AESNI"     /* AES Crypto */
758                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
759                                 "\034OSXSAVE"   /* OS-Enabled State Management */
760                                 "\035AVX"       /* Advanced Vector Extensions */
761                                 "\036F16C"      /* Half-precision conversions */
762                                 "\037<b30>"
763                                 "\040VMM"       /* Running on a hypervisor */
764                                 );
765                         }
766
767                         /*
768                          * AMD64 Architecture Programmer's Manual Volume 3:
769                          * General-Purpose and System Instructions
770                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
771                          *
772                          * IA-32 Intel Architecture Software Developer's Manual,
773                          * Volume 2A: Instruction Set Reference, A-M
774                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
775                          */
776                         if (amd_feature != 0) {
777                                 kprintf("\n  AMD Features=0x%b", amd_feature,
778                                 "\020"          /* in hex */
779                                 "\001<s0>"      /* Same */
780                                 "\002<s1>"      /* Same */
781                                 "\003<s2>"      /* Same */
782                                 "\004<s3>"      /* Same */
783                                 "\005<s4>"      /* Same */
784                                 "\006<s5>"      /* Same */
785                                 "\007<s6>"      /* Same */
786                                 "\010<s7>"      /* Same */
787                                 "\011<s8>"      /* Same */
788                                 "\012<s9>"      /* Same */
789                                 "\013<b10>"     /* Undefined */
790                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
791                                 "\015<s12>"     /* Same */
792                                 "\016<s13>"     /* Same */
793                                 "\017<s14>"     /* Same */
794                                 "\020<s15>"     /* Same */
795                                 "\021<s16>"     /* Same */
796                                 "\022<s17>"     /* Same */
797                                 "\023<b18>"     /* Reserved, unknown */
798                                 "\024MP"        /* Multiprocessor Capable */
799                                 "\025NX"        /* Has EFER.NXE, NX */
800                                 "\026<b21>"     /* Undefined */
801                                 "\027MMX+"      /* AMD MMX Extensions */
802                                 "\030<s23>"     /* Same */
803                                 "\031<s24>"     /* Same */
804                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
805                                 "\033Page1GB"   /* 1-GB large page support */
806                                 "\034RDTSCP"    /* RDTSCP */
807                                 "\035<b28>"     /* Undefined */
808                                 "\036LM"        /* 64 bit long mode */
809                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
810                                 "\0403DNow!"    /* AMD 3DNow! */
811                                 );
812                         }
813
814                         if (amd_feature2 != 0) {
815                                 kprintf("\n  AMD Features2=0x%b", amd_feature2,
816                                 "\020"
817                                 "\001LAHF"      /* LAHF/SAHF in long mode */
818                                 "\002CMP"       /* CMP legacy */
819                                 "\003SVM"       /* Secure Virtual Mode */
820                                 "\004ExtAPIC"   /* Extended APIC register */
821                                 "\005CR8"       /* CR8 in legacy mode */
822                                 "\006ABM"       /* LZCNT instruction */
823                                 "\007SSE4A"     /* SSE4A */
824                                 "\010MAS"       /* Misaligned SSE mode */
825                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
826                                 "\012OSVW"      /* OS visible workaround */
827                                 "\013IBS"       /* Instruction based sampling */
828                                 "\014XOP"       /* XOP extended instructions */
829                                 "\015SKINIT"    /* SKINIT/STGI */
830                                 "\016WDT"       /* Watchdog timer */
831                                 "\017<b14>"
832                                 "\020LWP"       /* Lightweight Profiling */
833                                 "\021FMA4"      /* 4-operand FMA instructions */
834                                 "\022<b17>"
835                                 "\023<b18>"
836                                 "\024NodeId"    /* NodeId MSR support */
837                                 "\025<b20>"
838                                 "\026TBM"       /* Trailing Bit Manipulation */
839                                 "\027Topology"  /* Topology Extensions */
840                                 "\030<b23>"
841                                 "\031<b24>"
842                                 "\032<b25>"
843                                 "\033<b26>"
844                                 "\034<b27>"
845                                 "\035<b28>"
846                                 "\036<b29>"
847                                 "\037<b30>"
848                                 "\040<b31>"
849                                 );
850                         }
851
852                         if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
853                                 print_via_padlock_info();
854
855                         if ((cpu_feature & CPUID_HTT) &&
856                             cpu_vendor_id == CPU_VENDOR_AMD)
857                                 cpu_feature &= ~CPUID_HTT;
858
859                         /*
860                          * If this CPU supports HTT or CMP then mention the
861                          * number of physical/logical cores it contains.
862                          */
863                         if (cpu_feature & CPUID_HTT)
864                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
865                         if (cpu_vendor_id == CPU_VENDOR_AMD &&
866                             (amd_feature2 & AMDID2_CMP))
867                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
868                         else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
869                             (cpu_high >= 4)) {
870                                 cpuid_count(4, 0, regs);
871                                 if ((regs[0] & 0x1f) != 0)
872                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
873                         }
874
875 #ifdef foo
876                         /*
877                          * XXX For Intel CPUs, this is max number of cores per
878                          * package, not the actual cores per package.
879                          */
880                         cpu_cores = cmp;
881                         cpu_logical = htt / cmp;
882
883                         if (cpu_cores > 1)
884                                 kprintf("\n  Cores per package: %d", cpu_cores);
885                         if (cpu_logical > 1) {
886                                 kprintf("\n  Logical CPUs per core: %d",
887                                     cpu_logical);
888                         }
889 #endif
890
891 #if 0
892                         /*
893                          * If this CPU supports P-state invariant TSC then
894                          * mention the capability.
895                          */
896                         switch (cpu_vendor_id) {
897                         case CPU_VENDOR_AMD:
898                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
899                                     CPUID_TO_FAMILY(cpu_id) >= 0x10 ||
900                                     cpu_id == 0x60fb2)
901                                         tsc_is_invariant = 1;
902                                 break;
903                         case CPU_VENDOR_INTEL:
904                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
905                                     (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
906                                     CPUID_TO_MODEL(cpu_id) >= 0xe) ||
907                                     (CPUID_TO_FAMILY(cpu_id) == 0xf &&
908                                     CPUID_TO_MODEL(cpu_id) >= 0x3))
909                                         tsc_is_invariant = 1;
910                                 break;
911                         case CPU_VENDOR_CENTAUR:
912                                 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
913                                     CPUID_TO_MODEL(cpu_id) >= 0xf &&
914                                     (rdmsr(0x1203) & 0x100000000ULL) == 0)
915                                         tsc_is_invariant = 1;
916                                 break;
917                         }
918                         if (tsc_is_invariant)
919                                 kprintf("\n  TSC: P-state invariant");
920 #endif
921
922                 }
923         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
924                 kprintf("  DIR=0x%04x", cyrix_did);
925                 kprintf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
926                 kprintf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
927 #ifndef CYRIX_CACHE_REALLY_WORKS
928                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
929                         kprintf("\n  CPU cache: write-through mode");
930 #endif
931         }
932
933         /* Avoid ugly blank lines: only print newline when we have to. */
934         if (*cpu_vendor || cpu_id)
935                 kprintf("\n");
936
937         for (i = 0; i < additional_cpu_info_count; ++i) {
938                 kprintf("  %s\n", additional_cpu_info_ary[i]);
939         }
940
941         if (!bootverbose)
942                 return;
943
944         if (cpu_vendor_id == CPU_VENDOR_AMD)
945                 print_AMD_info();
946         else if (cpu_vendor_id == CPU_VENDOR_INTEL)
947                 print_INTEL_info();
948         else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
949                 print_transmeta_info();
950
951 #ifdef CPU_HAS_SSE2
952         kprintf("Use SSE2 (lfence, mfence)\n");
953 #endif
954 #ifdef CPU_HAS_FXSR
955         kprintf("Use FXSR (sfence)\n");
956 #endif
957 }
958
959 void
960 panicifcpuunsupported(void)
961 {
962
963 #if !defined(lint)
964 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
965 #error This kernel is not configured for one of the supported CPUs
966 #endif
967 #else /* lint */
968 #endif /* lint */
969         /*
970          * Now that we have told the user what they have,
971          * let them know if that machine type isn't configured.
972          */
973         switch (cpu_class) {
974         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
975         case CPUCLASS_386:
976 #if !defined(I486_CPU)
977         case CPUCLASS_486:
978 #endif
979 #if !defined(I586_CPU)
980         case CPUCLASS_586:
981 #endif
982 #if !defined(I686_CPU)
983         case CPUCLASS_686:
984 #endif
985                 panic("CPU class not configured");
986         default:
987                 break;
988         }
989 }
990
991
992 static  volatile u_int trap_by_rdmsr;
993
994 /*
995  * Special exception 6 handler.
996  * The rdmsr instruction generates invalid opcodes fault on 486-class
997  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
998  * function identblue() when this handler is called.  Stacked eip should
999  * be advanced.
1000  */
1001 inthand_t       bluetrap6;
1002
1003 __asm
1004 ("                                                                      \n\
1005         .text                                                           \n\
1006         .p2align 2,0x90                                                 \n\
1007         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1008 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1009         ss                                                              \n\
1010         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1011         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1012         iret                                                            \n\
1013 ");
1014
1015 /*
1016  * Special exception 13 handler.
1017  * Accessing non-existent MSR generates general protection fault.
1018  */
1019 inthand_t       bluetrap13;
1020
1021 __asm
1022 ("                                                                      \n\
1023         .text                                                           \n\
1024         .p2align 2,0x90                                                 \n\
1025         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1026 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1027         ss                                                              \n\
1028         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1029         popl    %eax            /* discard error code */                \n\
1030         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1031         iret                                                            \n\
1032 ");
1033
1034 /*
1035  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1036  * support cpuid instruction.  This function should be called after
1037  * loading interrupt descriptor table register.
1038  *
1039  * I don't like this method that handles fault, but I couldn't get
1040  * information for any other methods.  Does blue giant know?
1041  */
1042 static int
1043 identblue(void)
1044 {
1045
1046         trap_by_rdmsr = 0;
1047
1048         /*
1049          * Cyrix 486-class CPU does not support rdmsr instruction.
1050          * The rdmsr instruction generates invalid opcode fault, and exception
1051          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1052          * bluetrap6() set the magic number to trap_by_rdmsr.
1053          */
1054         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1055             GSEL(GCODE_SEL, SEL_KPL));
1056
1057         /*
1058          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1059          * In this case, rdmsr generates general protection fault, and
1060          * exception will be trapped by bluetrap13().
1061          */
1062         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1063             GSEL(GCODE_SEL, SEL_KPL));
1064
1065         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1066
1067         if (trap_by_rdmsr == 0xa8c1d)
1068                 return IDENTBLUE_CYRIX486;
1069         else if (trap_by_rdmsr == 0xa89c4)
1070                 return IDENTBLUE_CYRIXM2;
1071         return IDENTBLUE_IBMCPU;
1072 }
1073
1074
1075 /*
1076  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1077  *
1078  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1079  * +-------+-------+---------------+
1080  * |  SID  |  RID  |   Device ID   |
1081  * |    (DIR 1)    |    (DIR 0)    |
1082  * +-------+-------+---------------+
1083  */
1084 static void
1085 identifycyrix(void)
1086 {
1087         int     ccr2_test = 0, dir_test = 0;
1088         u_char  ccr2, ccr3;
1089
1090         mpintr_lock();
1091
1092         ccr2 = read_cyrix_reg(CCR2);
1093         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1094         read_cyrix_reg(CCR2);
1095         if (read_cyrix_reg(CCR2) != ccr2)
1096                 ccr2_test = 1;
1097         write_cyrix_reg(CCR2, ccr2);
1098
1099         ccr3 = read_cyrix_reg(CCR3);
1100         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1101         read_cyrix_reg(CCR3);
1102         if (read_cyrix_reg(CCR3) != ccr3)
1103                 dir_test = 1;                                   /* CPU supports DIRs. */
1104         write_cyrix_reg(CCR3, ccr3);
1105
1106         if (dir_test) {
1107                 /* Device ID registers are available. */
1108                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1109                 cyrix_did += read_cyrix_reg(DIR0);
1110         } else if (ccr2_test)
1111                 cyrix_did = 0x0010;             /* 486S A-step */
1112         else
1113                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1114         mpintr_unlock();
1115 }
1116
1117 #if 0
1118 /* Update TSC freq with the value indicated by the caller. */
1119 static void
1120 tsc_frequency_changed(void *arg, const struct cf_level *level, int status)
1121 {
1122         /*
1123          * If there was an error during the transition or
1124          * TSC is P-state invariant, don't do anything.
1125          */
1126         if (status != 0 || tsc_is_invariant)
1127                 return;
1128
1129         /* Total setting for this level gives the new frequency in MHz. */
1130         hw_clockrate = level->total_set.freq;
1131 }
1132 #endif
1133
1134 /*
1135  * Final stage of CPU identification. -- Should I check TI?
1136  */
1137 void
1138 finishidentcpu(void)
1139 {
1140         int     isblue = 0;
1141         u_char  ccr3;
1142         u_int   regs[4];
1143
1144         cpu_vendor_id = find_cpu_vendor_id();
1145
1146         /*
1147          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1148          * function number again if it is set from BIOS.  It is necessary
1149          * for probing correct CPU topology later.
1150          * XXX This is only done on the BSP package.
1151          */
1152         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1153             ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1154             (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1155                 uint64_t msr;
1156                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1157                 if ((msr & 0x400000ULL) != 0) {
1158                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1159                         do_cpuid(0, regs);
1160                         cpu_high = regs[0];
1161                 }
1162         }
1163
1164         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
1165         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1166             cpu_vendor_id == CPU_VENDOR_AMD) {
1167                 init_exthigh();
1168                 if (cpu_exthigh >= 0x80000001) {
1169                         do_cpuid(0x80000001, regs);
1170                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1171                         amd_feature2 = regs[2];
1172                 }
1173 #if 0
1174                 if (cpu_exthigh >= 0x80000007) {
1175                         do_cpuid(0x80000007, regs);
1176                         amd_pminfo = regs[3];
1177                 }
1178 #endif
1179                 if (cpu_exthigh >= 0x80000008) {
1180                         do_cpuid(0x80000008, regs);
1181                         cpu_procinfo2 = regs[2];
1182                 }
1183         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1184                 if (cpu == CPU_486) {
1185                         /*
1186                          * These conditions are equivalent to:
1187                          *     - CPU does not support cpuid instruction.
1188                          *     - Cyrix/IBM CPU is detected.
1189                          */
1190                         isblue = identblue();
1191                         if (isblue == IDENTBLUE_IBMCPU) {
1192                                 strcpy(cpu_vendor, "IBM");
1193                                 cpu_vendor_id = CPU_VENDOR_IBM;
1194                                 cpu = CPU_BLUE;
1195                                 goto finish;
1196                         }
1197                 }
1198                 switch (cpu_id & 0xf00) {
1199                 case 0x600:
1200                         /*
1201                          * Cyrix's datasheet does not describe DIRs.
1202                          * Therefor, I assume it does not have them
1203                          * and use the result of the cpuid instruction.
1204                          * XXX they seem to have it for now at least. -Peter
1205                          */
1206                         identifycyrix();
1207                         cpu = CPU_M2;
1208                         break;
1209                 default:
1210                         identifycyrix();
1211                         /*
1212                          * This routine contains a trick.
1213                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1214                          */
1215                         switch (cyrix_did & 0x00f0) {
1216                         case 0x00:
1217                         case 0xf0:
1218                                 cpu = CPU_486DLC;
1219                                 break;
1220                         case 0x10:
1221                                 cpu = CPU_CY486DX;
1222                                 break;
1223                         case 0x20:
1224                                 if ((cyrix_did & 0x000f) < 8)
1225                                         cpu = CPU_M1;
1226                                 else
1227                                         cpu = CPU_M1SC;
1228                                 break;
1229                         case 0x30:
1230                                 cpu = CPU_M1;
1231                                 break;
1232                         case 0x40:
1233                                 /* MediaGX CPU */
1234                                 cpu = CPU_M1SC;
1235                                 break;
1236                         default:
1237                                 /* M2 and later CPUs are treated as M2. */
1238                                 cpu = CPU_M2;
1239
1240                                 /*
1241                                  * enable cpuid instruction.
1242                                  */
1243                                 ccr3 = read_cyrix_reg(CCR3);
1244                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1245                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1246                                 write_cyrix_reg(CCR3, ccr3);
1247
1248                                 do_cpuid(0, regs);
1249                                 cpu_high = regs[0];     /* eax */
1250                                 do_cpuid(1, regs);
1251                                 cpu_id = regs[0];       /* eax */
1252                                 cpu_feature = regs[3];  /* edx */
1253                                 break;
1254                         }
1255                 }
1256         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1257                 /*
1258                  * There are BlueLightning CPUs that do not change
1259                  * undefined flags by dividing 5 by 2.  In this case,
1260                  * the CPU identification routine in locore.s leaves
1261                  * cpu_vendor null string and puts CPU_486 into the
1262                  * cpu.
1263                  */
1264                 isblue = identblue();
1265                 if (isblue == IDENTBLUE_IBMCPU) {
1266                         strcpy(cpu_vendor, "IBM");
1267                         cpu_vendor_id = CPU_VENDOR_IBM;
1268                         cpu = CPU_BLUE;
1269                 }
1270         }
1271
1272         /*
1273          * Set MI flags for MI procedures implemented using machine-specific
1274          * features.
1275          */
1276 finish:
1277         if (cpu_feature & CPUID_SSE2)
1278                 cpu_mi_feature |= CPU_MI_BZERONT;
1279
1280         if (cpu_feature2 & CPUID2_MON)
1281                 cpu_mi_feature |= CPU_MI_MONITOR;
1282
1283 #ifdef CPU_HAS_SSE2
1284         if ((cpu_feature & CPUID_SSE2) == 0)
1285                 panic("CPU does not has SSE2, remove options CPU_HAS_SSE2\n");
1286 #endif
1287 #ifdef CPU_HAS_FXSR
1288         if ((cpu_feature & CPUID_FXSR) == 0)
1289                 panic("CPU does not has FXSR, remove options CPU_HAS_FXSR\n");
1290 #endif
1291 }
1292
1293 static u_int
1294 find_cpu_vendor_id(void)
1295 {
1296         int     i;
1297
1298         for (i = 0; i < NELEM(cpu_vendors); i++)
1299                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1300                         return (cpu_vendors[i].vendor_id);
1301         return (0);
1302 }
1303
1304 static void
1305 print_AMD_assoc(int i)
1306 {
1307         if (i == 255)
1308                 kprintf(", fully associative\n");
1309         else
1310                 kprintf(", %d-way associative\n", i);
1311 }
1312
1313 /*
1314  * #31116 Rev 3.06 section 3.9
1315  * CPUID Fn8000_0006 L2/L3 Cache and L2 TLB Identifiers
1316  */
1317 static void
1318 print_AMD_L2L3_assoc(int i)
1319 {
1320         static const char *assoc_str[] = {
1321                 [0x0] = "disabled",
1322                 [0x1] = "direct mapped",
1323                 [0x2] = "2-way associative",
1324                 [0x4] = "4-way associative",
1325                 [0x6] = "8-way associative",
1326                 [0x8] = "16-way associative",
1327                 [0xa] = "32-way associative",
1328                 [0xb] = "48-way associative",
1329                 [0xc] = "64-way associative",
1330                 [0xd] = "96-way associative",
1331                 [0xe] = "128-way associative",
1332                 [0xf] = "fully associative"
1333         };
1334
1335         i &= 0xf;
1336         if (assoc_str[i] == NULL)
1337                 kprintf(", unknown associative\n");
1338         else
1339                 kprintf(", %s\n", assoc_str[i]);
1340 }
1341
1342 static void
1343 print_AMD_info(void)
1344 {
1345         quad_t amd_whcr;
1346
1347         if (cpu_exthigh >= 0x80000005) {
1348                 u_int regs[4];
1349
1350                 do_cpuid(0x80000005, regs);
1351                 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1352                 print_AMD_assoc(regs[1] >> 24);
1353                 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1354                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1355                 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1356                 kprintf(", %d bytes/line", regs[2] & 0xff);
1357                 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1358                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1359                 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1360                 kprintf(", %d bytes/line", regs[3] & 0xff);
1361                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1362                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1363                 if (cpu_exthigh >= 0x80000006) {        /* K6-III or later */
1364                         do_cpuid(0x80000006, regs);
1365                         /*
1366                          * Report right L2 cache size on Duron rev. A0.
1367                          */
1368                         if ((cpu_id & 0xFF0) == 0x630)
1369                                 kprintf("L2 internal cache: 64 kbytes");
1370                         else
1371                                 kprintf("L2 internal cache: %d kbytes", regs[2] >> 16);
1372
1373                         kprintf(", %d bytes/line", regs[2] & 0xff);
1374                         kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1375                         print_AMD_L2L3_assoc((regs[2] >> 12) & 0x0f);
1376
1377                         /*
1378                          * #31116 Rev 3.06 section 2.16.2:
1379                          * ... If EDX[31:16] is not zero then the processor
1380                          * includes an L3. ...
1381                          */
1382                         if ((regs[3] & 0xffff0000) != 0) {
1383                                 kprintf("L3 shared cache: %d kbytes",
1384                                         (regs[3] >> 18) * 512);
1385                                 kprintf(", %d bytes/line", regs[3] & 0xff);
1386                                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0x0f);
1387                                 print_AMD_L2L3_assoc((regs[3] >> 12) & 0x0f);
1388                         }
1389                 }
1390         }
1391         if (((cpu_id & 0xf00) == 0x500)
1392             && (((cpu_id & 0x0f0) > 0x80)
1393                 || (((cpu_id & 0x0f0) == 0x80)
1394                     && (cpu_id & 0x00f) > 0x07))) {
1395                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1396                 amd_whcr = rdmsr(0xc0000082);
1397                 if (!(amd_whcr & (0x3ff << 22))) {
1398                         kprintf("Write Allocate Disable\n");
1399                 } else {
1400                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1401                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1402                         kprintf("Write Allocate 15-16M bytes: %s\n",
1403                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1404                 }
1405         } else if (((cpu_id & 0xf00) == 0x500)
1406                    && ((cpu_id & 0x0f0) > 0x50)) {
1407                 /* K6, K6-2(old core) */
1408                 amd_whcr = rdmsr(0xc0000082);
1409                 if (!(amd_whcr & (0x7f << 1))) {
1410                         kprintf("Write Allocate Disable\n");
1411                 } else {
1412                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1413                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1414                         kprintf("Write Allocate 15-16M bytes: %s\n",
1415                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1416                         kprintf("Hardware Write Allocate Control: %s\n",
1417                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1418                 }
1419         }
1420
1421         /*
1422          * Opteron Rev E shows a bug as in very rare occasions a read memory
1423          * barrier is not performed as expected if it is followed by a
1424          * non-atomic read-modify-write instruction.
1425          * As long as that bug pops up very rarely (intensive machine usage
1426          * on other operating systems generally generates one unexplainable
1427          * crash any 2 months) and as long as a model specific fix would be
1428          * impratical at this stage, print out a warning string if the broken
1429          * model and family are identified.
1430          */
1431         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1432             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1433                 kprintf("WARNING: This architecture revision has known SMP "
1434                     "hardware bugs which may cause random instability\n");
1435 }
1436
1437 static void
1438 print_INTEL_info(void)
1439 {
1440         u_int regs[4];
1441         u_int rounds, regnum;
1442         u_int nwaycode, nway;
1443
1444         if (cpu_high >= 2) {
1445                 rounds = 0;
1446                 do {
1447                         do_cpuid(0x2, regs);
1448                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1449                                 break;  /* we have a buggy CPU */
1450
1451                         for (regnum = 0; regnum <= 3; ++regnum) {
1452                                 if (regs[regnum] & (1<<31))
1453                                         continue;
1454                                 if (regnum != 0)
1455                                         print_INTEL_TLB(regs[regnum] & 0xff);
1456                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1457                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1458                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1459                         }
1460                 } while (--rounds > 0);
1461         }
1462
1463         if (cpu_exthigh >= 0x80000006) {
1464                 do_cpuid(0x80000006, regs);
1465                 nwaycode = (regs[2] >> 12) & 0x0f;
1466                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1467                         nway = 1 << (nwaycode / 2);
1468                 else
1469                         nway = 0;
1470                 kprintf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1471                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1472         }
1473
1474         kprintf("\n");
1475 }
1476
1477 static void
1478 print_INTEL_TLB(u_int data)
1479 {
1480         switch (data) {
1481         case 0x0:
1482         case 0x40:
1483         default:
1484                 break;
1485         case 0x1:
1486                 kprintf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1487                 break;
1488         case 0x2:
1489                 kprintf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1490                 break;
1491         case 0x3:
1492                 kprintf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1493                 break;
1494         case 0x4:
1495                 kprintf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1496                 break;
1497         case 0x6:
1498                 kprintf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1499                 break;
1500         case 0x8:
1501                 kprintf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1502                 break;
1503         case 0xa:
1504                 kprintf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1505                 break;
1506         case 0xc:
1507                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1508                 break;
1509         case 0x22:
1510                 kprintf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1511                 break;
1512         case 0x23:
1513                 kprintf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1514                 break;
1515         case 0x25:
1516                 kprintf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1517                 break;
1518         case 0x29:
1519                 kprintf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1520                 break;
1521         case 0x2c:
1522                 kprintf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1523                 break;
1524         case 0x30:
1525                 kprintf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1526                 break;
1527         case 0x39:
1528                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1529                 break;
1530         case 0x3b:
1531                 kprintf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1532                 break;
1533         case 0x3c:
1534                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1535                 break;
1536         case 0x41:
1537                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1538                 break;
1539         case 0x42:
1540                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1541                 break;
1542         case 0x43:
1543                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1544                 break;
1545         case 0x44:
1546                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1547                 break;
1548         case 0x45:
1549                 kprintf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1550                 break;
1551         case 0x46:
1552                 kprintf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1553                 break;
1554         case 0x47:
1555                 kprintf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1556                 break;
1557         case 0x50:
1558                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1559                 break;
1560         case 0x51:
1561                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1562                 break;
1563         case 0x52:
1564                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1565                 break;
1566         case 0x5b:
1567                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1568                 break;
1569         case 0x5c:
1570                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1571                 break;
1572         case 0x5d:
1573                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1574                 break;
1575         case 0x60:
1576                 kprintf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1577                 break;
1578         case 0x66:
1579                 kprintf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1580                 break;
1581         case 0x67:
1582                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1583                 break;
1584         case 0x68:
1585                 kprintf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1586                 break;
1587         case 0x70:
1588                 kprintf("\nTrace cache: 12K-uops, 8-way set associative");
1589                 break;
1590         case 0x71:
1591                 kprintf("\nTrace cache: 16K-uops, 8-way set associative");
1592                 break;
1593         case 0x72:
1594                 kprintf("\nTrace cache: 32K-uops, 8-way set associative");
1595                 break;
1596         case 0x78:
1597                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1598                 break;
1599         case 0x79:
1600                 kprintf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1601                 break;
1602         case 0x7a:
1603                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1604                 break;
1605         case 0x7b:
1606                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1607                 break;
1608         case 0x7c:
1609                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1610                 break;
1611         case 0x7d:
1612                 kprintf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1613                 break;
1614         case 0x7f:
1615                 kprintf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1616                 break;
1617         case 0x82:
1618                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1619                 break;
1620         case 0x83:
1621                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1622                 break;
1623         case 0x84:
1624                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1625                 break;
1626         case 0x85:
1627                 kprintf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1628                 break;
1629         case 0x86:
1630                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1631                 break;
1632         case 0x87:
1633                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1634                 break;
1635         case 0xb0:
1636                 kprintf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1637                 break;
1638         case 0xb3:
1639                 kprintf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1640                 break;
1641         }
1642 }
1643
1644 static void
1645 print_transmeta_info(void)
1646 {
1647         u_int regs[4], nreg = 0;
1648
1649         do_cpuid(0x80860000, regs);
1650         nreg = regs[0];
1651         if (nreg >= 0x80860001) {
1652                 do_cpuid(0x80860001, regs);
1653                 kprintf("  Processor revision %u.%u.%u.%u\n",
1654                        (regs[1] >> 24) & 0xff,
1655                        (regs[1] >> 16) & 0xff,
1656                        (regs[1] >> 8) & 0xff,
1657                        regs[1] & 0xff);
1658         }
1659         if (nreg >= 0x80860002) {
1660                 do_cpuid(0x80860002, regs);
1661                 kprintf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1662                        (regs[1] >> 24) & 0xff,
1663                        (regs[1] >> 16) & 0xff,
1664                        (regs[1] >> 8) & 0xff,
1665                        regs[1] & 0xff,
1666                        regs[2]);
1667         }
1668         if (nreg >= 0x80860006) {
1669                 char info[65];
1670                 do_cpuid(0x80860003, (u_int*) &info[0]);
1671                 do_cpuid(0x80860004, (u_int*) &info[16]);
1672                 do_cpuid(0x80860005, (u_int*) &info[32]);
1673                 do_cpuid(0x80860006, (u_int*) &info[48]);
1674                 info[64] = 0;
1675                 kprintf("  %s\n", info);
1676         }
1677 }
1678
1679 static void
1680 print_via_padlock_info(void)
1681 {
1682         u_int regs[4];
1683
1684         /* Check for supported models. */
1685         switch (cpu_id & 0xff0) {
1686         case 0x690:
1687                 if ((cpu_id & 0xf) < 3)
1688                         return;
1689         case 0x6a0:
1690         case 0x6d0:
1691         case 0x6f0:
1692                 break;
1693         default:
1694                 return;
1695         }
1696
1697         do_cpuid(0xc0000000, regs);
1698         if (regs[0] >= 0xc0000001)
1699                 do_cpuid(0xc0000001, regs);
1700         else
1701                 return;
1702
1703         kprintf("\n  VIA Padlock Features=0x%b", regs[3],
1704         "\020"
1705         "\003RNG"               /* RNG */
1706         "\007AES"               /* ACE */
1707         "\011AES-CTR"           /* ACE2 */
1708         "\013SHA1,SHA256"       /* PHE */
1709         "\015RSA"               /* PMM */
1710         );
1711 }
1712
1713 void
1714 additional_cpu_info(const char *line)
1715 {
1716         int i;
1717
1718         if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1719                 additional_cpu_info_ary[i] = line;
1720                 ++additional_cpu_info_count;
1721         }
1722 }