kernel/printcpuinfo(): Sync feature bit descriptions with FreeBSD.
[dragonfly.git] / sys / platform / pc64 / x86_64 / identcpu.c
1 /*-
2  * Copyright (c) 1992 Terrence R. Lambert.
3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4  * Copyright (c) 1997 KATO Takenori.
5  * Copyright (c) 2008 The DragonFly Project.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to Berkeley by
9  * William Jolitz.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *      This product includes software developed by the University of
22  *      California, Berkeley and its contributors.
23  * 4. Neither the name of the University nor the names of its contributors
24  *    may be used to endorse or promote products derived from this software
25  *    without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37  * SUCH DAMAGE.
38  *
39  * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
40  */
41
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/eventhandler.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/sysctl.h>
50 #include <sys/power.h>
51
52 #include <machine/asmacros.h>
53 #include <machine/clock.h>
54 #include <machine/cputypes.h>
55 #include <machine/frame.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
59
60 /* XXX - should be in header file: */
61 void printcpuinfo(void);
62 void identify_cpu(void);
63 void earlysetcpuclass(void);
64 void panicifcpuunsupported(void);
65
66 static u_int find_cpu_vendor_id(void);
67 static void print_AMD_info(void);
68 static void print_AMD_assoc(int i);
69 static void print_via_padlock_info(void);
70
71 int     cpu_class;
72 char machine[] = "x86_64";
73 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
74     machine, 0, "Machine class");
75
76 static char cpu_model[128];
77 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
78     cpu_model, 0, "Machine model");
79
80 static int hw_clockrate;
81 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
82     &hw_clockrate, 0, "CPU instruction clock rate");
83
84 static char cpu_brand[48];
85
86 static struct {
87         char    *cpu_name;
88         int     cpu_class;
89 } x86_64_cpus[] = {
90         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
91         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
92 };
93
94 static struct {
95         char    *vendor;
96         u_int   vendor_id;
97 } cpu_vendors[] = {
98         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
99         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
100         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
101 };
102
103 #ifdef foo
104 static int cpu_cores;
105 static int cpu_logical;
106 #endif
107
108 extern int pq_l2size;
109 extern int pq_l2nways;
110
111 void
112 printcpuinfo(void)
113 {
114         u_int regs[4], i;
115         char *brand;
116
117         cpu_class = x86_64_cpus[cpu].cpu_class;
118         kprintf("CPU: ");
119         strncpy(cpu_model, x86_64_cpus[cpu].cpu_name, sizeof (cpu_model));
120
121         /* Check for extended CPUID information and a processor name. */
122         if (cpu_exthigh >= 0x80000004) {
123                 brand = cpu_brand;
124                 for (i = 0x80000002; i < 0x80000005; i++) {
125                         do_cpuid(i, regs);
126                         memcpy(brand, regs, sizeof(regs));
127                         brand += sizeof(regs);
128                 }
129         }
130
131         switch (cpu_vendor_id) {
132         case CPU_VENDOR_INTEL:
133                 /* Please make up your mind folks! */
134                 strcat(cpu_model, "EM64T");
135                 break;
136         case CPU_VENDOR_AMD:
137                 /*
138                  * Values taken from AMD Processor Recognition
139                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
140                  * (also describes ``Features'' encodings.
141                  */
142                 strcpy(cpu_model, "AMD ");
143                 if ((cpu_id & 0xf00) == 0xf00)
144                         strcat(cpu_model, "AMD64 Processor");
145                 else
146                         strcat(cpu_model, "Unknown");
147                 break;
148         case CPU_VENDOR_CENTAUR:
149                 strcpy(cpu_model, "VIA ");
150                 if ((cpu_id & 0xff0) == 0x6f0)
151                         strcat(cpu_model, "Nano Processor");
152                 else
153                         strcat(cpu_model, "Unknown");
154                 break;
155         default:
156                 strcat(cpu_model, "Unknown");
157                 break;
158         }
159
160         /*
161          * Replace cpu_model with cpu_brand minus leading spaces if
162          * we have one.
163          */
164         brand = cpu_brand;
165         while (*brand == ' ')
166                 ++brand;
167         if (*brand != '\0')
168                 strcpy(cpu_model, brand);
169
170         kprintf("%s (", cpu_model);
171         switch(cpu_class) {
172         case CPUCLASS_K8:
173                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
174                 kprintf("%jd.%02d-MHz ",
175                        (intmax_t)(tsc_frequency + 4999) / 1000000,
176                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
177                 kprintf("K8");
178                 break;
179         default:
180                 kprintf("Unknown");     /* will panic below... */
181         }
182         kprintf("-class CPU)\n");
183         if (*cpu_vendor)
184                 kprintf("  Origin = \"%s\"", cpu_vendor);
185         if (cpu_id)
186                 kprintf("  Id = 0x%x", cpu_id);
187
188         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
189             cpu_vendor_id == CPU_VENDOR_AMD ||
190             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
191                 kprintf("  Stepping = %u", cpu_id & 0xf);
192                 if (cpu_high > 0) {
193                         u_int cmp = 1, htt = 1;
194
195                         /*
196                          * Here we should probably set up flags indicating
197                          * whether or not various features are available.
198                          * The interesting ones are probably VME, PSE, PAE,
199                          * and PGE.  The code already assumes without bothering
200                          * to check that all CPUs >= Pentium have a TSC and
201                          * MSRs.
202                          */
203                         kprintf("\n  Features=0x%b", cpu_feature,
204                         "\020"
205                         "\001FPU"       /* Integral FPU */
206                         "\002VME"       /* Extended VM86 mode support */
207                         "\003DE"        /* Debugging Extensions (CR4.DE) */
208                         "\004PSE"       /* 4MByte page tables */
209                         "\005TSC"       /* Timestamp counter */
210                         "\006MSR"       /* Machine specific registers */
211                         "\007PAE"       /* Physical address extension */
212                         "\010MCE"       /* Machine Check support */
213                         "\011CX8"       /* CMPEXCH8 instruction */
214                         "\012APIC"      /* SMP local APIC */
215                         "\013oldMTRR"   /* Previous implementation of MTRR */
216                         "\014SEP"       /* Fast System Call */
217                         "\015MTRR"      /* Memory Type Range Registers */
218                         "\016PGE"       /* PG_G (global bit) support */
219                         "\017MCA"       /* Machine Check Architecture */
220                         "\020CMOV"      /* CMOV instruction */
221                         "\021PAT"       /* Page attributes table */
222                         "\022PSE36"     /* 36 bit address space support */
223                         "\023PN"        /* Processor Serial number */
224                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
225                         "\025<b20>"
226                         "\026DTS"       /* Debug Trace Store */
227                         "\027ACPI"      /* ACPI support */
228                         "\030MMX"       /* MMX instructions */
229                         "\031FXSR"      /* FXSAVE/FXRSTOR */
230                         "\032SSE"       /* Streaming SIMD Extensions */
231                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
232                         "\034SS"        /* Self snoop */
233                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
234                         "\036TM"        /* Thermal Monitor clock slowdown */
235                         "\037IA64"      /* CPU can execute IA64 instructions */
236                         "\040PBE"       /* Pending Break Enable */
237                         );
238
239                         if (cpu_feature2 != 0) {
240                                 kprintf("\n  Features2=0x%b", cpu_feature2,
241                                 "\020"
242                                 "\001SSE3"      /* SSE3 */
243                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
244                                 "\003DTES64"    /* 64-bit Debug Trace */
245                                 "\004MON"       /* MONITOR/MWAIT Instructions */
246                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
247                                 "\006VMX"       /* Virtual Machine Extensions */
248                                 "\007SMX"       /* Safer Mode Extensions */
249                                 "\010EST"       /* Enhanced SpeedStep */
250                                 "\011TM2"       /* Thermal Monitor 2 */
251                                 "\012SSSE3"     /* SSSE3 */
252                                 "\013CNXT-ID"   /* L1 context ID available */
253                                 "\014<b11>"
254                                 "\015FMA"       /* Fused Multiply Add */
255                                 "\016CX16"      /* CMPXCHG16B Instruction */
256                                 "\017xTPR"      /* Send Task Priority Messages */
257                                 "\020PDCM"      /* Perf/Debug Capability MSR */
258                                 "\021<b16>"
259                                 "\022PCID"      /* Process-context Identifiers */
260                                 "\023DCA"       /* Direct Cache Access */
261                                 "\024SSE4.1"    /* SSE 4.1 */
262                                 "\025SSE4.2"    /* SSE 4.2 */
263                                 "\026x2APIC"    /* xAPIC Extensions */
264                                 "\027MOVBE"     /* MOVBE Instruction */
265                                 "\030POPCNT"    /* POPCNT Instruction */
266                                 "\031TSCDLT"    /* TSC-Deadline Timer */
267                                 "\032AESNI"     /* AES Crypto */
268                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
269                                 "\034OSXSAVE"   /* OS-Enabled State Management */
270                                 "\035AVX"       /* Advanced Vector Extensions */
271                                 "\036F16C"      /* Half-precision conversions */
272                                 "\037<b30>"
273                                 "\040VMM"       /*  Running on a hypervisor */
274                                 );
275                         }
276
277                         /*
278                          * AMD64 Architecture Programmer's Manual Volume 3:
279                          * General-Purpose and System Instructions
280                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
281                          *
282                          * IA-32 Intel Architecture Software Developer's Manual,
283                          * Volume 2A: Instruction Set Reference, A-M
284                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
285                          */
286                         if (amd_feature != 0) {
287                                 kprintf("\n  AMD Features=0x%b", amd_feature,
288                                 "\020"          /* in hex */
289                                 "\001<s0>"      /* Same */
290                                 "\002<s1>"      /* Same */
291                                 "\003<s2>"      /* Same */
292                                 "\004<s3>"      /* Same */
293                                 "\005<s4>"      /* Same */
294                                 "\006<s5>"      /* Same */
295                                 "\007<s6>"      /* Same */
296                                 "\010<s7>"      /* Same */
297                                 "\011<s8>"      /* Same */
298                                 "\012<s9>"      /* Same */
299                                 "\013<b10>"     /* Undefined */
300                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
301                                 "\015<s12>"     /* Same */
302                                 "\016<s13>"     /* Same */
303                                 "\017<s14>"     /* Same */
304                                 "\020<s15>"     /* Same */
305                                 "\021<s16>"     /* Same */
306                                 "\022<s17>"     /* Same */
307                                 "\023<b18>"     /* Reserved, unknown */
308                                 "\024MP"        /* Multiprocessor Capable */
309                                 "\025NX"        /* Has EFER.NXE, NX */
310                                 "\026<b21>"     /* Undefined */
311                                 "\027MMX+"      /* AMD MMX Extensions */
312                                 "\030<s23>"     /* Same */
313                                 "\031<s24>"     /* Same */
314                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
315                                 "\033Page1GB"   /* 1-GB large page support */
316                                 "\034RDTSCP"    /* RDTSCP */
317                                 "\035<b28>"     /* Undefined */
318                                 "\036LM"        /* 64 bit long mode */
319                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
320                                 "\0403DNow!"    /* AMD 3DNow! */
321                                 );
322                         }
323
324                         if (amd_feature2 != 0) {
325                                 kprintf("\n  AMD Features2=0x%b", amd_feature2,
326                                 "\020"
327                                 "\001LAHF"      /* LAHF/SAHF in long mode */
328                                 "\002CMP"       /* CMP legacy */
329                                 "\003SVM"       /* Secure Virtual Mode */
330                                 "\004ExtAPIC"   /* Extended APIC register */
331                                 "\005CR8"       /* CR8 in legacy mode */
332                                 "\006ABM"       /* LZCNT instruction */
333                                 "\007SSE4A"     /* SSE4A */
334                                 "\010MAS"       /* Misaligned SSE mode */
335                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
336                                 "\012OSVW"      /* OS visible workaround */
337                                 "\013IBS"       /* Instruction based sampling */
338                                 "\014XOP"       /* XOP extended instructions */
339                                 "\015SKINIT"    /* SKINIT/STGI */
340                                 "\016WDT"       /* Watchdog timer */
341                                 "\017<b14>"
342                                 "\020LWP"       /* Lightweight Profiling */
343                                 "\021FMA4"      /* 4-operand FMA instructions */
344                                 "\022<b17>"
345                                 "\023<b18>"
346                                 "\024NodeId"    /* NodeId MSR support */
347                                 "\025<b20>"
348                                 "\026TBM"       /* Trailing Bit Manipulation */
349                                 "\027Topology"  /* Topology Extensions */
350                                 "\030<b23>"
351                                 "\031<b24>"
352                                 "\032<b25>"
353                                 "\033<b26>"
354                                 "\034<b27>"
355                                 "\035<b28>"
356                                 "\036<b29>"
357                                 "\037<b30>"
358                                 "\040<b31>"
359                                 );
360                         }
361
362                         if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
363                                 print_via_padlock_info();
364
365                         if ((cpu_feature & CPUID_HTT) &&
366                             cpu_vendor_id == CPU_VENDOR_AMD)
367                                 cpu_feature &= ~CPUID_HTT;
368
369                         /*
370                          * If this CPU supports HTT or CMP then mention the
371                          * number of physical/logical cores it contains.
372                          */
373                         if (cpu_feature & CPUID_HTT)
374                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
375                         if (cpu_vendor_id == CPU_VENDOR_AMD &&
376                             (amd_feature2 & AMDID2_CMP))
377                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
378                         else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
379                             (cpu_high >= 4)) {
380                                 cpuid_count(4, 0, regs);
381                                 if ((regs[0] & 0x1f) != 0)
382                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
383                         }
384
385 #ifdef foo
386                         /*
387                          * XXX For Intel CPUs, this is max number of cores per
388                          * package, not the actual cores per package.
389                          */
390                         cpu_cores = cmp;
391                         cpu_logical = htt / cmp;
392
393                         if (cpu_cores > 1)
394                                 kprintf("\n  Cores per package: %d", cpu_cores);
395                         if (cpu_logical > 1) {
396                                 kprintf("\n  Logical CPUs per core: %d",
397                                     cpu_logical);
398                         }
399 #endif
400                 }
401         }
402         /* Avoid ugly blank lines: only print newline when we have to. */
403         if (*cpu_vendor || cpu_id)
404                 kprintf("\n");
405
406         if (!bootverbose)
407                 return;
408
409         if (cpu_vendor_id == CPU_VENDOR_AMD)
410                 print_AMD_info();
411 }
412
413 void
414 panicifcpuunsupported(void)
415 {
416
417 #ifndef HAMMER_CPU
418 #error "You need to specify a cpu type"
419 #endif
420         /*
421          * Now that we have told the user what they have,
422          * let them know if that machine type isn't configured.
423          */
424         switch (cpu_class) {
425         case CPUCLASS_X86:
426 #ifndef HAMMER_CPU
427         case CPUCLASS_K8:
428 #endif
429                 panic("CPU class not configured");
430         default:
431                 break;
432         }
433 }
434
435
436 #if JG
437 /* Update TSC freq with the value indicated by the caller. */
438 static void
439 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
440 {
441         /* If there was an error during the transition, don't do anything. */
442         if (status != 0)
443                 return;
444
445         /* Total setting for this level gives the new frequency in MHz. */
446         hw_clockrate = level->total_set.freq;
447 }
448
449 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
450     EVENTHANDLER_PRI_ANY);
451 #endif
452
453 /*
454  * Final stage of CPU identification.
455  */
456 void
457 identify_cpu(void)
458 {
459         u_int regs[4];
460
461         do_cpuid(0, regs);
462         cpu_high = regs[0];
463         ((u_int *)&cpu_vendor)[0] = regs[1];
464         ((u_int *)&cpu_vendor)[1] = regs[3];
465         ((u_int *)&cpu_vendor)[2] = regs[2];
466         cpu_vendor[12] = '\0';
467         cpu_vendor_id = find_cpu_vendor_id();
468
469         do_cpuid(1, regs);
470         cpu_id = regs[0];
471         cpu_procinfo = regs[1];
472         cpu_feature = regs[3];
473         cpu_feature2 = regs[2];
474
475         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
476             cpu_vendor_id == CPU_VENDOR_AMD ||
477             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
478                 do_cpuid(0x80000000, regs);
479                 cpu_exthigh = regs[0];
480         }
481         if (cpu_exthigh >= 0x80000001) {
482                 do_cpuid(0x80000001, regs);
483                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
484                 amd_feature2 = regs[2];
485         }
486         if (cpu_exthigh >= 0x80000008) {
487                 do_cpuid(0x80000008, regs);
488                 cpu_procinfo2 = regs[2];
489         }
490
491         /* XXX */
492         cpu = CPU_CLAWHAMMER;
493
494         if (cpu_feature & CPUID_SSE2)
495                 cpu_mi_feature |= CPU_MI_BZERONT;
496
497         if (cpu_feature2 & CPUID2_MON)
498                 cpu_mi_feature |= CPU_MI_MONITOR;
499 }
500
501 static u_int
502 find_cpu_vendor_id(void)
503 {
504         int     i;
505
506         for (i = 0; i < NELEM(cpu_vendors); i++)
507                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
508                         return (cpu_vendors[i].vendor_id);
509         return (0);
510 }
511
512 static void
513 print_AMD_assoc(int i)
514 {
515         if (i == 255)
516                 kprintf(", fully associative\n");
517         else
518                 kprintf(", %d-way associative\n", i);
519 }
520
521 static void
522 print_AMD_l2_assoc(int i)
523 {
524         switch (i & 0x0f) {
525         case 0: kprintf(", disabled/not present\n"); break;
526         case 1: kprintf(", direct mapped\n"); break;
527         case 2: kprintf(", 2-way associative\n"); break;
528         case 4: kprintf(", 4-way associative\n"); break;
529         case 6: kprintf(", 8-way associative\n"); break;
530         case 8: kprintf(", 16-way associative\n"); break;
531         case 15: kprintf(", fully associative\n"); break;
532         default: kprintf(", reserved configuration\n"); break;
533         }
534 }
535
536 static void
537 print_AMD_info(void)
538 {
539         u_int regs[4];
540
541         if (cpu_exthigh < 0x80000005)
542                 return;
543
544         do_cpuid(0x80000005, regs);
545         kprintf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
546         print_AMD_assoc(regs[0] >> 24);
547
548         kprintf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
549         print_AMD_assoc((regs[0] >> 8) & 0xff);
550
551         kprintf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
552         print_AMD_assoc(regs[1] >> 24);
553
554         kprintf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
555         print_AMD_assoc((regs[1] >> 8) & 0xff);
556
557         kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
558         kprintf(", %d bytes/line", regs[2] & 0xff);
559         kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
560         print_AMD_assoc((regs[2] >> 16) & 0xff);
561
562         kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
563         kprintf(", %d bytes/line", regs[3] & 0xff);
564         kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
565         print_AMD_assoc((regs[3] >> 16) & 0xff);
566
567         if (cpu_exthigh >= 0x80000006) {
568                 do_cpuid(0x80000006, regs);
569                 if ((regs[0] >> 16) != 0) {
570                         kprintf("L2 2MB data TLB: %d entries",
571                             (regs[0] >> 16) & 0xfff);
572                         print_AMD_l2_assoc(regs[0] >> 28);
573                         kprintf("L2 2MB instruction TLB: %d entries",
574                             regs[0] & 0xfff);
575                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
576                 } else {
577                         kprintf("L2 2MB unified TLB: %d entries",
578                             regs[0] & 0xfff);
579                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
580                 }
581                 if ((regs[1] >> 16) != 0) {
582                         kprintf("L2 4KB data TLB: %d entries",
583                             (regs[1] >> 16) & 0xfff);
584                         print_AMD_l2_assoc(regs[1] >> 28);
585
586                         kprintf("L2 4KB instruction TLB: %d entries",
587                             (regs[1] >> 16) & 0xfff);
588                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
589                 } else {
590                         kprintf("L2 4KB unified TLB: %d entries",
591                             (regs[1] >> 16) & 0xfff);
592                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
593                 }
594                 kprintf("L2 unified cache: %d kbytes", regs[2] >> 16);
595                 kprintf(", %d bytes/line", regs[2] & 0xff);
596                 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
597                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);     
598         }
599 }
600
601 static void
602 print_via_padlock_info(void)
603 {
604         u_int regs[4];
605
606         /* Check for supported models. */
607         switch (cpu_id & 0xff0) {
608         case 0x690:
609                 if ((cpu_id & 0xf) < 3)
610                         return;
611         case 0x6a0:
612         case 0x6d0:
613         case 0x6f0:
614                 break;
615         default:
616                 return;
617         }
618
619         do_cpuid(0xc0000000, regs);
620         if (regs[0] >= 0xc0000001)
621                 do_cpuid(0xc0000001, regs);
622         else
623                 return;
624
625         kprintf("\n  VIA Padlock Features=0x%b", regs[3],
626         "\020"
627         "\003RNG"               /* RNG */
628         "\007AES"               /* ACE */
629         "\011AES-CTR"           /* ACE2 */
630         "\013SHA1,SHA256"       /* PHE */
631         "\015RSA"               /* PMM */
632         );
633 }