sys/net/i4b/layer1/ifpnp/i4b_ifpnp_avm.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Udo Schweigert. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpnp_avm.c: AVM Fritz!Card PnP hardware driver
  34  *      ---------------------------------------------------
  35  *
  36  * $FreeBSD: src/sys/i4b/layer1/ifpnp/i4b_ifpnp_avm.c,v 1.5.2.1 2001/08/10 14:08:37 obrien Exp $
  37  * $DragonFly: src/sys/net/i4b/layer1/ifpnp/i4b_ifpnp_avm.c,v 1.12 2006/12/22 23:44:56 swildner Exp $
  38  *
  39  *      last edit-date: [Fri Jan 12 17:05:28 2001]
  40  *
  41  *---------------------------------------------------------------------------*/
  42
  43 #include "use_ifpnp.h"
  44 #include "opt_i4b.h"
  45
  46 #if (NIFPNP > 0)
  47
  48 #include <sys/param.h>
  49 #include <sys/kernel.h>
  50 #include <sys/systm.h>
  51 #include <sys/mbuf.h>
  52 #include <sys/bus.h>
  53 #include <sys/rman.h>
  54 #include <sys/socket.h>
  55 #include <sys/thread2.h>
  56
  57 #include <bus/isa/isavar.h>
  58
  59 #include <net/if.h>
  60 #include <net/i4b/include/machine/i4b_debug.h>
  61 #include <net/i4b/include/machine/i4b_ioctl.h>
  62 #include <net/i4b/include/machine/i4b_trace.h>
  63
  64 #include "../../include/i4b_global.h"
  65 #include "../../include/i4b_mbuf.h"
  66
  67 #include "../i4b_l1.h"
  68 #include "../isic/i4b_isic.h"
  69 #include "../isic/i4b_isac.h"
  70 #include "../isic/i4b_hscx.h"
  71
  72 #include "i4b_ifpnp_ext.h"
  73
  74 /* prototypes */
  75 static void avm_pnp_intr(void *);
  76 static void hscx_write_reg(int, u_int, struct l1_softc *, u_int);
  77 static void hscx_write_reg_val(int, u_int, u_int8_t, struct l1_softc *);
  78 static u_int hscx_read_reg(int, u_int, struct l1_softc *);
  79 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  80 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  81 static void avm_pnp_hscx_int_handler(struct l1_softc *);
  82 static void avm_pnp_hscx_intr(int, u_int, u_int, struct l1_softc *);
  83 static void avm_pnp_init_linktab(struct l1_softc *);
  84 static void avm_pnp_bchannel_setup(int, int, int, int);
  85 static void avm_pnp_bchannel_start(int, int);
  86 static void avm_pnp_hscx_init(struct l1_softc *, int, int);
  87 static void avm_pnp_bchannel_stat(int, int, bchan_statistics_t *);
  88 static void avm_pnp_set_linktab(int, int, drvr_link_t *);
  89 static isdn_link_t * avm_pnp_ret_linktab(int, int);
  90 static int avm_pnp_probe(device_t);
  91 static int avm_pnp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
  92 int avm_pnp_attach(device_t);
  93 static void ifpnp_isac_intr(struct l1_softc *sc);
  94
  95 static device_method_t avm_pnp_methods[] = {
  96         /* Device interface */
  97         DEVMETHOD(device_probe,         avm_pnp_probe),
  98         DEVMETHOD(device_attach,        avm_pnp_attach),
  99         { 0, 0 }
 100 };
 101
 102 static driver_t avm_pnp_driver = {
 103         "ifpnp",
 104         avm_pnp_methods,
 105         sizeof(struct l1_softc)
 106 };
 107
 108 static devclass_t avm_pnp_devclass;
 109
 110 DRIVER_MODULE(avm_pnp, isa, avm_pnp_driver, avm_pnp_devclass, 0, 0);
 111
 112 /* jump table for multiplex routines */
 113
 114 struct i4b_l1mux_func avm_pnp_l1mux_func = {
 115         avm_pnp_ret_linktab,
 116         avm_pnp_set_linktab,
 117         ifpnp_mph_command_req,
 118         ifpnp_ph_data_req,
 119         ifpnp_ph_activate_req,
 120 };
 121
 122 struct l1_softc *ifpnp_scp[IFPNP_MAXUNIT];
 123
 124 /*---------------------------------------------------------------------------*
 125  *      AVM PnP Fritz!Card special registers
 126  *---------------------------------------------------------------------------*/
 127
 128 /*
 129  *      register offsets from i/o base
 130  */
 131 #define CLASS_OFFSET            0x00
 132 #define REVISION_OFFSET         0x01
 133 #define STAT0_OFFSET            0x02
 134 #define STAT1_OFFSET            0x03
 135 #define ADDR_REG_OFFSET         0x04
 136 /*#define MODREG_OFFSET         0x06
 137 #define VERREG_OFFSET           0x07*/
 138
 139 /* these 2 are used to select an ISAC register set */
 140 #define ISAC_LO_REG_OFFSET      0x04
 141 #define ISAC_HI_REG_OFFSET      0x06
 142
 143 /* offset higher than this goes to the HI register set */
 144 #define MAX_LO_REG_OFFSET       0x2f
 145
 146 /* mask for the offset */
 147 #define ISAC_REGSET_MASK        0x0f
 148
 149 /* the offset from the base to the ISAC registers */
 150 #define ISAC_REG_OFFSET         0x10
 151
 152 /* the offset from the base to the ISAC FIFO */
 153 #define ISAC_FIFO               0x02
 154
 155 /* not really the HSCX, but sort of */
 156 #define HSCX_FIFO               0x00
 157 #define HSCX_STAT               0x04
 158
 159 /*
 160  *      AVM PnP Status Latch 0 read only bits
 161  */
 162 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 163 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 164 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 165 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 166 /* actually active LOW */
 167 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 168
 169 /*
 170  *      AVM Status Latch 0 write only bits
 171  */
 172 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 173 #define ASL_TIMERDISABLE        0x02  /* active high */
 174 #define ASL_TIMERRESET          0x04  /* active high */
 175 #define ASL_ENABLE_INT          0x08  /* active high */
 176 #define ASL_TESTBIT             0x10  /* active high */
 177
 178 /*
 179  *      AVM Status Latch 1 write only bits
 180  */
 181 #define ASL1_INTSEL              0x0f  /* active high */
 182 #define ASL1_ENABLE_IOM          0x80  /* active high */
 183
 184 /*
 185  * "HSCX" mode bits
 186  */
 187 #define  HSCX_MODE_ITF_FLG      0x01
 188 #define  HSCX_MODE_TRANS        0x02
 189 #define  HSCX_MODE_CCR_7        0x04
 190 #define  HSCX_MODE_CCR_16       0x08
 191 #define  HSCX_MODE_TESTLOOP     0x80
 192
 193 /*
 194  * "HSCX" status bits
 195  */
 196 #define  HSCX_STAT_RME          0x01
 197 #define  HSCX_STAT_RDO          0x10
 198 #define  HSCX_STAT_CRCVFRRAB    0x0E
 199 #define  HSCX_STAT_CRCVFR       0x06
 200 #define  HSCX_STAT_RML_MASK     0x3f00
 201
 202 /*
 203  * "HSCX" interrupt bits
 204  */
 205 #define  HSCX_INT_XPR           0x80
 206 #define  HSCX_INT_XDU           0x40
 207 #define  HSCX_INT_RPR           0x20
 208 #define  HSCX_INT_MASK          0xE0
 209
 210 /*
 211  * "HSCX" command bits
 212  */
 213 #define  HSCX_CMD_XRS           0x80
 214 #define  HSCX_CMD_XME           0x01
 215 #define  HSCX_CMD_RRS           0x20
 216 #define  HSCX_CMD_XML_MASK      0x3f00
 217
 218 /*
 219  * to prevent deactivating the "HSCX" when both channels are active we
 220  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 221  * flag in avm_pnp_bchannel_setup upon active and cleared upon deactivation.
 222  * It is set high to allow room for new flags.
 223  */
 224 #define HSCX_AVMA1PP_ACTIVE     0x1000
 225
 226 /*---------------------------------------------------------------------------*
 227  *      AVM read fifo routines
 228  *---------------------------------------------------------------------------*/
 229
 230 static void
 231 avm_pnp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 232 {
 233         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 234         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 235
 236         switch (what) {
 237                 case ISIC_WHAT_ISAC:
 238                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 239                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 240                         break;
 241                 case ISIC_WHAT_HSCXA:
 242                         hscx_read_fifo(0, buf, size, sc);
 243                         break;
 244                 case ISIC_WHAT_HSCXB:
 245                         hscx_read_fifo(1, buf, size, sc);
 246                         break;
 247         }
 248 }
 249
 250 static void
 251 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 252 {
 253         u_int8_t *ip;
 254         size_t cnt;
 255         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 256         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 257
 258         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 259         ip = (u_int8_t *)buf;
 260         cnt = 0;
 261         while (cnt++ < len)
 262         {
 263                 *ip++ = bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET);
 264         }
 265 }
 266
 267 /*---------------------------------------------------------------------------*
 268  *      AVM write fifo routines
 269  *---------------------------------------------------------------------------*/
 270 static void
 271 avm_pnp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 272 {
 273         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 274         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 275
 276         switch (what) {
 277                 case ISIC_WHAT_ISAC:
 278                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 279                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 280                         break;
 281                 case ISIC_WHAT_HSCXA:
 282                         hscx_write_fifo(0, buf, size, sc);
 283                         break;
 284                 case ISIC_WHAT_HSCXB:
 285                         hscx_write_fifo(1, buf, size, sc);
 286                         break;
 287         }
 288 }
 289
 290 static void
 291 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 292 {
 293         u_int8_t *ip;
 294         size_t cnt;
 295         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 296         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 297         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 298
 299         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 300         sc->avma1pp_txl = 0;
 301
 302         if (Bchan->out_mbuf_cur == NULL)
 303         {
 304           if (Bchan->bprot != BPROT_NONE)
 305                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 306         }
 307         if (len != sc->sc_bfifolen)
 308                 sc->avma1pp_txl = len;
 309
 310         hscx_write_reg(chan, HSCX_STAT, sc, 3);
 311
 312         ip = (u_int8_t *)buf;
 313         cnt = 0;
 314         while (cnt++ < len)
 315         {
 316                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET, *ip++);
 317         }
 318 }
 319
 320 /*---------------------------------------------------------------------------*
 321  *      AVM write register routines
 322  *---------------------------------------------------------------------------*/
 323
 324 static void
 325 avm_pnp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 326 {
 327         u_char reg_bank;
 328         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 329         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 330
 331         switch (what) {
 332                 case ISIC_WHAT_ISAC:
 333                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 334                         /* set the register bank */
 335                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 336                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 337                         break;
 338                 case ISIC_WHAT_HSCXA:
 339                         hscx_write_reg_val(0, offs, data, sc);
 340                         break;
 341                 case ISIC_WHAT_HSCXB:
 342                         hscx_write_reg_val(1, offs, data, sc);
 343                         break;
 344         }
 345 }
 346
 347 static void
 348 hscx_write_reg(int chan, u_int off, struct l1_softc *sc, u_int which)
 349 {
 350         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 351         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 352
 353         /* point at the correct channel */
 354         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 355         if (which & 4)
 356                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 2, sc->avma1pp_prot);
 357         if (which & 2)
 358                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off + 1, sc->avma1pp_txl);
 359         if (which & 1)
 360                 bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, sc->avma1pp_cmd);
 361 }
 362
 363 static void
 364 hscx_write_reg_val(int chan, u_int off, u_int8_t val, struct l1_softc *sc)
 365 {
 366         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 367         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 368
 369         /* point at the correct channel */
 370         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 371         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + off, val);
 372 }
 373
 374 /*---------------------------------------------------------------------------*
 375  *      AVM read register routines
 376  *---------------------------------------------------------------------------*/
 377 static u_int8_t
 378 avm_pnp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 379 {
 380         u_char reg_bank;
 381         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 382         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 383
 384         switch (what) {
 385                 case ISIC_WHAT_ISAC:
 386                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 387                         /* set the register bank */
 388                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 389                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 390                                 (offs & ISAC_REGSET_MASK)));
 391                 case ISIC_WHAT_HSCXA:
 392                         return hscx_read_reg(0, offs, sc);
 393                 case ISIC_WHAT_HSCXB:
 394                         return hscx_read_reg(1, offs, sc);
 395         }
 396         return 0;
 397 }
 398
 399 static u_int
 400 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 401 {
 402         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 403         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 404
 405         /* point at the correct channel */
 406         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, chan);
 407         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET + off));
 408 }
 409
 410
 411 static struct ifpnp_ids {
 412         u_long vend_id;
 413         char *id_str;
 414 } ifpnp_ids[] = {
 415         { 0x0009cd06,           "AVM Fritz!Card PnP"            },
 416         { 0, 0 }
 417 };
 418
 419 /*---------------------------------------------------------------------------*
 420  *      avm_pnp_probe - probe for a card
 421  *---------------------------------------------------------------------------*/
 422 static int
 423 avm_pnp_probe(device_t dev)
 424 {
 425         struct ifpnp_ids *ids;                  /* pnp id's */
 426         char *string = NULL;                            /* the name */
 427         u_int32_t vend_id = isa_get_vendorid(dev);      /* vendor id */
 428
 429         /* search table of knowd id's */
 430
 431         for(ids = ifpnp_ids; ids->vend_id != 0; ids++)
 432         {
 433                 if(vend_id == ids->vend_id)
 434                 {
 435                         string = ids->id_str;
 436                         break;
 437                 }
 438         }
 439
 440         if(string)              /* set name if we have one */
 441         {
 442                 device_set_desc(dev, string);   /* set description */
 443                 return 0;
 444         }
 445         else
 446         {
 447                 return ENXIO;
 448         }
 449 }
 450
 451 /*---------------------------------------------------------------------------*
 452  *      avm_pnp_attach - attach Fritz!Card PnP
 453  *---------------------------------------------------------------------------*/
 454 int
 455 avm_pnp_attach(device_t dev)
 456 {
 457         struct l1_softc *sc;
 458         u_int v;
 459         int unit, error = 0;
 460         u_int16_t vid;
 461         void *ih = 0;
 462         bus_space_handle_t bhandle;
 463         bus_space_tag_t btag;
 464
 465         crit_enter();
 466
 467         vid = isa_get_vendorid(dev);
 468         sc = device_get_softc(dev);
 469         unit = device_get_unit(dev);
 470         bzero(sc, sizeof(struct l1_softc));
 471
 472         /* probably not really required */
 473         if(unit > IFPNP_MAXUNIT) {
 474                 kprintf("avm_pnp%d: Error, unit > IFPNP_MAXUNIT!\n", unit);
 475                 crit_exit();
 476                 return(ENXIO);
 477         }
 478
 479         ifpnp_scp[unit] = sc;
 480
 481
 482         /* get io_base */
 483         if(!(sc->sc_resources.io_base[0] =
 484                         bus_alloc_resource(dev, SYS_RES_IOPORT,
 485                                                 &sc->sc_resources.io_rid[0],
 486                                                 0UL, ~0UL, 1, RF_ACTIVE ) ))
 487         {
 488                 kprintf("avm_pnp_attach: Couldn't get my io_base.\n");
 489                 return ENXIO;
 490         }
 491         if (sc->sc_resources.io_base[0] == NULL) {
 492                 kprintf("avm_pnp%d: couldn't map IO port\n", unit);
 493                 error = ENXIO;
 494                 goto fail;
 495         }
 496
 497         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 498         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 499
 500         /* will not be used for pnp devices */
 501         sc->sc_port = rman_get_start(sc->sc_resources.io_base[0]);
 502
 503         /* get irq, release io_base if we don't get it */
 504
 505         if(!(sc->sc_resources.irq =
 506                         bus_alloc_resource(dev, SYS_RES_IRQ,
 507                                            &sc->sc_resources.irq_rid,
 508                                            0UL, ~0UL, 1, RF_ACTIVE)))
 509         {
 510                 kprintf("avm_pnp%d: Could not get irq.\n",unit);
 511                 error = ENXIO;
 512                 goto fail;
 513         }
 514
 515         /* not needed */
 516         sc->sc_irq = rman_get_start(sc->sc_resources.irq);
 517         bus_setup_intr(dev, sc->sc_resources.irq, 0,
 518                        (void(*)(void*))avm_pnp_intr, sc,
 519                        &ih, NULL);
 520         sc->sc_unit = unit;
 521
 522         /* end of new-bus stuff */
 523
 524         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 525
 526         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 527         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 528
 529         /* setup access routines */
 530
 531         sc->clearirq = NULL;
 532         sc->readreg = avm_pnp_read_reg;
 533         sc->writereg = avm_pnp_write_reg;
 534
 535         sc->readfifo = avm_pnp_read_fifo;
 536         sc->writefifo = avm_pnp_write_fifo;
 537
 538         /* setup card type */
 539
 540         sc->sc_cardtyp = CARD_TYPEP_AVM_PNP;
 541
 542         /* setup IOM bus type */
 543
 544         sc->sc_bustyp = BUS_TYPE_IOM2;
 545
 546         /* set up some other miscellaneous things */
 547         sc->sc_ipac = 0;
 548         sc->sc_bfifolen = HSCX_FIFO_LEN;
 549
 550         /* reset the card */
 551         /* the Linux driver does this to clear any pending ISAC interrupts */
 552         v = 0;
 553         v = ISAC_READ(I_STAR);
 554         v = ISAC_READ(I_MODE);
 555         v = ISAC_READ(I_ADF2);
 556         v = ISAC_READ(I_ISTA);
 557         if (v & ISAC_ISTA_EXI)
 558         {
 559                  v = ISAC_READ(I_EXIR);
 560         }
 561         v = ISAC_READ(I_CIRR);
 562         ISAC_WRITE(I_MASK, 0xff);
 563         /* the Linux driver does this to clear any pending HSCX interrupts */
 564         v = hscx_read_reg(0, HSCX_STAT, sc);
 565         v = hscx_read_reg(1, HSCX_STAT, sc);
 566
 567         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 568         DELAY(SEC_DELAY/100); /* 10 ms */
 569         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 570         DELAY(SEC_DELAY/100); /* 10 ms */
 571         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 572         DELAY(SEC_DELAY/100); /* 10 ms */
 573
 574          kprintf("ifpnp%d: AVM Fritz!Card PnP Class %#x Revision %d \n", unit,
 575                         bus_space_read_1(btag, bhandle, CLASS_OFFSET),
 576                         bus_space_read_1(btag, bhandle, REVISION_OFFSET));
 577
 578          kprintf("ifpnp%d: ISAC %s (IOM-%c)\n", unit,
 579                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 580                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 581
 582
 583         /* init the ISAC */
 584         ifpnp_isac_init(sc);
 585
 586         /* init the "HSCX" */
 587         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 588
 589         avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 590
 591         /* can't use the normal B-Channel stuff */
 592         avm_pnp_init_linktab(sc);
 593
 594         /* set trace level */
 595
 596         sc->sc_trace = TRACE_OFF;
 597
 598         sc->sc_state = ISAC_IDLE;
 599
 600         sc->sc_ibuf = NULL;
 601         sc->sc_ib = NULL;
 602         sc->sc_ilen = 0;
 603
 604         sc->sc_obuf = NULL;
 605         sc->sc_op = NULL;
 606         sc->sc_ol = 0;
 607         sc->sc_freeflag = 0;
 608
 609         sc->sc_obuf2 = NULL;
 610         sc->sc_freeflag2 = 0;
 611
 612         callout_init(&sc->sc_T3_timeout);
 613         callout_init(&sc->sc_T4_timeout);
 614
 615         /* init higher protocol layers */
 616
 617         i4b_l1_mph_status_ind(L0IFPNPUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avm_pnp_l1mux_func);
 618
 619   fail:
 620         crit_exit();
 621         return(error);
 622 }
 623
 624 /*
 625  * this is the real interrupt routine
 626  */
 627 static void
 628 avm_pnp_hscx_intr(int h_chan, u_int stat, u_int cnt, struct l1_softc *sc)
 629 {
 630         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 631         int activity = -1;
 632
 633         NDBGL1(L1_H_IRQ, "%#x", stat);
 634
 635         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 636         {
 637                 chan->stat_XDU++;
 638                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 639                 /* abort the transmission */
 640                 sc->avma1pp_txl = 0;
 641                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 642                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 643                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 644                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 645
 646                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 647                 {
 648                         i4b_Bfreembuf(chan->out_mbuf_head);
 649                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 650                 }
 651         }
 652
 653         /*
 654          * The following is based on examination of the Linux driver.
 655          *
 656          * The logic here is different than with a "real" HSCX; all kinds
 657          * of information (interrupt/status bits) are in stat.
 658          *              HSCX_INT_RPR indicates a receive interrupt
 659          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 660          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 661          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 662          *                      CRC/framing errors are only reported in this state.
 663          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 664          *                                      CRC/framing error
 665          */
 666
 667         if(stat & HSCX_INT_RPR)
 668         {
 669                 int fifo_data_len;
 670                 int error = 0;
 671                 /* always have to read the FIFO, so use a scratch buffer */
 672                 u_char scrbuf[HSCX_FIFO_LEN];
 673
 674                 if(stat & HSCX_STAT_RDO)
 675                 {
 676                         chan->stat_RDO++;
 677                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 678                         error++;
 679                 }
 680
 681                 /*
 682                  * check whether we're receiving data for an inactive B-channel
 683                  * and discard it. This appears to happen for telephony when
 684                  * both B-channels are active and one is deactivated. Since
 685                  * it is not really possible to deactivate the channel in that
 686                  * case (the ASIC seems to deactivate _both_ channels), the
 687                  * "deactivated" channel keeps receiving data which can lead
 688                  * to exhaustion of mbufs and a kernel panic.
 689                  *
 690                  * This is a hack, but it's the only solution I can think of
 691                  * without having the documentation for the ASIC.
 692                  * GJ - 28 Nov 1999
 693                  */
 694                  if (chan->state == HSCX_IDLE)
 695                  {
 696                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 697                         error++;
 698                  }
 699
 700                 fifo_data_len = cnt;
 701
 702                 if(fifo_data_len == 0)
 703                         fifo_data_len = sc->sc_bfifolen;
 704
 705                 /* ALWAYS read data from HSCX fifo */
 706
 707                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 708                 chan->rxcount += fifo_data_len;
 709
 710                 /* all error conditions checked, now decide and take action */
 711
 712                 if(error == 0)
 713                 {
 714                         if(chan->in_mbuf == NULL)
 715                         {
 716                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 717                                         panic("L1 avm_pnp_hscx_intr: RME, cannot allocate mbuf!\n");
 718                                 chan->in_cbptr = chan->in_mbuf->m_data;
 719                                 chan->in_len = 0;
 720                         }
 721
 722                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 723                         {
 724                                 /* OK to copy the data */
 725                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 726                                 chan->in_cbptr += fifo_data_len;
 727                                 chan->in_len += fifo_data_len;
 728
 729                                 /* setup mbuf data length */
 730
 731                                 chan->in_mbuf->m_len = chan->in_len;
 732                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 733
 734                                 if(sc->sc_trace & TRACE_B_RX)
 735                                 {
 736                                         i4b_trace_hdr_t hdr;
 737                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 738                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 739                                         hdr.dir = FROM_NT;
 740                                         hdr.count = ++sc->sc_trace_bcount;
 741                                         MICROTIME(hdr.time);
 742                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 743                                 }
 744
 745                                 if (stat & HSCX_STAT_RME)
 746                                 {
 747                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 748                                   {
 749                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 750                                          activity = ACT_RX;
 751
 752                                          /* mark buffer ptr as unused */
 753
 754                                          chan->in_mbuf = NULL;
 755                                          chan->in_cbptr = NULL;
 756                                          chan->in_len = 0;
 757                                   }
 758                                   else
 759                                   {
 760                                                 chan->stat_CRC++;
 761                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 762                                           if (chan->in_mbuf != NULL)
 763                                           {
 764                                                   i4b_Bfreembuf(chan->in_mbuf);
 765                                                   chan->in_mbuf = NULL;
 766                                                   chan->in_cbptr = NULL;
 767                                                   chan->in_len = 0;
 768                                           }
 769                                   }
 770                                 }
 771                         } /* END enough space in mbuf */
 772                         else
 773                         {
 774                                  if(chan->bprot == BPROT_NONE)
 775                                  {
 776                                           /* setup mbuf data length */
 777
 778                                           chan->in_mbuf->m_len = chan->in_len;
 779                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 780
 781                                           if(sc->sc_trace & TRACE_B_RX)
 782                                           {
 783                                                         i4b_trace_hdr_t hdr;
 784                                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 785                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 786                                                         hdr.dir = FROM_NT;
 787                                                         hdr.count = ++sc->sc_trace_bcount;
 788                                                         MICROTIME(hdr.time);
 789                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 790                                                 }
 791
 792                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 793                                                  activity = ACT_RX;
 794
 795                                           /* move rx'd data to rx queue */
 796                                           if(!(IF_QFULL(&chan->rx_queue)))
 797                                           {
 798                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 799                                           }
 800                                           else
 801                                           {
 802                                                 i4b_Bfreembuf(chan->in_mbuf);
 803                                           }
 804                                           /* signal upper layer that data are available */
 805                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 806
 807                                           /* alloc new buffer */
 808
 809                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 810                                                  panic("L1 avm_pnp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 811
 812                                           /* setup new data ptr */
 813
 814                                           chan->in_cbptr = chan->in_mbuf->m_data;
 815
 816                                           /* OK to copy the data */
 817                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 818
 819                                           chan->in_cbptr += fifo_data_len;
 820                                           chan->in_len = fifo_data_len;
 821
 822                                           chan->rxcount += fifo_data_len;
 823                                         }
 824                                  else
 825                                         {
 826                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 827                                           chan->in_cbptr = chan->in_mbuf->m_data;
 828                                           chan->in_len = 0;
 829                                         }
 830                           }
 831                 } /* if(error == 0) */
 832                 else
 833                 {
 834                         /* land here for RDO */
 835                         if (chan->in_mbuf != NULL)
 836                         {
 837                                 i4b_Bfreembuf(chan->in_mbuf);
 838                                 chan->in_mbuf = NULL;
 839                                 chan->in_cbptr = NULL;
 840                                 chan->in_len = 0;
 841                         }
 842                         sc->avma1pp_txl = 0;
 843                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 844                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 845                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 846                         hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 847                 }
 848         }
 849
 850
 851         /* transmit fifo empty, new data can be written to fifo */
 852
 853         if(stat & HSCX_INT_XPR)
 854         {
 855                 /*
 856                  * for a description what is going on here, please have
 857                  * a look at isic_bchannel_start() in i4b_bchan.c !
 858                  */
 859
 860                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 861
 862                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 863                 {
 864                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 865
 866                         if(chan->out_mbuf_head == NULL)
 867                         {
 868                                 chan->state &= ~HSCX_TX_ACTIVE;
 869                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 870                         }
 871                         else
 872                         {
 873                                 chan->state |= HSCX_TX_ACTIVE;
 874                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 875                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 876                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 877
 878                                 if(sc->sc_trace & TRACE_B_TX)
 879                                 {
 880                                         i4b_trace_hdr_t hdr;
 881                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
 882                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 883                                         hdr.dir = FROM_TE;
 884                                         hdr.count = ++sc->sc_trace_bcount;
 885                                         MICROTIME(hdr.time);
 886                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 887                                 }
 888
 889                                 if(chan->bprot == BPROT_NONE)
 890                                 {
 891                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 892                                                 activity = ACT_TX;
 893                                 }
 894                                 else
 895                                 {
 896                                         activity = ACT_TX;
 897                                 }
 898                         }
 899                 }
 900
 901                 avm_pnp_hscx_fifo(chan, sc);
 902         }
 903
 904         /* call timeout handling routine */
 905
 906         if(activity == ACT_RX || activity == ACT_TX)
 907                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 908 }
 909
 910 /*
 911  * this is the main routine which checks each channel and then calls
 912  * the real interrupt routine as appropriate
 913  */
 914 static void
 915 avm_pnp_hscx_int_handler(struct l1_softc *sc)
 916 {
 917         u_char stat = 0;
 918         u_char cnt = 0;
 919
 920         stat = hscx_read_reg(0, HSCX_STAT, sc);
 921         if (stat & HSCX_INT_RPR)
 922           cnt = hscx_read_reg(0, HSCX_STAT+1, sc);
 923         if (stat & HSCX_INT_MASK)
 924           avm_pnp_hscx_intr(0, stat, cnt, sc);
 925
 926         cnt = 0;
 927         stat = hscx_read_reg(1, HSCX_STAT, sc);
 928         if (stat & HSCX_INT_RPR)
 929           cnt = hscx_read_reg(1, HSCX_STAT+1, sc);
 930         if (stat & HSCX_INT_MASK)
 931           avm_pnp_hscx_intr(1, stat, cnt, sc);
 932 }
 933
 934 static void
 935 avm_pnp_intr(void *xsc)
 936 {
 937         u_char stat;
 938         struct l1_softc *sc;
 939         bus_space_handle_t bhandle;
 940         bus_space_tag_t btag;
 941
 942         sc = xsc;
 943         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 944         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 945
 946         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 947         NDBGL1(L1_H_IRQ, "stat %x", stat);
 948         /* was there an interrupt from this card ? */
 949         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
 950                 return; /* no */
 951         /* interrupts are low active */
 952         if (!(stat & ASL_IRQ_TIMER))
 953           NDBGL1(L1_H_IRQ, "timer interrupt ???");
 954         if (!(stat & ASL_IRQ_HSCX))
 955         {
 956           NDBGL1(L1_H_IRQ, "HSCX");
 957                 avm_pnp_hscx_int_handler(sc);
 958         }
 959         if (!(stat & ASL_IRQ_ISAC))
 960         {
 961           NDBGL1(L1_H_IRQ, "ISAC");
 962                 ifpnp_isac_intr(sc);
 963         }
 964 }
 965
 966 static void
 967 avm_pnp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 968 {
 969         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 970
 971         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
 972                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
 973
 974         if (activate == 0)
 975         {
 976                 /* only deactivate if both channels are idle */
 977                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 978                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 979                 {
 980                         return;
 981                 }
 982                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 983                 sc->avma1pp_prot = HSCX_MODE_TRANS;
 984                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 985                 return;
 986         }
 987         if(chan->bprot == BPROT_RHDLC)
 988         {
 989                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
 990
 991                 /* HDLC Frames, transparent mode 0 */
 992                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
 993                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
 994                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
 995                 sc->avma1pp_cmd = HSCX_CMD_XRS;
 996                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
 997                 sc->avma1pp_cmd = 0;
 998         }
 999         else
1000         {
1001                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1002
1003                 /* Raw Telephony, extended transparent mode 1 */
1004                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1005                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1006                 hscx_write_reg(h_chan, HSCX_STAT, sc, 5);
1007                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1008                 hscx_write_reg(h_chan, HSCX_STAT, sc, 1);
1009                 sc->avma1pp_cmd = 0;
1010         }
1011 }
1012
1013 static void
1014 avm_pnp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1015 {
1016         struct l1_softc *sc = ifpnp_scp[unit];
1017         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1018
1019         crit_enter();
1020
1021         if(activate == 0)
1022         {
1023                 /* deactivation */
1024                 chan->state = HSCX_IDLE;
1025                 avm_pnp_hscx_init(sc, h_chan, activate);
1026         }
1027
1028         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1029                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1030
1031         /* general part */
1032
1033         chan->unit = sc->sc_unit;       /* unit number */
1034         chan->channel = h_chan;         /* B channel */
1035         chan->bprot = bprot;            /* B channel protocol */
1036         chan->state = HSCX_IDLE;        /* B channel state */
1037
1038         /* receiver part */
1039
1040         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1041
1042         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1043
1044         chan->rxcount = 0;              /* reset rx counter */
1045
1046         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1047
1048         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1049         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1050         chan->in_len = 0;               /* reset mbuf data len */
1051
1052         /* transmitter part */
1053
1054         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1055
1056         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1057
1058         chan->txcount = 0;              /* reset tx counter */
1059
1060         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1061
1062         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1063         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1064         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1065         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1066
1067         if(activate != 0)
1068         {
1069                 /* activation */
1070                 avm_pnp_hscx_init(sc, h_chan, activate);
1071                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1072         }
1073
1074         crit_exit();
1075 }
1076
1077 static void
1078 avm_pnp_bchannel_start(int unit, int h_chan)
1079 {
1080         struct l1_softc *sc = ifpnp_scp[unit];
1081         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1082         int activity = -1;
1083
1084         crit_enter();
1085         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1086         {
1087                 crit_exit();
1088                 return;                         /* yes, leave */
1089         }
1090
1091         /* get next mbuf from queue */
1092
1093         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1094
1095         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1096         {
1097                 crit_exit();
1098                 return;                         /* yes, exit */
1099         }
1100
1101         /* init current mbuf values */
1102
1103         chan->out_mbuf_cur = chan->out_mbuf_head;
1104         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1105         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1106
1107         /* activity indicator for timeout handling */
1108
1109         if(chan->bprot == BPROT_NONE)
1110         {
1111                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1112                         activity = ACT_TX;
1113         }
1114         else
1115         {
1116                 activity = ACT_TX;
1117         }
1118
1119         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1120
1121         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1122         {
1123                 i4b_trace_hdr_t hdr;
1124                 hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1125                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1126                 hdr.dir = FROM_TE;
1127                 hdr.count = ++sc->sc_trace_bcount;
1128                 MICROTIME(hdr.time);
1129                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1130         }
1131
1132         avm_pnp_hscx_fifo(chan, sc);
1133
1134         /* call timeout handling routine */
1135
1136         if(activity == ACT_RX || activity == ACT_TX)
1137                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1138
1139         crit_exit();
1140 }
1141
1142 /*---------------------------------------------------------------------------*
1143  *      return the address of isic drivers linktab
1144  *---------------------------------------------------------------------------*/
1145 static isdn_link_t *
1146 avm_pnp_ret_linktab(int unit, int channel)
1147 {
1148         struct l1_softc *sc = ifpnp_scp[unit];
1149         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1150
1151         return(&chan->isic_isdn_linktab);
1152 }
1153
1154 /*---------------------------------------------------------------------------*
1155  *      set the driver linktab in the b channel softc
1156  *---------------------------------------------------------------------------*/
1157 static void
1158 avm_pnp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1159 {
1160         struct l1_softc *sc = ifpnp_scp[unit];
1161         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1162
1163         chan->isic_drvr_linktab = dlt;
1164 }
1165
1166
1167 /*---------------------------------------------------------------------------*
1168  *      initialize our local linktab
1169  *---------------------------------------------------------------------------*/
1170 static void
1171 avm_pnp_init_linktab(struct l1_softc *sc)
1172 {
1173         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1174         isdn_link_t *lt = &chan->isic_isdn_linktab;
1175
1176         /* make sure the hardware driver is known to layer 4 */
1177         /* avoid overwriting if already set */
1178         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1179         {
1180                 ctrl_types[CTRL_PASSIVE].set_linktab = avm_pnp_set_linktab;
1181                 ctrl_types[CTRL_PASSIVE].get_linktab = avm_pnp_ret_linktab;
1182         }
1183
1184         /* local setup */
1185         lt->unit = sc->sc_unit;
1186         lt->channel = HSCX_CH_A;
1187         lt->bch_config = avm_pnp_bchannel_setup;
1188         lt->bch_tx_start = avm_pnp_bchannel_start;
1189         lt->bch_stat = avm_pnp_bchannel_stat;
1190         lt->tx_queue = &chan->tx_queue;
1191
1192         /* used by non-HDLC data transfers, i.e. telephony drivers */
1193         lt->rx_queue = &chan->rx_queue;
1194
1195         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1196         lt->rx_mbuf = &chan->in_mbuf;
1197
1198         chan = &sc->sc_chan[HSCX_CH_B];
1199         lt = &chan->isic_isdn_linktab;
1200
1201         lt->unit = sc->sc_unit;
1202         lt->channel = HSCX_CH_B;
1203         lt->bch_config = avm_pnp_bchannel_setup;
1204         lt->bch_tx_start = avm_pnp_bchannel_start;
1205         lt->bch_stat = avm_pnp_bchannel_stat;
1206         lt->tx_queue = &chan->tx_queue;
1207
1208         /* used by non-HDLC data transfers, i.e. telephony drivers */
1209         lt->rx_queue = &chan->rx_queue;
1210
1211         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1212         lt->rx_mbuf = &chan->in_mbuf;
1213 }
1214
1215 /*
1216  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1217  */
1218 static void
1219 avm_pnp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1220 {
1221         struct l1_softc *sc = ifpnp_scp[unit];
1222         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1223
1224         crit_enter();
1225
1226         bsp->outbytes = chan->txcount;
1227         bsp->inbytes = chan->rxcount;
1228
1229         chan->txcount = 0;
1230         chan->rxcount = 0;
1231
1232         crit_exit();
1233 }
1234
1235 /*---------------------------------------------------------------------------*
1236  *      fill HSCX fifo with data from the current mbuf
1237  *      Put this here until it can go into i4b_hscx.c
1238  *---------------------------------------------------------------------------*/
1239 static int
1240 avm_pnp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1241 {
1242         int len;
1243         int nextlen;
1244         int i;
1245         int cmd = 0;
1246         /* using a scratch buffer simplifies writing to the FIFO */
1247         u_char scrbuf[HSCX_FIFO_LEN];
1248
1249         len = 0;
1250
1251         /*
1252          * fill the HSCX tx fifo with data from the current mbuf. if
1253          * current mbuf holds less data than HSCX fifo length, try to
1254          * get the next mbuf from (a possible) mbuf chain. if there is
1255          * not enough data in a single mbuf or in a chain, then this
1256          * is the last mbuf and we tell the HSCX that it has to send
1257          * CRC and closing flag
1258          */
1259
1260         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1261         {
1262                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1263
1264 #ifdef NOTDEF
1265                 kprintf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1266                         chan->out_mbuf_head,
1267                         chan->out_mbuf_cur,
1268                         chan->out_mbuf_cur_ptr,
1269                         chan->out_mbuf_cur_len,
1270                         len,
1271                         nextlen);
1272 #endif
1273
1274                 cmd |= HSCX_CMDR_XTF;
1275                 /* collect the data in the scratch buffer */
1276                 for (i = 0; i < nextlen; i++)
1277                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1278
1279                 len += nextlen;
1280                 chan->txcount += nextlen;
1281
1282                 chan->out_mbuf_cur_ptr += nextlen;
1283                 chan->out_mbuf_cur_len -= nextlen;
1284
1285                 if(chan->out_mbuf_cur_len == 0)
1286                 {
1287                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1288                         {
1289                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1290                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1291
1292                                 if(sc->sc_trace & TRACE_B_TX)
1293                                 {
1294                                         i4b_trace_hdr_t hdr;
1295                                         hdr.unit = L0IFPNPUNIT(sc->sc_unit);
1296                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1297                                         hdr.dir = FROM_TE;
1298                                         hdr.count = ++sc->sc_trace_bcount;
1299                                         MICROTIME(hdr.time);
1300                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1301                                 }
1302                         }
1303                         else
1304                         {
1305                                 if (chan->bprot != BPROT_NONE)
1306                                         cmd |= HSCX_CMDR_XME;
1307                                 i4b_Bfreembuf(chan->out_mbuf_head);
1308                                 chan->out_mbuf_head = NULL;
1309                         }
1310                 }
1311         }
1312         /* write what we have from the scratch buf to the HSCX fifo */
1313         if (len != 0)
1314                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1315         return(cmd);
1316 }
1317
1318 /*---------------------------------------------------------------------------*
1319  *      ifpnp - ISAC interrupt routine
1320  *---------------------------------------------------------------------------*/
1321 static void
1322 ifpnp_isac_intr(struct l1_softc *sc)
1323 {
1324         u_char isac_irq_stat;
1325
1326         for(;;)
1327         {
1328                 /* get isac irq status */
1329                 isac_irq_stat = ISAC_READ(I_ISTA);
1330
1331                 if(isac_irq_stat)
1332                         ifpnp_isac_irq(sc, isac_irq_stat); /* isac handler */
1333                 else
1334                         break;
1335         }
1336
1337         ISAC_WRITE(I_MASK, 0xff);
1338
1339         DELAY(100);
1340
1341         ISAC_WRITE(I_MASK, ISAC_IMASK);
1342 }
1343
1344 /*---------------------------------------------------------------------------*
1345  *      ifpnp_recover - try to recover from irq lockup
1346  *---------------------------------------------------------------------------*/
1347 void
1348 ifpnp_recover(struct l1_softc *sc)
1349 {
1350         u_char byte;
1351
1352         /* get isac irq status */
1353
1354         byte = ISAC_READ(I_ISTA);
1355
1356         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1357
1358         if(byte & ISAC_ISTA_EXI)
1359                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1360
1361         if(byte & ISAC_ISTA_CISQ)
1362         {
1363                 byte = ISAC_READ(I_CIRR);
1364
1365                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1366
1367                 if(byte & ISAC_CIRR_SQC)
1368                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1369         }
1370
1371         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1372
1373         ISAC_WRITE(I_MASK, 0xff);
1374         DELAY(100);
1375         ISAC_WRITE(I_MASK, ISAC_IMASK);
1376 }
1377
1378 #endif /* NIFPNP > 0 */