2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/isa/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 void *oem_table_pointer;
114 u_short oem_table_size;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_long cpu_signature;
129 u_long feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 typedef int (*mptable_iter_func)(void *, const void *, int);
174 * this code MUST be enabled here and in mpboot.s.
175 * it follows the very early stages of AP boot by placing values in CMOS ram.
176 * it NORMALLY will never be needed and thus the primitive method for enabling.
179 #if defined(CHECK_POINTS)
180 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
181 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
183 #define CHECK_INIT(D); \
184 CHECK_WRITE(0x34, (D)); \
185 CHECK_WRITE(0x35, (D)); \
186 CHECK_WRITE(0x36, (D)); \
187 CHECK_WRITE(0x37, (D)); \
188 CHECK_WRITE(0x38, (D)); \
189 CHECK_WRITE(0x39, (D));
191 #define CHECK_PRINT(S); \
192 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
201 #else /* CHECK_POINTS */
203 #define CHECK_INIT(D)
204 #define CHECK_PRINT(S)
206 #endif /* CHECK_POINTS */
209 * Values to send to the POST hardware.
211 #define MP_BOOTADDRESS_POST 0x10
212 #define MP_PROBE_POST 0x11
213 #define MPTABLE_PASS1_POST 0x12
215 #define MP_START_POST 0x13
216 #define MP_ENABLE_POST 0x14
217 #define MPTABLE_PASS2_POST 0x15
219 #define START_ALL_APS_POST 0x16
220 #define INSTALL_AP_TRAMP_POST 0x17
221 #define START_AP_POST 0x18
223 #define MP_ANNOUNCE_POST 0x19
225 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226 int current_postcode;
228 /** XXX FIXME: what system files declare these??? */
229 extern struct region_descriptor r_gdt, r_idt;
231 int mp_naps; /* # of Applications processors */
233 static int mp_nbusses; /* # of busses */
234 int mp_napics; /* # of IO APICs */
237 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
238 u_int32_t *io_apic_versions;
242 u_int32_t cpu_apic_versions[MAXCPU];
244 extern int64_t tsc_offsets[];
246 extern u_long ebda_addr;
249 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
256 int cpu_num_to_apic_id[NAPICID];
258 int io_num_to_apic_id[NAPICID];
260 int apic_id_to_logical[NAPICID];
262 /* AP uses this during bootstrap. Do not staticize. */
266 /* Hotwire a 0->4MB V==P mapping */
267 extern pt_entry_t *KPTphys;
270 * SMP page table page. Setup by locore to point to a page table
271 * page from which we allocate per-cpu privatespace areas io_apics,
275 #define IO_MAPPING_START_INDEX \
276 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
278 extern pt_entry_t *SMPpt;
279 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
281 struct pcb stoppcbs[MAXCPU];
283 static basetable_entry basetable_entry_types[] =
285 {0, 20, "Processor"},
293 * Local data and functions.
296 static u_int boot_address;
297 static u_int base_memory;
298 static int mp_finish;
300 static void mp_enable(u_int boot_addr);
302 static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
304 static int mptable_probe(void);
305 static int mptable_search(void);
306 static int mptable_check(vm_paddr_t);
307 static int mptable_search_sig(u_int32_t target, int count);
308 static int mptable_hyperthread_fixup(u_int, int);
310 static void mptable_pass1(struct mptable_pos *);
311 static void mptable_pass2(struct mptable_pos *);
312 static void mptable_default(int type);
313 static void mptable_fix(void);
315 static int mptable_map(struct mptable_pos *, vm_paddr_t);
316 static void mptable_unmap(struct mptable_pos *);
317 static void mptable_imcr(struct mptable_pos *);
319 static int mptable_lapic_probe(struct lapic_enumerator *);
320 static void mptable_lapic_enumerate(struct lapic_enumerator *);
321 static void mptable_lapic_default(void);
324 static void setup_apic_irq_mapping(void);
325 static int apic_int_is_bus_type(int intr, int bus_type);
327 static int start_all_aps(u_int boot_addr);
328 static void install_ap_tramp(u_int boot_addr);
329 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
330 static int smitest(void);
332 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
333 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
334 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
337 * Calculate usable address in base memory for AP trampoline code.
340 mp_bootaddress(u_int basemem)
342 POSTCODE(MP_BOOTADDRESS_POST);
344 base_memory = basemem;
346 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
347 if ((base_memory - boot_address) < bootMP_size)
348 boot_address -= 4096; /* not enough, lower by 4k */
359 mpfps_paddr = mptable_search();
360 if (mptable_check(mpfps_paddr))
367 * Look for an Intel MP spec table (ie, SMP capable hardware).
376 * Make sure our SMPpt[] page table is big enough to hold all the
379 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
381 POSTCODE(MP_PROBE_POST);
383 /* see if EBDA exists */
384 if (ebda_addr != 0) {
385 /* search first 1K of EBDA */
386 target = (u_int32_t)ebda_addr;
387 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
390 /* last 1K of base memory, effective 'top of base' passed in */
391 target = (u_int32_t)(base_memory - 0x400);
392 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
396 /* search the BIOS */
397 target = (u_int32_t)BIOS_BASE;
398 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
401 /* search the extended BIOS */
402 target = (u_int32_t)BIOS_BASE2;
403 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
410 struct mptable_check_cbarg {
416 mptable_check_callback(void *xarg, const void *pos, int type)
418 const struct PROCENTRY *ent;
419 struct mptable_check_cbarg *arg = xarg;
425 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
429 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
430 if (arg->found_bsp) {
431 kprintf("more than one BSP in base MP table\n");
440 mptable_check(vm_paddr_t mpfps_paddr)
442 struct mptable_pos mpt;
443 struct mptable_check_cbarg arg;
447 if (mpfps_paddr == 0)
450 error = mptable_map(&mpt, mpfps_paddr);
454 if (mpt.mp_fps->mpfb1 != 0)
462 if (cth->apic_address == 0)
465 bzero(&arg, sizeof(arg));
466 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
468 if (arg.cpu_count == 0) {
469 kprintf("MP table contains no processor entries\n");
471 } else if (!arg.found_bsp) {
472 kprintf("MP table does not contains BSP entry\n");
482 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
484 int count, total_size;
485 const void *position;
487 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
488 total_size = cth->base_table_length - sizeof(struct MPCTH);
489 position = (const uint8_t *)cth + sizeof(struct MPCTH);
490 count = cth->entry_count;
495 KKASSERT(total_size >= 0);
496 if (total_size == 0) {
497 kprintf("invalid base MP table, "
498 "entry count and length mismatch\n");
502 type = *(const uint8_t *)position;
504 case 0: /* processor_entry */
505 case 1: /* bus_entry */
506 case 2: /* io_apic_entry */
507 case 3: /* int_entry */
508 case 4: /* int_entry */
511 kprintf("unknown base MP table entry type %d\n", type);
515 if (total_size < basetable_entry_types[type].length) {
516 kprintf("invalid base MP table length, "
517 "does not contain all entries\n");
520 total_size -= basetable_entry_types[type].length;
522 error = func(arg, position, type);
526 position = (const uint8_t *)position +
527 basetable_entry_types[type].length;
534 * Startup the SMP processors.
539 POSTCODE(MP_START_POST);
540 mp_enable(boot_address);
545 * Print various information about the SMP system hardware and setup.
552 POSTCODE(MP_ANNOUNCE_POST);
554 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
555 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
556 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
557 for (x = 1; x <= mp_naps; ++x) {
558 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
559 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
563 for (x = 0; x < mp_napics; ++x) {
564 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
565 kprintf(", version: 0x%08x", io_apic_versions[x]);
566 kprintf(", at 0x%08lx\n", io_apic_address[x]);
569 kprintf(" Warning: APIC I/O disabled\n");
574 * AP cpu's call this to sync up protected mode.
576 * WARNING! We must ensure that the cpu is sufficiently initialized to
577 * be able to use to the FP for our optimized bzero/bcopy code before
578 * we enter more mainstream C code.
580 * WARNING! %fs is not set up on entry. This routine sets up %fs.
586 int x, myid = bootAP;
588 struct mdglobaldata *md;
589 struct privatespace *ps;
591 ps = &CPU_prvspace[myid];
593 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
594 gdt_segs[GPROC0_SEL].ssd_base =
595 (int) &ps->mdglobaldata.gd_common_tss;
596 ps->mdglobaldata.mi.gd_prvspace = ps;
598 for (x = 0; x < NGDT; x++) {
599 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
602 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
603 r_gdt.rd_base = (int) &gdt[myid * NGDT];
604 lgdt(&r_gdt); /* does magic intra-segment return */
609 mdcpu->gd_currentldt = _default_ldt;
611 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
612 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
614 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
616 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
617 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
618 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
619 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
620 md->gd_common_tssd = *md->gd_tss_gdt;
624 * Set to a known state:
625 * Set by mpboot.s: CR0_PG, CR0_PE
626 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
629 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
631 pmap_set_opt(); /* PSE/4MB pages, etc */
633 /* set up CPU registers and state */
636 /* set up FPU state on the AP */
637 npxinit(__INITIAL_NPXCW__);
639 /* set up SSE registers */
643 /*******************************************************************
644 * local functions and data
648 * start the SMP system
651 mp_enable(u_int boot_addr)
657 vm_paddr_t mpfps_paddr;
658 struct mptable_pos mpt;
660 POSTCODE(MP_ENABLE_POST);
664 mpfps_paddr = mptable_probe();
666 mptable_map(&mpt, mpfps_paddr);
673 panic("no MP table, disable APIC_IO!\n");
675 mptable_map(&mpt, mpfps_paddr);
678 * Examine the MP table for needed info
685 /* Post scan cleanup */
688 setup_apic_irq_mapping();
690 /* fill the LOGICAL io_apic_versions table */
691 for (apic = 0; apic < mp_napics; ++apic) {
692 ux = io_apic_read(apic, IOAPIC_VER);
693 io_apic_versions[apic] = ux;
694 io_apic_set_id(apic, IO_TO_ID(apic));
697 /* program each IO APIC in the system */
698 for (apic = 0; apic < mp_napics; ++apic)
699 if (io_apic_setup(apic) < 0)
700 panic("IO APIC setup failure");
705 * These are required for SMP operation
708 /* install a 'Spurious INTerrupt' vector */
709 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
710 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
712 /* install an inter-CPU IPI for TLB invalidation */
713 setidt(XINVLTLB_OFFSET, Xinvltlb,
714 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
716 /* install an inter-CPU IPI for IPIQ messaging */
717 setidt(XIPIQ_OFFSET, Xipiq,
718 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
720 /* install a timer vector */
721 setidt(XTIMER_OFFSET, Xtimer,
722 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
724 /* install an inter-CPU IPI for CPU stop/restart */
725 setidt(XCPUSTOP_OFFSET, Xcpustop,
726 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
728 /* start each Application Processor */
729 start_all_aps(boot_addr);
734 * look for the MP spec signature
737 /* string defined by the Intel MP Spec as identifying the MP table */
738 #define MP_SIG 0x5f504d5f /* _MP_ */
739 #define NEXT(X) ((X) += 4)
741 mptable_search_sig(u_int32_t target, int count)
747 KKASSERT(target != 0);
749 map_size = count * sizeof(u_int32_t);
750 addr = pmap_mapdev((vm_paddr_t)target, map_size);
753 for (x = 0; x < count; NEXT(x)) {
754 if (addr[x] == MP_SIG) {
755 /* make array index a byte index */
756 ret = target + (x * sizeof(u_int32_t));
761 pmap_unmapdev((vm_offset_t)addr, map_size);
766 typedef struct BUSDATA {
768 enum busTypes bus_type;
771 typedef struct INTDATA {
781 typedef struct BUSTYPENAME {
788 static bus_type_name bus_type_table[] =
794 {UNKNOWN_BUSTYPE, "---"},
797 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
801 {UNKNOWN_BUSTYPE, "---"},
803 {UNKNOWN_BUSTYPE, "---"},
804 {UNKNOWN_BUSTYPE, "---"},
805 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"}
810 /* from MP spec v1.4, table 5-1 */
811 static int default_data[7][5] =
813 /* nbus, id0, type0, id1, type1 */
814 {1, 0, ISA, 255, 255},
815 {1, 0, EISA, 255, 255},
816 {1, 0, EISA, 255, 255},
817 {1, 0, MCA, 255, 255},
819 {2, 0, EISA, 1, PCI},
825 static bus_datum *bus_data;
827 /* the IO INT data, one entry per possible APIC INTerrupt */
828 static io_int *io_apic_ints;
833 static int processor_entry (const struct PROCENTRY *entry, int cpu);
835 static int bus_entry (const struct BUSENTRY *entry, int bus);
836 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
837 static int int_entry (const struct INTENTRY *entry, int intr);
838 static int lookup_bus_type (char *name);
844 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
846 const struct IOAPICENTRY *ioapic_ent;
849 case 1: /* bus_entry */
853 case 2: /* io_apic_entry */
855 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
856 io_apic_address[mp_napics++] =
857 (vm_offset_t)ioapic_ent->apic_address;
861 case 3: /* int_entry */
869 * 1st pass on motherboard's Intel MP specification table.
878 mptable_pass1(struct mptable_pos *mpt)
883 POSTCODE(MPTABLE_PASS1_POST);
886 KKASSERT(fps != NULL);
888 /* clear various tables */
889 for (x = 0; x < NAPICID; ++x)
890 io_apic_address[x] = ~0; /* IO APIC address table */
896 /* check for use of 'default' configuration */
897 if (fps->mpfb1 != 0) {
898 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
899 mp_nbusses = default_data[fps->mpfb1 - 1][0];
905 error = mptable_iterate_entries(mpt->mp_cth,
906 mptable_ioapic_pass1_callback, NULL);
908 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
912 struct mptable_ioapic2_cbarg {
919 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
921 struct mptable_ioapic2_cbarg *arg = xarg;
925 if (bus_entry(pos, arg->bus))
930 if (io_apic_entry(pos, arg->apic))
935 if (int_entry(pos, arg->intr))
943 * 2nd pass on motherboard's Intel MP specification table.
946 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
947 * IO_TO_ID(N), logical IO to APIC ID table
952 mptable_pass2(struct mptable_pos *mpt)
954 struct mptable_ioapic2_cbarg arg;
958 POSTCODE(MPTABLE_PASS2_POST);
961 KKASSERT(fps != NULL);
963 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
965 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
966 M_DEVBUF, M_WAITOK | M_ZERO);
967 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
969 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
972 for (x = 0; x < mp_napics; x++)
973 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
975 /* clear various tables */
976 for (x = 0; x < NAPICID; ++x) {
977 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
978 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
981 /* clear bus data table */
982 for (x = 0; x < mp_nbusses; ++x)
983 bus_data[x].bus_id = 0xff;
985 /* clear IO APIC INT table */
986 for (x = 0; x < (nintrs + 1); ++x) {
987 io_apic_ints[x].int_type = 0xff;
988 io_apic_ints[x].int_vector = 0xff;
991 /* check for use of 'default' configuration */
992 if (fps->mpfb1 != 0) {
993 mptable_default(fps->mpfb1);
997 bzero(&arg, sizeof(arg));
998 error = mptable_iterate_entries(mpt->mp_cth,
999 mptable_ioapic_pass2_callback, &arg);
1001 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1004 #endif /* APIC_IO */
1007 * Check if we should perform a hyperthreading "fix-up" to
1008 * enumerate any logical CPU's that aren't already listed
1011 * XXX: We assume that all of the physical CPUs in the
1012 * system have the same number of logical CPUs.
1014 * XXX: We assume that APIC ID's are allocated such that
1015 * the APIC ID's for a physical processor are aligned
1016 * with the number of logical CPU's in the processor.
1019 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1021 int i, id, lcpus_max, logical_cpus;
1023 if ((cpu_feature & CPUID_HTT) == 0)
1026 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1030 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1032 * INSTRUCTION SET REFERENCE, A-M (#253666)
1033 * Page 3-181, Table 3-20
1034 * "The nearest power-of-2 integer that is not smaller
1035 * than EBX[23:16] is the number of unique initial APIC
1036 * IDs reserved for addressing different logical
1037 * processors in a physical package."
1039 for (i = 0; ; ++i) {
1040 if ((1 << i) >= lcpus_max) {
1047 KKASSERT(cpu_count != 0);
1048 if (cpu_count == lcpus_max) {
1049 /* We have nothing to fix */
1051 } else if (cpu_count == 1) {
1052 /* XXX this may be incorrect */
1053 logical_cpus = lcpus_max;
1055 int cur, prev, dist;
1058 * Calculate the distances between two nearest
1059 * APIC IDs. If all such distances are same,
1060 * then it is the number of missing cpus that
1061 * we are going to fill later.
1063 dist = cur = prev = -1;
1064 for (id = 0; id < MAXCPU; ++id) {
1065 if ((id_mask & 1 << id) == 0)
1070 int new_dist = cur - prev;
1076 * Make sure that all distances
1077 * between two nearest APIC IDs
1080 if (dist != new_dist)
1088 /* Must be power of 2 */
1089 if (dist & (dist - 1))
1092 /* Can't exceed CPU package capacity */
1093 if (dist > lcpus_max)
1094 logical_cpus = lcpus_max;
1096 logical_cpus = dist;
1100 * For each APIC ID of a CPU that is set in the mask,
1101 * scan the other candidate APIC ID's for this
1102 * physical processor. If any of those ID's are
1103 * already in the table, then kill the fixup.
1105 for (id = 0; id < MAXCPU; id++) {
1106 if ((id_mask & 1 << id) == 0)
1108 /* First, make sure we are on a logical_cpus boundary. */
1109 if (id % logical_cpus != 0)
1111 for (i = id + 1; i < id + logical_cpus; i++)
1112 if ((id_mask & 1 << i) != 0)
1115 return logical_cpus;
1119 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1123 vm_size_t cth_mapsz = 0;
1125 bzero(mpt, sizeof(*mpt));
1127 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1128 if (fps->pap != 0) {
1130 * Map configuration table header to get
1131 * the base table size
1133 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1134 cth_mapsz = cth->base_table_length;
1135 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1137 if (cth_mapsz < sizeof(*cth)) {
1138 kprintf("invalid base MP table length %d\n",
1140 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1145 * Map the base table
1147 cth = pmap_mapdev(fps->pap, cth_mapsz);
1152 mpt->mp_cth_mapsz = cth_mapsz;
1158 mptable_unmap(struct mptable_pos *mpt)
1160 if (mpt->mp_cth != NULL) {
1161 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1163 mpt->mp_cth_mapsz = 0;
1165 if (mpt->mp_fps != NULL) {
1166 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1174 assign_apic_irq(int apic, int intpin, int irq)
1178 if (int_to_apicintpin[irq].ioapic != -1)
1179 panic("assign_apic_irq: inconsistent table");
1181 int_to_apicintpin[irq].ioapic = apic;
1182 int_to_apicintpin[irq].int_pin = intpin;
1183 int_to_apicintpin[irq].apic_address = ioapic[apic];
1184 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1186 for (x = 0; x < nintrs; x++) {
1187 if ((io_apic_ints[x].int_type == 0 ||
1188 io_apic_ints[x].int_type == 3) &&
1189 io_apic_ints[x].int_vector == 0xff &&
1190 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1191 io_apic_ints[x].dst_apic_int == intpin)
1192 io_apic_ints[x].int_vector = irq;
1197 revoke_apic_irq(int irq)
1203 if (int_to_apicintpin[irq].ioapic == -1)
1204 panic("revoke_apic_irq: inconsistent table");
1206 oldapic = int_to_apicintpin[irq].ioapic;
1207 oldintpin = int_to_apicintpin[irq].int_pin;
1209 int_to_apicintpin[irq].ioapic = -1;
1210 int_to_apicintpin[irq].int_pin = 0;
1211 int_to_apicintpin[irq].apic_address = NULL;
1212 int_to_apicintpin[irq].redirindex = 0;
1214 for (x = 0; x < nintrs; x++) {
1215 if ((io_apic_ints[x].int_type == 0 ||
1216 io_apic_ints[x].int_type == 3) &&
1217 io_apic_ints[x].int_vector != 0xff &&
1218 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1219 io_apic_ints[x].dst_apic_int == oldintpin)
1220 io_apic_ints[x].int_vector = 0xff;
1228 allocate_apic_irq(int intr)
1234 if (io_apic_ints[intr].int_vector != 0xff)
1235 return; /* Interrupt handler already assigned */
1237 if (io_apic_ints[intr].int_type != 0 &&
1238 (io_apic_ints[intr].int_type != 3 ||
1239 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1240 io_apic_ints[intr].dst_apic_int == 0)))
1241 return; /* Not INT or ExtInt on != (0, 0) */
1244 while (irq < APIC_INTMAPSIZE &&
1245 int_to_apicintpin[irq].ioapic != -1)
1248 if (irq >= APIC_INTMAPSIZE)
1249 return; /* No free interrupt handlers */
1251 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1252 intpin = io_apic_ints[intr].dst_apic_int;
1254 assign_apic_irq(apic, intpin, irq);
1255 io_apic_setup_intpin(apic, intpin);
1260 swap_apic_id(int apic, int oldid, int newid)
1267 return; /* Nothing to do */
1269 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1270 apic, oldid, newid);
1272 /* Swap physical APIC IDs in interrupt entries */
1273 for (x = 0; x < nintrs; x++) {
1274 if (io_apic_ints[x].dst_apic_id == oldid)
1275 io_apic_ints[x].dst_apic_id = newid;
1276 else if (io_apic_ints[x].dst_apic_id == newid)
1277 io_apic_ints[x].dst_apic_id = oldid;
1280 /* Swap physical APIC IDs in IO_TO_ID mappings */
1281 for (oapic = 0; oapic < mp_napics; oapic++)
1282 if (IO_TO_ID(oapic) == newid)
1285 if (oapic < mp_napics) {
1286 kprintf("Changing APIC ID for IO APIC #%d from "
1287 "%d to %d in MP table\n",
1288 oapic, newid, oldid);
1289 IO_TO_ID(oapic) = oldid;
1291 IO_TO_ID(apic) = newid;
1296 fix_id_to_io_mapping(void)
1300 for (x = 0; x < NAPICID; x++)
1303 for (x = 0; x <= mp_naps; x++)
1304 if (CPU_TO_ID(x) < NAPICID)
1305 ID_TO_IO(CPU_TO_ID(x)) = x;
1307 for (x = 0; x < mp_napics; x++)
1308 if (IO_TO_ID(x) < NAPICID)
1309 ID_TO_IO(IO_TO_ID(x)) = x;
1314 first_free_apic_id(void)
1318 for (freeid = 0; freeid < NAPICID; freeid++) {
1319 for (x = 0; x <= mp_naps; x++)
1320 if (CPU_TO_ID(x) == freeid)
1324 for (x = 0; x < mp_napics; x++)
1325 if (IO_TO_ID(x) == freeid)
1336 io_apic_id_acceptable(int apic, int id)
1338 int cpu; /* Logical CPU number */
1339 int oapic; /* Logical IO APIC number for other IO APIC */
1342 return 0; /* Out of range */
1344 for (cpu = 0; cpu <= mp_naps; cpu++)
1345 if (CPU_TO_ID(cpu) == id)
1346 return 0; /* Conflict with CPU */
1348 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1349 if (IO_TO_ID(oapic) == id)
1350 return 0; /* Conflict with other APIC */
1352 return 1; /* ID is acceptable for IO APIC */
1357 io_apic_find_int_entry(int apic, int pin)
1361 /* search each of the possible INTerrupt sources */
1362 for (x = 0; x < nintrs; ++x) {
1363 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1364 (pin == io_apic_ints[x].dst_apic_int))
1365 return (&io_apic_ints[x]);
1371 * parse an Intel MP specification table
1378 int apic; /* IO APIC unit number */
1379 int freeid; /* Free physical APIC ID */
1380 int physid; /* Current physical IO APIC ID */
1382 int bus_0 = 0; /* Stop GCC warning */
1383 int bus_pci = 0; /* Stop GCC warning */
1387 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1388 * did it wrong. The MP spec says that when more than 1 PCI bus
1389 * exists the BIOS must begin with bus entries for the PCI bus and use
1390 * actual PCI bus numbering. This implies that when only 1 PCI bus
1391 * exists the BIOS can choose to ignore this ordering, and indeed many
1392 * MP motherboards do ignore it. This causes a problem when the PCI
1393 * sub-system makes requests of the MP sub-system based on PCI bus
1394 * numbers. So here we look for the situation and renumber the
1395 * busses and associated INTs in an effort to "make it right".
1398 /* find bus 0, PCI bus, count the number of PCI busses */
1399 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1400 if (bus_data[x].bus_id == 0) {
1403 if (bus_data[x].bus_type == PCI) {
1409 * bus_0 == slot of bus with ID of 0
1410 * bus_pci == slot of last PCI bus encountered
1413 /* check the 1 PCI bus case for sanity */
1414 /* if it is number 0 all is well */
1415 if (num_pci_bus == 1 &&
1416 bus_data[bus_pci].bus_id != 0) {
1418 /* mis-numbered, swap with whichever bus uses slot 0 */
1420 /* swap the bus entry types */
1421 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1422 bus_data[bus_0].bus_type = PCI;
1424 /* swap each relavant INTerrupt entry */
1425 id = bus_data[bus_pci].bus_id;
1426 for (x = 0; x < nintrs; ++x) {
1427 if (io_apic_ints[x].src_bus_id == id) {
1428 io_apic_ints[x].src_bus_id = 0;
1430 else if (io_apic_ints[x].src_bus_id == 0) {
1431 io_apic_ints[x].src_bus_id = id;
1436 /* Assign IO APIC IDs.
1438 * First try the existing ID. If a conflict is detected, try
1439 * the ID in the MP table. If a conflict is still detected, find
1442 * We cannot use the ID_TO_IO table before all conflicts has been
1443 * resolved and the table has been corrected.
1445 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1447 /* First try to use the value set by the BIOS */
1448 physid = io_apic_get_id(apic);
1449 if (io_apic_id_acceptable(apic, physid)) {
1450 if (IO_TO_ID(apic) != physid)
1451 swap_apic_id(apic, IO_TO_ID(apic), physid);
1455 /* Then check if the value in the MP table is acceptable */
1456 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1459 /* Last resort, find a free APIC ID and use it */
1460 freeid = first_free_apic_id();
1461 if (freeid >= NAPICID)
1462 panic("No free physical APIC IDs found");
1464 if (io_apic_id_acceptable(apic, freeid)) {
1465 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1468 panic("Free physical APIC ID not usable");
1470 fix_id_to_io_mapping();
1472 /* detect and fix broken Compaq MP table */
1473 if (apic_int_type(0, 0) == -1) {
1474 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1475 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1476 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1477 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1478 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1479 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1481 } else if (apic_int_type(0, 0) == 0) {
1482 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1483 for (x = 0; x < nintrs; ++x)
1484 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1485 (0 == io_apic_ints[x].dst_apic_int)) {
1486 io_apic_ints[x].int_type = 3;
1487 io_apic_ints[x].int_vector = 0xff;
1493 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1494 * controllers universally come in pairs. If IRQ 14 is specified
1495 * as an ISA interrupt, then IRQ 15 had better be too.
1497 * [ Shuttle XPC / AMD Athlon X2 ]
1498 * The MPTable is missing an entry for IRQ 15. Note that the
1499 * ACPI table has an entry for both 14 and 15.
1501 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1502 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1503 io14 = io_apic_find_int_entry(0, 14);
1504 io_apic_ints[nintrs] = *io14;
1505 io_apic_ints[nintrs].src_bus_irq = 15;
1506 io_apic_ints[nintrs].dst_apic_int = 15;
1511 /* Assign low level interrupt handlers */
1513 setup_apic_irq_mapping(void)
1519 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1520 int_to_apicintpin[x].ioapic = -1;
1521 int_to_apicintpin[x].int_pin = 0;
1522 int_to_apicintpin[x].apic_address = NULL;
1523 int_to_apicintpin[x].redirindex = 0;
1525 /* Default to masked */
1526 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1529 /* First assign ISA/EISA interrupts */
1530 for (x = 0; x < nintrs; x++) {
1531 int_vector = io_apic_ints[x].src_bus_irq;
1532 if (int_vector < APIC_INTMAPSIZE &&
1533 io_apic_ints[x].int_vector == 0xff &&
1534 int_to_apicintpin[int_vector].ioapic == -1 &&
1535 (apic_int_is_bus_type(x, ISA) ||
1536 apic_int_is_bus_type(x, EISA)) &&
1537 io_apic_ints[x].int_type == 0) {
1538 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1539 io_apic_ints[x].dst_apic_int,
1544 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1545 for (x = 0; x < nintrs; x++) {
1546 if (io_apic_ints[x].dst_apic_int == 0 &&
1547 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1548 io_apic_ints[x].int_vector == 0xff &&
1549 int_to_apicintpin[0].ioapic == -1 &&
1550 io_apic_ints[x].int_type == 3) {
1551 assign_apic_irq(0, 0, 0);
1555 /* PCI interrupt assignment is deferred */
1561 mp_set_cpuids(int cpu_id, int apic_id)
1563 CPU_TO_ID(cpu_id) = apic_id;
1564 ID_TO_CPU(apic_id) = cpu_id;
1568 processor_entry(const struct PROCENTRY *entry, int cpu)
1572 /* check for usability */
1573 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1576 /* check for BSP flag */
1577 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1578 mp_set_cpuids(0, entry->apic_id);
1579 return 0; /* its already been counted */
1582 /* add another AP to list, if less than max number of CPUs */
1583 else if (cpu < MAXCPU) {
1584 mp_set_cpuids(cpu, entry->apic_id);
1594 bus_entry(const struct BUSENTRY *entry, int bus)
1599 /* encode the name into an index */
1600 for (x = 0; x < 6; ++x) {
1601 if ((c = entry->bus_type[x]) == ' ')
1607 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1608 panic("unknown bus type: '%s'", name);
1610 bus_data[bus].bus_id = entry->bus_id;
1611 bus_data[bus].bus_type = x;
1617 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1619 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1622 IO_TO_ID(apic) = entry->apic_id;
1623 ID_TO_IO(entry->apic_id) = apic;
1629 lookup_bus_type(char *name)
1633 for (x = 0; x < MAX_BUSTYPE; ++x)
1634 if (strcmp(bus_type_table[x].name, name) == 0)
1635 return bus_type_table[x].type;
1637 return UNKNOWN_BUSTYPE;
1641 int_entry(const struct INTENTRY *entry, int intr)
1645 io_apic_ints[intr].int_type = entry->int_type;
1646 io_apic_ints[intr].int_flags = entry->int_flags;
1647 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1648 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1649 if (entry->dst_apic_id == 255) {
1650 /* This signal goes to all IO APICS. Select an IO APIC
1651 with sufficient number of interrupt pins */
1652 for (apic = 0; apic < mp_napics; apic++)
1653 if (((io_apic_read(apic, IOAPIC_VER) &
1654 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1655 entry->dst_apic_int)
1657 if (apic < mp_napics)
1658 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1660 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1662 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1663 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1669 apic_int_is_bus_type(int intr, int bus_type)
1673 for (bus = 0; bus < mp_nbusses; ++bus)
1674 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1675 && ((int) bus_data[bus].bus_type == bus_type))
1682 * Given a traditional ISA INT mask, return an APIC mask.
1685 isa_apic_mask(u_int isa_mask)
1690 #if defined(SKIP_IRQ15_REDIRECT)
1691 if (isa_mask == (1 << 15)) {
1692 kprintf("skipping ISA IRQ15 redirect\n");
1695 #endif /* SKIP_IRQ15_REDIRECT */
1697 isa_irq = ffs(isa_mask); /* find its bit position */
1698 if (isa_irq == 0) /* doesn't exist */
1700 --isa_irq; /* make it zero based */
1702 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1706 return (1 << apic_pin); /* convert pin# to a mask */
1710 * Determine which APIC pin an ISA/EISA INT is attached to.
1712 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1713 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1714 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1715 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1717 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1719 isa_apic_irq(int isa_irq)
1723 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1724 if (INTTYPE(intr) == 0) { /* standard INT */
1725 if (SRCBUSIRQ(intr) == isa_irq) {
1726 if (apic_int_is_bus_type(intr, ISA) ||
1727 apic_int_is_bus_type(intr, EISA)) {
1728 if (INTIRQ(intr) == 0xff)
1729 return -1; /* unassigned */
1730 return INTIRQ(intr); /* found */
1735 return -1; /* NOT found */
1740 * Determine which APIC pin a PCI INT is attached to.
1742 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1743 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1744 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1746 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1750 --pciInt; /* zero based */
1752 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1753 if ((INTTYPE(intr) == 0) /* standard INT */
1754 && (SRCBUSID(intr) == pciBus)
1755 && (SRCBUSDEVICE(intr) == pciDevice)
1756 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1757 if (apic_int_is_bus_type(intr, PCI)) {
1758 if (INTIRQ(intr) == 0xff)
1759 allocate_apic_irq(intr);
1760 if (INTIRQ(intr) == 0xff)
1761 return -1; /* unassigned */
1762 return INTIRQ(intr); /* exact match */
1767 return -1; /* NOT found */
1771 next_apic_irq(int irq)
1778 for (intr = 0; intr < nintrs; intr++) {
1779 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1781 bus = SRCBUSID(intr);
1782 bustype = apic_bus_type(bus);
1783 if (bustype != ISA &&
1789 if (intr >= nintrs) {
1792 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1793 if (INTTYPE(ointr) != 0)
1795 if (bus != SRCBUSID(ointr))
1797 if (bustype == PCI) {
1798 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1800 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1803 if (bustype == ISA || bustype == EISA) {
1804 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1807 if (INTPIN(intr) == INTPIN(ointr))
1811 if (ointr >= nintrs) {
1814 return INTIRQ(ointr);
1829 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1832 * Exactly what this means is unclear at this point. It is a solution
1833 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1834 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1835 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1839 undirect_isa_irq(int rirq)
1843 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1844 /** FIXME: tickle the MB redirector chip */
1848 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1855 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1858 undirect_pci_irq(int rirq)
1862 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1864 /** FIXME: tickle the MB redirector chip */
1868 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1878 * given a bus ID, return:
1879 * the bus type if found
1883 apic_bus_type(int id)
1887 for (x = 0; x < mp_nbusses; ++x)
1888 if (bus_data[x].bus_id == id)
1889 return bus_data[x].bus_type;
1895 * given a LOGICAL APIC# and pin#, return:
1896 * the associated src bus ID if found
1900 apic_src_bus_id(int apic, int pin)
1904 /* search each of the possible INTerrupt sources */
1905 for (x = 0; x < nintrs; ++x)
1906 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1907 (pin == io_apic_ints[x].dst_apic_int))
1908 return (io_apic_ints[x].src_bus_id);
1910 return -1; /* NOT found */
1914 * given a LOGICAL APIC# and pin#, return:
1915 * the associated src bus IRQ if found
1919 apic_src_bus_irq(int apic, int pin)
1923 for (x = 0; x < nintrs; x++)
1924 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1925 (pin == io_apic_ints[x].dst_apic_int))
1926 return (io_apic_ints[x].src_bus_irq);
1928 return -1; /* NOT found */
1933 * given a LOGICAL APIC# and pin#, return:
1934 * the associated INTerrupt type if found
1938 apic_int_type(int apic, int pin)
1942 /* search each of the possible INTerrupt sources */
1943 for (x = 0; x < nintrs; ++x) {
1944 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1945 (pin == io_apic_ints[x].dst_apic_int))
1946 return (io_apic_ints[x].int_type);
1948 return -1; /* NOT found */
1952 * Return the IRQ associated with an APIC pin
1955 apic_irq(int apic, int pin)
1960 for (x = 0; x < nintrs; ++x) {
1961 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1962 (pin == io_apic_ints[x].dst_apic_int)) {
1963 res = io_apic_ints[x].int_vector;
1966 if (apic != int_to_apicintpin[res].ioapic)
1967 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1968 if (pin != int_to_apicintpin[res].int_pin)
1969 panic("apic_irq inconsistent table (2)");
1978 * given a LOGICAL APIC# and pin#, return:
1979 * the associated trigger mode if found
1983 apic_trigger(int apic, int pin)
1987 /* search each of the possible INTerrupt sources */
1988 for (x = 0; x < nintrs; ++x)
1989 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1990 (pin == io_apic_ints[x].dst_apic_int))
1991 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1993 return -1; /* NOT found */
1998 * given a LOGICAL APIC# and pin#, return:
1999 * the associated 'active' level if found
2003 apic_polarity(int apic, int pin)
2007 /* search each of the possible INTerrupt sources */
2008 for (x = 0; x < nintrs; ++x)
2009 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2010 (pin == io_apic_ints[x].dst_apic_int))
2011 return (io_apic_ints[x].int_flags & 0x03);
2013 return -1; /* NOT found */
2017 * set data according to MP defaults
2018 * FIXME: probably not complete yet...
2021 mptable_default(int type)
2027 kprintf(" MP default config type: %d\n", type);
2030 kprintf(" bus: ISA, APIC: 82489DX\n");
2033 kprintf(" bus: EISA, APIC: 82489DX\n");
2036 kprintf(" bus: EISA, APIC: 82489DX\n");
2039 kprintf(" bus: MCA, APIC: 82489DX\n");
2042 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2045 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2048 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2051 kprintf(" future type\n");
2057 /* one and only IO APIC */
2058 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2061 * sanity check, refer to MP spec section 3.6.6, last paragraph
2062 * necessary as some hardware isn't properly setting up the IO APIC
2064 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2065 if (io_apic_id != 2) {
2067 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2068 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2069 io_apic_set_id(0, 2);
2072 IO_TO_ID(0) = io_apic_id;
2073 ID_TO_IO(io_apic_id) = 0;
2075 /* fill out bus entries */
2084 bus_data[0].bus_id = default_data[type - 1][1];
2085 bus_data[0].bus_type = default_data[type - 1][2];
2086 bus_data[1].bus_id = default_data[type - 1][3];
2087 bus_data[1].bus_type = default_data[type - 1][4];
2090 /* case 4: case 7: MCA NOT supported */
2091 default: /* illegal/reserved */
2092 panic("BAD default MP config: %d", type);
2096 /* general cases from MP v1.4, table 5-2 */
2097 for (pin = 0; pin < 16; ++pin) {
2098 io_apic_ints[pin].int_type = 0;
2099 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2100 io_apic_ints[pin].src_bus_id = 0;
2101 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2102 io_apic_ints[pin].dst_apic_id = io_apic_id;
2103 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2106 /* special cases from MP v1.4, table 5-2 */
2108 io_apic_ints[2].int_type = 0xff; /* N/C */
2109 io_apic_ints[13].int_type = 0xff; /* N/C */
2110 #if !defined(APIC_MIXED_MODE)
2112 panic("sorry, can't support type 2 default yet");
2113 #endif /* APIC_MIXED_MODE */
2116 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2119 io_apic_ints[0].int_type = 0xff; /* N/C */
2121 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2124 #endif /* APIC_IO */
2127 * Map a physical memory address representing I/O into KVA. The I/O
2128 * block is assumed not to cross a page boundary.
2131 permanent_io_mapping(vm_paddr_t pa)
2137 KKASSERT(pa < 0x100000000LL);
2139 pgeflag = 0; /* not used for SMP yet */
2142 * If the requested physical address has already been incidently
2143 * mapped, just use the existing mapping. Otherwise create a new
2146 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2147 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2148 ((vm_offset_t)pa & PG_FRAME)) {
2152 if (i == SMPpt_alloc_index) {
2153 if (i == NPTEPG - 2) {
2154 panic("permanent_io_mapping: We ran out of space"
2157 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2158 ((vm_offset_t)pa & PG_FRAME));
2159 ++SMPpt_alloc_index;
2161 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2162 ((vm_offset_t)pa & PAGE_MASK);
2163 return ((void *)vaddr);
2167 * start each AP in our list
2170 start_all_aps(u_int boot_addr)
2177 u_char mpbiosreason;
2178 u_long mpbioswarmvec;
2179 struct mdglobaldata *gd;
2180 struct privatespace *ps;
2184 POSTCODE(START_ALL_APS_POST);
2186 /* Initialize BSP's local APIC */
2187 apic_initialize(TRUE);
2189 /* install the AP 1st level boot code */
2190 install_ap_tramp(boot_addr);
2193 /* save the current value of the warm-start vector */
2194 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2195 outb(CMOS_REG, BIOS_RESET);
2196 mpbiosreason = inb(CMOS_DATA);
2198 /* setup a vector to our boot code */
2199 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2200 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2201 outb(CMOS_REG, BIOS_RESET);
2202 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2205 * If we have a TSC we can figure out the SMI interrupt rate.
2206 * The SMI does not necessarily use a constant rate. Spend
2207 * up to 250ms trying to figure it out.
2210 if (cpu_feature & CPUID_TSC) {
2211 set_apic_timer(275000);
2212 smilast = read_apic_timer();
2213 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2214 smicount = smitest();
2215 if (smibest == 0 || smilast - smicount < smibest)
2216 smibest = smilast - smicount;
2219 if (smibest > 250000)
2222 smibest = smibest * (int64_t)1000000 /
2223 get_apic_timer_frequency();
2227 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2228 1000000 / smibest, smibest);
2231 /* set up temporary P==V mapping for AP boot */
2232 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2233 kptbase = (uintptr_t)(void *)KPTphys;
2234 for (x = 0; x < NKPT; x++) {
2235 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2236 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2241 for (x = 1; x <= mp_naps; ++x) {
2243 /* This is a bit verbose, it will go away soon. */
2245 /* first page of AP's private space */
2246 pg = x * i386_btop(sizeof(struct privatespace));
2248 /* allocate new private data page(s) */
2249 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2250 MDGLOBALDATA_BASEALLOC_SIZE);
2251 /* wire it into the private page table page */
2252 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2253 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2254 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2256 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2258 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2259 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2260 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2261 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2263 /* allocate and set up an idle stack data page */
2264 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2265 for (i = 0; i < UPAGES; i++) {
2266 SMPpt[pg + 4 + i] = (pt_entry_t)
2267 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2270 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2271 bzero(gd, sizeof(*gd));
2272 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2274 /* prime data page for it to use */
2275 mi_gdinit(&gd->mi, x);
2277 gd->gd_CMAP1 = &SMPpt[pg + 0];
2278 gd->gd_CMAP2 = &SMPpt[pg + 1];
2279 gd->gd_CMAP3 = &SMPpt[pg + 2];
2280 gd->gd_PMAP1 = &SMPpt[pg + 3];
2281 gd->gd_GDMAP1 = &PTD[KGDTDI+x];
2282 gd->gd_CADDR1 = ps->CPAGE1;
2283 gd->gd_CADDR2 = ps->CPAGE2;
2284 gd->gd_CADDR3 = ps->CPAGE3;
2285 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2286 gd->gd_GDADDR1= (unsigned *)VADDR(KGDTDI+x, 0);
2287 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2288 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2291 * Setup the AP boot stack
2293 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2296 /* attempt to start the Application Processor */
2297 CHECK_INIT(99); /* setup checkpoints */
2298 if (!start_ap(gd, boot_addr, smibest)) {
2299 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2300 CHECK_PRINT("trace"); /* show checkpoints */
2301 /* better panic as the AP may be running loose */
2302 kprintf("panic y/n? [y] ");
2303 if (cngetc() != 'n')
2306 CHECK_PRINT("trace"); /* show checkpoints */
2308 /* record its version info */
2309 cpu_apic_versions[x] = cpu_apic_versions[0];
2312 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2315 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2316 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2319 ncpus2_shift = shift;
2320 ncpus2 = 1 << shift;
2321 ncpus2_mask = ncpus2 - 1;
2323 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2324 if ((1 << shift) < ncpus)
2326 ncpus_fit = 1 << shift;
2327 ncpus_fit_mask = ncpus_fit - 1;
2329 /* build our map of 'other' CPUs */
2330 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2331 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2332 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2334 /* fill in our (BSP) APIC version */
2335 cpu_apic_versions[0] = lapic.version;
2337 /* restore the warmstart vector */
2338 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2339 outb(CMOS_REG, BIOS_RESET);
2340 outb(CMOS_DATA, mpbiosreason);
2343 * NOTE! The idlestack for the BSP was setup by locore. Finish
2344 * up, clean out the P==V mapping we did earlier.
2346 for (x = 0; x < NKPT; x++)
2350 /* number of APs actually started */
2356 * load the 1st level AP boot code into base memory.
2359 /* targets for relocation */
2360 extern void bigJump(void);
2361 extern void bootCodeSeg(void);
2362 extern void bootDataSeg(void);
2363 extern void MPentry(void);
2364 extern u_int MP_GDT;
2365 extern u_int mp_gdtbase;
2368 install_ap_tramp(u_int boot_addr)
2371 int size = *(int *) ((u_long) & bootMP_size);
2372 u_char *src = (u_char *) ((u_long) bootMP);
2373 u_char *dst = (u_char *) boot_addr + KERNBASE;
2374 u_int boot_base = (u_int) bootMP;
2379 POSTCODE(INSTALL_AP_TRAMP_POST);
2381 for (x = 0; x < size; ++x)
2385 * modify addresses in code we just moved to basemem. unfortunately we
2386 * need fairly detailed info about mpboot.s for this to work. changes
2387 * to mpboot.s might require changes here.
2390 /* boot code is located in KERNEL space */
2391 dst = (u_char *) boot_addr + KERNBASE;
2393 /* modify the lgdt arg */
2394 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2395 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2397 /* modify the ljmp target for MPentry() */
2398 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2399 *dst32 = ((u_int) MPentry - KERNBASE);
2401 /* modify the target for boot code segment */
2402 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2403 dst8 = (u_int8_t *) (dst16 + 1);
2404 *dst16 = (u_int) boot_addr & 0xffff;
2405 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2407 /* modify the target for boot data segment */
2408 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2409 dst8 = (u_int8_t *) (dst16 + 1);
2410 *dst16 = (u_int) boot_addr & 0xffff;
2411 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2416 * This function starts the AP (application processor) identified
2417 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2418 * to accomplish this. This is necessary because of the nuances
2419 * of the different hardware we might encounter. It ain't pretty,
2420 * but it seems to work.
2422 * NOTE: eventually an AP gets to ap_init(), which is called just
2423 * before the AP goes into the LWKT scheduler's idle loop.
2426 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2430 u_long icr_lo, icr_hi;
2432 POSTCODE(START_AP_POST);
2434 /* get the PHYSICAL APIC ID# */
2435 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2437 /* calculate the vector */
2438 vector = (boot_addr >> 12) & 0xff;
2440 /* We don't want anything interfering */
2443 /* Make sure the target cpu sees everything */
2447 * Try to detect when a SMI has occurred, wait up to 200ms.
2449 * If a SMI occurs during an AP reset but before we issue
2450 * the STARTUP command, the AP may brick. To work around
2451 * this problem we hold off doing the AP startup until
2452 * after we have detected the SMI. Hopefully another SMI
2453 * will not occur before we finish the AP startup.
2455 * Retries don't seem to help. SMIs have a window of opportunity
2456 * and if USB->legacy keyboard emulation is enabled in the BIOS
2457 * the interrupt rate can be quite high.
2459 * NOTE: Don't worry about the L1 cache load, it might bloat
2460 * ldelta a little but ndelta will be so huge when the SMI
2461 * occurs the detection logic will still work fine.
2464 set_apic_timer(200000);
2469 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2470 * and running the target CPU. OR this INIT IPI might be latched (P5
2471 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2474 * see apic/apicreg.h for icr bit definitions.
2476 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2480 * Setup the address for the target AP. We can setup
2481 * icr_hi once and then just trigger operations with
2484 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2485 icr_hi |= (physical_cpu << 24);
2486 icr_lo = lapic.icr_lo & 0xfff00000;
2487 lapic.icr_hi = icr_hi;
2490 * Do an INIT IPI: assert RESET
2492 * Use edge triggered mode to assert INIT
2494 lapic.icr_lo = icr_lo | 0x0000c500;
2495 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2499 * The spec calls for a 10ms delay but we may have to use a
2500 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2501 * interrupt. We have other loops here too and dividing by 2
2502 * doesn't seem to be enough even after subtracting 350us,
2503 * so we divide by 4.
2505 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2506 * interrupt was detected we use the full 10ms.
2510 else if (smibest < 150 * 4 + 350)
2512 else if ((smibest - 350) / 4 < 10000)
2513 u_sleep((smibest - 350) / 4);
2518 * Do an INIT IPI: deassert RESET
2520 * Use level triggered mode to deassert. It is unclear
2521 * why we need to do this.
2523 lapic.icr_lo = icr_lo | 0x00008500;
2524 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2526 u_sleep(150); /* wait 150us */
2529 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2530 * latched, (P5 bug) this 1st STARTUP would then terminate
2531 * immediately, and the previously started INIT IPI would continue. OR
2532 * the previous INIT IPI has already run. and this STARTUP IPI will
2533 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2536 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2537 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2539 u_sleep(200); /* wait ~200uS */
2542 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2543 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2544 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2545 * recognized after hardware RESET or INIT IPI.
2547 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2548 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2551 /* Resume normal operation */
2554 /* wait for it to start, see ap_init() */
2555 set_apic_timer(5000000);/* == 5 seconds */
2556 while (read_apic_timer()) {
2557 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2558 return 1; /* return SUCCESS */
2561 return 0; /* return FAILURE */
2576 while (read_apic_timer()) {
2578 for (count = 0; count < 100; ++count)
2579 ntsc = rdtsc(); /* force loop to occur */
2581 ndelta = ntsc - ltsc;
2582 if (ldelta > ndelta)
2584 if (ndelta > ldelta * 2)
2587 ldelta = ntsc - ltsc;
2590 return(read_apic_timer());
2594 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2596 * If for some reason we were unable to start all cpus we cannot safely
2597 * use broadcast IPIs.
2603 if (smp_startup_mask == smp_active_mask) {
2604 all_but_self_ipi(XINVLTLB_OFFSET);
2606 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2607 APIC_DELMODE_FIXED);
2613 * When called the executing CPU will send an IPI to all other CPUs
2614 * requesting that they halt execution.
2616 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2618 * - Signals all CPUs in map to stop.
2619 * - Waits for each to stop.
2626 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2627 * from executing at same time.
2630 stop_cpus(u_int map)
2632 map &= smp_active_mask;
2634 /* send the Xcpustop IPI to all CPUs in map */
2635 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2637 while ((stopped_cpus & map) != map)
2645 * Called by a CPU to restart stopped CPUs.
2647 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2649 * - Signals all CPUs in map to restart.
2650 * - Waits for each to restart.
2658 restart_cpus(u_int map)
2660 /* signal other cpus to restart */
2661 started_cpus = map & smp_active_mask;
2663 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2670 * This is called once the mpboot code has gotten us properly relocated
2671 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2672 * and when it returns the scheduler will call the real cpu_idle() main
2673 * loop for the idlethread. Interrupts are disabled on entry and should
2674 * remain disabled at return.
2682 * Adjust smp_startup_mask to signal the BSP that we have started
2683 * up successfully. Note that we do not yet hold the BGL. The BSP
2684 * is waiting for our signal.
2686 * We can't set our bit in smp_active_mask yet because we are holding
2687 * interrupts physically disabled and remote cpus could deadlock
2688 * trying to send us an IPI.
2690 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2694 * Interlock for finalization. Wait until mp_finish is non-zero,
2695 * then get the MP lock.
2697 * Note: We are in a critical section.
2699 * Note: We have to synchronize td_mpcount to our desired MP state
2700 * before calling cpu_try_mplock().
2702 * Note: we are the idle thread, we can only spin.
2704 * Note: The load fence is memory volatile and prevents the compiler
2705 * from improperly caching mp_finish, and the cpu from improperly
2708 while (mp_finish == 0)
2710 ++curthread->td_mpcount;
2711 while (cpu_try_mplock() == 0)
2714 if (cpu_feature & CPUID_TSC) {
2716 * The BSP is constantly updating tsc0_offset, figure out the
2717 * relative difference to synchronize ktrdump.
2719 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2722 /* BSP may have changed PTD while we're waiting for the lock */
2725 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2729 /* Build our map of 'other' CPUs. */
2730 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2732 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2734 /* A quick check from sanity claus */
2735 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2736 if (mycpu->gd_cpuid != apic_id) {
2737 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2738 kprintf("SMP: apic_id = %d\n", apic_id);
2739 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2740 panic("cpuid mismatch! boom!!");
2743 /* Initialize AP's local APIC for irq's */
2744 apic_initialize(FALSE);
2746 /* Set memory range attributes for this CPU to match the BSP */
2747 mem_range_AP_init();
2750 * Once we go active we must process any IPIQ messages that may
2751 * have been queued, because no actual IPI will occur until we
2752 * set our bit in the smp_active_mask. If we don't the IPI
2753 * message interlock could be left set which would also prevent
2756 * The idle loop doesn't expect the BGL to be held and while
2757 * lwkt_switch() normally cleans things up this is a special case
2758 * because we returning almost directly into the idle loop.
2760 * The idle thread is never placed on the runq, make sure
2761 * nothing we've done put it there.
2763 KKASSERT(curthread->td_mpcount == 1);
2764 smp_active_mask |= 1 << mycpu->gd_cpuid;
2767 * Enable interrupts here. idle_restore will also do it, but
2768 * doing it here lets us clean up any strays that got posted to
2769 * the CPU during the AP boot while we are still in a critical
2772 __asm __volatile("sti; pause; pause"::);
2773 mdcpu->gd_fpending = 0;
2775 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2776 lwkt_process_ipiq();
2779 * Releasing the mp lock lets the BSP finish up the SMP init
2782 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2786 * Get SMP fully working before we start initializing devices.
2794 kprintf("Finish MP startup\n");
2795 if (cpu_feature & CPUID_TSC)
2796 tsc0_offset = rdtsc();
2799 while (smp_active_mask != smp_startup_mask) {
2801 if (cpu_feature & CPUID_TSC)
2802 tsc0_offset = rdtsc();
2804 while (try_mplock() == 0)
2807 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2810 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2813 cpu_send_ipiq(int dcpu)
2815 if ((1 << dcpu) & smp_active_mask)
2816 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2819 #if 0 /* single_apic_ipi_passive() not working yet */
2821 * Returns 0 on failure, 1 on success
2824 cpu_send_ipiq_passive(int dcpu)
2827 if ((1 << dcpu) & smp_active_mask) {
2828 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2829 APIC_DELMODE_FIXED);
2835 struct mptable_lapic_cbarg1 {
2838 u_int ht_apicid_mask;
2842 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2844 const struct PROCENTRY *ent;
2845 struct mptable_lapic_cbarg1 *arg = xarg;
2851 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2855 if (ent->apic_id < 32) {
2856 arg->ht_apicid_mask |= 1 << ent->apic_id;
2857 } else if (arg->ht_fixup) {
2858 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2864 struct mptable_lapic_cbarg2 {
2871 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2873 const struct PROCENTRY *ent;
2874 struct mptable_lapic_cbarg2 *arg = xarg;
2880 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2881 KKASSERT(!arg->found_bsp);
2885 if (processor_entry(ent, arg->cpu))
2888 if (arg->logical_cpus) {
2889 struct PROCENTRY proc;
2893 * Create fake mptable processor entries
2894 * and feed them to processor_entry() to
2895 * enumerate the logical CPUs.
2897 bzero(&proc, sizeof(proc));
2899 proc.cpu_flags = PROCENTRY_FLAG_EN;
2900 proc.apic_id = ent->apic_id;
2902 for (i = 1; i < arg->logical_cpus; i++) {
2904 processor_entry(&proc, arg->cpu);
2912 mptable_imcr(struct mptable_pos *mpt)
2914 /* record whether PIC or virtual-wire mode */
2915 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2916 mpt->mp_fps->mpfb2 & 0x80);
2919 struct mptable_lapic_enumerator {
2920 struct lapic_enumerator enumerator;
2921 vm_paddr_t mpfps_paddr;
2925 mptable_lapic_default(void)
2927 int ap_apicid, bsp_apicid;
2929 mp_naps = 1; /* exclude BSP */
2931 /* Map local apic before the id field is accessed */
2932 lapic_map(DEFAULT_APIC_BASE);
2934 bsp_apicid = APIC_ID(lapic.id);
2935 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2938 mp_set_cpuids(0, bsp_apicid);
2939 /* one and only AP */
2940 mp_set_cpuids(1, ap_apicid);
2946 * ID_TO_CPU(N), APIC ID to logical CPU table
2947 * CPU_TO_ID(N), logical CPU to APIC ID table
2950 mptable_lapic_enumerate(struct lapic_enumerator *e)
2952 struct mptable_pos mpt;
2953 struct mptable_lapic_cbarg1 arg1;
2954 struct mptable_lapic_cbarg2 arg2;
2956 int error, logical_cpus = 0;
2957 vm_offset_t lapic_addr;
2958 vm_paddr_t mpfps_paddr;
2960 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
2961 KKASSERT(mpfps_paddr != 0);
2963 error = mptable_map(&mpt, mpfps_paddr);
2965 panic("mptable_lapic_enumerate mptable_map failed\n");
2967 KKASSERT(mpt.mp_fps != NULL);
2970 * Check for use of 'default' configuration
2972 if (mpt.mp_fps->mpfb1 != 0) {
2973 mptable_lapic_default();
2974 mptable_unmap(&mpt);
2979 KKASSERT(cth != NULL);
2981 /* Save local apic address */
2982 lapic_addr = (vm_offset_t)cth->apic_address;
2983 KKASSERT(lapic_addr != 0);
2986 * Find out how many CPUs do we have
2988 bzero(&arg1, sizeof(arg1));
2989 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2991 error = mptable_iterate_entries(cth,
2992 mptable_lapic_pass1_callback, &arg1);
2994 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2995 KKASSERT(arg1.cpu_count != 0);
2997 /* See if we need to fixup HT logical CPUs. */
2998 if (arg1.ht_fixup) {
2999 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3001 if (logical_cpus != 0)
3002 arg1.cpu_count *= logical_cpus;
3004 mp_naps = arg1.cpu_count;
3006 /* Qualify the numbers again, after possible HT fixup */
3007 if (mp_naps > MAXCPU) {
3008 kprintf("Warning: only using %d of %d available CPUs!\n",
3013 --mp_naps; /* subtract the BSP */
3016 * Link logical CPU id to local apic id
3018 bzero(&arg2, sizeof(arg2));
3020 arg2.logical_cpus = logical_cpus;
3022 error = mptable_iterate_entries(cth,
3023 mptable_lapic_pass2_callback, &arg2);
3025 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3026 KKASSERT(arg2.found_bsp);
3028 /* Map local apic */
3029 lapic_map(lapic_addr);
3031 mptable_unmap(&mpt);
3035 mptable_lapic_probe(struct lapic_enumerator *e)
3037 vm_paddr_t mpfps_paddr;
3039 mpfps_paddr = mptable_probe();
3040 if (mpfps_paddr == 0)
3043 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3047 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3049 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3050 .lapic_probe = mptable_lapic_probe,
3051 .lapic_enumerate = mptable_lapic_enumerate
3056 mptable_apic_register(void)
3058 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3060 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);