2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
38 #include <sys/cpu_topology.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/lapic.h>
60 #include <machine_base/apic/ioapic.h>
61 #include <machine_base/acpica/acpi_md_cpu.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
68 #include <machine/clock.h>
70 #include <machine/md_var.h> /* setidt() */
71 #include <machine_base/icu/icu.h> /* IPIs */
72 #include <machine_base/icu/icu_var.h>
73 #include <machine_base/apic/ioapic_abi.h>
74 #include <machine/intr_machdep.h> /* IPIs */
76 #define WARMBOOT_TARGET 0
77 #define WARMBOOT_OFF (KERNBASE + 0x0467)
78 #define WARMBOOT_SEG (KERNBASE + 0x0469)
80 #define CMOS_REG (0x70)
81 #define CMOS_DATA (0x71)
82 #define BIOS_RESET (0x0f)
83 #define BIOS_WARM (0x0a)
86 * this code MUST be enabled here and in mpboot.s.
87 * it follows the very early stages of AP boot by placing values in CMOS ram.
88 * it NORMALLY will never be needed and thus the primitive method for enabling.
91 #if defined(CHECK_POINTS)
92 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
93 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
95 #define CHECK_INIT(D); \
96 CHECK_WRITE(0x34, (D)); \
97 CHECK_WRITE(0x35, (D)); \
98 CHECK_WRITE(0x36, (D)); \
99 CHECK_WRITE(0x37, (D)); \
100 CHECK_WRITE(0x38, (D)); \
101 CHECK_WRITE(0x39, (D));
103 #define CHECK_PRINT(S); \
104 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
113 #else /* CHECK_POINTS */
115 #define CHECK_INIT(D)
116 #define CHECK_PRINT(S)
118 #endif /* CHECK_POINTS */
121 * Values to send to the POST hardware.
123 #define MP_BOOTADDRESS_POST 0x10
124 #define MP_PROBE_POST 0x11
125 #define MPTABLE_PASS1_POST 0x12
127 #define MP_START_POST 0x13
128 #define MP_ENABLE_POST 0x14
129 #define MPTABLE_PASS2_POST 0x15
131 #define START_ALL_APS_POST 0x16
132 #define INSTALL_AP_TRAMP_POST 0x17
133 #define START_AP_POST 0x18
135 #define MP_ANNOUNCE_POST 0x19
137 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
138 int current_postcode;
140 /** XXX FIXME: what system files declare these??? */
141 extern struct region_descriptor r_gdt;
147 extern int64_t tsc_offsets[];
149 /* AP uses this during bootstrap. Do not staticize. */
153 struct pcb stoppcbs[MAXCPU];
155 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
158 * Local data and functions.
161 static u_int boot_address;
162 static int mp_finish;
163 static int mp_finish_lapic;
165 static int start_all_aps(u_int boot_addr);
167 static void install_ap_tramp(u_int boot_addr);
169 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
170 static int smitest(void);
171 static void mp_bsp_simple_setup(void);
173 /* which cpus have been started */
174 static cpumask_t smp_startup_mask = CPUMASK_INITIALIZER_ONLYONE;
175 /* which cpus have lapic been inited */
176 static cpumask_t smp_lapic_mask = CPUMASK_INITIALIZER_ONLYONE;
177 /* which cpus are ready for IPIs etc? */
178 cpumask_t smp_active_mask = CPUMASK_INITIALIZER_ONLYONE;
179 cpumask_t smp_finalize_mask = CPUMASK_INITIALIZER_ONLYONE;
181 SYSCTL_OPAQUE(_machdep, OID_AUTO, smp_active, CTLFLAG_RD,
182 &smp_active_mask, sizeof(smp_active_mask), "LU", "");
183 static u_int bootMP_size;
184 static u_int report_invlpg_src;
185 SYSCTL_INT(_machdep, OID_AUTO, report_invlpg_src, CTLFLAG_RW,
186 &report_invlpg_src, 0, "");
187 static u_int report_invltlb_src;
188 SYSCTL_INT(_machdep, OID_AUTO, report_invltlb_src, CTLFLAG_RW,
189 &report_invltlb_src, 0, "");
190 static int optimized_invltlb;
191 SYSCTL_INT(_machdep, OID_AUTO, optimized_invltlb, CTLFLAG_RW,
192 &optimized_invltlb, 0, "");
193 static int all_but_self_ipi_enable = 1;
194 SYSCTL_INT(_machdep, OID_AUTO, all_but_self_ipi_enable, CTLFLAG_RW,
195 &all_but_self_ipi_enable, 0, "");
197 /* Local data for detecting CPU TOPOLOGY */
198 static int core_bits = 0;
199 static int logical_CPU_bits = 0;
203 * Calculate usable address in base memory for AP trampoline code.
206 mp_bootaddress(u_int basemem)
208 POSTCODE(MP_BOOTADDRESS_POST);
210 bootMP_size = mptramp_end - mptramp_start;
211 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
212 if (((basemem * 1024) - boot_address) < bootMP_size)
213 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
214 /* 3 levels of page table pages */
215 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
217 return mptramp_pagetables;
221 * Print various information about the SMP system hardware and setup.
228 POSTCODE(MP_ANNOUNCE_POST);
230 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
231 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
232 for (x = 1; x <= naps; ++x)
233 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
236 kprintf(" Warning: APIC I/O disabled\n");
240 * AP cpu's call this to sync up protected mode.
242 * WARNING! %gs is not set up on entry. This routine sets up %gs.
248 int x, myid = bootAP;
250 struct mdglobaldata *md;
251 struct privatespace *ps;
253 ps = CPU_prvspace[myid];
255 gdt_segs[GPROC0_SEL].ssd_base =
256 (long) &ps->mdglobaldata.gd_common_tss;
257 ps->mdglobaldata.mi.gd_prvspace = ps;
259 /* We fill the 32-bit segment descriptors */
260 for (x = 0; x < NGDT; x++) {
261 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
262 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
264 /* And now a 64-bit one */
265 ssdtosyssd(&gdt_segs[GPROC0_SEL],
266 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
268 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
269 r_gdt.rd_base = (long) &gdt[myid * NGDT];
270 lgdt(&r_gdt); /* does magic intra-segment return */
272 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
273 wrmsr(MSR_FSBASE, 0); /* User value */
274 wrmsr(MSR_GSBASE, (u_int64_t)ps);
275 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
277 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]);
281 mdcpu->gd_currentldt = _default_ldt;
284 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
285 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
287 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
289 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
291 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
293 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
294 md->gd_common_tssd = *md->gd_tss_gdt;
296 /* double fault stack */
297 md->gd_common_tss.tss_ist1 =
298 (long)&md->mi.gd_prvspace->idlestack[
299 sizeof(md->mi.gd_prvspace->idlestack)];
304 * Set to a known state:
305 * Set by mpboot.s: CR0_PG, CR0_PE
306 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
309 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
312 /* Set up the fast syscall stuff */
313 msr = rdmsr(MSR_EFER) | EFER_SCE;
314 wrmsr(MSR_EFER, msr);
315 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
316 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
317 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
318 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
319 wrmsr(MSR_STAR, msr);
320 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
322 pmap_set_opt(); /* PSE/4MB pages, etc */
323 pmap_init_pat(); /* Page Attribute Table */
325 /* set up CPU registers and state */
328 /* set up SSE/NX registers */
331 /* set up FPU state on the AP */
334 /* disable the APIC, just to be SURE */
335 lapic->svr &= ~APIC_SVR_ENABLE;
338 /*******************************************************************
339 * local functions and data
343 * Start the SMP system
346 mp_start_aps(void *dummy __unused)
349 /* start each Application Processor */
350 start_all_aps(boot_address);
352 mp_bsp_simple_setup();
355 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL);
358 * start each AP in our list
361 start_all_aps(u_int boot_addr)
363 vm_offset_t va = boot_address + KERNBASE;
364 u_int64_t *pt4, *pt3, *pt2;
372 u_long mpbioswarmvec;
373 struct mdglobaldata *gd;
374 struct privatespace *ps;
377 POSTCODE(START_ALL_APS_POST);
379 /* install the AP 1st level boot code */
380 pmap_kenter(va, boot_address);
381 cpu_invlpg((void *)va); /* JG XXX */
382 bcopy(mptramp_start, (void *)va, bootMP_size);
384 /* Locate the page tables, they'll be below the trampoline */
385 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
386 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
387 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
389 /* Create the initial 1GB replicated page tables */
390 for (i = 0; i < 512; i++) {
391 /* Each slot of the level 4 pages points to the same level 3 page */
392 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
393 pt4[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
394 kernel_pmap.pmap_bits[PG_RW_IDX] |
395 kernel_pmap.pmap_bits[PG_U_IDX];
397 /* Each slot of the level 3 pages points to the same level 2 page */
398 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
399 pt3[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
400 kernel_pmap.pmap_bits[PG_RW_IDX] |
401 kernel_pmap.pmap_bits[PG_U_IDX];
403 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
404 pt2[i] = i * (2 * 1024 * 1024);
405 pt2[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
406 kernel_pmap.pmap_bits[PG_RW_IDX] |
407 kernel_pmap.pmap_bits[PG_PS_IDX] |
408 kernel_pmap.pmap_bits[PG_U_IDX];
411 /* save the current value of the warm-start vector */
412 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
413 outb(CMOS_REG, BIOS_RESET);
414 mpbiosreason = inb(CMOS_DATA);
416 /* setup a vector to our boot code */
417 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
418 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
419 outb(CMOS_REG, BIOS_RESET);
420 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
423 * If we have a TSC we can figure out the SMI interrupt rate.
424 * The SMI does not necessarily use a constant rate. Spend
425 * up to 250ms trying to figure it out.
428 if (cpu_feature & CPUID_TSC) {
429 set_apic_timer(275000);
430 smilast = read_apic_timer();
431 for (x = 0; x < 20 && read_apic_timer(); ++x) {
432 smicount = smitest();
433 if (smibest == 0 || smilast - smicount < smibest)
434 smibest = smilast - smicount;
437 if (smibest > 250000)
441 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
442 1000000 / smibest, smibest);
445 for (x = 1; x <= naps; ++x) {
446 /* This is a bit verbose, it will go away soon. */
448 pssize = sizeof(struct privatespace);
449 ps = (void *)kmem_alloc3(&kernel_map, pssize, VM_SUBSYS_GD,
451 CPU_prvspace[x] = ps;
453 kprintf("ps %d %p %d\n", x, ps, pssize);
456 gd = &ps->mdglobaldata;
457 gd->mi.gd_prvspace = ps;
459 /* prime data page for it to use */
460 mi_gdinit(&gd->mi, x);
462 ipiq_size = sizeof(struct lwkt_ipiq) * (naps + 1);
463 gd->mi.gd_ipiq = (void *)kmem_alloc3(&kernel_map, ipiq_size,
464 VM_SUBSYS_IPIQ, KM_CPU(x));
465 bzero(gd->mi.gd_ipiq, ipiq_size);
467 gd->gd_acpi_id = CPUID_TO_ACPIID(gd->mi.gd_cpuid);
469 /* initialize arc4random. */
472 /* setup a vector to our boot code */
473 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
474 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
475 outb(CMOS_REG, BIOS_RESET);
476 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
479 * Setup the AP boot stack
481 bootSTK = &ps->idlestack[UPAGES * PAGE_SIZE - PAGE_SIZE];
484 /* attempt to start the Application Processor */
485 CHECK_INIT(99); /* setup checkpoints */
486 if (!start_ap(gd, boot_addr, smibest)) {
487 kprintf("\nAP #%d (PHY# %d) failed!\n",
488 x, CPUID_TO_APICID(x));
489 CHECK_PRINT("trace"); /* show checkpoints */
490 /* better panic as the AP may be running loose */
491 kprintf("panic y/n? [y] ");
497 CHECK_PRINT("trace"); /* show checkpoints */
500 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
503 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
504 for (shift = 0; (1 << shift) <= ncpus; ++shift)
507 ncpus2_shift = shift;
509 ncpus2_mask = ncpus2 - 1;
511 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
512 if ((1 << shift) < ncpus)
514 ncpus_fit = 1 << shift;
515 ncpus_fit_mask = ncpus_fit - 1;
517 /* build our map of 'other' CPUs */
518 mycpu->gd_other_cpus = smp_startup_mask;
519 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
521 gd = (struct mdglobaldata *)mycpu;
522 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid);
524 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
525 mycpu->gd_ipiq = (void *)kmem_alloc3(&kernel_map, ipiq_size,
526 VM_SUBSYS_IPIQ, KM_CPU(0));
527 bzero(mycpu->gd_ipiq, ipiq_size);
529 /* initialize arc4random. */
532 /* restore the warmstart vector */
533 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
534 outb(CMOS_REG, BIOS_RESET);
535 outb(CMOS_DATA, mpbiosreason);
538 * NOTE! The idlestack for the BSP was setup by locore. Finish
539 * up, clean out the P==V mapping we did earlier.
544 * Wait all APs to finish initializing LAPIC
547 kprintf("SMP: Waiting APs LAPIC initialization\n");
548 if (cpu_feature & CPUID_TSC)
549 tsc0_offset = rdtsc();
554 while (CPUMASK_CMPMASKNEQ(smp_lapic_mask, smp_startup_mask)) {
557 if (cpu_feature & CPUID_TSC)
558 tsc0_offset = rdtsc();
560 while (try_mplock() == 0) {
565 /* number of APs actually started */
571 * load the 1st level AP boot code into base memory.
574 /* targets for relocation */
575 extern void bigJump(void);
576 extern void bootCodeSeg(void);
577 extern void bootDataSeg(void);
578 extern void MPentry(void);
580 extern u_int mp_gdtbase;
585 install_ap_tramp(u_int boot_addr)
588 int size = *(int *) ((u_long) & bootMP_size);
589 u_char *src = (u_char *) ((u_long) bootMP);
590 u_char *dst = (u_char *) boot_addr + KERNBASE;
591 u_int boot_base = (u_int) bootMP;
596 POSTCODE(INSTALL_AP_TRAMP_POST);
598 for (x = 0; x < size; ++x)
602 * modify addresses in code we just moved to basemem. unfortunately we
603 * need fairly detailed info about mpboot.s for this to work. changes
604 * to mpboot.s might require changes here.
607 /* boot code is located in KERNEL space */
608 dst = (u_char *) boot_addr + KERNBASE;
610 /* modify the lgdt arg */
611 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
612 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
614 /* modify the ljmp target for MPentry() */
615 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
616 *dst32 = ((u_int) MPentry - KERNBASE);
618 /* modify the target for boot code segment */
619 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
620 dst8 = (u_int8_t *) (dst16 + 1);
621 *dst16 = (u_int) boot_addr & 0xffff;
622 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
624 /* modify the target for boot data segment */
625 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
626 dst8 = (u_int8_t *) (dst16 + 1);
627 *dst16 = (u_int) boot_addr & 0xffff;
628 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
634 * This function starts the AP (application processor) identified
635 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
636 * to accomplish this. This is necessary because of the nuances
637 * of the different hardware we might encounter. It ain't pretty,
638 * but it seems to work.
640 * NOTE: eventually an AP gets to ap_init(), which is called just
641 * before the AP goes into the LWKT scheduler's idle loop.
644 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
648 u_long icr_lo, icr_hi;
650 POSTCODE(START_AP_POST);
652 /* get the PHYSICAL APIC ID# */
653 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
655 /* calculate the vector */
656 vector = (boot_addr >> 12) & 0xff;
658 /* We don't want anything interfering */
661 /* Make sure the target cpu sees everything */
665 * Try to detect when a SMI has occurred, wait up to 200ms.
667 * If a SMI occurs during an AP reset but before we issue
668 * the STARTUP command, the AP may brick. To work around
669 * this problem we hold off doing the AP startup until
670 * after we have detected the SMI. Hopefully another SMI
671 * will not occur before we finish the AP startup.
673 * Retries don't seem to help. SMIs have a window of opportunity
674 * and if USB->legacy keyboard emulation is enabled in the BIOS
675 * the interrupt rate can be quite high.
677 * NOTE: Don't worry about the L1 cache load, it might bloat
678 * ldelta a little but ndelta will be so huge when the SMI
679 * occurs the detection logic will still work fine.
682 set_apic_timer(200000);
687 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
688 * and running the target CPU. OR this INIT IPI might be latched (P5
689 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
692 * see apic/apicreg.h for icr bit definitions.
694 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
698 * Setup the address for the target AP. We can setup
699 * icr_hi once and then just trigger operations with
702 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
703 icr_hi |= (physical_cpu << 24);
704 icr_lo = lapic->icr_lo & 0xfff00000;
705 lapic->icr_hi = icr_hi;
708 * Do an INIT IPI: assert RESET
710 * Use edge triggered mode to assert INIT
712 lapic->icr_lo = icr_lo | 0x00004500;
713 while (lapic->icr_lo & APIC_DELSTAT_MASK)
717 * The spec calls for a 10ms delay but we may have to use a
718 * MUCH lower delay to avoid bricking an AP due to a fast SMI
719 * interrupt. We have other loops here too and dividing by 2
720 * doesn't seem to be enough even after subtracting 350us,
723 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
724 * interrupt was detected we use the full 10ms.
728 else if (smibest < 150 * 4 + 350)
730 else if ((smibest - 350) / 4 < 10000)
731 u_sleep((smibest - 350) / 4);
736 * Do an INIT IPI: deassert RESET
738 * Use level triggered mode to deassert. It is unclear
739 * why we need to do this.
741 lapic->icr_lo = icr_lo | 0x00008500;
742 while (lapic->icr_lo & APIC_DELSTAT_MASK)
744 u_sleep(150); /* wait 150us */
747 * Next we do a STARTUP IPI: the previous INIT IPI might still be
748 * latched, (P5 bug) this 1st STARTUP would then terminate
749 * immediately, and the previously started INIT IPI would continue. OR
750 * the previous INIT IPI has already run. and this STARTUP IPI will
751 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
754 lapic->icr_lo = icr_lo | 0x00000600 | vector;
755 while (lapic->icr_lo & APIC_DELSTAT_MASK)
757 u_sleep(200); /* wait ~200uS */
760 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
761 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
762 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
763 * recognized after hardware RESET or INIT IPI.
765 lapic->icr_lo = icr_lo | 0x00000600 | vector;
766 while (lapic->icr_lo & APIC_DELSTAT_MASK)
769 /* Resume normal operation */
772 /* wait for it to start, see ap_init() */
773 set_apic_timer(5000000);/* == 5 seconds */
774 while (read_apic_timer()) {
775 if (CPUMASK_TESTBIT(smp_startup_mask, gd->mi.gd_cpuid))
776 return 1; /* return SUCCESS */
779 return 0; /* return FAILURE */
794 while (read_apic_timer()) {
796 for (count = 0; count < 100; ++count)
797 ntsc = rdtsc(); /* force loop to occur */
799 ndelta = ntsc - ltsc;
802 if (ndelta > ldelta * 2)
805 ldelta = ntsc - ltsc;
808 return(read_apic_timer());
812 * Synchronously flush the TLB on all other CPU's. The current cpu's
813 * TLB is not flushed. If the caller wishes to flush the current cpu's
814 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
816 * This routine may be called concurrently from multiple cpus. When this
817 * happens, smp_invltlb() can wind up sticking around in the confirmation
818 * while() loop at the end as additional cpus are added to the global
819 * cpumask, until they are acknowledged by another IPI.
821 * NOTE: If for some reason we were unable to start all cpus we cannot
822 * safely use broadcast IPIs.
825 cpumask_t smp_smurf_mask;
826 static cpumask_t smp_invltlb_mask;
830 cpumask_t smp_in_mask;
832 cpumask_t smp_invmask;
833 extern cpumask_t smp_idleinvl_mask;
834 extern cpumask_t smp_idleinvl_reqs;
837 * Atomically OR bits in *mask to smp_smurf_mask. Adjust *mask to remove
838 * bits that do not need to be IPId. These bits are still part of the command,
839 * but the target cpus have already been signalled and do not need to be
842 #include <sys/spinlock.h>
843 #include <sys/spinlock2.h>
847 smp_smurf_fetchset(cpumask_t *mask)
855 while (i < CPUMASK_ELEMENTS) {
856 obits = smp_smurf_mask.ary[i];
858 nbits = obits | mask->ary[i];
859 if (atomic_cmpset_long(&smp_smurf_mask.ary[i], obits, nbits)) {
860 omask.ary[i] = obits;
864 CPUMASK_NANDMASK(*mask, omask);
868 * This is a mechanism which guarantees that cpu_invltlb() will be executed
869 * on idle cpus without having to signal or wake them up. The invltlb will be
870 * executed when they wake up, prior to any scheduling or interrupt thread.
872 * (*mask) is modified to remove the cpus we successfully negotiate this
873 * function with. This function may only be used with semi-synchronous
874 * commands (typically invltlb's or semi-synchronous invalidations which
875 * are usually associated only with kernel memory).
878 smp_smurf_idleinvlclr(cpumask_t *mask)
880 if (optimized_invltlb) {
881 ATOMIC_CPUMASK_ORMASK(smp_idleinvl_reqs, *mask);
882 /* cpu_lfence() not needed */
883 CPUMASK_NANDMASK(*mask, smp_idleinvl_mask);
888 * Issue cpu_invltlb() across all cpus except the current cpu.
890 * This function will arrange to avoid idle cpus, but still gurantee that
891 * invltlb is run on them when they wake up prior to any scheduling or
897 struct mdglobaldata *md = mdcpu;
899 unsigned long rflags;
901 uint64_t tsc_base = rdtsc();
905 if (report_invltlb_src > 0) {
906 if (--report_invltlb_src <= 0)
911 * Disallow normal interrupts, set all active cpus except our own
912 * in the global smp_invltlb_mask.
914 ++md->mi.gd_cnt.v_smpinvltlb;
915 crit_enter_gd(&md->mi);
918 * Bits we want to set in smp_invltlb_mask. We do not want to signal
919 * our own cpu. Also try to remove bits associated with idle cpus
920 * that we can flag for auto-invltlb.
922 mask = smp_active_mask;
923 CPUMASK_NANDBIT(mask, md->mi.gd_cpuid);
924 smp_smurf_idleinvlclr(&mask);
926 rflags = read_rflags();
928 ATOMIC_CPUMASK_ORMASK(smp_invltlb_mask, mask);
931 * IPI non-idle cpus represented by mask. The omask calculation
932 * removes cpus from the mask which already have a Xinvltlb IPI
933 * pending (avoid double-queueing the IPI).
935 * We must disable real interrupts when setting the smurf flags or
936 * we might race a XINVLTLB before we manage to send the ipi's for
939 * NOTE: We are not signalling ourselves, mask already does NOT
940 * include our own cpu.
942 smp_smurf_fetchset(&mask);
945 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
946 * the critical section count on the target cpus.
948 CPUMASK_ORMASK(mask, md->mi.gd_cpumask);
949 if (all_but_self_ipi_enable &&
950 (all_but_self_ipi_enable >= 2 ||
951 CPUMASK_CMPMASKEQ(smp_startup_mask, mask))) {
952 all_but_self_ipi(XINVLTLB_OFFSET);
954 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask);
955 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
959 * Wait for acknowledgement by all cpus. smp_inval_intr() will
960 * temporarily enable interrupts to avoid deadlocking the lapic,
961 * and will also handle running cpu_invltlb() and remote invlpg
962 * command son our cpu if some other cpu requests it of us.
964 * WARNING! I originally tried to implement this as a hard loop
965 * checking only smp_invltlb_mask (and issuing a local
966 * cpu_invltlb() if requested), with interrupts enabled
967 * and without calling smp_inval_intr(). This DID NOT WORK.
968 * It resulted in weird races where smurf bits would get
969 * cleared without any action being taken.
972 CPUMASK_ASSZERO(mask);
973 while (CPUMASK_CMPMASKNEQ(smp_invltlb_mask, mask)) {
977 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) {
979 * cpuid - cpu doing the waiting
980 * invltlb_mask - IPI in progress
982 kprintf("smp_invltlb %d: waited too long inv=%08jx "
987 "idle=%08jx/%08jx\n",
989 smp_invltlb_mask.ary[0],
990 smp_smurf_mask.ary[0],
994 smp_idleinvl_mask.ary[0],
995 smp_idleinvl_reqs.ary[0]);
996 mdcpu->gd_xinvaltlb = 0;
997 ATOMIC_CPUMASK_NANDMASK(smp_smurf_mask,
999 smp_invlpg(&smp_active_mask);
1001 if (++repeats > 10) {
1002 kprintf("smp_invltlb: giving up\n");
1003 CPUMASK_ASSZERO(smp_invltlb_mask);
1008 write_rflags(rflags);
1009 crit_exit_gd(&md->mi);
1013 * Called from a critical section with interrupts hard-disabled.
1014 * This function issues an XINVLTLB IPI and then executes any pending
1015 * command on the current cpu before returning.
1018 smp_invlpg(cpumask_t *cmdmask)
1020 struct mdglobaldata *md = mdcpu;
1023 if (report_invlpg_src > 0) {
1024 if (--report_invlpg_src <= 0)
1029 * Disallow normal interrupts, set all active cpus in the pmap,
1030 * plus our own for completion processing (it might or might not
1031 * be part of the set).
1033 mask = smp_active_mask;
1034 CPUMASK_ANDMASK(mask, *cmdmask);
1035 CPUMASK_ORMASK(mask, md->mi.gd_cpumask);
1038 * Avoid double-queuing IPIs, which can deadlock us. We must disable
1039 * real interrupts when setting the smurf flags or we might race a
1040 * XINVLTLB before we manage to send the ipi's for the bits we set.
1042 * NOTE: We might be including our own cpu in the smurf mask.
1044 smp_smurf_fetchset(&mask);
1047 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
1048 * the critical section count on the target cpus.
1050 * We do not include our own cpu when issuing the IPI.
1052 if (all_but_self_ipi_enable &&
1053 (all_but_self_ipi_enable >= 2 ||
1054 CPUMASK_CMPMASKEQ(smp_startup_mask, mask))) {
1055 all_but_self_ipi(XINVLTLB_OFFSET);
1057 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask);
1058 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1062 * This will synchronously wait for our command to complete,
1063 * as well as process commands from other cpus. It also handles
1066 * (interrupts are disabled and we are in a critical section here)
1074 globaldata_t gd = mycpu;
1079 * Ignore all_but_self_ipi_enable here and just use it.
1081 rflags = read_rflags();
1083 all_but_self_ipi(XSNIFF_OFFSET);
1084 gd->gd_sample_pc = smp_sniff;
1085 gd->gd_sample_sp = &dummy;
1086 write_rflags(rflags);
1092 globaldata_t rgd = globaldata_find(dcpu);
1097 * Ignore all_but_self_ipi_enable here and just use it.
1099 rflags = read_rflags();
1101 single_apic_ipi(dcpu, XSNIFF_OFFSET, APIC_DELMODE_FIXED);
1102 rgd->gd_sample_pc = cpu_sniff;
1103 rgd->gd_sample_sp = &dummy;
1104 write_rflags(rflags);
1108 * Called from Xinvltlb assembly with interrupts hard-disabled and in a
1109 * critical section. gd_intr_nesting_level may or may not be bumped
1110 * depending on entry.
1112 * THIS CODE IS INTENDED TO EXPLICITLY IGNORE THE CRITICAL SECTION COUNT.
1113 * THAT IS, THE INTERRUPT IS INTENDED TO FUNCTION EVEN WHEN MAINLINE CODE
1114 * IS IN A CRITICAL SECTION.
1117 smp_inval_intr(void)
1119 struct mdglobaldata *md = mdcpu;
1122 uint64_t tsc_base = rdtsc();
1127 * The idle code is in a critical section, but that doesn't stop
1128 * Xinvltlb from executing, so deal with the race which can occur
1129 * in that situation. Otherwise r-m-w operations by pmap_inval_intr()
1130 * may have problems.
1132 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, md->mi.gd_cpuid)) {
1133 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, md->mi.gd_cpuid);
1140 * This is a real mess. I'd like to just leave interrupts disabled
1141 * but it can cause the lapic to deadlock if too many interrupts queue
1142 * to it, due to the idiotic design of the lapic. So instead we have
1143 * to enter a critical section so normal interrupts are made pending
1144 * and track whether this one was reentered.
1146 if (md->gd_xinvaltlb) { /* reentrant on cpu */
1147 md->gd_xinvaltlb = 2;
1150 md->gd_xinvaltlb = 1;
1153 * Check only those cpus with active Xinvl* commands pending.
1155 * We are going to enable interrupts so make sure we are in a
1156 * critical section. This is necessary to avoid deadlocking
1157 * the lapic and to ensure that we execute our commands prior to
1158 * any nominal interrupt or preemption.
1160 * WARNING! It is very important that we only clear out but in
1161 * smp_smurf_mask once for each interrupt we take. In
1162 * this case, we clear it on initial entry and only loop
1163 * on the reentrancy detect (caused by another interrupt).
1165 cpumask = smp_invmask;
1167 ATOMIC_CPUMASK_ORBIT(smp_in_mask, md->mi.gd_cpuid);
1171 ATOMIC_CPUMASK_NANDBIT(smp_smurf_mask, md->mi.gd_cpuid);
1174 * Specific page request(s), and we can't return until all bits
1181 * Also execute any pending full invalidation request in
1184 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) {
1185 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask,
1192 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) {
1194 * cpuid - cpu doing the waiting
1195 * invmask - IPI in progress
1196 * invltlb_mask - which ones are TLB invalidations?
1198 kprintf("smp_inval_intr %d inv=%08jx tlbm=%08jx "
1203 "idle=%08jx/%08jx\n",
1206 smp_invltlb_mask.ary[0],
1207 smp_smurf_mask.ary[0],
1211 smp_idleinvl_mask.ary[0],
1212 smp_idleinvl_reqs.ary[0]);
1223 * We can only add bits to the cpumask to test during the
1224 * loop because the smp_invmask bit is cleared once the
1225 * originator completes the command (the targets may still
1226 * be cycling their own completions in this loop, afterwords).
1228 * lfence required prior to all tests as this Xinvltlb
1229 * interrupt could race the originator (already be in progress
1230 * wnen the originator decides to issue, due to an issue by
1234 CPUMASK_ORMASK(cpumask, smp_invmask);
1235 /*cpumask = smp_active_mask;*/ /* XXX */
1238 if (pmap_inval_intr(&cpumask, toolong) == 0) {
1240 * Clear our smurf mask to allow new IPIs, but deal
1241 * with potential races.
1247 * Test if someone sent us another invalidation IPI, break
1248 * out so we can take it to avoid deadlocking the lapic
1249 * interrupt queue (? stupid intel, amd).
1251 if (md->gd_xinvaltlb == 2)
1254 if (CPUMASK_TESTBIT(smp_smurf_mask, md->mi.gd_cpuid))
1260 * Full invalidation request
1262 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) {
1263 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask,
1270 * Check to see if another Xinvltlb interrupt occurred and loop up
1274 if (md->gd_xinvaltlb == 2) {
1275 md->gd_xinvaltlb = 1;
1279 ATOMIC_CPUMASK_NANDBIT(smp_in_mask, md->mi.gd_cpuid);
1281 md->gd_xinvaltlb = 0;
1285 cpu_wbinvd_on_all_cpus_callback(void *arg)
1291 * When called the executing CPU will send an IPI to all other CPUs
1292 * requesting that they halt execution.
1294 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1296 * - Signals all CPUs in map to stop.
1297 * - Waits for each to stop.
1304 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1305 * from executing at same time.
1308 stop_cpus(cpumask_t map)
1312 CPUMASK_ANDMASK(map, smp_active_mask);
1314 /* send the Xcpustop IPI to all CPUs in map */
1315 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1318 mask = stopped_cpus;
1319 CPUMASK_ANDMASK(mask, map);
1321 } while (CPUMASK_CMPMASKNEQ(mask, map));
1328 * Called by a CPU to restart stopped CPUs.
1330 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1332 * - Signals all CPUs in map to restart.
1333 * - Waits for each to restart.
1341 restart_cpus(cpumask_t map)
1345 /* signal other cpus to restart */
1347 CPUMASK_ANDMASK(mask, smp_active_mask);
1349 started_cpus = mask;
1352 /* wait for each to clear its bit */
1353 while (CPUMASK_CMPMASKNEQ(stopped_cpus, map))
1360 * This is called once the mpboot code has gotten us properly relocated
1361 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1362 * and when it returns the scheduler will call the real cpu_idle() main
1363 * loop for the idlethread. Interrupts are disabled on entry and should
1364 * remain disabled at return.
1372 * Adjust smp_startup_mask to signal the BSP that we have started
1373 * up successfully. Note that we do not yet hold the BGL. The BSP
1374 * is waiting for our signal.
1376 * We can't set our bit in smp_active_mask yet because we are holding
1377 * interrupts physically disabled and remote cpus could deadlock
1378 * trying to send us an IPI.
1380 ATOMIC_CPUMASK_ORBIT(smp_startup_mask, mycpu->gd_cpuid);
1384 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1385 * non-zero, then get the MP lock.
1387 * Note: We are in a critical section.
1389 * Note: we are the idle thread, we can only spin.
1391 * Note: The load fence is memory volatile and prevents the compiler
1392 * from improperly caching mp_finish_lapic, and the cpu from improperly
1395 while (mp_finish_lapic == 0) {
1400 while (try_mplock() == 0) {
1406 if (cpu_feature & CPUID_TSC) {
1408 * The BSP is constantly updating tsc0_offset, figure out
1409 * the relative difference to synchronize ktrdump.
1411 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1414 /* BSP may have changed PTD while we're waiting for the lock */
1417 /* Build our map of 'other' CPUs. */
1418 mycpu->gd_other_cpus = smp_startup_mask;
1419 ATOMIC_CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
1421 /* A quick check from sanity claus */
1422 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1423 if (mycpu->gd_cpuid != cpu_id) {
1424 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1425 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1426 cpu_id, (lapic->id & 0xff000000) >> 24);
1428 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1430 panic("cpuid mismatch! boom!!");
1433 /* Initialize AP's local APIC for irq's */
1436 /* LAPIC initialization is done */
1437 ATOMIC_CPUMASK_ORBIT(smp_lapic_mask, mycpu->gd_cpuid);
1441 /* Let BSP move onto the next initialization stage */
1446 * Interlock for finalization. Wait until mp_finish is non-zero,
1447 * then get the MP lock.
1449 * Note: We are in a critical section.
1451 * Note: we are the idle thread, we can only spin.
1453 * Note: The load fence is memory volatile and prevents the compiler
1454 * from improperly caching mp_finish, and the cpu from improperly
1457 while (mp_finish == 0) {
1462 /* BSP may have changed PTD while we're waiting for the lock */
1465 /* Set memory range attributes for this CPU to match the BSP */
1466 mem_range_AP_init();
1469 * Once we go active we must process any IPIQ messages that may
1470 * have been queued, because no actual IPI will occur until we
1471 * set our bit in the smp_active_mask. If we don't the IPI
1472 * message interlock could be left set which would also prevent
1475 * The idle loop doesn't expect the BGL to be held and while
1476 * lwkt_switch() normally cleans things up this is a special case
1477 * because we returning almost directly into the idle loop.
1479 * The idle thread is never placed on the runq, make sure
1480 * nothing we've done put it there.
1484 * Hold a critical section and allow real interrupts to occur. Zero
1485 * any spurious interrupts which have accumulated, then set our
1486 * smp_active_mask indicating that we are fully operational.
1489 __asm __volatile("sti; pause; pause"::);
1490 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1491 ATOMIC_CPUMASK_ORBIT(smp_active_mask, mycpu->gd_cpuid);
1494 * Wait until all cpus have set their smp_active_mask and have fully
1495 * operational interrupts before proceeding.
1497 * We need a final cpu_invltlb() because we would not have received
1498 * any until we set our bit in smp_active_mask.
1500 while (mp_finish == 1) {
1507 * Initialize per-cpu clocks and do other per-cpu initialization.
1508 * At this point code is expected to be able to use the full kernel
1511 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1514 * Since we may have cleaned up the interrupt triggers, manually
1515 * process any pending IPIs before exiting our critical section.
1516 * Once the critical section has exited, normal interrupt processing
1519 atomic_swap_int(&mycpu->gd_npoll, 0);
1520 lwkt_process_ipiq();
1524 * Final final, allow the waiting BSP to resume the boot process,
1525 * return 'into' the idle thread bootstrap.
1527 ATOMIC_CPUMASK_ORBIT(smp_finalize_mask, mycpu->gd_cpuid);
1528 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1532 * Get SMP fully working before we start initializing devices.
1539 kprintf("Finish MP startup\n");
1543 * Wait for the active mask to complete, after which all cpus will
1544 * be accepting interrupts.
1547 while (CPUMASK_CMPMASKNEQ(smp_active_mask, smp_startup_mask)) {
1553 * Wait for the finalization mask to complete, after which all cpus
1554 * have completely finished initializing and are entering or are in
1555 * their idle thread.
1557 * BSP should have received all required invltlbs but do another
1562 while (CPUMASK_CMPMASKNEQ(smp_finalize_mask, smp_startup_mask)) {
1567 while (try_mplock() == 0) {
1573 kprintf("Active CPU Mask: %016jx\n",
1574 (uintmax_t)CPUMASK_LOWMASK(smp_active_mask));
1578 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL);
1581 * Interrupts must be hard-disabled by caller
1584 cpu_send_ipiq(int dcpu)
1586 if (CPUMASK_TESTBIT(smp_active_mask, dcpu))
1587 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1590 #if 0 /* single_apic_ipi_passive() not working yet */
1592 * Returns 0 on failure, 1 on success
1595 cpu_send_ipiq_passive(int dcpu)
1598 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) {
1599 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1600 APIC_DELMODE_FIXED);
1607 mp_bsp_simple_setup(void)
1609 struct mdglobaldata *gd;
1612 /* build our map of 'other' CPUs */
1613 mycpu->gd_other_cpus = smp_startup_mask;
1614 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
1616 gd = (struct mdglobaldata *)mycpu;
1617 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid);
1619 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
1620 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size,
1622 bzero(mycpu->gd_ipiq, ipiq_size);
1624 /* initialize arc4random. */
1629 if (cpu_feature & CPUID_TSC)
1630 tsc0_offset = rdtsc();
1635 * CPU TOPOLOGY DETECTION FUNCTIONS
1638 /* Detect intel topology using CPUID
1639 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41
1642 detect_intel_topology(int count_htt_cores)
1646 int core_plus_logical_bits = 0;
1647 int cores_per_package;
1648 int logical_per_package;
1649 int logical_per_core;
1652 if (cpu_high >= 0xb) {
1655 } else if (cpu_high >= 0x4) {
1660 for (shift = 0; (1 << shift) < count_htt_cores; ++shift)
1662 logical_CPU_bits = 1 << shift;
1667 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p);
1669 /* if 0xb not supported - fallback to 0x4 */
1670 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) {
1674 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]);
1676 ecx_index = FUNC_B_THREAD_LEVEL + 1;
1678 cpuid_count(0xb, ecx_index, p);
1680 /* Check for the Core type in the implemented sub leaves. */
1681 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) {
1682 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]);
1688 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE);
1690 core_bits = core_plus_logical_bits - logical_CPU_bits;
1695 cpuid_count(0x4, 0, p);
1696 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1;
1698 logical_per_package = count_htt_cores;
1699 logical_per_core = logical_per_package / cores_per_package;
1701 for (shift = 0; (1 << shift) < logical_per_core; ++shift)
1703 logical_CPU_bits = shift;
1705 for (shift = 0; (1 << shift) < cores_per_package; ++shift)
1712 /* Detect AMD topology using CPUID
1713 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page
1716 detect_amd_topology(int count_htt_cores)
1719 if ((cpu_feature & CPUID_HTT) && (amd_feature2 & AMDID2_CMP)) {
1720 if (cpu_procinfo2 & AMDID_COREID_SIZE) {
1721 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
1722 AMDID_COREID_SIZE_SHIFT;
1724 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
1725 for (shift = 0; (1 << shift) < core_bits; ++shift)
1730 logical_CPU_bits = count_htt_cores >> core_bits;
1731 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift)
1733 logical_CPU_bits = shift;
1735 for (shift = 0; (1 << shift) < count_htt_cores; ++shift)
1738 logical_CPU_bits = 0;
1743 amd_get_compute_unit_id(void *arg)
1747 do_cpuid(0x8000001e, regs);
1748 cpu_node_t * mynode = get_cpu_node_by_cpuid(mycpuid);
1751 * AMD - CPUID Specification September 2010
1752 * page 34 - //ComputeUnitID = ebx[0:7]//
1754 mynode->compute_unit_id = regs[1] & 0xff;
1758 fix_amd_topology(void)
1762 if (cpu_vendor_id != CPU_VENDOR_AMD)
1764 if ((amd_feature2 & AMDID2_TOPOEXT) == 0)
1767 CPUMASK_ASSALLONES(mask);
1768 lwkt_cpusync_simple(mask, amd_get_compute_unit_id, NULL);
1770 kprintf("Compute unit iDS:\n");
1772 for (i = 0; i < ncpus; i++) {
1773 kprintf("%d-%d; \n",
1774 i, get_cpu_node_by_cpuid(i)->compute_unit_id);
1781 * - logical_CPU_bits
1783 * With the values above (for AMD or INTEL) we are able to generally
1784 * detect the CPU topology (number of cores for each level):
1785 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1786 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf
1789 detect_cpu_topology(void)
1791 static int topology_detected = 0;
1794 if (topology_detected)
1796 if ((cpu_feature & CPUID_HTT) == 0) {
1798 logical_CPU_bits = 0;
1801 count = (cpu_procinfo & CPUID_HTT_CORES) >> CPUID_HTT_CORE_SHIFT;
1803 if (cpu_vendor_id == CPU_VENDOR_INTEL)
1804 detect_intel_topology(count);
1805 else if (cpu_vendor_id == CPU_VENDOR_AMD)
1806 detect_amd_topology(count);
1807 topology_detected = 1;
1811 kprintf("Bits within APICID: logical_CPU_bits: %d; "
1813 logical_CPU_bits, core_bits);
1818 * Interface functions to calculate chip_ID,
1819 * core_number and logical_number
1820 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1823 get_chip_ID(int cpuid)
1825 return get_apicid_from_cpuid(cpuid) >>
1826 (logical_CPU_bits + core_bits);
1830 get_chip_ID_from_APICID(int apicid)
1832 return apicid >> (logical_CPU_bits + core_bits);
1836 get_core_number_within_chip(int cpuid)
1838 return ((get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) &
1839 ((1 << core_bits) - 1));
1843 get_logical_CPU_number_within_core(int cpuid)
1845 return (get_apicid_from_cpuid(cpuid) &
1846 ((1 << logical_CPU_bits) - 1));