2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.27 2005/08/29 10:19:52 sephe Exp $
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
50 #include <sys/thread2.h>
53 #include <net/ifq_var.h>
54 #include <net/if_arp.h>
55 #include <net/ethernet.h>
56 #include <net/if_dl.h>
57 #include <net/if_media.h>
61 #include <net/vlan/if_vlan_var.h>
63 #include <vm/vm.h> /* for vtophys */
64 #include <vm/pmap.h> /* for vtophys */
65 #include <machine/bus_memio.h>
66 #include <machine/bus_pio.h>
67 #include <machine/bus.h>
68 #include <machine/resource.h>
72 #include <bus/pci/pcireg.h>
73 #include <bus/pci/pcivar.h>
75 #include "../mii_layer/mii.h"
76 #include "../mii_layer/miivar.h"
77 #include "../mii_layer/miidevs.h"
78 #include "../mii_layer/lxtphyreg.h"
80 #include "miibus_if.h"
85 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
86 static void epic_intr(void *);
87 static void epic_tx_underrun(epic_softc_t *);
88 static int epic_common_attach(epic_softc_t *);
89 static void epic_ifstart(struct ifnet *);
90 static void epic_ifwatchdog(struct ifnet *);
91 static void epic_stats_update(void *);
92 static int epic_init(epic_softc_t *);
93 static void epic_stop(epic_softc_t *);
94 static void epic_rx_done(epic_softc_t *);
95 static void epic_tx_done(epic_softc_t *);
96 static int epic_init_rings(epic_softc_t *);
97 static void epic_free_rings(epic_softc_t *);
98 static void epic_stop_activity(epic_softc_t *);
99 static int epic_queue_last_packet(epic_softc_t *);
100 static void epic_start_activity(epic_softc_t *);
101 static void epic_set_rx_mode(epic_softc_t *);
102 static void epic_set_tx_mode(epic_softc_t *);
103 static void epic_set_mc_table(epic_softc_t *);
104 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
105 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
106 static u_int16_t epic_input_eepromw(epic_softc_t *);
107 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
108 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
109 static u_int8_t epic_read_eepromreg(epic_softc_t *);
111 static int epic_read_phy_reg(epic_softc_t *, int, int);
112 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
114 static int epic_miibus_readreg(device_t, int, int);
115 static int epic_miibus_writereg(device_t, int, int, int);
116 static void epic_miibus_statchg(device_t);
117 static void epic_miibus_mediainit(device_t);
119 static int epic_ifmedia_upd(struct ifnet *);
120 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
122 static int epic_probe(device_t);
123 static int epic_attach(device_t);
124 static void epic_shutdown(device_t);
125 static int epic_detach(device_t);
126 static struct epic_type *epic_devtype(device_t);
128 static device_method_t epic_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, epic_probe),
131 DEVMETHOD(device_attach, epic_attach),
132 DEVMETHOD(device_detach, epic_detach),
133 DEVMETHOD(device_shutdown, epic_shutdown),
136 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
137 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
138 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
139 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
144 static driver_t epic_driver = {
150 static devclass_t epic_devclass;
152 DECLARE_DUMMY_MODULE(if_tx);
153 MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
154 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
155 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
157 static struct epic_type epic_devs[] = {
158 { SMC_VENDORID, SMC_DEVICEID_83C170,
159 "SMC EtherPower II 10/100" },
169 t = epic_devtype(dev);
172 device_set_desc(dev, t->name);
179 static struct epic_type *
187 while(t->name != NULL) {
188 if ((pci_get_vendor(dev) == t->ven_id) &&
189 (pci_get_device(dev) == t->dev_id)) {
197 #if defined(EPIC_USEIOSPACE)
198 #define EPIC_RES SYS_RES_IOPORT
199 #define EPIC_RID PCIR_BASEIO
201 #define EPIC_RES SYS_RES_MEMORY
202 #define EPIC_RID PCIR_BASEMEM
206 * Attach routine: map registers, allocate softc, rings and descriptors.
207 * Reset to known state.
218 sc = device_get_softc(dev);
220 /* Preinitialize softc structure */
222 callout_init(&sc->tx_stat_timer);
224 /* Fill ifnet structure */
226 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
228 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
229 ifp->if_ioctl = epic_ifioctl;
230 ifp->if_start = epic_ifstart;
231 ifp->if_watchdog = epic_ifwatchdog;
232 ifp->if_init = (if_init_f_t*)epic_init;
234 ifp->if_baudrate = 10000000;
235 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
236 ifq_set_ready(&ifp->if_snd);
238 pci_enable_busmaster(dev);
241 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
243 if (sc->res == NULL) {
244 device_printf(dev, "couldn't map ports/memory\n");
249 sc->sc_st = rman_get_bustag(sc->res);
250 sc->sc_sh = rman_get_bushandle(sc->res);
252 /* Allocate interrupt */
254 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
255 RF_SHAREABLE | RF_ACTIVE);
257 if (sc->irq == NULL) {
258 device_printf(dev, "couldn't map interrupt\n");
263 /* Do OS independent part, including chip wakeup and reset */
264 error = epic_common_attach(sc);
270 /* Do ifmedia setup */
271 if (mii_phy_probe(dev, &sc->miibus,
272 epic_ifmedia_upd, epic_ifmedia_sts)) {
273 device_printf(dev, "ERROR! MII without any PHY!?\n");
278 /* board type and ... */
280 for(i=0x2c;i<0x32;i++) {
281 tmp = epic_read_eeprom(sc, i);
282 if (' ' == (u_int8_t)tmp) break;
283 printf("%c", (u_int8_t)tmp);
285 if (' ' == (u_int8_t)tmp) break;
286 printf("%c", (u_int8_t)tmp);
290 /* Attach to OS's managers */
291 ether_ifattach(ifp, sc->sc_macaddr);
292 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
294 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
295 epic_intr, sc, &sc->sc_ih, NULL);
298 device_printf(dev, "couldn't set up irq\n");
311 * Detach driver and free resources
320 sc = device_get_softc(dev);
321 ifp = &sc->arpcom.ac_if;
325 if (device_is_attached(dev)) {
331 device_delete_child(dev, sc->miibus);
332 bus_generic_detach(dev);
335 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
340 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
342 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
345 free(sc->tx_flist, M_DEVBUF);
347 free(sc->tx_desc, M_DEVBUF);
349 free(sc->rx_desc, M_DEVBUF);
358 * Stop all chip I/O so that the kernel's probe routines don't
359 * get confused by errant DMAs when rebooting.
367 sc = device_get_softc(dev);
375 * This is if_ioctl handler.
378 epic_ifioctl(ifp, command, data, cr)
384 epic_softc_t *sc = ifp->if_softc;
385 struct mii_data *mii;
386 struct ifreq *ifr = (struct ifreq *) data;
393 if (ifp->if_mtu == ifr->ifr_mtu)
396 /* XXX Though the datasheet doesn't imply any
397 * limitations on RX and TX sizes beside max 64Kb
398 * DMA transfer, seems we can't send more then 1600
399 * data bytes per ethernet packet. (Transmitter hangs
400 * up if more data is sent)
402 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
403 ifp->if_mtu = ifr->ifr_mtu;
412 * If the interface is marked up and stopped, then start it.
413 * If it is marked down and running, then stop it.
415 if (ifp->if_flags & IFF_UP) {
416 if ((ifp->if_flags & IFF_RUNNING) == 0) {
421 if (ifp->if_flags & IFF_RUNNING) {
427 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
428 epic_stop_activity(sc);
429 epic_set_mc_table(sc);
430 epic_set_rx_mode(sc);
431 epic_start_activity(sc);
436 epic_set_mc_table(sc);
442 mii = device_get_softc(sc->miibus);
443 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
447 error = ether_ioctl(ifp, command, data);
456 * OS-independed part of attach process. allocate memory for descriptors
457 * and frag lists, wake up chip, read MAC address and PHY identyfier.
458 * Return -1 on failure.
461 epic_common_attach(sc)
466 sc->tx_flist = malloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
467 M_DEVBUF, M_WAITOK | M_ZERO);
468 sc->tx_desc = malloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
469 M_DEVBUF, M_WAITOK | M_ZERO);
470 sc->rx_desc = malloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
471 M_DEVBUF, M_WAITOK | M_ZERO);
473 /* Bring the chip out of low-power mode. */
474 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
477 /* Workaround for Application Note 7-15 */
478 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
480 /* Read mac address from EEPROM */
481 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
482 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
484 /* Set Non-Volatile Control Register from EEPROM */
485 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
488 sc->tx_threshold = TRANSMIT_THRESHOLD;
489 sc->txcon = TXCON_DEFAULT;
490 sc->miicfg = MIICFG_SMI_ENABLE;
491 sc->phyid = EPIC_UNKN_PHY;
495 sc->cardvend = pci_get_subvendor(sc->dev);
496 sc->cardid = pci_get_subdevice(sc->dev);
498 if (sc->cardvend != SMC_VENDORID)
499 device_printf(sc->dev, "unknown card vendor %04xh\n", sc->cardvend);
505 * This is if_start handler. It takes mbufs from if_snd queue
506 * and queue them for transmit, one by one, until TX ring become full
507 * or queue become empty.
513 epic_softc_t *sc = ifp->if_softc;
514 struct epic_tx_buffer *buf;
515 struct epic_tx_desc *desc;
516 struct epic_frag_list *flist;
521 while (sc->pending_txs < TX_RING_SIZE) {
522 buf = sc->tx_buffer + sc->cur_tx;
523 desc = sc->tx_desc + sc->cur_tx;
524 flist = sc->tx_flist + sc->cur_tx;
526 /* Get next packet to send */
527 m0 = ifq_dequeue(&ifp->if_snd);
529 /* If nothing to send, return */
533 /* Fill fragments list */
535 (NULL != m) && (i < EPIC_MAX_FRAGS);
536 m = m->m_next, i++) {
537 flist->frag[i].fraglen = m->m_len;
538 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
542 /* If packet was more than EPIC_MAX_FRAGS parts, */
543 /* recopy packet to new allocated mbuf cluster */
552 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
553 flist->frag[0].fraglen =
554 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
555 m->m_pkthdr.rcvif = ifp;
558 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
565 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
566 desc->control = 0x01;
568 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
569 desc->status = 0x8000;
570 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
572 /* Set watchdog timer */
578 ifp->if_flags |= IFF_OACTIVE;
585 * Synopsis: Finish all received frames.
592 struct ifnet *ifp = &sc->sc_if;
593 struct epic_rx_buffer *buf;
594 struct epic_rx_desc *desc;
597 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
598 buf = sc->rx_buffer + sc->cur_rx;
599 desc = sc->rx_desc + sc->cur_rx;
601 /* Switch to next descriptor */
602 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
605 * Check for RX errors. This should only happen if
606 * SAVE_ERRORED_PACKETS is set. RX errors generate
607 * RXE interrupt usually.
609 if ((desc->status & 1) == 0) {
610 sc->sc_if.if_ierrors++;
611 desc->status = 0x8000;
615 /* Save packet length and mbuf contained packet */
616 len = desc->rxlength - ETHER_CRC_LEN;
619 /* Try to get mbuf cluster */
620 EPIC_MGETCLUSTER(buf->mbuf);
621 if (NULL == buf->mbuf) {
623 desc->status = 0x8000;
628 /* Point to new mbuf, and give descriptor to chip */
629 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
630 desc->status = 0x8000;
632 /* First mbuf in packet holds the ethernet and packet headers */
633 m->m_pkthdr.rcvif = ifp;
634 m->m_pkthdr.len = m->m_len = len;
636 /* Give mbuf to OS */
637 (*ifp->if_input)(ifp, m);
639 /* Successfuly received frame */
647 * Synopsis: Do last phase of transmission. I.e. if desc is
648 * transmitted, decrease pending_txs counter, free mbuf contained
649 * packet, switch to next descriptor and repeat until no packets
650 * are pending or descriptor is not transmitted yet.
656 struct epic_tx_buffer *buf;
657 struct epic_tx_desc *desc;
660 while (sc->pending_txs > 0) {
661 buf = sc->tx_buffer + sc->dirty_tx;
662 desc = sc->tx_desc + sc->dirty_tx;
663 status = desc->status;
665 /* If packet is not transmitted, thou followed */
666 /* packets are not transmitted too */
667 if (status & 0x8000) break;
669 /* Packet is transmitted. Switch to next and */
672 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
676 /* Check for errors and collisions */
677 if (status & 0x0001) sc->sc_if.if_opackets++;
678 else sc->sc_if.if_oerrors++;
679 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
680 #if defined(EPIC_DIAG)
681 if ((status & 0x1001) == 0x1001) {
682 if_printf(&sc->sc_if,
683 "Tx ERROR: excessive coll. number\n");
688 if (sc->pending_txs < TX_RING_SIZE)
689 sc->sc_if.if_flags &= ~IFF_OACTIVE;
699 epic_softc_t * sc = (epic_softc_t *) arg;
702 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
703 CSR_WRITE_4(sc, INTSTAT, status);
705 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
707 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
708 #if defined(EPIC_DIAG)
709 if (status & INTSTAT_OVW)
710 if_printf(&sc->sc_if, "RX buffer overflow\n");
711 if (status & INTSTAT_RQE)
712 if_printf(&sc->sc_if, "RX FIFO overflow\n");
714 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
715 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
716 sc->sc_if.if_ierrors++;
720 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
722 if (!ifq_is_empty(&sc->sc_if.if_snd))
723 epic_ifstart(&sc->sc_if);
726 /* Check for rare errors */
727 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
728 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
729 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
730 INTSTAT_APE|INTSTAT_DPE)) {
731 if_printf(&sc->sc_if, "PCI fatal errors occured: %s%s%s%s\n",
732 (status&INTSTAT_PMA)?"PMA ":"",
733 (status&INTSTAT_PTA)?"PTA ":"",
734 (status&INTSTAT_APE)?"APE ":"",
735 (status&INTSTAT_DPE)?"DPE":""
744 if (status & INTSTAT_RXE) {
745 #if defined(EPIC_DIAG)
746 if_printf(sc->sc_if, "CRC/Alignment error\n");
748 sc->sc_if.if_ierrors++;
751 if (status & INTSTAT_TXU) {
752 epic_tx_underrun(sc);
753 sc->sc_if.if_oerrors++;
758 /* If no packets are pending, then no timeouts */
759 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
765 * Handle the TX underrun error: increase the TX threshold
766 * and restart the transmitter.
772 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
773 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
774 #if defined(EPIC_DIAG)
775 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n");
778 sc->tx_threshold += 0x40;
779 #if defined(EPIC_DIAG)
780 if_printf(&sc->sc_if, "Tx UNDERRUN: "
781 "TX threshold increased to %d\n", sc->tx_threshold);
785 /* We must set TXUGO to reset the stuck transmitter */
786 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
788 /* Update the TX threshold */
789 epic_stop_activity(sc);
790 epic_set_tx_mode(sc);
791 epic_start_activity(sc);
797 * Synopsis: This one is called if packets wasn't transmitted
798 * during timeout. Try to deallocate transmitted packets, and
799 * if success continue to work.
805 epic_softc_t *sc = ifp->if_softc;
809 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs);
811 /* Try to finish queued packets */
814 /* If not successful */
815 if (sc->pending_txs > 0) {
817 ifp->if_oerrors+=sc->pending_txs;
819 /* Reinitialize board */
820 if_printf(ifp, "reinitialization\n");
825 if_printf(ifp, "seems we can continue normaly\n");
828 if (!ifq_is_empty(&ifp->if_snd))
835 * Despite the name of this function, it doesn't update statistics, it only
836 * helps in autonegotiation process.
839 epic_stats_update(void *xsc)
841 epic_softc_t *sc = xsc;
842 struct mii_data * mii;
846 mii = device_get_softc(sc->miibus);
849 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
858 epic_ifmedia_upd(ifp)
862 struct mii_data *mii;
864 struct mii_softc *miisc;
868 mii = device_get_softc(sc->miibus);
869 ifm = &mii->mii_media;
870 media = ifm->ifm_cur->ifm_media;
872 /* Do not do anything if interface is not up */
873 if ((ifp->if_flags & IFF_UP) == 0)
877 * Lookup current selected PHY
879 if (IFM_INST(media) == sc->serinst) {
880 sc->phyid = EPIC_SERIAL;
883 /* If we're not selecting serial interface, select MII mode */
884 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
885 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
887 /* Default to unknown PHY */
888 sc->phyid = EPIC_UNKN_PHY;
890 /* Lookup selected PHY */
891 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
892 miisc = LIST_NEXT(miisc, mii_list)) {
893 if (IFM_INST(media) == miisc->mii_inst) {
899 /* Identify selected PHY */
901 int id1, id2, model, oui;
903 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
904 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
906 oui = MII_OUI(id1, id2);
907 model = MII_MODEL(id2);
909 case MII_OUI_QUALSEMI:
910 if (model == MII_MODEL_QUALSEMI_QS6612)
911 sc->phyid = EPIC_QS6612_PHY;
913 case MII_OUI_xxALTIMA:
914 if (model == MII_MODEL_xxALTIMA_AC101)
915 sc->phyid = EPIC_AC101_PHY;
917 case MII_OUI_xxLEVEL1:
918 if (model == MII_MODEL_xxLEVEL1_LXT970)
919 sc->phyid = EPIC_LXT970_PHY;
926 * Do PHY specific card setup
929 /* Call this, to isolate all not selected PHYs and
934 /* Do our own setup */
936 case EPIC_QS6612_PHY:
939 /* We have to powerup fiber tranceivers */
940 if (IFM_SUBTYPE(media) == IFM_100_FX)
941 sc->miicfg |= MIICFG_694_ENABLE;
943 sc->miicfg &= ~MIICFG_694_ENABLE;
944 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
947 case EPIC_LXT970_PHY:
948 /* We have to powerup fiber tranceivers */
949 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
950 if (IFM_SUBTYPE(media) == IFM_100_FX)
951 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
953 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
954 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
958 /* Select serial PHY, (10base2/BNC usually) */
959 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
960 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
962 /* There is no driver to fill this */
963 mii->mii_media_active = media;
964 mii->mii_media_status = 0;
966 /* We need to call this manualy as i wasn't called
969 epic_miibus_statchg(sc->dev);
973 if_printf(ifp, "ERROR! Unknown PHY selected\n");
981 * Report current media status.
984 epic_ifmedia_sts(ifp, ifmr)
986 struct ifmediareq *ifmr;
989 struct mii_data *mii;
993 mii = device_get_softc(sc->miibus);
994 ifm = &mii->mii_media;
996 /* Nothing should be selected if interface is down */
997 if ((ifp->if_flags & IFF_UP) == 0) {
998 ifmr->ifm_active = IFM_NONE;
999 ifmr->ifm_status = 0;
1004 /* Call underlying pollstat, if not serial PHY */
1005 if (sc->phyid != EPIC_SERIAL)
1008 /* Simply copy media info */
1009 ifmr->ifm_active = mii->mii_media_active;
1010 ifmr->ifm_status = mii->mii_media_status;
1016 * Callback routine, called on media change.
1019 epic_miibus_statchg(dev)
1023 struct mii_data *mii;
1026 sc = device_get_softc(dev);
1027 mii = device_get_softc(sc->miibus);
1028 media = mii->mii_media_active;
1030 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1032 /* If we are in full-duplex mode or loopback operation,
1033 * we need to decouple receiver and transmitter.
1035 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1036 sc->txcon |= TXCON_FULL_DUPLEX;
1038 /* On some cards we need manualy set fullduplex led */
1039 if (sc->cardid == SMC9432FTX ||
1040 sc->cardid == SMC9432FTX_SC) {
1041 if (IFM_OPTIONS(media) & IFM_FDX)
1042 sc->miicfg |= MIICFG_694_ENABLE;
1044 sc->miicfg &= ~MIICFG_694_ENABLE;
1046 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1049 /* Update baudrate */
1050 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1051 IFM_SUBTYPE(media) == IFM_100_FX)
1052 sc->sc_if.if_baudrate = 100000000;
1054 sc->sc_if.if_baudrate = 10000000;
1056 epic_stop_activity(sc);
1057 epic_set_tx_mode(sc);
1058 epic_start_activity(sc);
1064 epic_miibus_mediainit(dev)
1068 struct mii_data *mii;
1069 struct ifmedia *ifm;
1072 sc = device_get_softc(dev);
1073 mii = device_get_softc(sc->miibus);
1074 ifm = &mii->mii_media;
1076 /* Add Serial Media Interface if present, this applies to
1079 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1080 /* Store its instance */
1081 sc->serinst = mii->mii_instance++;
1083 /* Add as 10base2/BNC media */
1084 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1085 ifmedia_add(ifm, media, 0, NULL);
1087 /* Report to user */
1088 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n");
1095 * Reset chip, allocate rings, and update media.
1101 struct ifnet *ifp = &sc->sc_if;
1106 /* If interface is already running, then we need not do anything */
1107 if (ifp->if_flags & IFF_RUNNING) {
1112 /* Soft reset the chip (we have to power up card before) */
1113 CSR_WRITE_4(sc, GENCTL, 0);
1114 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1117 * Reset takes 15 pci ticks which depends on PCI bus speed.
1118 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1123 CSR_WRITE_4(sc, GENCTL, 0);
1125 /* Workaround for Application Note 7-15 */
1126 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1128 /* Initialize rings */
1129 if (epic_init_rings(sc)) {
1130 if_printf(ifp, "failed to init rings\n");
1135 /* Give rings to EPIC */
1136 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1137 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1139 /* Put node address to EPIC */
1140 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1141 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1142 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1144 /* Set tx mode, includeing transmit threshold */
1145 epic_set_tx_mode(sc);
1147 /* Compute and set RXCON. */
1148 epic_set_rx_mode(sc);
1150 /* Set multicast table */
1151 epic_set_mc_table(sc);
1153 /* Enable interrupts by setting the interrupt mask. */
1154 CSR_WRITE_4(sc, INTMASK,
1155 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1156 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1159 /* Acknowledge all pending interrupts */
1160 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1162 /* Enable interrupts, set for PCI read multiple and etc */
1163 CSR_WRITE_4(sc, GENCTL,
1164 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1165 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1167 /* Mark interface running ... */
1168 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1169 else ifp->if_flags &= ~IFF_RUNNING;
1172 ifp->if_flags &= ~IFF_OACTIVE;
1174 /* Start Rx process */
1175 epic_start_activity(sc);
1177 /* Set appropriate media */
1178 epic_ifmedia_upd(ifp);
1180 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
1188 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1192 epic_set_rx_mode(sc)
1195 u_int32_t flags = sc->sc_if.if_flags;
1196 u_int32_t rxcon = RXCON_DEFAULT;
1198 #if defined(EPIC_EARLY_RX)
1199 rxcon |= RXCON_EARLY_RX;
1202 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1204 CSR_WRITE_4(sc, RXCON, rxcon);
1210 * Synopsis: Set transmit control register. Chip must be in idle state to
1214 epic_set_tx_mode(sc)
1217 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1218 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1220 CSR_WRITE_4(sc, TXCON, sc->txcon);
1224 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1225 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1226 * individual frames, multicast filter must be manually programmed)
1228 * Note: EPIC must be in idle state.
1231 epic_set_mc_table(sc)
1234 struct ifnet *ifp = &sc->sc_if;
1235 struct ifmultiaddr *ifma;
1236 u_int16_t filter[4];
1239 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1240 CSR_WRITE_4(sc, MC0, 0xFFFF);
1241 CSR_WRITE_4(sc, MC1, 0xFFFF);
1242 CSR_WRITE_4(sc, MC2, 0xFFFF);
1243 CSR_WRITE_4(sc, MC3, 0xFFFF);
1253 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1254 if (ifma->ifma_addr->sa_family != AF_LINK)
1256 h = (ether_crc32_be(
1257 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1258 ETHER_ADDR_LEN) >> 26) & 0x3f;
1259 filter[h >> 4] |= 1 << (h & 0xF);
1262 CSR_WRITE_4(sc, MC0, filter[0]);
1263 CSR_WRITE_4(sc, MC1, filter[1]);
1264 CSR_WRITE_4(sc, MC2, filter[2]);
1265 CSR_WRITE_4(sc, MC3, filter[3]);
1271 * Synopsis: Start receive process and transmit one, if they need.
1274 epic_start_activity(sc)
1277 /* Start rx process */
1278 CSR_WRITE_4(sc, COMMAND,
1279 COMMAND_RXQUEUED | COMMAND_START_RX |
1280 (sc->pending_txs?COMMAND_TXQUEUED:0));
1284 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1285 * packet needs to be queued to stop Tx DMA.
1288 epic_stop_activity(sc)
1293 /* Stop Tx and Rx DMA */
1294 CSR_WRITE_4(sc, COMMAND,
1295 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1297 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1298 for (i=0; i<0x1000; i++) {
1299 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1300 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1305 /* Catch all finished packets */
1309 status = CSR_READ_4(sc, INTSTAT);
1311 if ((status & INTSTAT_RXIDLE) == 0)
1312 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n");
1314 if ((status & INTSTAT_TXIDLE) == 0)
1315 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n");
1318 * May need to queue one more packet if TQE, this is rare
1319 * but existing case.
1321 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1322 (void) epic_queue_last_packet(sc);
1327 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1328 * a packet from current descriptor will be copied to internal RAM. We
1329 * compose a dummy packet here and queue it for transmission.
1331 * XXX the packet will then be actually sent over network...
1334 epic_queue_last_packet(sc)
1337 struct epic_tx_desc *desc;
1338 struct epic_frag_list *flist;
1339 struct epic_tx_buffer *buf;
1343 if_printf(&sc->sc_if, "queue last packet\n");
1345 desc = sc->tx_desc + sc->cur_tx;
1346 flist = sc->tx_flist + sc->cur_tx;
1347 buf = sc->tx_buffer + sc->cur_tx;
1349 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1352 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
1357 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1358 flist->frag[0].fraglen = m0->m_len;
1359 m0->m_pkthdr.len = m0->m_len;
1360 m0->m_pkthdr.rcvif = &sc->sc_if;
1361 bzero(mtod(m0,caddr_t), m0->m_len);
1363 /* Fill fragments list */
1364 flist->frag[0].fraglen = m0->m_len;
1365 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1366 flist->numfrags = 1;
1368 /* Fill in descriptor */
1371 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1372 desc->control = 0x01;
1373 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1374 desc->status = 0x8000;
1376 /* Launch transmition */
1377 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1379 /* Wait Tx DMA to stop (for how long??? XXX) */
1380 for (i=0; i<1000; i++) {
1381 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1386 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1387 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n");
1395 * Synopsis: Shut down board and deallocates rings.
1404 sc->sc_if.if_timer = 0;
1406 callout_stop(&sc->tx_stat_timer);
1408 /* Disable interrupts */
1409 CSR_WRITE_4(sc, INTMASK, 0);
1410 CSR_WRITE_4(sc, GENCTL, 0);
1412 /* Try to stop Rx and TX processes */
1413 epic_stop_activity(sc);
1416 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1419 /* Make chip go to bed */
1420 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1422 /* Free memory allocated for rings */
1423 epic_free_rings(sc);
1425 /* Mark as stoped */
1426 sc->sc_if.if_flags &= ~IFF_RUNNING;
1433 * Synopsis: This function should free all memory allocated for rings.
1441 for (i=0; i<RX_RING_SIZE; i++) {
1442 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1443 struct epic_rx_desc *desc = sc->rx_desc + i;
1446 desc->buflength = 0;
1449 if (buf->mbuf) m_freem(buf->mbuf);
1453 for (i=0; i<TX_RING_SIZE; i++) {
1454 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1455 struct epic_tx_desc *desc = sc->tx_desc + i;
1458 desc->buflength = 0;
1461 if (buf->mbuf) m_freem(buf->mbuf);
1467 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1468 * Point Tx descs to fragment lists. Check that all descs and fraglists
1469 * are bounded and aligned properly.
1477 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1479 for (i = 0; i < RX_RING_SIZE; i++) {
1480 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1481 struct epic_rx_desc *desc = sc->rx_desc + i;
1483 desc->status = 0; /* Owned by driver */
1484 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1486 if ((desc->next & 3) ||
1487 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1488 epic_free_rings(sc);
1492 EPIC_MGETCLUSTER(buf->mbuf);
1493 if (NULL == buf->mbuf) {
1494 epic_free_rings(sc);
1497 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1499 desc->buflength = MCLBYTES; /* Max RX buffer length */
1500 desc->status = 0x8000; /* Set owner bit to NIC */
1503 for (i = 0; i < TX_RING_SIZE; i++) {
1504 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1505 struct epic_tx_desc *desc = sc->tx_desc + i;
1508 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1510 if ((desc->next & 3) ||
1511 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1512 epic_free_rings(sc);
1517 desc->bufaddr = vtophys(sc->tx_flist + i);
1519 if ((desc->bufaddr & 3) ||
1520 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1521 epic_free_rings(sc);
1530 * EEPROM operation functions
1533 epic_write_eepromreg(sc, val)
1539 CSR_WRITE_1(sc, EECTL, val);
1541 for (i=0; i<0xFF; i++)
1542 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1548 epic_read_eepromreg(sc)
1551 return CSR_READ_1(sc, EECTL);
1555 epic_eeprom_clock(sc, val)
1559 epic_write_eepromreg(sc, val);
1560 epic_write_eepromreg(sc, (val | 0x4));
1561 epic_write_eepromreg(sc, val);
1563 return epic_read_eepromreg(sc);
1567 epic_output_eepromw(sc, val)
1573 for (i = 0xF; i >= 0; i--) {
1575 epic_eeprom_clock(sc, 0x0B);
1577 epic_eeprom_clock(sc, 0x03);
1582 epic_input_eepromw(sc)
1585 u_int16_t retval = 0;
1588 for (i = 0xF; i >= 0; i--) {
1589 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1597 epic_read_eeprom(sc, loc)
1604 epic_write_eepromreg(sc, 3);
1606 if (epic_read_eepromreg(sc) & 0x40)
1607 read_cmd = (loc & 0x3F) | 0x180;
1609 read_cmd = (loc & 0xFF) | 0x600;
1611 epic_output_eepromw(sc, read_cmd);
1613 dataval = epic_input_eepromw(sc);
1615 epic_write_eepromreg(sc, 1);
1621 * Here goes MII read/write routines
1624 epic_read_phy_reg(sc, phy, reg)
1630 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1632 for (i = 0; i < 0x100; i++) {
1633 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1637 return (CSR_READ_4(sc, MIIDATA));
1641 epic_write_phy_reg(sc, phy, reg, val)
1647 CSR_WRITE_4(sc, MIIDATA, val);
1648 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1650 for(i=0;i<0x100;i++) {
1651 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1659 epic_miibus_readreg(dev, phy, reg)
1665 sc = device_get_softc(dev);
1667 return (PHY_READ_2(sc, phy, reg));
1671 epic_miibus_writereg(dev, phy, reg, data)
1677 sc = device_get_softc(dev);
1679 PHY_WRITE_2(sc, phy, reg, data);