2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
41 * BCM570x memory map. The internal memory layout varies somewhat
42 * depending on whether or not we have external SSRAM attached.
43 * The BCM5700 can have up to 16MB of external memory. The BCM5701
44 * is apparently not designed to use external SSRAM. The mappings
45 * up to the first 4 send rings are the same for both internal and
46 * external memory configurations. Note that mini RX ring space is
47 * only available with external SSRAM configurations, which means
48 * the mini RX ring is not supported on the BCM5701.
50 * The NIC's memory can be accessed by the host in one of 3 ways:
52 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
53 * registers in PCI config space can be used to read any 32-bit
54 * address within the NIC's memory.
56 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
57 * space can be used in conjunction with the memory window in the
58 * device register space at offset 0x8000 to read any 32K chunk
61 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
62 * set, the device I/O mapping consumes 32MB of host address space,
63 * allowing all of the registers and internal NIC memory to be
64 * accessed directly. NIC memory addresses are offset by 0x01000000.
65 * Flat mode consumes so much host address space that it is not
68 #define BGE_PAGE_ZERO 0x00000000
69 #define BGE_PAGE_ZERO_END 0x000000FF
70 #define BGE_SEND_RING_RCB 0x00000100
71 #define BGE_SEND_RING_RCB_END 0x000001FF
72 #define BGE_RX_RETURN_RING_RCB 0x00000200
73 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
74 #define BGE_STATS_BLOCK 0x00000300
75 #define BGE_STATS_BLOCK_END 0x00000AFF
76 #define BGE_STATUS_BLOCK 0x00000B00
77 #define BGE_STATUS_BLOCK_END 0x00000B4F
78 #define BGE_SOFTWARE_GENCOMM 0x00000B50
79 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
80 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
81 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
82 #define BGE_UNMAPPED 0x00001000
83 #define BGE_UNMAPPED_END 0x00001FFF
84 #define BGE_DMA_DESCRIPTORS 0x00002000
85 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF
86 #define BGE_SEND_RING_5717 0x00004000
87 #define BGE_SEND_RING_1_TO_4 0x00004000
88 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF
90 /* Mappings for internal memory configuration */
91 #define BGE_STD_RX_RINGS 0x00006000
92 #define BGE_STD_RX_RINGS_END 0x00006FFF
93 #define BGE_JUMBO_RX_RINGS 0x00007000
94 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF
95 #define BGE_BUFFPOOL_1 0x00008000
96 #define BGE_BUFFPOOL_1_END 0x0000FFFF
97 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
98 #define BGE_BUFFPOOL_2_END 0x00017FFF
99 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
100 #define BGE_BUFFPOOL_3_END 0x0001FFFF
101 #define BGE_STD_RX_RINGS_5717 0x00040000
102 #define BGE_JUMBO_RX_RINGS_5717 0x00044400
104 /* Mappings for external SSRAM configurations */
105 #define BGE_SEND_RING_5_TO_6 0x00006000
106 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF
107 #define BGE_SEND_RING_7_TO_8 0x00007000
108 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF
109 #define BGE_SEND_RING_9_TO_16 0x00008000
110 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
111 #define BGE_EXT_STD_RX_RINGS 0x0000C000
112 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
113 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
114 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
115 #define BGE_MINI_RX_RINGS 0x0000E000
116 #define BGE_MINI_RX_RINGS_END 0x0000FFFF
117 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
118 #define BGE_AVAIL_REGION1_END 0x00017FFF
119 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
120 #define BGE_AVAIL_REGION2_END 0x0001FFFF
121 #define BGE_EXT_SSRAM 0x00020000
122 #define BGE_EXT_SSRAM_END 0x000FFFFF
126 * BCM570x register offsets. These are memory mapped registers
127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
128 * Each register must be accessed using 32 bit operations.
130 * All registers are accessed through a 32K shared memory block.
131 * The first group of registers are actually copies of the PCI
132 * configuration space registers.
136 * PCI registers defined in the PCI 2.2 spec.
138 #define BGE_PCI_VID 0x00
139 #define BGE_PCI_DID 0x02
140 #define BGE_PCI_CMD 0x04
141 #define BGE_PCI_STS 0x06
142 #define BGE_PCI_REV 0x08
143 #define BGE_PCI_CLASS 0x09
144 #define BGE_PCI_CACHESZ 0x0C
145 #define BGE_PCI_LATTIMER 0x0D
146 #define BGE_PCI_HDRTYPE 0x0E
147 #define BGE_PCI_BIST 0x0F
148 #define BGE_PCI_BAR0 0x10
149 #define BGE_PCI_BAR1 0x14
150 #define BGE_PCI_SUBSYS 0x2C
151 #define BGE_PCI_SUBVID 0x2E
152 #define BGE_PCI_ROMBASE 0x30
153 #define BGE_PCI_CAPPTR 0x34
154 #define BGE_PCI_INTLINE 0x3C
155 #define BGE_PCI_INTPIN 0x3D
156 #define BGE_PCI_MINGNT 0x3E
157 #define BGE_PCI_MAXLAT 0x3F
158 #define BGE_PCI_PCIXCAP 0x40
159 #define BGE_PCI_NEXTPTR_PM 0x41
160 #define BGE_PCI_PCIX_CMD 0x42
161 #define BGE_PCI_PCIX_STS 0x44
162 #define BGE_PCI_PWRMGMT_CAPID 0x48
163 #define BGE_PCI_NEXTPTR_VPD 0x49
164 #define BGE_PCI_PWRMGMT_CAPS 0x4A
165 #define BGE_PCI_PWRMGMT_CMD 0x4C
166 #define BGE_PCI_PWRMGMT_STS 0x4D
167 #define BGE_PCI_PWRMGMT_DATA 0x4F
168 #define BGE_PCI_VPD_CAPID 0x50
169 #define BGE_PCI_NEXTPTR_MSI 0x51
170 #define BGE_PCI_VPD_ADDR 0x52
171 #define BGE_PCI_VPD_DATA 0x54
172 #define BGE_PCI_MSI_CAPID 0x58
173 #define BGE_PCI_NEXTPTR_NONE 0x59
174 #define BGE_PCI_MSI_CTL 0x5A
175 #define BGE_PCI_MSI_ADDR_HI 0x5C
176 #define BGE_PCI_MSI_ADDR_LO 0x60
177 #define BGE_PCI_MSI_DATA 0x64
180 #define BGE_PCIE_CAPID_REG 0xD0
181 #define BGE_PCIE_CAPID 0x10
184 * PCI registers specific to the BCM570x family.
186 #define BGE_PCI_MISC_CTL 0x68
187 #define BGE_PCI_DMA_RW_CTL 0x6C
188 #define BGE_PCI_PCISTATE 0x70
189 #define BGE_PCI_CLKCTL 0x74
190 #define BGE_PCI_REG_BASEADDR 0x78
191 #define BGE_PCI_MEMWIN_BASEADDR 0x7C
192 #define BGE_PCI_REG_DATA 0x80
193 #define BGE_PCI_MEMWIN_DATA 0x84
194 #define BGE_PCI_MODECTL 0x88
195 #define BGE_PCI_MISC_CFG 0x8C
196 #define BGE_PCI_MISC_LOCALCTL 0x90
197 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
198 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
199 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
200 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
201 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
202 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
203 #define BGE_PCI_ISR_MBX_HI 0xB0
204 #define BGE_PCI_ISR_MBX_LO 0xB4
205 #define BGE_PCI_PRODID_ASICREV 0xBC
206 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4
207 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC
209 /* PCI Misc. Host control register */
210 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
211 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
212 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
213 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
214 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
215 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
216 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
217 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
218 #define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200
219 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
220 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16
222 #if BYTE_ORDER == LITTLE_ENDIAN
223 #define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\
224 BGE_MODECTL_BYTESWAP_DATA | \
225 BGE_MODECTL_WORDSWAP_DATA)
227 #define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\
228 BGE_MODECTL_BYTESWAP_NONFRAME |\
229 BGE_MODECTL_BYTESWAP_DATA |
230 BGE_MODECTL_WORDSWAP_DATA)
233 #define BGE_HIF_SWAP_OPTIONS BGE_PCIMISCCTL_ENDIAN_WORDSWAP
234 #define BGE_INIT (BGE_HIF_SWAP_OPTIONS | \
235 BGE_PCIMISCCTL_CLEAR_INTA | \
236 BGE_PCIMISCCTL_MASK_PCI_INTR | \
237 BGE_PCIMISCCTL_INDIRECT_ACCESS)
239 #define BGE_PCISTAT_INTR_NOTACT 0x2
241 #define BGE_CHIPID_TIGON_I 0x4000
242 #define BGE_CHIPID_TIGON_II 0x6000
243 #define BGE_CHIPID_BCM5700_A0 0x7000
244 #define BGE_CHIPID_BCM5700_A1 0x7001
245 #define BGE_CHIPID_BCM5700_B0 0x7100
246 #define BGE_CHIPID_BCM5700_B1 0x7101
247 #define BGE_CHIPID_BCM5700_B2 0x7102
248 #define BGE_CHIPID_BCM5700_B3 0x7103
249 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104
250 #define BGE_CHIPID_BCM5700_C0 0x7200
251 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
252 #define BGE_CHIPID_BCM5701_B0 0x0100
253 #define BGE_CHIPID_BCM5701_B2 0x0102
254 #define BGE_CHIPID_BCM5701_B5 0x0105
255 #define BGE_CHIPID_BCM5703_A0 0x1000
256 #define BGE_CHIPID_BCM5703_A1 0x1001
257 #define BGE_CHIPID_BCM5703_A2 0x1002
258 #define BGE_CHIPID_BCM5703_A3 0x1003
259 #define BGE_CHIPID_BCM5703_B0 0x1100
260 #define BGE_CHIPID_BCM5704_A0 0x2000
261 #define BGE_CHIPID_BCM5704_A1 0x2001
262 #define BGE_CHIPID_BCM5704_A2 0x2002
263 #define BGE_CHIPID_BCM5704_A3 0x2003
264 #define BGE_CHIPID_BCM5704_B0 0x2100
265 #define BGE_CHIPID_BCM5705_A0 0x3000
266 #define BGE_CHIPID_BCM5705_A1 0x3001
267 #define BGE_CHIPID_BCM5705_A2 0x3002
268 #define BGE_CHIPID_BCM5705_A3 0x3003
269 #define BGE_CHIPID_BCM5750_A0 0x4000
270 #define BGE_CHIPID_BCM5750_A1 0x4001
271 #define BGE_CHIPID_BCM5750_A3 0x4003
272 #define BGE_CHIPID_BCM5750_B0 0x4100
273 #define BGE_CHIPID_BCM5750_B1 0x4101
274 #define BGE_CHIPID_BCM5750_C0 0x4200
275 #define BGE_CHIPID_BCM5750_C1 0x4201
276 #define BGE_CHIPID_BCM5750_C2 0x4202
277 #define BGE_CHIPID_BCM5714_A0 0x5000
278 #define BGE_CHIPID_BCM5752_A0 0x6000
279 #define BGE_CHIPID_BCM5752_A1 0x6001
280 #define BGE_CHIPID_BCM5752_A2 0x6002
281 #define BGE_CHIPID_BCM5714_B0 0x8000
282 #define BGE_CHIPID_BCM5714_B3 0x8003
283 #define BGE_CHIPID_BCM5715_A0 0x9000
284 #define BGE_CHIPID_BCM5715_A1 0x9001
285 #define BGE_CHIPID_BCM5715_A3 0x9003
286 #define BGE_CHIPID_BCM5722_A0 0xa200
287 #define BGE_CHIPID_BCM5755_A0 0xa000
288 #define BGE_CHIPID_BCM5755_A1 0xa001
289 #define BGE_CHIPID_BCM5755_A2 0xa002
290 #define BGE_CHIPID_BCM5754_A0 0xb000
291 #define BGE_CHIPID_BCM5754_A1 0xb001
292 #define BGE_CHIPID_BCM5754_A2 0xb002
293 #define BGE_CHIPID_BCM5761_A0 0x5761000
294 #define BGE_CHIPID_BCM5761_A1 0x5761100
295 #define BGE_CHIPID_BCM5784_A0 0x5784000
296 #define BGE_CHIPID_BCM5784_A1 0x5784100
297 #define BGE_CHIPID_BCM5787_A0 0xb000
298 #define BGE_CHIPID_BCM5787_A1 0xb001
299 #define BGE_CHIPID_BCM5787_A2 0xb002
300 #define BGE_CHIPID_BCM5906_A0 0xc000
301 #define BGE_CHIPID_BCM5906_A1 0xc001
302 #define BGE_CHIPID_BCM5906_A2 0xc002
303 #define BGE_CHIPID_BCM57780_A0 0x57780000
304 #define BGE_CHIPID_BCM57780_A1 0x57780001
305 #define BGE_CHIPID_BCM5717_A0 0x05717000
306 #define BGE_CHIPID_BCM5717_B0 0x05717100
307 #define BGE_CHIPID_BCM5717_C0 0x05717200
308 #define BGE_CHIPID_BCM5719_A0 0x05719000
309 #define BGE_CHIPID_BCM5720_A0 0x05720000
310 #define BGE_CHIPID_BCM5762_A0 0x05762000
311 #define BGE_CHIPID_BCM57765_A0 0x57785000
312 #define BGE_CHIPID_BCM57765_B0 0x57785100
315 #define BGE_ASICREV(x) ((x) >> 12)
316 #define BGE_ASICREV_BCM5701 0x00
317 #define BGE_ASICREV_BCM5703 0x01
318 #define BGE_ASICREV_BCM5704 0x02
319 #define BGE_ASICREV_BCM5705 0x03
320 #define BGE_ASICREV_BCM5750 0x04
321 #define BGE_ASICREV_BCM5714_A0 0x05
322 #define BGE_ASICREV_BCM5752 0x06
323 #define BGE_ASICREV_BCM5700 0x07
324 #define BGE_ASICREV_BCM5780 0x08
325 #define BGE_ASICREV_BCM5714 0x09
326 #define BGE_ASICREV_BCM5755 0x0a
327 #define BGE_ASICREV_BCM5754 0x0b
328 #define BGE_ASICREV_BCM5787 0x0b
329 #define BGE_ASICREV_BCM5906 0x0c
331 /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
332 #define BGE_ASICREV_USE_PRODID_REG 0x0f
333 /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
334 #define BGE_ASICREV_BCM5717 0x5717
335 #define BGE_ASICREV_BCM5719 0x5719
336 #define BGE_ASICREV_BCM5720 0x5720
337 #define BGE_ASICREV_BCM5761 0x5761
338 #define BGE_ASICREV_BCM5762 0x5762
339 #define BGE_ASICREV_BCM5784 0x5784
340 #define BGE_ASICREV_BCM5785 0x5785
341 #define BGE_ASICREV_BCM57765 0x57785
342 #define BGE_ASICREV_BCM57766 0x57766
343 #define BGE_ASICREV_BCM57780 0x57780
346 #define BGE_CHIPREV(x) ((x) >> 8)
347 #define BGE_CHIPREV_5700_AX 0x70
348 #define BGE_CHIPREV_5700_BX 0x71
349 #define BGE_CHIPREV_5700_CX 0x72
350 #define BGE_CHIPREV_5701_AX 0x00
351 #define BGE_CHIPREV_5703_AX 0x10
352 #define BGE_CHIPREV_5704_AX 0x20
353 #define BGE_CHIPREV_5704_BX 0x21
354 #define BGE_CHIPREV_5750_AX 0x40
355 #define BGE_CHIPREV_5750_BX 0x41
356 /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
357 #define BGE_CHIPREV_5717_AX 0x57170
358 #define BGE_CHIPREV_5717_BX 0x57171
359 #define BGE_CHIPREV_5761_AX 0x57611
360 #define BGE_CHIPREV_5784_AX 0x57841
361 #define BGE_CHIPREV_57765_AX 0x577850
363 /* PCI DMA Read/Write Control register */
364 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF
365 #define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001
366 #define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080
367 #define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380
368 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
369 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
370 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
371 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
372 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000
373 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
374 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000
375 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
376 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000
377 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
378 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
379 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
380 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
381 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
383 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
384 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
385 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
386 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
387 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
388 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
389 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
390 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
392 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
393 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
394 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
395 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
396 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
397 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
398 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
399 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
402 * PCI state register -- note, this register is read only
403 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
406 #define BGE_PCISTATE_FORCE_RESET 0x00000001
407 #define BGE_PCISTATE_INTR_STATE 0x00000002
408 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
409 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
410 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
411 #define BGE_PCISTATE_WANT_EXPROM 0x00000020
412 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040
413 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
414 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
417 * PCI Clock Control register -- note, this register is read only
418 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
421 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
422 #define BGE_PCICLOCKCTL_M66EN 0x00000080
423 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
424 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
425 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
426 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000
427 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
428 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
429 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
430 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
434 * High priority mailbox registers
435 * Each mailbox is 64-bits wide, though we only use the
436 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
437 * first. The NIC will load the mailbox after the lower 32 bit word
440 #define BGE_MBX_IRQ0_HI 0x0200
441 #define BGE_MBX_IRQ0_LO 0x0204
442 #define BGE_MBX_IRQ1_HI 0x0208
443 #define BGE_MBX_IRQ1_LO 0x020C
444 #define BGE_MBX_IRQ2_HI 0x0210
445 #define BGE_MBX_IRQ2_LO 0x0214
446 #define BGE_MBX_IRQ3_HI 0x0218
447 #define BGE_MBX_IRQ3_LO 0x021C
448 #define BGE_MBX_GEN0_HI 0x0220
449 #define BGE_MBX_GEN0_LO 0x0224
450 #define BGE_MBX_GEN1_HI 0x0228
451 #define BGE_MBX_GEN1_LO 0x022C
452 #define BGE_MBX_GEN2_HI 0x0230
453 #define BGE_MBX_GEN2_LO 0x0234
454 #define BGE_MBX_GEN3_HI 0x0228
455 #define BGE_MBX_GEN3_LO 0x022C
456 #define BGE_MBX_GEN4_HI 0x0240
457 #define BGE_MBX_GEN4_LO 0x0244
458 #define BGE_MBX_GEN5_HI 0x0248
459 #define BGE_MBX_GEN5_LO 0x024C
460 #define BGE_MBX_GEN6_HI 0x0250
461 #define BGE_MBX_GEN6_LO 0x0254
462 #define BGE_MBX_GEN7_HI 0x0258
463 #define BGE_MBX_GEN7_LO 0x025C
464 #define BGE_MBX_RELOAD_STATS_HI 0x0260
465 #define BGE_MBX_RELOAD_STATS_LO 0x0264
466 #define BGE_MBX_RX_STD_PROD_HI 0x0268
467 #define BGE_MBX_RX_STD_PROD_LO 0x026C
468 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
469 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
470 #define BGE_MBX_RX_MINI_PROD_HI 0x0278
471 #define BGE_MBX_RX_MINI_PROD_LO 0x027C
472 #define BGE_MBX_RX_CONS0_HI 0x0280
473 #define BGE_MBX_RX_CONS0_LO 0x0284
474 #define BGE_MBX_RX_CONS1_HI 0x0288
475 #define BGE_MBX_RX_CONS1_LO 0x028C
476 #define BGE_MBX_RX_CONS2_HI 0x0290
477 #define BGE_MBX_RX_CONS2_LO 0x0294
478 #define BGE_MBX_RX_CONS3_HI 0x0298
479 #define BGE_MBX_RX_CONS3_LO 0x029C
480 #define BGE_MBX_RX_CONS4_HI 0x02A0
481 #define BGE_MBX_RX_CONS4_LO 0x02A4
482 #define BGE_MBX_RX_CONS5_HI 0x02A8
483 #define BGE_MBX_RX_CONS5_LO 0x02AC
484 #define BGE_MBX_RX_CONS6_HI 0x02B0
485 #define BGE_MBX_RX_CONS6_LO 0x02B4
486 #define BGE_MBX_RX_CONS7_HI 0x02B8
487 #define BGE_MBX_RX_CONS7_LO 0x02BC
488 #define BGE_MBX_RX_CONS8_HI 0x02C0
489 #define BGE_MBX_RX_CONS8_LO 0x02C4
490 #define BGE_MBX_RX_CONS9_HI 0x02C8
491 #define BGE_MBX_RX_CONS9_LO 0x02CC
492 #define BGE_MBX_RX_CONS10_HI 0x02D0
493 #define BGE_MBX_RX_CONS10_LO 0x02D4
494 #define BGE_MBX_RX_CONS11_HI 0x02D8
495 #define BGE_MBX_RX_CONS11_LO 0x02DC
496 #define BGE_MBX_RX_CONS12_HI 0x02E0
497 #define BGE_MBX_RX_CONS12_LO 0x02E4
498 #define BGE_MBX_RX_CONS13_HI 0x02E8
499 #define BGE_MBX_RX_CONS13_LO 0x02EC
500 #define BGE_MBX_RX_CONS14_HI 0x02F0
501 #define BGE_MBX_RX_CONS14_LO 0x02F4
502 #define BGE_MBX_RX_CONS15_HI 0x02F8
503 #define BGE_MBX_RX_CONS15_LO 0x02FC
504 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300
505 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304
506 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308
507 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C
508 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310
509 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314
510 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318
511 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C
512 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320
513 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324
514 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328
515 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C
516 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330
517 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334
518 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338
519 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C
520 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340
521 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344
522 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348
523 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C
524 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350
525 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354
526 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358
527 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C
528 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360
529 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364
530 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368
531 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C
532 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370
533 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374
534 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378
535 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C
536 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380
537 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384
538 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388
539 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C
540 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390
541 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394
542 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398
543 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C
544 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
545 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
546 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
547 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
548 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
549 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
550 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
551 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
552 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
553 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
554 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
555 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
556 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
557 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
558 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
559 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
560 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
561 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
562 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
563 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
564 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
565 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
566 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
567 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
569 #define BGE_TX_RINGS_MAX 4
570 #define BGE_TX_RINGS_EXTSSRAM_MAX 16
571 #define BGE_RX_RINGS_MAX 16
572 #define BGE_RX_RINGS_MAX_5717 17
574 /* Ethernet MAC control registers */
575 #define BGE_MAC_MODE 0x0400
576 #define BGE_MAC_STS 0x0404
577 #define BGE_MAC_EVT_ENB 0x0408
578 #define BGE_MAC_LED_CTL 0x040C
579 #define BGE_MAC_ADDR1_LO 0x0410
580 #define BGE_MAC_ADDR1_HI 0x0414
581 #define BGE_MAC_ADDR2_LO 0x0418
582 #define BGE_MAC_ADDR2_HI 0x041C
583 #define BGE_MAC_ADDR3_LO 0x0420
584 #define BGE_MAC_ADDR3_HI 0x0424
585 #define BGE_MAC_ADDR4_LO 0x0428
586 #define BGE_MAC_ADDR4_HI 0x042C
587 #define BGE_WOL_PATPTR 0x0430
588 #define BGE_WOL_PATCFG 0x0434
589 #define BGE_TX_RANDOM_BACKOFF 0x0438
590 #define BGE_RX_MTU 0x043C
591 #define BGE_GBIT_PCS_TEST 0x0440
592 #define BGE_TX_TBI_AUTONEG 0x0444
593 #define BGE_RX_TBI_AUTONEG 0x0448
594 #define BGE_MI_COMM 0x044C
595 #define BGE_MI_STS 0x0450
596 #define BGE_MI_MODE 0x0454
597 #define BGE_AUTOPOLL_STS 0x0458
598 #define BGE_TX_MODE 0x045C
599 #define BGE_TX_STS 0x0460
600 #define BGE_TX_LENGTHS 0x0464
601 #define BGE_RX_MODE 0x0468
602 #define BGE_RX_STS 0x046C
603 #define BGE_MAR0 0x0470
604 #define BGE_MAR1 0x0474
605 #define BGE_MAR2 0x0478
606 #define BGE_MAR3 0x047C
607 #define BGE_RX_BD_RULES_CTL0 0x0480
608 #define BGE_RX_BD_RULES_MASKVAL0 0x0484
609 #define BGE_RX_BD_RULES_CTL1 0x0488
610 #define BGE_RX_BD_RULES_MASKVAL1 0x048C
611 #define BGE_RX_BD_RULES_CTL2 0x0490
612 #define BGE_RX_BD_RULES_MASKVAL2 0x0494
613 #define BGE_RX_BD_RULES_CTL3 0x0498
614 #define BGE_RX_BD_RULES_MASKVAL3 0x049C
615 #define BGE_RX_BD_RULES_CTL4 0x04A0
616 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4
617 #define BGE_RX_BD_RULES_CTL5 0x04A8
618 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC
619 #define BGE_RX_BD_RULES_CTL6 0x04B0
620 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4
621 #define BGE_RX_BD_RULES_CTL7 0x04B8
622 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC
623 #define BGE_RX_BD_RULES_CTL8 0x04C0
624 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4
625 #define BGE_RX_BD_RULES_CTL9 0x04C8
626 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC
627 #define BGE_RX_BD_RULES_CTL10 0x04D0
628 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4
629 #define BGE_RX_BD_RULES_CTL11 0x04D8
630 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC
631 #define BGE_RX_BD_RULES_CTL12 0x04E0
632 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4
633 #define BGE_RX_BD_RULES_CTL13 0x04E8
634 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC
635 #define BGE_RX_BD_RULES_CTL14 0x04F0
636 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4
637 #define BGE_RX_BD_RULES_CTL15 0x04F8
638 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC
639 #define BGE_RX_RULES_CFG 0x0500
640 #define BGE_MAX_RX_FRAME_LOWAT 0x0504
641 #define BGE_SERDES_CFG 0x0590
642 #define BGE_SERDES_STS 0x0594
643 #define BGE_SGDIG_CFG 0x05B0
644 #define BGE_SGDIG_STS 0x05B4
645 #define BGE_RX_STATS 0x0800
646 #define BGE_TX_STATS 0x0880
648 /* Ethernet MAC Mode register */
649 #define BGE_MACMODE_RESET 0x00000001
650 #define BGE_MACMODE_HALF_DUPLEX 0x00000002
651 #define BGE_MACMODE_PORTMODE 0x0000000C
652 #define BGE_MACMODE_LOOPBACK 0x00000010
653 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
654 #define BGE_MACMODE_TX_BURST_ENB 0x00000100
655 #define BGE_MACMODE_MAX_DEFER 0x00000200
656 #define BGE_MACMODE_LINK_POLARITY 0x00000400
657 #define BGE_MACMODE_RX_STATS_ENB 0x00000800
658 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
659 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
660 #define BGE_MACMODE_TX_STATS_ENB 0x00004000
661 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
662 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
663 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
664 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
665 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
666 #define BGE_MACMODE_MIP_ENB 0x00100000
667 #define BGE_MACMODE_TXDMA_ENB 0x00200000
668 #define BGE_MACMODE_RXDMA_ENB 0x00400000
669 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
671 #define BGE_PORTMODE_NONE 0x00000000
672 #define BGE_PORTMODE_MII 0x00000004
673 #define BGE_PORTMODE_GMII 0x00000008
674 #define BGE_PORTMODE_TBI 0x0000000C
676 /* MAC Status register */
677 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
678 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
679 #define BGE_MACSTAT_RX_CFG 0x00000004
680 #define BGE_MACSTAT_CFG_CHANGED 0x00000008
681 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010
682 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
683 #define BGE_MACSTAT_LINK_CHANGED 0x00001000
684 #define BGE_MACSTAT_MI_COMPLETE 0x00400000
685 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000
686 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
687 #define BGE_MACSTAT_ODI_ERROR 0x02000000
688 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
689 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
691 /* MAC Event Enable Register */
692 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
693 #define BGE_EVTENB_LINK_CHANGED 0x00001000
694 #define BGE_EVTENB_MI_COMPLETE 0x00400000
695 #define BGE_EVTENB_MI_INTERRUPT 0x00800000
696 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
697 #define BGE_EVTENB_ODI_ERROR 0x02000000
698 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
699 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
701 /* LED Control Register */
702 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
703 #define BGE_LEDCTL_1000MBPS_LED 0x00000002
704 #define BGE_LEDCTL_100MBPS_LED 0x00000004
705 #define BGE_LEDCTL_10MBPS_LED 0x00000008
706 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
707 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
708 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
709 #define BGE_LEDCTL_1000MBPS_STS 0x00000080
710 #define BGE_LEDCTL_100MBPS_STS 0x00000100
711 #define BGE_LEDCTL_10MBPS_STS 0x00000200
712 #define BGE_LEDCTL_TRADLED_STS 0x00000400
713 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
714 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
716 /* TX backoff seed register */
717 #define BGE_TX_BACKOFF_SEED_MASK 0x3F
719 /* Autopoll status register */
720 #define BGE_AUTOPOLLSTS_ERROR 0x00000001
722 /* Transmit MAC mode register */
723 #define BGE_TXMODE_RESET 0x00000001
724 #define BGE_TXMODE_ENABLE 0x00000002
725 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
726 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
727 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
728 #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100
729 #define BGE_TXMODE_JMB_FRM_LEN 0x00400000
730 #define BGE_TXMODE_CNT_DN_MODE 0x00800000
732 /* Transmit MAC status register */
733 #define BGE_TXSTAT_RX_XOFFED 0x00000001
734 #define BGE_TXSTAT_SENT_XOFF 0x00000002
735 #define BGE_TXSTAT_SENT_XON 0x00000004
736 #define BGE_TXSTAT_LINK_UP 0x00000008
737 #define BGE_TXSTAT_ODI_UFLOW 0x00000010
738 #define BGE_TXSTAT_ODI_OFLOW 0x00000020
740 /* Transmit MAC lengths register */
741 #define BGE_TXLEN_SLOTTIME 0x000000FF
742 #define BGE_TXLEN_IPG 0x00000F00
743 #define BGE_TXLEN_CRS 0x00003000
744 #define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000
745 #define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000
747 /* Receive MAC mode register */
748 #define BGE_RXMODE_RESET 0x00000001
749 #define BGE_RXMODE_ENABLE 0x00000002
750 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
751 #define BGE_RXMODE_RX_GIANTS 0x00000020
752 #define BGE_RXMODE_RX_RUNTS 0x00000040
753 #define BGE_RXMODE_8022_LENCHECK 0x00000080
754 #define BGE_RXMODE_RX_PROMISC 0x00000100
755 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
756 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
758 /* Receive MAC status register */
759 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
760 #define BGE_RXSTAT_RCVD_XOFF 0x00000002
761 #define BGE_RXSTAT_RCVD_XON 0x00000004
763 /* Receive Rules Control register */
764 #define BGE_RXRULECTL_OFFSET 0x000000FF
765 #define BGE_RXRULECTL_CLASS 0x00001F00
766 #define BGE_RXRULECTL_HDRTYPE 0x0000E000
767 #define BGE_RXRULECTL_COMPARE_OP 0x00030000
768 #define BGE_RXRULECTL_MAP 0x01000000
769 #define BGE_RXRULECTL_DISCARD 0x02000000
770 #define BGE_RXRULECTL_MASK 0x04000000
771 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
772 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
773 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
774 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
776 /* Receive Rules Mask register */
777 #define BGE_RXRULEMASK_VALUE 0x0000FFFF
778 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
780 /* SERDES configuration register */
781 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
782 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
783 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
784 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
785 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
786 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
787 #define BGE_SERDESCFG_TXMODE 0x00001000
788 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
789 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
790 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
791 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
792 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
793 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
794 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
795 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
796 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
798 /* SERDES status register */
799 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
800 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
802 /* SGDIG config (not documented) */
803 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
804 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
805 #define BGE_SGDIGCFG_SEND 0x40000000
806 #define BGE_SGDIGCFG_AUTO 0x80000000
808 /* SGDIG status (not documented) */
809 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
810 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
811 #define BGE_SGDIGSTS_DONE 0x00000002
812 #define BGE_SGDIGSTS_IS_SERDES 0x00000100
814 /* MI communication register */
815 #define BGE_MICOMM_DATA 0x0000FFFF
816 #define BGE_MICOMM_REG 0x001F0000
817 #define BGE_MICOMM_PHY 0x03E00000
818 #define BGE_MICOMM_CMD 0x0C000000
819 #define BGE_MICOMM_READFAIL 0x10000000
820 #define BGE_MICOMM_BUSY 0x20000000
822 #define BGE_MIREG(x) ((x & 0x1F) << 16)
823 #define BGE_MIPHY(x) ((x & 0x1F) << 21)
824 #define BGE_MICMD_WRITE 0x04000000
825 #define BGE_MICMD_READ 0x08000000
827 /* MI status register */
828 #define BGE_MISTS_LINK 0x00000001
829 #define BGE_MISTS_10MBPS 0x00000002
831 #define BGE_MIMODE_CLK_10MHZ 0x00000001
832 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002
833 #define BGE_MIMODE_AUTOPOLL 0x00000010
834 #define BGE_MIMODE_CLKCNT 0x001F0000
835 #define BGE_MIMODE_500KHZ_CONST 0x00008000
836 #define BGE_MIMODE_BASE 0x000C0000
840 * Send data initiator control registers.
842 #define BGE_SDI_MODE 0x0C00
843 #define BGE_SDI_STATUS 0x0C04
844 #define BGE_SDI_STATS_CTL 0x0C08
845 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
846 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
847 #define BGE_ISO_PKT_TX 0x0C20
848 #define BGE_LOCSTATS_COS0 0x0C80
849 #define BGE_LOCSTATS_COS1 0x0C84
850 #define BGE_LOCSTATS_COS2 0x0C88
851 #define BGE_LOCSTATS_COS3 0x0C8C
852 #define BGE_LOCSTATS_COS4 0x0C90
853 #define BGE_LOCSTATS_COS5 0x0C84
854 #define BGE_LOCSTATS_COS6 0x0C98
855 #define BGE_LOCSTATS_COS7 0x0C9C
856 #define BGE_LOCSTATS_COS8 0x0CA0
857 #define BGE_LOCSTATS_COS9 0x0CA4
858 #define BGE_LOCSTATS_COS10 0x0CA8
859 #define BGE_LOCSTATS_COS11 0x0CAC
860 #define BGE_LOCSTATS_COS12 0x0CB0
861 #define BGE_LOCSTATS_COS13 0x0CB4
862 #define BGE_LOCSTATS_COS14 0x0CB8
863 #define BGE_LOCSTATS_COS15 0x0CBC
864 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
865 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
866 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
867 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
868 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
869 #define BGE_LOCSTATS_IRQS 0x0CD4
870 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
871 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
873 /* Send Data Initiator mode register */
874 #define BGE_SDIMODE_RESET 0x00000001
875 #define BGE_SDIMODE_ENABLE 0x00000002
876 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
877 #define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008
879 /* Send Data Initiator stats register */
880 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
882 /* Send Data Initiator stats control register */
883 #define BGE_SDISTATSCTL_ENABLE 0x00000001
884 #define BGE_SDISTATSCTL_FASTER 0x00000002
885 #define BGE_SDISTATSCTL_CLEAR 0x00000004
886 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
887 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010
890 * Send Data Completion Control registers
892 #define BGE_SDC_MODE 0x1000
893 #define BGE_SDC_STATUS 0x1004
895 /* Send Data completion mode register */
896 #define BGE_SDCMODE_RESET 0x00000001
897 #define BGE_SDCMODE_ENABLE 0x00000002
898 #define BGE_SDCMODE_ATTN 0x00000004
899 #define BGE_SDCMODE_CDELAY 0x00000010
901 /* Send Data completion status register */
902 #define BGE_SDCSTAT_ATTN 0x00000004
905 * Send BD Ring Selector Control registers
907 #define BGE_SRS_MODE 0x1400
908 #define BGE_SRS_STATUS 0x1404
909 #define BGE_SRS_HWDIAG 0x1408
910 #define BGE_SRS_LOC_NIC_CONS0 0x1440
911 #define BGE_SRS_LOC_NIC_CONS1 0x1444
912 #define BGE_SRS_LOC_NIC_CONS2 0x1448
913 #define BGE_SRS_LOC_NIC_CONS3 0x144C
914 #define BGE_SRS_LOC_NIC_CONS4 0x1450
915 #define BGE_SRS_LOC_NIC_CONS5 0x1454
916 #define BGE_SRS_LOC_NIC_CONS6 0x1458
917 #define BGE_SRS_LOC_NIC_CONS7 0x145C
918 #define BGE_SRS_LOC_NIC_CONS8 0x1460
919 #define BGE_SRS_LOC_NIC_CONS9 0x1464
920 #define BGE_SRS_LOC_NIC_CONS10 0x1468
921 #define BGE_SRS_LOC_NIC_CONS11 0x146C
922 #define BGE_SRS_LOC_NIC_CONS12 0x1470
923 #define BGE_SRS_LOC_NIC_CONS13 0x1474
924 #define BGE_SRS_LOC_NIC_CONS14 0x1478
925 #define BGE_SRS_LOC_NIC_CONS15 0x147C
927 /* Send BD Ring Selector Mode register */
928 #define BGE_SRSMODE_RESET 0x00000001
929 #define BGE_SRSMODE_ENABLE 0x00000002
930 #define BGE_SRSMODE_ATTN 0x00000004
932 /* Send BD Ring Selector Status register */
933 #define BGE_SRSSTAT_ERROR 0x00000004
935 /* Send BD Ring Selector HW Diagnostics register */
936 #define BGE_SRSHWDIAG_STATE 0x0000000F
937 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
938 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
939 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
942 * Send BD Initiator Selector Control registers
944 #define BGE_SBDI_MODE 0x1800
945 #define BGE_SBDI_STATUS 0x1804
946 #define BGE_SBDI_LOC_NIC_PROD0 0x1808
947 #define BGE_SBDI_LOC_NIC_PROD1 0x180C
948 #define BGE_SBDI_LOC_NIC_PROD2 0x1810
949 #define BGE_SBDI_LOC_NIC_PROD3 0x1814
950 #define BGE_SBDI_LOC_NIC_PROD4 0x1818
951 #define BGE_SBDI_LOC_NIC_PROD5 0x181C
952 #define BGE_SBDI_LOC_NIC_PROD6 0x1820
953 #define BGE_SBDI_LOC_NIC_PROD7 0x1824
954 #define BGE_SBDI_LOC_NIC_PROD8 0x1828
955 #define BGE_SBDI_LOC_NIC_PROD9 0x182C
956 #define BGE_SBDI_LOC_NIC_PROD10 0x1830
957 #define BGE_SBDI_LOC_NIC_PROD11 0x1834
958 #define BGE_SBDI_LOC_NIC_PROD12 0x1838
959 #define BGE_SBDI_LOC_NIC_PROD13 0x183C
960 #define BGE_SBDI_LOC_NIC_PROD14 0x1840
961 #define BGE_SBDI_LOC_NIC_PROD15 0x1844
963 /* Send BD Initiator Mode register */
964 #define BGE_SBDIMODE_RESET 0x00000001
965 #define BGE_SBDIMODE_ENABLE 0x00000002
966 #define BGE_SBDIMODE_ATTN 0x00000004
968 /* Send BD Initiator Status register */
969 #define BGE_SBDISTAT_ERROR 0x00000004
972 * Send BD Completion Control registers
974 #define BGE_SBDC_MODE 0x1C00
975 #define BGE_SBDC_STATUS 0x1C04
977 /* Send BD Completion Control Mode register */
978 #define BGE_SBDCMODE_RESET 0x00000001
979 #define BGE_SBDCMODE_ENABLE 0x00000002
980 #define BGE_SBDCMODE_ATTN 0x00000004
982 /* Send BD Completion Control Status register */
983 #define BGE_SBDCSTAT_ATTN 0x00000004
986 * Receive List Placement Control registers
988 #define BGE_RXLP_MODE 0x2000
989 #define BGE_RXLP_STATUS 0x2004
990 #define BGE_RXLP_SEL_LIST_LOCK 0x2008
991 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
992 #define BGE_RXLP_CFG 0x2010
993 #define BGE_RXLP_STATS_CTL 0x2014
994 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018
995 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
996 #define BGE_RXLP_HEAD0 0x2100
997 #define BGE_RXLP_TAIL0 0x2104
998 #define BGE_RXLP_COUNT0 0x2108
999 #define BGE_RXLP_HEAD1 0x2110
1000 #define BGE_RXLP_TAIL1 0x2114
1001 #define BGE_RXLP_COUNT1 0x2118
1002 #define BGE_RXLP_HEAD2 0x2120
1003 #define BGE_RXLP_TAIL2 0x2124
1004 #define BGE_RXLP_COUNT2 0x2128
1005 #define BGE_RXLP_HEAD3 0x2130
1006 #define BGE_RXLP_TAIL3 0x2134
1007 #define BGE_RXLP_COUNT3 0x2138
1008 #define BGE_RXLP_HEAD4 0x2140
1009 #define BGE_RXLP_TAIL4 0x2144
1010 #define BGE_RXLP_COUNT4 0x2148
1011 #define BGE_RXLP_HEAD5 0x2150
1012 #define BGE_RXLP_TAIL5 0x2154
1013 #define BGE_RXLP_COUNT5 0x2158
1014 #define BGE_RXLP_HEAD6 0x2160
1015 #define BGE_RXLP_TAIL6 0x2164
1016 #define BGE_RXLP_COUNT6 0x2168
1017 #define BGE_RXLP_HEAD7 0x2170
1018 #define BGE_RXLP_TAIL7 0x2174
1019 #define BGE_RXLP_COUNT7 0x2178
1020 #define BGE_RXLP_HEAD8 0x2180
1021 #define BGE_RXLP_TAIL8 0x2184
1022 #define BGE_RXLP_COUNT8 0x2188
1023 #define BGE_RXLP_HEAD9 0x2190
1024 #define BGE_RXLP_TAIL9 0x2194
1025 #define BGE_RXLP_COUNT9 0x2198
1026 #define BGE_RXLP_HEAD10 0x21A0
1027 #define BGE_RXLP_TAIL10 0x21A4
1028 #define BGE_RXLP_COUNT10 0x21A8
1029 #define BGE_RXLP_HEAD11 0x21B0
1030 #define BGE_RXLP_TAIL11 0x21B4
1031 #define BGE_RXLP_COUNT11 0x21B8
1032 #define BGE_RXLP_HEAD12 0x21C0
1033 #define BGE_RXLP_TAIL12 0x21C4
1034 #define BGE_RXLP_COUNT12 0x21C8
1035 #define BGE_RXLP_HEAD13 0x21D0
1036 #define BGE_RXLP_TAIL13 0x21D4
1037 #define BGE_RXLP_COUNT13 0x21D8
1038 #define BGE_RXLP_HEAD14 0x21E0
1039 #define BGE_RXLP_TAIL14 0x21E4
1040 #define BGE_RXLP_COUNT14 0x21E8
1041 #define BGE_RXLP_HEAD15 0x21F0
1042 #define BGE_RXLP_TAIL15 0x21F4
1043 #define BGE_RXLP_COUNT15 0x21F8
1044 #define BGE_RXLP_LOCSTAT_COS0 0x2200
1045 #define BGE_RXLP_LOCSTAT_COS1 0x2204
1046 #define BGE_RXLP_LOCSTAT_COS2 0x2208
1047 #define BGE_RXLP_LOCSTAT_COS3 0x220C
1048 #define BGE_RXLP_LOCSTAT_COS4 0x2210
1049 #define BGE_RXLP_LOCSTAT_COS5 0x2214
1050 #define BGE_RXLP_LOCSTAT_COS6 0x2218
1051 #define BGE_RXLP_LOCSTAT_COS7 0x221C
1052 #define BGE_RXLP_LOCSTAT_COS8 0x2220
1053 #define BGE_RXLP_LOCSTAT_COS9 0x2224
1054 #define BGE_RXLP_LOCSTAT_COS10 0x2228
1055 #define BGE_RXLP_LOCSTAT_COS11 0x222C
1056 #define BGE_RXLP_LOCSTAT_COS12 0x2230
1057 #define BGE_RXLP_LOCSTAT_COS13 0x2234
1058 #define BGE_RXLP_LOCSTAT_COS14 0x2238
1059 #define BGE_RXLP_LOCSTAT_COS15 0x223C
1060 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1061 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1062 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1063 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1064 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1065 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1066 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1069 /* Receive List Placement mode register */
1070 #define BGE_RXLPMODE_RESET 0x00000001
1071 #define BGE_RXLPMODE_ENABLE 0x00000002
1072 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1073 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1074 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1076 /* Receive List Placement Status register */
1077 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1078 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1079 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1082 * Receive Data and Receive BD Initiator Control Registers
1084 #define BGE_RDBDI_MODE 0x2400
1085 #define BGE_RDBDI_STATUS 0x2404
1086 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1087 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1088 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1089 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1090 #define BGE_RX_STD_RCB_HADDR_HI 0x2450
1091 #define BGE_RX_STD_RCB_HADDR_LO 0x2454
1092 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1093 #define BGE_RX_STD_RCB_NICADDR 0x245C
1094 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1095 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1096 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1097 #define BGE_RX_MINI_RCB_NICADDR 0x246C
1098 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1099 #define BGE_RDBDI_STD_RX_CONS 0x2474
1100 #define BGE_RDBDI_MINI_RX_CONS 0x2478
1101 #define BGE_RDBDI_RETURN_PROD0 0x2480
1102 #define BGE_RDBDI_RETURN_PROD1 0x2484
1103 #define BGE_RDBDI_RETURN_PROD2 0x2488
1104 #define BGE_RDBDI_RETURN_PROD3 0x248C
1105 #define BGE_RDBDI_RETURN_PROD4 0x2490
1106 #define BGE_RDBDI_RETURN_PROD5 0x2494
1107 #define BGE_RDBDI_RETURN_PROD6 0x2498
1108 #define BGE_RDBDI_RETURN_PROD7 0x249C
1109 #define BGE_RDBDI_RETURN_PROD8 0x24A0
1110 #define BGE_RDBDI_RETURN_PROD9 0x24A4
1111 #define BGE_RDBDI_RETURN_PROD10 0x24A8
1112 #define BGE_RDBDI_RETURN_PROD11 0x24AC
1113 #define BGE_RDBDI_RETURN_PROD12 0x24B0
1114 #define BGE_RDBDI_RETURN_PROD13 0x24B4
1115 #define BGE_RDBDI_RETURN_PROD14 0x24B8
1116 #define BGE_RDBDI_RETURN_PROD15 0x24BC
1117 #define BGE_RDBDI_HWDIAG 0x24C0
1120 /* Receive Data and Receive BD Initiator Mode register */
1121 #define BGE_RDBDIMODE_RESET 0x00000001
1122 #define BGE_RDBDIMODE_ENABLE 0x00000002
1123 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1124 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1125 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1127 /* Receive Data and Receive BD Initiator Status register */
1128 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1129 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1130 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1134 * Receive Data Completion Control registers
1136 #define BGE_RDC_MODE 0x2800
1138 /* Receive Data Completion Mode register */
1139 #define BGE_RDCMODE_RESET 0x00000001
1140 #define BGE_RDCMODE_ENABLE 0x00000002
1141 #define BGE_RDCMODE_ATTN 0x00000004
1144 * Receive BD Initiator Control registers
1146 #define BGE_RBDI_MODE 0x2C00
1147 #define BGE_RBDI_STATUS 0x2C04
1148 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1149 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1150 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1151 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1152 #define BGE_RBDI_STD_REPL_THRESH 0x2C18
1153 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1155 #define BGE_STD_REPLENISH_LWM 0x2D00
1156 #define BGE_JMB_REPLENISH_LWM 0x2D04
1158 /* Receive BD Initiator Mode register */
1159 #define BGE_RBDIMODE_RESET 0x00000001
1160 #define BGE_RBDIMODE_ENABLE 0x00000002
1161 #define BGE_RBDIMODE_ATTN 0x00000004
1163 /* Receive BD Initiator Status register */
1164 #define BGE_RBDISTAT_ATTN 0x00000004
1167 * Receive BD Completion Control registers
1169 #define BGE_RBDC_MODE 0x3000
1170 #define BGE_RBDC_STATUS 0x3004
1171 #define BGE_RBDC_JUMBO_BD_PROD 0x3008
1172 #define BGE_RBDC_STD_BD_PROD 0x300C
1173 #define BGE_RBDC_MINI_BD_PROD 0x3010
1175 /* Receive BD completion mode register */
1176 #define BGE_RBDCMODE_RESET 0x00000001
1177 #define BGE_RBDCMODE_ENABLE 0x00000002
1178 #define BGE_RBDCMODE_ATTN 0x00000004
1180 /* Receive BD completion status register */
1181 #define BGE_RBDCSTAT_ERROR 0x00000004
1184 * Receive List Selector Control registers
1186 #define BGE_RXLS_MODE 0x3400
1187 #define BGE_RXLS_STATUS 0x3404
1189 /* Receive List Selector Mode register */
1190 #define BGE_RXLSMODE_RESET 0x00000001
1191 #define BGE_RXLSMODE_ENABLE 0x00000002
1192 #define BGE_RXLSMODE_ATTN 0x00000004
1194 /* Receive List Selector Status register */
1195 #define BGE_RXLSSTAT_ERROR 0x00000004
1197 #define BGE_CPMU_CTRL 0x3600
1198 #define BGE_CPMU_LSPD_10MB_CLK 0x3604
1199 #define BGE_CPMU_LSPD_1000MB_CLK 0x360C
1200 #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610
1201 #define BGE_CPMU_HST_ACC 0x361C
1202 #define BGE_CPMU_CLCK_STAT 0x3630
1203 #define BGE_CPMU_CLCK_ORIDE 0x3624
1204 #define BGE_CPMU_MUTEX_REQ 0x365C
1205 #define BGE_CPMU_MUTEX_GNT 0x3660
1206 #define BGE_CPMU_PHY_STRAP 0x3664
1207 #define BGE_CPMU_PADRNG_CTL 0x3668
1209 /* Central Power Management Unit (CPMU) register */
1210 #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1211 #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1212 #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1213 #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1215 /* Link Speed 10MB/No Link Power Mode Clock Policy register */
1216 #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000
1217 #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1219 /* Link Speed 1000MB Power Mode Clock Policy register */
1220 #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1221 #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1222 #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000
1224 /* Link Aware Power Mode Clock Policy register */
1225 #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000
1226 #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1228 #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000
1229 #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000
1231 /* Clock Speed Override Policy register */
1232 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1234 /* CPMU Clock Status register */
1235 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000
1236 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1237 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1238 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1240 /* CPMU Mutex Request register */
1241 #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000
1242 #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000
1244 /* CPMU GPHY Strap register */
1245 #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1247 /* CPMU Padring Control register */
1248 #define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000
1251 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1253 #define BGE_MBCF_MODE 0x3800
1254 #define BGE_MBCF_STATUS 0x3804
1256 /* Mbuf Cluster Free mode register */
1257 #define BGE_MBCFMODE_RESET 0x00000001
1258 #define BGE_MBCFMODE_ENABLE 0x00000002
1259 #define BGE_MBCFMODE_ATTN 0x00000004
1261 /* Mbuf Cluster Free status register */
1262 #define BGE_MBCFSTAT_ERROR 0x00000004
1265 * Host Coalescing Control registers
1267 #define BGE_HCC_MODE 0x3C00
1268 #define BGE_HCC_STATUS 0x3C04
1269 #define BGE_HCC_RX_COAL_TICKS 0x3C08
1270 #define BGE_HCC_TX_COAL_TICKS 0x3C0C
1271 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1272 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1273 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1274 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1275 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1276 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1277 #define BGE_HCC_STATS_TICKS 0x3C28
1278 #define BGE_HCC_STATS_ADDR_HI 0x3C30
1279 #define BGE_HCC_STATS_ADDR_LO 0x3C34
1280 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1281 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1282 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1283 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1284 #define BGE_FLOW_ATTN 0x3C48
1285 #define BGE_HCC_JUMBO_BD_CONS 0x3C50
1286 #define BGE_HCC_STD_BD_CONS 0x3C54
1287 #define BGE_HCC_MINI_BD_CONS 0x3C58
1288 #define BGE_HCC_RX_RETURN_PROD0 0x3C80
1289 #define BGE_HCC_RX_RETURN_PROD1 0x3C84
1290 #define BGE_HCC_RX_RETURN_PROD2 0x3C88
1291 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1292 #define BGE_HCC_RX_RETURN_PROD4 0x3C90
1293 #define BGE_HCC_RX_RETURN_PROD5 0x3C94
1294 #define BGE_HCC_RX_RETURN_PROD6 0x3C98
1295 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1296 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1297 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1298 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1299 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1300 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1301 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1302 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1303 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1304 #define BGE_HCC_TX_BD_CONS0 0x3CC0
1305 #define BGE_HCC_TX_BD_CONS1 0x3CC4
1306 #define BGE_HCC_TX_BD_CONS2 0x3CC8
1307 #define BGE_HCC_TX_BD_CONS3 0x3CCC
1308 #define BGE_HCC_TX_BD_CONS4 0x3CD0
1309 #define BGE_HCC_TX_BD_CONS5 0x3CD4
1310 #define BGE_HCC_TX_BD_CONS6 0x3CD8
1311 #define BGE_HCC_TX_BD_CONS7 0x3CDC
1312 #define BGE_HCC_TX_BD_CONS8 0x3CE0
1313 #define BGE_HCC_TX_BD_CONS9 0x3CE4
1314 #define BGE_HCC_TX_BD_CONS10 0x3CE8
1315 #define BGE_HCC_TX_BD_CONS11 0x3CEC
1316 #define BGE_HCC_TX_BD_CONS12 0x3CF0
1317 #define BGE_HCC_TX_BD_CONS13 0x3CF4
1318 #define BGE_HCC_TX_BD_CONS14 0x3CF8
1319 #define BGE_HCC_TX_BD_CONS15 0x3CFC
1322 /* Host coalescing mode register */
1323 #define BGE_HCCMODE_RESET 0x00000001
1324 #define BGE_HCCMODE_ENABLE 0x00000002
1325 #define BGE_HCCMODE_ATTN 0x00000004
1326 #define BGE_HCCMODE_COAL_NOW 0x00000008
1327 #define BGE_HCCMODE_MSI_BITS 0x0x000070
1328 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1329 #define BGE_HCCMODE_CLRTICK_RX 0x00000200
1330 #define BGE_HCCMODE_CLRTICK_TX 0x00000400
1332 #define BGE_STATBLKSZ_FULL 0x00000000
1333 #define BGE_STATBLKSZ_64BYTE 0x00000080
1334 #define BGE_STATBLKSZ_32BYTE 0x00000100
1336 /* Host coalescing status register */
1337 #define BGE_HCCSTAT_ERROR 0x00000004
1339 /* Flow attention register */
1340 #define BGE_FLOWATTN_MB_LOWAT 0x00000040
1341 #define BGE_FLOWATTN_MEMARB 0x00000080
1342 #define BGE_FLOWATTN_HOSTCOAL 0x00008000
1343 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1344 #define BGE_FLOWATTN_RCB_INVAL 0x00020000
1345 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1346 #define BGE_FLOWATTN_RDBDI 0x00080000
1347 #define BGE_FLOWATTN_RXLS 0x00100000
1348 #define BGE_FLOWATTN_RXLP 0x00200000
1349 #define BGE_FLOWATTN_RBDC 0x00400000
1350 #define BGE_FLOWATTN_RBDI 0x00800000
1351 #define BGE_FLOWATTN_SDC 0x08000000
1352 #define BGE_FLOWATTN_SDI 0x10000000
1353 #define BGE_FLOWATTN_SRS 0x20000000
1354 #define BGE_FLOWATTN_SBDC 0x40000000
1355 #define BGE_FLOWATTN_SBDI 0x80000000
1358 * Memory arbiter registers
1360 #define BGE_MARB_MODE 0x4000
1361 #define BGE_MARB_STATUS 0x4004
1362 #define BGE_MARB_TRAPADDR_HI 0x4008
1363 #define BGE_MARB_TRAPADDR_LO 0x400C
1365 /* Memory arbiter mode register */
1366 #define BGE_MARBMODE_RESET 0x00000001
1367 #define BGE_MARBMODE_ENABLE 0x00000002
1368 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1369 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1370 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1371 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1372 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1373 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1374 #define BGE_MARBMODE_PCI_TRAP 0x00000100
1375 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1376 #define BGE_MARBMODE_RXQ_TRAP 0x00000400
1377 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1378 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1379 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1380 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1381 #define BGE_MARBMODE_MBUF_TRAP 0x00008000
1382 #define BGE_MARBMODE_TXDI_TRAP 0x00010000
1383 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1384 #define BGE_MARBMODE_TXBD_TRAP 0x00040000
1385 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1386 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1387 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1388 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1389 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1390 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1391 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1393 /* Memory arbiter status register */
1394 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1395 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1396 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1397 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1398 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1399 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1400 #define BGE_MARBSTAT_PCI_TRAP 0x00000100
1401 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1402 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1403 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1404 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1405 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1406 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1407 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1408 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1409 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1410 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1411 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1412 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1413 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1414 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1415 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1416 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1417 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1420 * Buffer manager control registers
1422 #define BGE_BMAN_MODE 0x4400
1423 #define BGE_BMAN_STATUS 0x4404
1424 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1425 #define BGE_BMAN_MBUFPOOL_LEN 0x440C
1426 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1427 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1428 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1429 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1430 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1431 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1432 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1433 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1434 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1435 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1436 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1437 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1438 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1439 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1440 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1441 #define BGE_BMAN_HWDIAG_1 0x444C
1442 #define BGE_BMAN_HWDIAG_2 0x4450
1443 #define BGE_BMAN_HWDIAG_3 0x4454
1445 /* Buffer manager mode register */
1446 #define BGE_BMANMODE_RESET 0x00000001
1447 #define BGE_BMANMODE_ENABLE 0x00000002
1448 #define BGE_BMANMODE_ATTN 0x00000004
1449 #define BGE_BMANMODE_TESTMODE 0x00000008
1450 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1451 #define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000
1453 /* Buffer manager status register */
1454 #define BGE_BMANSTAT_ERRO 0x00000004
1455 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1459 * Read DMA Control registers
1461 #define BGE_RDMA_MODE 0x4800
1462 #define BGE_RDMA_STATUS 0x4804
1463 #define BGE_RDMA_RSRVCTRL2 0x4890
1464 #define BGE_RDMA_LSO_CRPTEN_CTRL2 0x48a0
1465 #define BGE_RDMA_RSRVCTRL 0x4900
1466 #define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910
1468 /* Read DMA mode register */
1469 #define BGE_RDMAMODE_RESET 0x00000001
1470 #define BGE_RDMAMODE_ENABLE 0x00000002
1471 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1472 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1473 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1474 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1475 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1476 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1477 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1478 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1479 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1480 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
1481 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
1482 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
1483 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
1484 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
1485 #define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000
1486 #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000
1487 #define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000
1489 /* Read DMA status register */
1490 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1491 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1492 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1493 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1494 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1495 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1496 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1497 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1499 /* Read DMA Reserved Control register */
1500 #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1501 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00
1502 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000
1503 #define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1504 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0
1505 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000
1506 #define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000
1508 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000
1509 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1510 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000
1513 * Write DMA control registers
1515 #define BGE_WDMA_MODE 0x4C00
1516 #define BGE_WDMA_STATUS 0x4C04
1518 /* Write DMA mode register */
1519 #define BGE_WDMAMODE_RESET 0x00000001
1520 #define BGE_WDMAMODE_ENABLE 0x00000002
1521 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1522 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1523 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1524 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1525 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1526 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1527 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1528 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1529 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1530 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000
1531 #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000
1533 /* Write DMA status register */
1534 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1535 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1536 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1537 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1538 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1539 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1540 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1541 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1547 #define BGE_RXCPU_MODE 0x5000
1548 #define BGE_RXCPU_STATUS 0x5004
1549 #define BGE_RXCPU_PC 0x501C
1551 /* RX CPU mode register */
1552 #define BGE_RXCPUMODE_RESET 0x00000001
1553 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1554 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1555 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1556 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1557 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1558 #define BGE_RXCPUMODE_ROMFAIL 0x00000040
1559 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1560 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1561 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1562 #define BGE_RXCPUMODE_HALTCPU 0x00000400
1563 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1564 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1565 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1567 /* RX CPU status register */
1568 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1569 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1570 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1571 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1572 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1573 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1574 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1575 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1576 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1577 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1578 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1579 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1580 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1581 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1582 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1583 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1584 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1589 #define BGE_VCPU_STATUS 0x5100
1590 #define BGE_VCPU_EXT_CTRL 0x6890
1592 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000
1593 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000
1595 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1596 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1602 #define BGE_TXCPU_MODE 0x5400
1603 #define BGE_TXCPU_STATUS 0x5404
1604 #define BGE_TXCPU_PC 0x541C
1606 /* TX CPU mode register */
1607 #define BGE_TXCPUMODE_RESET 0x00000001
1608 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1609 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1610 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1611 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1612 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1613 #define BGE_TXCPUMODE_ROMFAIL 0x00000040
1614 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1615 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1616 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1617 #define BGE_TXCPUMODE_HALTCPU 0x00000400
1618 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1619 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1621 /* TX CPU status register */
1622 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1623 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1624 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1625 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1626 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1627 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1628 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1629 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1630 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1631 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1632 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1633 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1634 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1635 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1636 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1637 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1638 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1642 * Low priority mailbox registers
1644 #define BGE_LPMBX_IRQ0_HI 0x5800
1645 #define BGE_LPMBX_IRQ0_LO 0x5804
1646 #define BGE_LPMBX_IRQ1_HI 0x5808
1647 #define BGE_LPMBX_IRQ1_LO 0x580C
1648 #define BGE_LPMBX_IRQ2_HI 0x5810
1649 #define BGE_LPMBX_IRQ2_LO 0x5814
1650 #define BGE_LPMBX_IRQ3_HI 0x5818
1651 #define BGE_LPMBX_IRQ3_LO 0x581C
1652 #define BGE_LPMBX_GEN0_HI 0x5820
1653 #define BGE_LPMBX_GEN0_LO 0x5824
1654 #define BGE_LPMBX_GEN1_HI 0x5828
1655 #define BGE_LPMBX_GEN1_LO 0x582C
1656 #define BGE_LPMBX_GEN2_HI 0x5830
1657 #define BGE_LPMBX_GEN2_LO 0x5834
1658 #define BGE_LPMBX_GEN3_HI 0x5828
1659 #define BGE_LPMBX_GEN3_LO 0x582C
1660 #define BGE_LPMBX_GEN4_HI 0x5840
1661 #define BGE_LPMBX_GEN4_LO 0x5844
1662 #define BGE_LPMBX_GEN5_HI 0x5848
1663 #define BGE_LPMBX_GEN5_LO 0x584C
1664 #define BGE_LPMBX_GEN6_HI 0x5850
1665 #define BGE_LPMBX_GEN6_LO 0x5854
1666 #define BGE_LPMBX_GEN7_HI 0x5858
1667 #define BGE_LPMBX_GEN7_LO 0x585C
1668 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1669 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1670 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1671 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1672 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1673 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1674 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1675 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1676 #define BGE_LPMBX_RX_CONS0_HI 0x5880
1677 #define BGE_LPMBX_RX_CONS0_LO 0x5884
1678 #define BGE_LPMBX_RX_CONS1_HI 0x5888
1679 #define BGE_LPMBX_RX_CONS1_LO 0x588C
1680 #define BGE_LPMBX_RX_CONS2_HI 0x5890
1681 #define BGE_LPMBX_RX_CONS2_LO 0x5894
1682 #define BGE_LPMBX_RX_CONS3_HI 0x5898
1683 #define BGE_LPMBX_RX_CONS3_LO 0x589C
1684 #define BGE_LPMBX_RX_CONS4_HI 0x58A0
1685 #define BGE_LPMBX_RX_CONS4_LO 0x58A4
1686 #define BGE_LPMBX_RX_CONS5_HI 0x58A8
1687 #define BGE_LPMBX_RX_CONS5_LO 0x58AC
1688 #define BGE_LPMBX_RX_CONS6_HI 0x58B0
1689 #define BGE_LPMBX_RX_CONS6_LO 0x58B4
1690 #define BGE_LPMBX_RX_CONS7_HI 0x58B8
1691 #define BGE_LPMBX_RX_CONS7_LO 0x58BC
1692 #define BGE_LPMBX_RX_CONS8_HI 0x58C0
1693 #define BGE_LPMBX_RX_CONS8_LO 0x58C4
1694 #define BGE_LPMBX_RX_CONS9_HI 0x58C8
1695 #define BGE_LPMBX_RX_CONS9_LO 0x58CC
1696 #define BGE_LPMBX_RX_CONS10_HI 0x58D0
1697 #define BGE_LPMBX_RX_CONS10_LO 0x58D4
1698 #define BGE_LPMBX_RX_CONS11_HI 0x58D8
1699 #define BGE_LPMBX_RX_CONS11_LO 0x58DC
1700 #define BGE_LPMBX_RX_CONS12_HI 0x58E0
1701 #define BGE_LPMBX_RX_CONS12_LO 0x58E4
1702 #define BGE_LPMBX_RX_CONS13_HI 0x58E8
1703 #define BGE_LPMBX_RX_CONS13_LO 0x58EC
1704 #define BGE_LPMBX_RX_CONS14_HI 0x58F0
1705 #define BGE_LPMBX_RX_CONS14_LO 0x58F4
1706 #define BGE_LPMBX_RX_CONS15_HI 0x58F8
1707 #define BGE_LPMBX_RX_CONS15_LO 0x58FC
1708 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1709 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1710 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1711 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1712 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1713 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1714 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1715 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1716 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1717 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1718 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1719 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1720 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1721 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1722 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1723 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1724 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1725 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1726 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1727 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1728 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1729 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1730 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1731 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1732 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1733 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1734 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1735 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1736 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1737 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1738 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1739 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1740 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1741 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1742 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1743 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1744 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1745 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1746 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1747 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1748 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1749 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1750 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1751 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1752 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1753 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1754 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1755 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1756 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1757 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1758 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1759 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1760 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1761 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1762 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1763 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1764 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1765 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1766 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1767 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1768 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1769 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1770 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1771 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1774 * Flow throw Queue reset register
1776 #define BGE_FTQ_RESET 0x5C00
1778 #define BGE_FTQRESET_DMAREAD 0x00000002
1779 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1780 #define BGE_FTQRESET_DMADONE 0x00000010
1781 #define BGE_FTQRESET_SBDC 0x00000020
1782 #define BGE_FTQRESET_SDI 0x00000040
1783 #define BGE_FTQRESET_WDMA 0x00000080
1784 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1785 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1786 #define BGE_FTQRESET_SDC 0x00000400
1787 #define BGE_FTQRESET_HCC 0x00000800
1788 #define BGE_FTQRESET_TXFIFO 0x00001000
1789 #define BGE_FTQRESET_MBC 0x00002000
1790 #define BGE_FTQRESET_RBDC 0x00004000
1791 #define BGE_FTQRESET_RXLP 0x00008000
1792 #define BGE_FTQRESET_RDBDI 0x00010000
1793 #define BGE_FTQRESET_RDC 0x00020000
1794 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1797 * Message Signaled Interrupt registers
1799 #define BGE_MSI_MODE 0x6000
1800 #define BGE_MSI_STATUS 0x6004
1801 #define BGE_MSI_FIFOACCESS 0x6008
1803 /* MSI mode register */
1804 #define BGE_MSIMODE_RESET 0x00000001
1805 #define BGE_MSIMODE_ENABLE 0x00000002
1806 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
1807 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1808 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
1809 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
1810 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
1812 * Duplicate MSI_FIFOUFLOW_ATTN, only applies to BCM57785 and BCM5718
1813 * families. See 5718-PG105-R.
1815 #define BGE_MSIMODE_ONESHOT_DISABLE 0x00000020
1817 /* MSI status register */
1818 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1819 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1820 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1821 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1822 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1826 * DMA Completion registers
1828 #define BGE_DMAC_MODE 0x6400
1830 /* DMA Completion mode register */
1831 #define BGE_DMACMODE_RESET 0x00000001
1832 #define BGE_DMACMODE_ENABLE 0x00000002
1836 * General control registers.
1838 #define BGE_MODE_CTL 0x6800
1839 #define BGE_MISC_CFG 0x6804
1840 #define BGE_MISC_LOCAL_CTL 0x6808
1841 #define BGE_EE_ADDR 0x6838
1842 #define BGE_EE_DATA 0x683C
1843 #define BGE_EE_CTL 0x6840
1844 #define BGE_MDI_CTL 0x6844
1845 #define BGE_EE_DELAY 0x6848
1846 #define BGE_FASTBOOT_PC 0x6894
1849 * NVRAM Control registers
1851 #define BGE_NVRAM_CMD 0x7000
1852 #define BGE_NVRAM_STAT 0x7004
1853 #define BGE_NVRAM_WRDATA 0x7008
1854 #define BGE_NVRAM_ADDR 0x700c
1855 #define BGE_NVRAM_RDDATA 0x7010
1856 #define BGE_NVRAM_CFG1 0x7014
1857 #define BGE_NVRAM_CFG2 0x7018
1858 #define BGE_NVRAM_CFG3 0x701c
1859 #define BGE_NVRAM_SWARB 0x7020
1860 #define BGE_NVRAM_ACCESS 0x7024
1861 #define BGE_NVRAM_WRITE1 0x7028
1863 #define BGE_NVRAMCMD_RESET 0x00000001
1864 #define BGE_NVRAMCMD_DONE 0x00000008
1865 #define BGE_NVRAMCMD_START 0x00000010
1866 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */
1867 #define BGE_NVRAMCMD_ERASE 0x00000040
1868 #define BGE_NVRAMCMD_FIRST 0x00000080
1869 #define BGE_NVRAMCMD_LAST 0x00000100
1871 #define BGE_NVRAM_READCMD \
1872 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1873 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
1874 #define BGE_NVRAM_WRITECMD \
1875 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1876 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
1878 #define BGE_NVRAMSWARB_SET0 0x00000001
1879 #define BGE_NVRAMSWARB_SET1 0x00000002
1880 #define BGE_NVRAMSWARB_SET2 0x00000003
1881 #define BGE_NVRAMSWARB_SET3 0x00000004
1882 #define BGE_NVRAMSWARB_CLR0 0x00000010
1883 #define BGE_NVRAMSWARB_CLR1 0x00000020
1884 #define BGE_NVRAMSWARB_CLR2 0x00000040
1885 #define BGE_NVRAMSWARB_CLR3 0x00000080
1886 #define BGE_NVRAMSWARB_GNT0 0x00000100
1887 #define BGE_NVRAMSWARB_GNT1 0x00000200
1888 #define BGE_NVRAMSWARB_GNT2 0x00000400
1889 #define BGE_NVRAMSWARB_GNT3 0x00000800
1890 #define BGE_NVRAMSWARB_REQ0 0x00001000
1891 #define BGE_NVRAMSWARB_REQ1 0x00002000
1892 #define BGE_NVRAMSWARB_REQ2 0x00004000
1893 #define BGE_NVRAMSWARB_REQ3 0x00008000
1895 #define BGE_NVRAMACC_ENABLE 0x00000001
1896 #define BGE_NVRAMACC_WRENABLE 0x00000002
1898 /* Mode control register */
1899 #define BGE_MODECTL_PCIE_TL_SEL 0x00000000
1900 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1901 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1902 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1903 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1904 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1905 #define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040
1906 #define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080
1907 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1908 #define BGE_MODECTL_NO_RX_CRC 0x00000400
1909 #define BGE_MODECTL_RX_BADFRAMES 0x00000800
1910 #define BGE_MODECTL_NO_TX_INTR 0x00002000
1911 #define BGE_MODECTL_NO_RX_INTR 0x00004000
1912 #define BGE_MODECTL_FORCE_PCI32 0x00008000
1913 #define BGE_MODECTL_B2HRX_ENABLE 0x00008000
1914 #define BGE_MODECTL_STACKUP 0x00010000
1915 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000
1916 #define BGE_MODECTL_HTX2B_ENABLE 0x00040000
1917 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1918 #define BGE_MODECTL_PCIE_PL_SEL 0x00400000
1919 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1920 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1921 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1922 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1923 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1924 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1925 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1926 #define BGE_MODECTL_PCIE_DL_SEL 0x20000000
1927 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1928 #define BGE_MODECTL_PCIE_HI1K_EN 0x80000000
1929 #define BGE_MODECTL_PCIE_PORTS \
1930 (BGE_MODECTL_PCIE_HI1K_EN | \
1931 BGE_MODECTL_PCIE_TL_SEL | \
1932 BGE_MODECTL_PCIE_PL_SEL | \
1933 BGE_MODECTL_PCIE_DL_SEL)
1935 /* Misc. config register */
1936 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1937 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1938 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000
1939 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000
1940 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000
1941 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000
1942 #define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000
1944 #define BGE_32BITTIME_66MHZ (0x41 << 1)
1946 /* Misc. Local Control */
1947 #define BGE_MLC_INTR_STATE 0x00000001
1948 #define BGE_MLC_INTR_CLR 0x00000002
1949 #define BGE_MLC_INTR_SET 0x00000004
1950 #define BGE_MLC_INTR_ONATTN 0x00000008
1951 #define BGE_MLC_MISCIO_IN0 0x00000100
1952 #define BGE_MLC_MISCIO_IN1 0x00000200
1953 #define BGE_MLC_MISCIO_IN2 0x00000400
1954 #define BGE_MLC_MISCIO_OUTEN0 0x00000800
1955 #define BGE_MLC_MISCIO_OUTEN1 0x00001000
1956 #define BGE_MLC_MISCIO_OUTEN2 0x00002000
1957 #define BGE_MLC_MISCIO_OUT0 0x00004000
1958 #define BGE_MLC_MISCIO_OUT1 0x00008000
1959 #define BGE_MLC_MISCIO_OUT2 0x00010000
1960 #define BGE_MLC_EXTRAM_ENB 0x00020000
1961 #define BGE_MLC_SRAM_SIZE 0x001C0000
1962 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
1963 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
1964 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
1965 #define BGE_MLC_AUTO_EEPROM 0x01000000
1967 #define BGE_SSRAMSIZE_256KB 0x00000000
1968 #define BGE_SSRAMSIZE_512KB 0x00040000
1969 #define BGE_SSRAMSIZE_1MB 0x00080000
1970 #define BGE_SSRAMSIZE_2MB 0x000C0000
1971 #define BGE_SSRAMSIZE_4MB 0x00100000
1972 #define BGE_SSRAMSIZE_8MB 0x00140000
1973 #define BGE_SSRAMSIZE_16M 0x00180000
1975 /* EEPROM address register */
1976 #define BGE_EEADDR_ADDRESS 0x0000FFFC
1977 #define BGE_EEADDR_HALFCLK 0x01FF0000
1978 #define BGE_EEADDR_START 0x02000000
1979 #define BGE_EEADDR_DEVID 0x1C000000
1980 #define BGE_EEADDR_RESET 0x20000000
1981 #define BGE_EEADDR_DONE 0x40000000
1982 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
1984 #define BGE_EEDEVID(x) ((x & 7) << 26)
1985 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
1986 #define BGE_HALFCLK_384SCL 0x60
1987 #define BGE_EE_READCMD \
1988 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1989 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1990 #define BGE_EE_WRCMD \
1991 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1992 BGE_EEADDR_START|BGE_EEADDR_DONE)
1994 /* EEPROM Control register */
1995 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
1996 #define BGE_EECTL_CLKOUT 0x00000002
1997 #define BGE_EECTL_CLKIN 0x00000004
1998 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
1999 #define BGE_EECTL_DATAOUT 0x00000010
2000 #define BGE_EECTL_DATAIN 0x00000020
2002 /* MDI (MII/GMII) access register */
2003 #define BGE_MDI_DATA 0x00000001
2004 #define BGE_MDI_DIR 0x00000002
2005 #define BGE_MDI_SEL 0x00000004
2006 #define BGE_MDI_CLK 0x00000008
2008 #define BGE_MEMWIN_START 0x00008000
2009 #define BGE_MEMWIN_END 0x0000FFFF
2012 * PCI-E Core Private Register Access to TL, DL & PL
2014 #define BGE_PCIE_TLDLPL_PORT 0x7c00
2015 #define BGE_PCIE_PL_LO_PHYCTL5 0x7c14
2016 #define BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
2017 #define BGE_PCIE_DL_LO_FTSMAX 0x7c0c
2018 #define BGE_PCIE_DL_LO_FTSMAX_MASK 0x000000ff
2019 #define BGE_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
2022 * PCI-E transaction configure register.
2023 * Applies to BCM5906 and BCM5755+. See 5722-PG101-R.
2025 * Earlier PCI-E chips, e.g. 5750, call it TLP workaround,
2026 * and there are no interesting bits in it.
2028 #define BGE_PCIE_TRANSACT 0x7c04
2029 #define BGE_PCIE_TRANSACT_ONESHOT_MSI 0x20000000
2031 /* PCI-E PHY test control register */
2032 #define BGE_PCIE_PHY_TSTCTL 0x7e2c
2033 #define BGE_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
2034 #define BGE_PCIE_PHY_TSTCTL_PCIE10 0x00000040
2036 #define PCI_SETBIT(dev, reg, x, s) \
2037 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s)
2038 #define PCI_CLRBIT(dev, reg, x, s) \
2039 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s)
2042 * This magic number is written to the firmware mailbox at 0xb50
2043 * before a software reset is issued. After the internal firmware
2044 * has completed its initialization it will write the opposite of
2045 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
2046 * driver to synchronize with the firmware.
2048 #define BGE_MAGIC_NUMBER 0x4B657654
2051 uint32_t bge_addr_hi;
2052 uint32_t bge_addr_lo;
2055 #define BGE_HOSTADDR(x, y) \
2057 (x).bge_addr_lo = ((uint64_t)(y) & 0xffffffff); \
2058 (x).bge_addr_hi = ((uint64_t)(y) >> 32); \
2061 #define BGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF)
2062 #define BGE_ADDR_HI(y) ((uint64_t)(y) >> 32)
2064 /* Ring control block structure */
2066 bge_hostaddr bge_hostaddr;
2067 uint32_t bge_maxlen_flags;
2068 uint32_t bge_nicaddr;
2070 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
2072 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
2073 #define BGE_RCB_FLAG_RING_DISABLED 0x0002
2076 bge_hostaddr bge_addr;
2077 #if BYTE_ORDER == LITTLE_ENDIAN
2080 uint16_t bge_vlan_tag;
2086 uint16_t bge_vlan_tag;
2090 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
2091 #define BGE_TXBDFLAG_IP_CSUM 0x0002
2092 #define BGE_TXBDFLAG_END 0x0004
2093 #define BGE_TXBDFLAG_IP_FRAG 0x0008
2094 #define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */
2095 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010
2096 #define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */
2097 #define BGE_TXBDFLAG_VLAN_TAG 0x0040
2098 #define BGE_TXBDFLAG_COAL_NOW 0x0080
2099 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
2100 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
2101 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
2102 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
2103 #define BGE_TXBDFLAG_NO_CRC 0x8000
2105 #define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */
2106 /* Bits [1:0] of the MSS header length. */
2107 #define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */
2109 #define BGE_NIC_TXRING_ADDR(ringno, size) \
2110 BGE_SEND_RING_1_TO_4 + \
2111 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
2114 bge_hostaddr bge_addr;
2115 #if BYTE_ORDER == LITTLE_ENDIAN
2120 uint16_t bge_tcp_udp_csum;
2121 uint16_t bge_ip_csum;
2122 uint16_t bge_vlan_tag;
2123 uint16_t bge_error_flag;
2129 uint16_t bge_ip_csum;
2130 uint16_t bge_tcp_udp_csum;
2131 uint16_t bge_error_flag;
2132 uint16_t bge_vlan_tag;
2135 uint32_t bge_opaque;
2138 #define BGE_RXBDFLAG_END 0x0004
2139 #define BGE_RXBDFLAG_JUMBO_RING 0x0020
2140 #define BGE_RXBDFLAG_VLAN_TAG 0x0040
2141 #define BGE_RXBDFLAG_ERROR 0x0400
2142 #define BGE_RXBDFLAG_MINI_RING 0x0800
2143 #define BGE_RXBDFLAG_IP_CSUM 0x1000
2144 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
2145 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
2146 #define BGE_RXBDFLAG_IPV6 0x8000
2148 #define BGE_RXERRFLAG_BAD_CRC 0x0001
2149 #define BGE_RXERRFLAG_COLL_DETECT 0x0002
2150 #define BGE_RXERRFLAG_LINK_LOST 0x0004
2151 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
2152 #define BGE_RXERRFLAG_MAC_ABORT 0x0010
2153 #define BGE_RXERRFLAG_RUNT 0x0020
2154 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
2155 #define BGE_RXERRFLAG_GIANT 0x0080
2156 #define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */
2158 struct bge_sts_idx {
2159 #if BYTE_ORDER == LITTLE_ENDIAN
2160 uint16_t bge_rx_prod_idx;
2161 uint16_t bge_tx_cons_idx;
2163 uint16_t bge_tx_cons_idx;
2164 uint16_t bge_rx_prod_idx;
2168 struct bge_status_block {
2169 uint32_t bge_status;
2170 uint32_t bge_status_tag;
2171 #if BYTE_ORDER == LITTLE_ENDIAN
2172 uint16_t bge_rx_jumbo_cons_idx;
2173 uint16_t bge_rx_std_cons_idx;
2174 uint16_t bge_rx_mini_cons_idx;
2177 uint16_t bge_rx_std_cons_idx;
2178 uint16_t bge_rx_jumbo_cons_idx;
2180 uint16_t bge_rx_mini_cons_idx;
2182 struct bge_sts_idx bge_idx[16];
2184 #define BGE_STATUS_BLK_SZ sizeof(struct bge_status_block)
2186 #define BGE_STATFLAG_UPDATED 0x00000001
2187 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
2188 #define BGE_STATFLAG_ERROR 0x00000004
2191 * Offset of MAC address inside EEPROM.
2193 #define BGE_EE_MAC_OFFSET 0x7C
2194 #define BGE_EE_MAC_OFFSET_5906 0x10
2195 #define BGE_EE_HWCFG_OFFSET 0xC8
2196 #define BGE_EE_MAC_OFFSET_5717 0xCC
2197 #define BGE_EE_MAC_OFFSET_5717_OFF 0x18C
2199 #define BGE_HWCFG_VOLTAGE 0x00000003
2200 #define BGE_HWCFG_PHYLED_MODE 0x0000000C
2201 #define BGE_HWCFG_MEDIA 0x00000030
2203 #define BGE_VOLTAGE_1POINT3 0x00000000
2204 #define BGE_VOLTAGE_1POINT8 0x00000001
2206 #define BGE_PHYLEDMODE_UNSPEC 0x00000000
2207 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2208 #define BGE_PHYLEDMODE_SINGLELED 0x00000008
2210 #define BGE_MEDIA_UNSPEC 0x00000000
2211 #define BGE_MEDIA_COPPER 0x00000010
2212 #define BGE_MEDIA_FIBER 0x00000020
2214 #define BGE_PCI_READ_CMD 0x06000000
2215 #define BGE_PCI_WRITE_CMD 0x70000000
2217 #define BGE_TICKS_PER_SEC 1000000
2220 * Ring size constants.
2222 #define BGE_EVENT_RING_CNT 256
2223 #define BGE_CMD_RING_CNT 64
2224 #define BGE_STD_RX_RING_CNT 512
2225 #define BGE_JUMBO_RX_RING_CNT 256
2226 #define BGE_MINI_RX_RING_CNT 1024
2227 #define BGE_RETURN_RING_CNT 1024
2229 /* 5705 has smaller return ring size */
2231 #define BGE_RETURN_RING_CNT_5705 512
2234 * Possible TX ring sizes.
2236 #define BGE_TX_RING_CNT_128 128
2237 #define BGE_TX_RING_BASE_128 0x3800
2239 #define BGE_TX_RING_CNT_256 256
2240 #define BGE_TX_RING_BASE_256 0x3000
2242 #define BGE_TX_RING_CNT_512 512
2243 #define BGE_TX_RING_BASE_512 0x2000
2245 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2246 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2249 * Tigon III statistics counters.
2251 /* Statistics maintained MAC Receive block. */
2252 struct bge_rx_mac_stats {
2253 bge_hostaddr ifHCInOctets;
2254 bge_hostaddr Reserved1;
2255 bge_hostaddr etherStatsFragments;
2256 bge_hostaddr ifHCInUcastPkts;
2257 bge_hostaddr ifHCInMulticastPkts;
2258 bge_hostaddr ifHCInBroadcastPkts;
2259 bge_hostaddr dot3StatsFCSErrors;
2260 bge_hostaddr dot3StatsAlignmentErrors;
2261 bge_hostaddr xonPauseFramesReceived;
2262 bge_hostaddr xoffPauseFramesReceived;
2263 bge_hostaddr macControlFramesReceived;
2264 bge_hostaddr xoffStateEntered;
2265 bge_hostaddr dot3StatsFramesTooLong;
2266 bge_hostaddr etherStatsJabbers;
2267 bge_hostaddr etherStatsUndersizePkts;
2268 bge_hostaddr inRangeLengthError;
2269 bge_hostaddr outRangeLengthError;
2270 bge_hostaddr etherStatsPkts64Octets;
2271 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2272 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2273 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2274 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2275 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2276 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2277 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2278 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2279 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
2283 /* Statistics maintained MAC Transmit block. */
2284 struct bge_tx_mac_stats {
2285 bge_hostaddr ifHCOutOctets;
2286 bge_hostaddr Reserved2;
2287 bge_hostaddr etherStatsCollisions;
2288 bge_hostaddr outXonSent;
2289 bge_hostaddr outXoffSent;
2290 bge_hostaddr flowControlDone;
2291 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2292 bge_hostaddr dot3StatsSingleCollisionFrames;
2293 bge_hostaddr dot3StatsMultipleCollisionFrames;
2294 bge_hostaddr dot3StatsDeferredTransmissions;
2295 bge_hostaddr Reserved3;
2296 bge_hostaddr dot3StatsExcessiveCollisions;
2297 bge_hostaddr dot3StatsLateCollisions;
2298 bge_hostaddr dot3Collided2Times;
2299 bge_hostaddr dot3Collided3Times;
2300 bge_hostaddr dot3Collided4Times;
2301 bge_hostaddr dot3Collided5Times;
2302 bge_hostaddr dot3Collided6Times;
2303 bge_hostaddr dot3Collided7Times;
2304 bge_hostaddr dot3Collided8Times;
2305 bge_hostaddr dot3Collided9Times;
2306 bge_hostaddr dot3Collided10Times;
2307 bge_hostaddr dot3Collided11Times;
2308 bge_hostaddr dot3Collided12Times;
2309 bge_hostaddr dot3Collided13Times;
2310 bge_hostaddr dot3Collided14Times;
2311 bge_hostaddr dot3Collided15Times;
2312 bge_hostaddr ifHCOutUcastPkts;
2313 bge_hostaddr ifHCOutMulticastPkts;
2314 bge_hostaddr ifHCOutBroadcastPkts;
2315 bge_hostaddr dot3StatsCarrierSenseErrors;
2316 bge_hostaddr ifOutDiscards;
2317 bge_hostaddr ifOutErrors;
2320 /* Stats counters access through registers */
2321 struct bge_mac_stats_regs {
2322 uint32_t ifHCOutOctets;
2324 uint32_t etherStatsCollisions;
2325 uint32_t outXonSent;
2326 uint32_t outXoffSent;
2328 uint32_t dot3StatsInternalMacTransmitErrors;
2329 uint32_t dot3StatsSingleCollisionFrames;
2330 uint32_t dot3StatsMultipleCollisionFrames;
2331 uint32_t dot3StatsDeferredTransmissions;
2333 uint32_t dot3StatsExcessiveCollisions;
2334 uint32_t dot3StatsLateCollisions;
2335 uint32_t Reserved3[14];
2336 uint32_t ifHCOutUcastPkts;
2337 uint32_t ifHCOutMulticastPkts;
2338 uint32_t ifHCOutBroadcastPkts;
2339 uint32_t Reserved4[2];
2340 uint32_t ifHCInOctets;
2342 uint32_t etherStatsFragments;
2343 uint32_t ifHCInUcastPkts;
2344 uint32_t ifHCInMulticastPkts;
2345 uint32_t ifHCInBroadcastPkts;
2346 uint32_t dot3StatsFCSErrors;
2347 uint32_t dot3StatsAlignmentErrors;
2348 uint32_t xonPauseFramesReceived;
2349 uint32_t xoffPauseFramesReceived;
2350 uint32_t macControlFramesReceived;
2351 uint32_t xoffStateEntered;
2352 uint32_t dot3StatsFramesTooLong;
2353 uint32_t etherStatsJabbers;
2354 uint32_t etherStatsUndersizePkts;
2358 uint8_t Reserved0[256];
2360 /* Statistics maintained by Receive MAC. */
2361 struct bge_rx_mac_stats rxstats;
2363 bge_hostaddr Unused1[37];
2365 /* Statistics maintained by Transmit MAC. */
2366 struct bge_tx_mac_stats txstats;
2368 bge_hostaddr Unused2[31];
2370 /* Statistics maintained by Receive List Placement. */
2371 bge_hostaddr COSIfHCInPkts[16];
2372 bge_hostaddr COSFramesDroppedDueToFilters;
2373 bge_hostaddr nicDmaWriteQueueFull;
2374 bge_hostaddr nicDmaWriteHighPriQueueFull;
2375 bge_hostaddr nicNoMoreRxBDs;
2376 bge_hostaddr ifInDiscards;
2377 bge_hostaddr ifInErrors;
2378 bge_hostaddr nicRecvThresholdHit;
2380 bge_hostaddr Unused3[9];
2382 /* Statistics maintained by Send Data Initiator. */
2383 bge_hostaddr COSIfHCOutPkts[16];
2384 bge_hostaddr nicDmaReadQueueFull;
2385 bge_hostaddr nicDmaReadHighPriQueueFull;
2386 bge_hostaddr nicSendDataCompQueueFull;
2388 /* Statistics maintained by Host Coalescing. */
2389 bge_hostaddr nicRingSetSendProdIndex;
2390 bge_hostaddr nicRingStatusUpdate;
2391 bge_hostaddr nicInterrupts;
2392 bge_hostaddr nicAvoidedInterrupts;
2393 bge_hostaddr nicSendThresholdHit;
2395 uint8_t Reserved4[320];
2397 #define BGE_STATS_SZ sizeof(struct bge_stats)
2399 #if (BUS_SPACE_MAXADDR != BUS_SPACE_MAXADDR_32BIT)
2400 #define BGE_DMA_MAXADDR_40BIT 0xFFFFFFFFFF
2401 #define BGE_DMA_BOUNDARY_4G 0x100000000ULL
2403 #define BGE_DMA_MAXADDR_40BIT BUS_SPACE_MAXADDR
2404 #define BGE_DMA_BOUNDARY_4G 0
2407 #define BGE_STD_RX_RING_SZ \
2408 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2409 #define BGE_JUMBO_RX_RING_SZ \
2410 (sizeof(struct bge_rx_bd) * BGE_JUMBO_RX_RING_CNT)
2411 #define BGE_TX_RING_SZ \
2412 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2413 #define BGE_RX_RTN_RING_SZ(cnt) \
2414 (sizeof(struct bge_rx_bd) * (cnt))
2416 #endif /* !_IF_BGEREG_H_ */