2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.43 2005/12/31 14:08:01 sephe Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
102 #include "opt_polling.h"
104 #include <sys/param.h>
105 #include <sys/systm.h>
106 #include <sys/sockio.h>
107 #include <sys/endian.h>
108 #include <sys/mbuf.h>
109 #include <sys/kernel.h>
110 #include <sys/socket.h>
111 #include <sys/serialize.h>
112 #include <sys/thread2.h>
115 #include <net/ifq_var.h>
116 #include <net/if_arp.h>
117 #include <net/ethernet.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/vlan/if_vlan_var.h>
124 #include <machine/bus_memio.h>
125 #include <machine/bus_pio.h>
126 #include <machine/bus.h>
127 #include <machine/resource.h>
129 #include <sys/rman.h>
131 #include "../mii_layer/mii.h"
132 #include "../mii_layer/miivar.h"
134 #include <bus/pci/pcireg.h>
135 #include <bus/pci/pcivar.h>
137 /* "controller miibus0" required. See GENERIC if you get errors here. */
138 #include "miibus_if.h"
140 #include "if_xlreg.h"
142 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
145 * Various supported device vendors/types and their names.
147 static struct xl_type xl_devs[] = {
148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
149 "3Com 3c900-TPO Etherlink XL" },
150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
151 "3Com 3c900-COMBO Etherlink XL" },
152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
153 "3Com 3c905-TX Fast Etherlink XL" },
154 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
155 "3Com 3c905-T4 Fast Etherlink XL" },
156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
157 "3Com 3c900B-TPO Etherlink XL" },
158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
159 "3Com 3c900B-COMBO Etherlink XL" },
160 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
161 "3Com 3c900B-TPC Etherlink XL" },
162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
163 "3Com 3c900B-FL Etherlink XL" },
164 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
165 "3Com 3c905B-TX Fast Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
167 "3Com 3c905B-T4 Fast Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
169 "3Com 3c905B-FX/SC Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
171 "3Com 3c905B-COMBO Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
173 "3Com 3c905C-TX Fast Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
175 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
177 "3Com 3c980 Fast Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
179 "3Com 3c980C Fast Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
181 "3Com 3cSOHO100-TX OfficeConnect" },
182 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
183 "3Com 3c450-TX HomeConnect" },
184 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
185 "3Com 3c555 Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
187 "3Com 3c556 Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
189 "3Com 3c556B Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
191 "3Com 3c575TX Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
193 "3Com 3c575B Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
195 "3Com 3c575C Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
197 "3Com 3c656 Fast Etherlink XL" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
199 "3Com 3c656B Fast Etherlink XL" },
200 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
201 "3Com 3c656C Fast Etherlink XL" },
205 static int xl_probe (device_t);
206 static int xl_attach (device_t);
207 static int xl_detach (device_t);
209 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
210 static void xl_stats_update (void *);
211 static void xl_stats_update_serialized(void *);
212 static int xl_encap (struct xl_softc *, struct xl_chain *,
214 static void xl_rxeof (struct xl_softc *, int);
215 static int xl_rx_resync (struct xl_softc *);
216 static void xl_txeof (struct xl_softc *);
217 static void xl_txeof_90xB (struct xl_softc *);
218 static void xl_txeoc (struct xl_softc *);
219 static void xl_intr (void *);
220 static void xl_start_body (struct ifnet *, int);
221 static void xl_start (struct ifnet *);
222 static void xl_start_90xB (struct ifnet *);
223 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
225 static void xl_init (void *);
226 static void xl_stop (struct xl_softc *);
227 static void xl_watchdog (struct ifnet *);
228 static void xl_shutdown (device_t);
229 static int xl_suspend (device_t);
230 static int xl_resume (device_t);
231 #ifdef DEVICE_POLLING
232 static void xl_poll (struct ifnet *, enum poll_cmd, int);
234 static void xl_enable_intrs (struct xl_softc *, uint16_t);
236 static int xl_ifmedia_upd (struct ifnet *);
237 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
239 static int xl_eeprom_wait (struct xl_softc *);
240 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
241 static void xl_mii_sync (struct xl_softc *);
242 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
243 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
244 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
246 static void xl_setcfg (struct xl_softc *);
247 static void xl_setmode (struct xl_softc *, int);
248 static void xl_setmulti (struct xl_softc *);
249 static void xl_setmulti_hash (struct xl_softc *);
250 static void xl_reset (struct xl_softc *);
251 static int xl_list_rx_init (struct xl_softc *);
252 static void xl_list_tx_init (struct xl_softc *);
253 static void xl_list_tx_init_90xB(struct xl_softc *);
254 static void xl_wait (struct xl_softc *);
255 static void xl_mediacheck (struct xl_softc *);
256 static void xl_choose_xcvr (struct xl_softc *, int);
257 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
258 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
260 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
263 static int xl_dma_alloc (device_t);
264 static void xl_dma_free (device_t);
267 static void xl_testpacket (struct xl_softc *);
270 static int xl_miibus_readreg (device_t, int, int);
271 static int xl_miibus_writereg (device_t, int, int, int);
272 static void xl_miibus_statchg (device_t);
273 static void xl_miibus_mediainit (device_t);
275 static device_method_t xl_methods[] = {
276 /* Device interface */
277 DEVMETHOD(device_probe, xl_probe),
278 DEVMETHOD(device_attach, xl_attach),
279 DEVMETHOD(device_detach, xl_detach),
280 DEVMETHOD(device_shutdown, xl_shutdown),
281 DEVMETHOD(device_suspend, xl_suspend),
282 DEVMETHOD(device_resume, xl_resume),
285 DEVMETHOD(bus_print_child, bus_generic_print_child),
286 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
289 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
290 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
291 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
292 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
297 static driver_t xl_driver = {
300 sizeof(struct xl_softc)
303 static devclass_t xl_devclass;
305 DECLARE_DUMMY_MODULE(if_xl);
306 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
307 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
308 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
309 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
312 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs)
314 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF);
315 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs);
316 if (sc->xl_flags & XL_FLAG_FUNCREG)
317 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
321 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
326 *paddr = segs->ds_addr;
330 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
331 bus_size_t mapsize, int error)
337 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
339 *paddr = segs->ds_addr;
343 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
344 bus_size_t mapsize, int error)
352 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
356 for (i = 0; i < nseg; i++) {
357 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
358 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
359 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
360 total_len += segs[i].ds_len;
362 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
364 l->xl_status = htole32(total_len);
369 * Murphy's law says that it's possible the chip can wedge and
370 * the 'command in progress' bit may never clear. Hence, we wait
371 * only a finite amount of time to avoid getting caught in an
372 * infinite loop. Normally this delay routine would be a macro,
373 * but it isn't called during normal operation so we can afford
374 * to make it a function.
377 xl_wait(struct xl_softc *sc)
381 for (i = 0; i < XL_TIMEOUT; i++) {
382 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
387 if_printf(&sc->arpcom.ac_if, "command never completed!");
393 * MII access routines are provided for adapters with external
394 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
395 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
396 * Note: if you don't perform the MDIO operations just right,
397 * it's possible to end up with code that works correctly with
398 * some chips/CPUs/processor speeds/bus speeds/etc but not
402 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
403 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
407 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
410 * Sync the PHYs by setting data bit and strobing the clock 32 times.
413 xl_mii_sync(struct xl_softc *sc)
418 MII_SET(XL_MII_DIR|XL_MII_DATA);
420 for (i = 0; i < 32; i++) {
422 MII_SET(XL_MII_DATA);
423 MII_SET(XL_MII_DATA);
425 MII_SET(XL_MII_DATA);
426 MII_SET(XL_MII_DATA);
433 * Clock a series of bits through the MII.
436 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
443 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
445 MII_SET(XL_MII_DATA);
447 MII_CLR(XL_MII_DATA);
455 * Read an PHY register through the MII.
458 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
463 * Set up frame for RX.
465 frame->mii_stdelim = XL_MII_STARTDELIM;
466 frame->mii_opcode = XL_MII_READOP;
467 frame->mii_turnaround = 0;
471 * Select register window 4.
476 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
485 * Send command/address info.
487 xl_mii_send(sc, frame->mii_stdelim, 2);
488 xl_mii_send(sc, frame->mii_opcode, 2);
489 xl_mii_send(sc, frame->mii_phyaddr, 5);
490 xl_mii_send(sc, frame->mii_regaddr, 5);
493 MII_CLR((XL_MII_CLK|XL_MII_DATA));
501 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
505 * Now try reading data bits. If the ack failed, we still
506 * need to clock through 16 cycles to keep the PHY(s) in sync.
509 for(i = 0; i < 16; i++) {
516 for (i = 0x8000; i; i >>= 1) {
519 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
520 frame->mii_data |= i;
536 * Write to a PHY register through the MII.
539 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
542 * Set up frame for TX.
545 frame->mii_stdelim = XL_MII_STARTDELIM;
546 frame->mii_opcode = XL_MII_WRITEOP;
547 frame->mii_turnaround = XL_MII_TURNAROUND;
550 * Select the window 4.
555 * Turn on data output.
561 xl_mii_send(sc, frame->mii_stdelim, 2);
562 xl_mii_send(sc, frame->mii_opcode, 2);
563 xl_mii_send(sc, frame->mii_phyaddr, 5);
564 xl_mii_send(sc, frame->mii_regaddr, 5);
565 xl_mii_send(sc, frame->mii_turnaround, 2);
566 xl_mii_send(sc, frame->mii_data, 16);
581 xl_miibus_readreg(device_t dev, int phy, int reg)
584 struct xl_mii_frame frame;
586 sc = device_get_softc(dev);
589 * Pretend that PHYs are only available at MII address 24.
590 * This is to guard against problems with certain 3Com ASIC
591 * revisions that incorrectly map the internal transceiver
592 * control registers at all MII addresses. This can cause
593 * the miibus code to attach the same PHY several times over.
595 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
598 bzero((char *)&frame, sizeof(frame));
600 frame.mii_phyaddr = phy;
601 frame.mii_regaddr = reg;
602 xl_mii_readreg(sc, &frame);
604 return(frame.mii_data);
608 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
611 struct xl_mii_frame frame;
613 sc = device_get_softc(dev);
615 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
618 bzero((char *)&frame, sizeof(frame));
620 frame.mii_phyaddr = phy;
621 frame.mii_regaddr = reg;
622 frame.mii_data = data;
624 xl_mii_writereg(sc, &frame);
630 xl_miibus_statchg(device_t dev)
633 struct mii_data *mii;
636 sc = device_get_softc(dev);
637 mii = device_get_softc(sc->xl_miibus);
641 /* Set ASIC's duplex mode to match the PHY. */
643 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
644 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
646 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
647 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
653 * Special support for the 3c905B-COMBO. This card has 10/100 support
654 * plus BNC and AUI ports. This means we will have both an miibus attached
655 * plus some non-MII media settings. In order to allow this, we have to
656 * add the extra media to the miibus's ifmedia struct, but we can't do
657 * that during xl_attach() because the miibus hasn't been attached yet.
658 * So instead, we wait until the miibus probe/attach is done, at which
659 * point we will get a callback telling is that it's safe to add our
663 xl_miibus_mediainit(device_t dev)
666 struct mii_data *mii;
669 sc = device_get_softc(dev);
670 mii = device_get_softc(sc->xl_miibus);
671 ifm = &mii->mii_media;
673 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
675 * Check for a 10baseFL board in disguise.
677 if (sc->xl_type == XL_TYPE_905B &&
678 sc->xl_media == XL_MEDIAOPT_10FL) {
680 device_printf(dev, "found 10baseFL\n");
681 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
682 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
683 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
685 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
688 device_printf(dev, "found AUI\n");
689 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
693 if (sc->xl_media & XL_MEDIAOPT_BNC) {
695 device_printf(dev, "found BNC\n");
696 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
703 * The EEPROM is slow: give it time to come ready after issuing
707 xl_eeprom_wait(struct xl_softc *sc)
711 for (i = 0; i < 100; i++) {
712 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
719 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
727 * Read a sequence of words from the EEPROM. Note that ethernet address
728 * data is stored in the EEPROM in network byte order.
731 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
734 u_int16_t word = 0, *ptr;
735 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
736 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
738 * It's easy to accidentally overwrite the rom content!
739 * Note: the 3c575 uses 8bit EEPROM offsets.
743 if (xl_eeprom_wait(sc))
746 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
749 for (i = 0; i < cnt; i++) {
750 if (sc->xl_flags & XL_FLAG_8BITROM)
751 CSR_WRITE_2(sc, XL_W0_EE_CMD,
752 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
754 CSR_WRITE_2(sc, XL_W0_EE_CMD,
755 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
756 err = xl_eeprom_wait(sc);
759 word = CSR_READ_2(sc, XL_W0_EE_DATA);
760 ptr = (u_int16_t *)(dest + (i * 2));
771 * NICs older than the 3c905B have only one multicast option, which
772 * is to enable reception of all multicast frames.
775 xl_setmulti(struct xl_softc *sc)
778 struct ifmultiaddr *ifma;
782 ifp = &sc->arpcom.ac_if;
785 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
787 if (ifp->if_flags & IFF_ALLMULTI) {
788 rxfilt |= XL_RXFILTER_ALLMULTI;
789 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
793 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
797 rxfilt |= XL_RXFILTER_ALLMULTI;
799 rxfilt &= ~XL_RXFILTER_ALLMULTI;
801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
807 * 3c905B adapters have a hash filter that we can program.
810 xl_setmulti_hash(struct xl_softc *sc)
814 struct ifmultiaddr *ifma;
818 ifp = &sc->arpcom.ac_if;
821 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
823 if (ifp->if_flags & IFF_ALLMULTI) {
824 rxfilt |= XL_RXFILTER_ALLMULTI;
825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
828 rxfilt &= ~XL_RXFILTER_ALLMULTI;
831 /* first, zot all the existing hash bits */
832 for (i = 0; i < XL_HASHFILT_SIZE; i++)
833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
835 /* now program new ones */
836 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
837 if (ifma->ifma_addr->sa_family != AF_LINK)
841 * Note: the 3c905B currently only supports a 64-bit
842 * hash table, which means we really only need 6 bits,
843 * but the manual indicates that future chip revisions
844 * will have a 256-bit hash table, hence the routine is
845 * set up to calculate 8 bits of position info in case
846 * we need it some day.
847 * Note II, The Sequel: _CURRENT_ versions of the 3c905B
848 * have a 256 bit hash table. This means we have to use
849 * all 8 bits regardless. On older cards, the upper 2
850 * bits will be ignored. Grrrr....
853 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
854 ETHER_ADDR_LEN) & 0xff;
855 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
860 rxfilt |= XL_RXFILTER_MULTIHASH;
862 rxfilt &= ~XL_RXFILTER_MULTIHASH;
864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
871 xl_testpacket(struct xl_softc *sc)
876 ifp = &sc->arpcom.ac_if;
878 MGETHDR(m, MB_DONTWAIT, MT_DATA);
883 bcopy(&sc->arpcom.ac_enaddr,
884 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
885 bcopy(&sc->arpcom.ac_enaddr,
886 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
887 mtod(m, struct ether_header *)->ether_type = htons(3);
888 mtod(m, unsigned char *)[14] = 0;
889 mtod(m, unsigned char *)[15] = 0;
890 mtod(m, unsigned char *)[16] = 0xE3;
891 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
892 IF_ENQUEUE(&ifp->if_snd, m);
900 xl_setcfg(struct xl_softc *sc)
905 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
906 icfg &= ~XL_ICFG_CONNECTOR_MASK;
907 if (sc->xl_media & XL_MEDIAOPT_MII ||
908 sc->xl_media & XL_MEDIAOPT_BT4)
909 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
910 if (sc->xl_media & XL_MEDIAOPT_BTX)
911 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
913 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
920 xl_setmode(struct xl_softc *sc, int media)
922 struct ifnet *ifp = &sc->arpcom.ac_if;
926 if_printf(ifp, "selecting ");
929 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
931 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
933 if (sc->xl_media & XL_MEDIAOPT_BT) {
934 if (IFM_SUBTYPE(media) == IFM_10_T) {
935 printf("10baseT transceiver, ");
936 sc->xl_xcvr = XL_XCVR_10BT;
937 icfg &= ~XL_ICFG_CONNECTOR_MASK;
938 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
939 mediastat |= XL_MEDIASTAT_LINKBEAT|
940 XL_MEDIASTAT_JABGUARD;
941 mediastat &= ~XL_MEDIASTAT_SQEENB;
945 if (sc->xl_media & XL_MEDIAOPT_BFX) {
946 if (IFM_SUBTYPE(media) == IFM_100_FX) {
947 printf("100baseFX port, ");
948 sc->xl_xcvr = XL_XCVR_100BFX;
949 icfg &= ~XL_ICFG_CONNECTOR_MASK;
950 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
951 mediastat |= XL_MEDIASTAT_LINKBEAT;
952 mediastat &= ~XL_MEDIASTAT_SQEENB;
956 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
957 if (IFM_SUBTYPE(media) == IFM_10_5) {
958 printf("AUI port, ");
959 sc->xl_xcvr = XL_XCVR_AUI;
960 icfg &= ~XL_ICFG_CONNECTOR_MASK;
961 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
962 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
963 XL_MEDIASTAT_JABGUARD);
964 mediastat |= ~XL_MEDIASTAT_SQEENB;
966 if (IFM_SUBTYPE(media) == IFM_10_FL) {
967 printf("10baseFL transceiver, ");
968 sc->xl_xcvr = XL_XCVR_AUI;
969 icfg &= ~XL_ICFG_CONNECTOR_MASK;
970 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
971 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
972 XL_MEDIASTAT_JABGUARD);
973 mediastat |= ~XL_MEDIASTAT_SQEENB;
977 if (sc->xl_media & XL_MEDIAOPT_BNC) {
978 if (IFM_SUBTYPE(media) == IFM_10_2) {
979 printf("BNC port, ");
980 sc->xl_xcvr = XL_XCVR_COAX;
981 icfg &= ~XL_ICFG_CONNECTOR_MASK;
982 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
983 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
984 XL_MEDIASTAT_JABGUARD|
985 XL_MEDIASTAT_SQEENB);
989 if ((media & IFM_GMASK) == IFM_FDX ||
990 IFM_SUBTYPE(media) == IFM_100_FX) {
991 printf("full duplex\n");
993 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
995 printf("half duplex\n");
997 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
998 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1001 if (IFM_SUBTYPE(media) == IFM_10_2)
1002 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1004 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1005 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1007 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1013 xl_reset(struct xl_softc *sc)
1018 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1019 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1020 XL_RESETOPT_DISADVFD:0));
1023 * If we're using memory mapped register mode, pause briefly
1024 * after issuing the reset command before trying to access any
1025 * other registers. With my 3c575C cardbus card, failing to do
1026 * this results in the system locking up while trying to poll
1027 * the command busy bit in the status register.
1029 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1032 for (i = 0; i < XL_TIMEOUT; i++) {
1034 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1038 if (i == XL_TIMEOUT)
1039 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
1041 /* Reset TX and RX. */
1042 /* Note: the RX reset takes an absurd amount of time
1043 * on newer versions of the Tornado chips such as those
1044 * on the 3c905CX and newer 3c908C cards. We wait an
1045 * extra amount of time so that xl_wait() doesn't complain
1046 * and annoy the users.
1048 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1051 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1054 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1055 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1057 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1058 XL_W2_RESET_OPTIONS)
1059 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1060 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1064 /* Wait a little while for the chip to get its brains in order. */
1070 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1071 * IDs against our list and return a device name if we find a match.
1074 xl_probe(device_t dev)
1079 vid = pci_get_vendor(dev);
1080 did = pci_get_device(dev);
1081 for (t = xl_devs; t->xl_name != NULL; t++) {
1082 if (vid == t->xl_vid && did == t->xl_did) {
1083 device_set_desc(dev, t->xl_name);
1091 * This routine is a kludge to work around possible hardware faults
1092 * or manufacturing defects that can cause the media options register
1093 * (or reset options register, as it's called for the first generation
1094 * 3c90x adapters) to return an incorrect result. I have encountered
1095 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1096 * which doesn't have any of the 'mediaopt' bits set. This screws up
1097 * the attach routine pretty badly because it doesn't know what media
1098 * to look for. If we find ourselves in this predicament, this routine
1099 * will try to guess the media options values and warn the user of a
1100 * possible manufacturing defect with his adapter/system/whatever.
1103 xl_mediacheck(struct xl_softc *sc)
1105 struct ifnet *ifp = &sc->arpcom.ac_if;
1108 * If some of the media options bits are set, assume they are
1109 * correct. If not, try to figure it out down below.
1110 * XXX I should check for 10baseFL, but I don't have an adapter
1113 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1115 * Check the XCVR value. If it's not in the normal range
1116 * of values, we need to fake it up here.
1118 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1121 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1124 "choosing new default based on card type\n");
1127 if (sc->xl_type == XL_TYPE_905B &&
1128 sc->xl_media & XL_MEDIAOPT_10FL)
1130 if_printf(ifp, "WARNING: no media options bits set in "
1131 "the media options register!!\n");
1132 if_printf(ifp, "this could be a manufacturing defect in "
1133 "your adapter or system\n");
1134 if_printf(ifp, "attempting to guess media type; you "
1135 "should probably consult your vendor\n");
1138 xl_choose_xcvr(sc, 1);
1142 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1144 struct ifnet *ifp = &sc->arpcom.ac_if;
1148 * Read the device ID from the EEPROM.
1149 * This is what's loaded into the PCI device ID register, so it has
1150 * to be correct otherwise we wouldn't have gotten this far.
1152 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1155 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1156 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1157 sc->xl_media = XL_MEDIAOPT_BT;
1158 sc->xl_xcvr = XL_XCVR_10BT;
1160 if_printf(ifp, "guessing 10BaseT transceiver\n");
1162 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1163 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1164 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1165 sc->xl_xcvr = XL_XCVR_10BT;
1167 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1169 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1170 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1171 sc->xl_xcvr = XL_XCVR_10BT;
1173 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1175 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1176 sc->xl_media = XL_MEDIAOPT_10FL;
1177 sc->xl_xcvr = XL_XCVR_AUI;
1179 if_printf(ifp, "guessing 10baseFL\n");
1181 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1182 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1183 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1184 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1185 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1186 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1187 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1188 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1189 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1190 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1191 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1192 sc->xl_media = XL_MEDIAOPT_MII;
1193 sc->xl_xcvr = XL_XCVR_MII;
1195 if_printf(ifp, "guessing MII\n");
1197 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1198 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1199 sc->xl_media = XL_MEDIAOPT_BT4;
1200 sc->xl_xcvr = XL_XCVR_MII;
1202 if_printf(ifp, "guessing 100BaseT4/MII\n");
1204 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1205 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1206 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1207 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1208 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1209 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1210 sc->xl_media = XL_MEDIAOPT_BTX;
1211 sc->xl_xcvr = XL_XCVR_AUTO;
1213 if_printf(ifp, "guessing 10/100 internal\n");
1215 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1216 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1217 sc->xl_xcvr = XL_XCVR_AUTO;
1219 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1223 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1224 sc->xl_media = XL_MEDIAOPT_BT;
1232 * Attach the interface. Allocate softc structures, do ifmedia
1233 * setup and ethernet/BPF attach.
1236 xl_attach(device_t dev)
1238 u_char eaddr[ETHER_ADDR_LEN];
1240 struct xl_softc *sc;
1242 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1243 int error = 0, rid, res;
1245 sc = device_get_softc(dev);
1247 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1250 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555)
1251 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1252 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1253 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1254 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1255 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1256 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1257 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 ||
1258 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1259 sc->xl_flags |= XL_FLAG_8BITROM;
1260 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1261 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1262 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1263 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1264 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1265 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1266 sc->xl_flags |= XL_FLAG_FUNCREG;
1267 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1268 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1269 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1270 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1271 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1272 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1274 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1275 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1276 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1277 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1278 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1279 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1280 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1281 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1282 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1283 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1284 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1285 XL_FLAG_INVERT_LED_PWR;
1286 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B)
1287 sc->xl_flags |= XL_FLAG_PHYOK;
1288 #ifndef BURN_BRIDGES
1290 * If this is a 3c905B, we have to check one extra thing.
1291 * The 905B supports power management and may be placed in
1292 * a low-power mode (D3 mode), typically by certain operating
1293 * systems which shall not be named. The PCI BIOS is supposed
1294 * to reset the NIC and bring it out of low-power mode, but
1295 * some do not. Consequently, we have to see if this chip
1296 * supports power management, and if so, make sure it's not
1297 * in low-power mode. If power management is available, the
1298 * capid byte will be 0x01.
1300 * I _think_ that what actually happens is that the chip
1301 * loses its PCI configuration during the transition from
1302 * D3 back to D0; this means that it should be possible for
1303 * us to save the PCI iobase, membase and IRQ, put the chip
1304 * back in the D0 state, then restore the PCI config ourselves.
1307 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1308 u_int32_t iobase, membase, irq;
1310 /* Save important PCI config data. */
1311 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1312 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1313 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1315 /* Reset the power state. */
1316 device_printf(dev, "chip is in D%d power mode "
1317 "-- setting to D0\n", pci_get_powerstate(dev));
1319 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1321 /* Restore PCI config data. */
1322 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1323 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1324 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1328 * Map control/status registers.
1330 pci_enable_busmaster(dev);
1333 res = SYS_RES_MEMORY;
1336 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1339 if (sc->xl_res != NULL) {
1340 sc->xl_flags |= XL_FLAG_USE_MMIO;
1342 device_printf(dev, "using memory mapped I/O\n");
1345 res = SYS_RES_IOPORT;
1346 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1347 if (sc->xl_res == NULL) {
1348 device_printf(dev, "couldn't map ports/memory\n");
1353 device_printf(dev, "using port I/O\n");
1356 sc->xl_btag = rman_get_bustag(sc->xl_res);
1357 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1359 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1360 rid = XL_PCI_FUNCMEM;
1361 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1364 if (sc->xl_fres == NULL) {
1365 device_printf(dev, "couldn't map funcreg memory\n");
1370 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1371 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1374 /* Allocate interrupt */
1376 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1377 RF_SHAREABLE | RF_ACTIVE);
1378 if (sc->xl_irq == NULL) {
1379 device_printf(dev, "couldn't map interrupt\n");
1384 ifp = &sc->arpcom.ac_if;
1385 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1387 /* Reset the adapter. */
1391 * Get station address from the EEPROM.
1393 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1394 device_printf(dev, "failed to read station address\n");
1399 callout_init(&sc->xl_stat_timer);
1401 error = xl_dma_alloc(dev);
1406 * Figure out the card type. 3c905B adapters have the
1407 * 'supportsNoTxLength' bit set in the capabilities
1408 * word in the EEPROM.
1409 * Note: my 3c575C cardbus card lies. It returns a value
1410 * of 0x1578 for its capabilities word, which is somewhat
1411 * nonsensical. Another way to distinguish a 3c90x chip
1412 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1413 * bit. This will only be set for 3c90x boomerage chips.
1415 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1416 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1417 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1418 sc->xl_type = XL_TYPE_905B;
1420 sc->xl_type = XL_TYPE_90X;
1422 device_printf(dev, "type %s\n",
1423 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X");
1427 ifp->if_mtu = ETHERMTU;
1428 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1429 ifp->if_ioctl = xl_ioctl;
1430 ifp->if_capabilities = 0;
1431 if (sc->xl_type == XL_TYPE_905B) {
1432 ifp->if_start = xl_start_90xB;
1433 ifp->if_capabilities |= IFCAP_HWCSUM;
1435 ifp->if_start = xl_start;
1437 ifp->if_watchdog = xl_watchdog;
1438 ifp->if_init = xl_init;
1439 #ifdef DEVICE_POLLING
1440 ifp->if_poll = xl_poll;
1442 ifp->if_baudrate = 10000000;
1443 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1444 ifq_set_ready(&ifp->if_snd);
1446 * NOTE: features disabled by default. This seems to corrupt
1447 * tx packet data one out of a million packets or so and then
1448 * generates a good checksum so the receiver doesn't
1449 * know the packet is bad
1451 ifp->if_capenable = 0; /*ifp->if_capabilities;*/
1452 if (ifp->if_capenable & IFCAP_TXCSUM)
1453 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1456 * Now we have to see what sort of media we have.
1457 * This includes probing for an MII interace and a
1461 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1463 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1465 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1466 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1467 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1468 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1472 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1473 || sc->xl_media & XL_MEDIAOPT_BT4) {
1475 if_printf(ifp, "found MII/AUTO\n");
1478 error = mii_phy_probe(dev, &sc->xl_miibus,
1479 xl_ifmedia_upd, xl_ifmedia_sts);
1481 if_printf(ifp, "no PHY found!\n");
1489 * Sanity check. If the user has selected "auto" and this isn't
1490 * a 10/100 card of some kind, we need to force the transceiver
1491 * type to something sane.
1493 if (sc->xl_xcvr == XL_XCVR_AUTO)
1494 xl_choose_xcvr(sc, bootverbose);
1499 if (sc->xl_media & XL_MEDIAOPT_BT) {
1501 if_printf(ifp, "found 10baseT\n");
1502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1503 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1504 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1505 ifmedia_add(&sc->ifmedia,
1506 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1509 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1511 * Check for a 10baseFL board in disguise.
1513 if (sc->xl_type == XL_TYPE_905B &&
1514 sc->xl_media == XL_MEDIAOPT_10FL) {
1516 if_printf(ifp, "found 10baseFL\n");
1517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1518 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1520 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1521 ifmedia_add(&sc->ifmedia,
1522 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1525 if_printf(ifp, "found AUI\n");
1526 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1530 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1532 if_printf(ifp, "found BNC\n");
1533 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1536 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1538 if_printf(ifp, "found 100baseFX\n");
1539 ifp->if_baudrate = 100000000;
1540 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1543 /* Choose a default media. */
1544 switch(sc->xl_xcvr) {
1546 media = IFM_ETHER|IFM_10_T;
1547 xl_setmode(sc, media);
1550 if (sc->xl_type == XL_TYPE_905B &&
1551 sc->xl_media == XL_MEDIAOPT_10FL) {
1552 media = IFM_ETHER|IFM_10_FL;
1553 xl_setmode(sc, media);
1555 media = IFM_ETHER|IFM_10_5;
1556 xl_setmode(sc, media);
1560 media = IFM_ETHER|IFM_10_2;
1561 xl_setmode(sc, media);
1564 case XL_XCVR_100BTX:
1566 /* Chosen by miibus */
1568 case XL_XCVR_100BFX:
1569 media = IFM_ETHER|IFM_100_FX;
1572 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1574 * This will probably be wrong, but it prevents
1575 * the ifmedia code from panicking.
1577 media = IFM_ETHER|IFM_10_T;
1581 if (sc->xl_miibus == NULL)
1582 ifmedia_set(&sc->ifmedia, media);
1586 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1588 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1592 * Call MI attach routine.
1594 ether_ifattach(ifp, eaddr, NULL);
1597 * Tell the upper layer(s) we support long frames.
1599 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1601 /* Hook interrupt last to avoid having to lock softc */
1602 error = bus_setup_intr(dev, sc->xl_irq, INTR_NETSAFE,
1603 xl_intr, sc, &sc->xl_intrhand,
1604 ifp->if_serializer);
1606 if_printf(ifp, "couldn't set up irq\n");
1607 ether_ifdetach(ifp);
1619 * Shutdown hardware and free up resources. This can be called any
1620 * time after the mutex has been initialized. It is called in both
1621 * the error case in attach and the normal detach case so it needs
1622 * to be careful about only freeing resources that have actually been
1626 xl_detach(device_t dev)
1628 struct xl_softc *sc;
1632 sc = device_get_softc(dev);
1633 ifp = &sc->arpcom.ac_if;
1635 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1637 res = SYS_RES_MEMORY;
1640 res = SYS_RES_IOPORT;
1643 if (device_is_attached(dev)) {
1644 lwkt_serialize_enter(ifp->if_serializer);
1647 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1648 lwkt_serialize_exit(ifp->if_serializer);
1650 ether_ifdetach(ifp);
1654 device_delete_child(dev, sc->xl_miibus);
1655 bus_generic_detach(dev);
1656 ifmedia_removeall(&sc->ifmedia);
1659 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1660 if (sc->xl_fres != NULL)
1661 bus_release_resource(dev, SYS_RES_MEMORY,
1662 XL_PCI_FUNCMEM, sc->xl_fres);
1664 bus_release_resource(dev, res, rid, sc->xl_res);
1672 xl_dma_alloc(device_t dev)
1674 struct xl_softc *sc;
1675 struct xl_chain_data *cd;
1676 struct xl_list_data *ld;
1679 sc = device_get_softc(dev);
1684 * Now allocate a tag for the DMA descriptor lists and a chunk
1685 * of DMA-able memory based on the tag. Also obtain the DMA
1686 * addresses of the RX and TX ring, which we'll need later.
1687 * All of our lists are allocated as a contiguous block
1690 error = bus_dma_tag_create(NULL, 8, 0,
1691 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1693 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ,
1696 device_printf(dev, "failed to allocate rx dma tag\n");
1700 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list,
1701 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1704 device_printf(dev, "no memory for rx list buffers!\n");
1705 bus_dma_tag_destroy(ld->xl_rx_tag);
1706 ld->xl_rx_tag = NULL;
1710 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap,
1711 ld->xl_rx_list, XL_RX_LIST_SZ,
1712 xl_dma_map_addr, &ld->xl_rx_dmaaddr,
1715 device_printf(dev, "cannot get dma address of the rx ring!\n");
1716 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1718 bus_dma_tag_destroy(ld->xl_rx_tag);
1719 ld->xl_rx_tag = NULL;
1723 error = bus_dma_tag_create(NULL, 8, 0,
1724 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1726 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ,
1729 device_printf(dev, "failed to allocate tx dma tag\n");
1733 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list,
1734 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1737 device_printf(dev, "no memory for list buffers!\n");
1738 bus_dma_tag_destroy(ld->xl_tx_tag);
1739 ld->xl_tx_tag = NULL;
1743 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap,
1744 ld->xl_tx_list, XL_TX_LIST_SZ,
1745 xl_dma_map_addr, &ld->xl_tx_dmaaddr,
1748 device_printf(dev, "cannot get dma address of the tx ring!\n");
1749 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1751 bus_dma_tag_destroy(ld->xl_tx_tag);
1752 ld->xl_tx_tag = NULL;
1757 * Allocate a DMA tag for the mapping of mbufs.
1759 error = bus_dma_tag_create(NULL, 1, 0,
1760 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1762 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS,
1763 MCLBYTES, 0, &sc->xl_mtag);
1765 device_printf(dev, "failed to allocate mbuf dma tag\n");
1770 * Allocate a spare DMA map for the RX ring.
1772 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1774 device_printf(dev, "failed to create mbuf dma map\n");
1775 bus_dma_tag_destroy(sc->xl_mtag);
1780 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1781 error = bus_dmamap_create(sc->xl_mtag, 0,
1782 &cd->xl_rx_chain[i].xl_map);
1784 device_printf(dev, "failed to create %dth "
1785 "rx descriptor dma map!\n", i);
1788 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1791 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1792 error = bus_dmamap_create(sc->xl_mtag, 0,
1793 &cd->xl_tx_chain[i].xl_map);
1795 device_printf(dev, "failed to create %dth "
1796 "tx descriptor dma map!\n", i);
1799 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1805 xl_dma_free(device_t dev)
1807 struct xl_softc *sc;
1808 struct xl_chain_data *cd;
1809 struct xl_list_data *ld;
1812 sc = device_get_softc(dev);
1816 for (i = 0; i < XL_RX_LIST_CNT; ++i) {
1817 if (cd->xl_rx_chain[i].xl_ptr != NULL) {
1818 if (cd->xl_rx_chain[i].xl_mbuf != NULL) {
1819 bus_dmamap_unload(sc->xl_mtag,
1820 cd->xl_rx_chain[i].xl_map);
1821 m_free(cd->xl_rx_chain[i].xl_mbuf);
1823 bus_dmamap_destroy(sc->xl_mtag,
1824 cd->xl_rx_chain[i].xl_map);
1828 for (i = 0; i < XL_TX_LIST_CNT; ++i) {
1829 if (cd->xl_tx_chain[i].xl_ptr != NULL) {
1830 if (cd->xl_tx_chain[i].xl_mbuf != NULL) {
1831 bus_dmamap_unload(sc->xl_mtag,
1832 cd->xl_tx_chain[i].xl_map);
1833 m_free(cd->xl_tx_chain[i].xl_mbuf);
1835 bus_dmamap_destroy(sc->xl_mtag,
1836 cd->xl_tx_chain[i].xl_map);
1840 if (ld->xl_rx_tag) {
1841 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap);
1842 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1844 bus_dma_tag_destroy(ld->xl_rx_tag);
1847 if (ld->xl_tx_tag) {
1848 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap);
1849 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1851 bus_dma_tag_destroy(ld->xl_tx_tag);
1855 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1856 bus_dma_tag_destroy(sc->xl_mtag);
1861 * Initialize the transmit descriptors.
1864 xl_list_tx_init(struct xl_softc *sc)
1866 struct xl_chain_data *cd;
1867 struct xl_list_data *ld;
1872 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1873 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1874 i * sizeof(struct xl_list);
1875 if (i == (XL_TX_LIST_CNT - 1))
1876 cd->xl_tx_chain[i].xl_next = NULL;
1878 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1881 cd->xl_tx_free = &cd->xl_tx_chain[0];
1882 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1884 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1888 * Initialize the transmit descriptors.
1891 xl_list_tx_init_90xB(struct xl_softc *sc)
1893 struct xl_chain_data *cd;
1894 struct xl_list_data *ld;
1899 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1900 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1901 i * sizeof(struct xl_list);
1902 if (i == (XL_TX_LIST_CNT - 1))
1903 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1905 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1907 cd->xl_tx_chain[i].xl_prev =
1908 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1910 cd->xl_tx_chain[i].xl_prev =
1911 &cd->xl_tx_chain[i - 1];
1915 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1921 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1925 * Initialize the RX descriptors and allocate mbufs for them. Note that
1926 * we arrange the descriptors in a closed ring, so that the last descriptor
1927 * points back to the first.
1930 xl_list_rx_init(struct xl_softc *sc)
1932 struct xl_chain_data *cd;
1933 struct xl_list_data *ld;
1940 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1941 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1944 if (i == (XL_RX_LIST_CNT - 1))
1948 nextptr = ld->xl_rx_dmaaddr +
1949 next * sizeof(struct xl_list_onefrag);
1950 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1951 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1954 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1955 cd->xl_rx_head = &cd->xl_rx_chain[0];
1961 * Initialize an RX descriptor and attach an MBUF cluster.
1962 * If we fail to do so, we need to leave the old mbuf and
1963 * the old DMA map untouched so that it can be reused.
1966 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1973 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1977 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1979 /* Force longword alignment for packet payload. */
1980 m_adj(m_new, ETHER_ALIGN);
1982 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1983 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1986 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n",
1991 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1993 c->xl_map = sc->xl_tmpmap;
1994 sc->xl_tmpmap = map;
1996 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1997 c->xl_ptr->xl_status = 0;
1998 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
1999 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
2004 xl_rx_resync(struct xl_softc *sc)
2006 struct xl_chain_onefrag *pos;
2009 pos = sc->xl_cdata.xl_rx_head;
2011 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2012 if (pos->xl_ptr->xl_status)
2017 if (i == XL_RX_LIST_CNT)
2020 sc->xl_cdata.xl_rx_head = pos;
2026 * A frame has been uploaded: pass the resulting mbuf chain up to
2027 * the higher level protocols.
2030 xl_rxeof(struct xl_softc *sc, int count)
2034 struct xl_chain_onefrag *cur_rx;
2038 ifp = &sc->arpcom.ac_if;
2042 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2043 BUS_DMASYNC_POSTREAD);
2044 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2045 #ifdef DEVICE_POLLING
2046 if (count >= 0 && count-- == 0)
2049 cur_rx = sc->xl_cdata.xl_rx_head;
2050 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2051 total_len = rxstat & XL_RXSTAT_LENMASK;
2054 * Since we have told the chip to allow large frames,
2055 * we need to trap giant frame errors in software. We allow
2056 * a little more than the normal frame size to account for
2057 * frames with VLAN tags.
2059 if (total_len > XL_MAX_FRAMELEN)
2060 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2063 * If an error occurs, update stats, clear the
2064 * status word and leave the mbuf cluster in place:
2065 * it should simply get re-used next time this descriptor
2066 * comes up in the ring.
2068 if (rxstat & XL_RXSTAT_UP_ERROR) {
2070 cur_rx->xl_ptr->xl_status = 0;
2071 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2072 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2077 * If the error bit was not set, the upload complete
2078 * bit should be set which means we have a valid packet.
2079 * If not, something truly strange has happened.
2081 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2083 "bad receive status -- packet dropped\n");
2085 cur_rx->xl_ptr->xl_status = 0;
2086 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2087 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2091 /* No errors; receive the packet. */
2092 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2093 BUS_DMASYNC_POSTREAD);
2094 m = cur_rx->xl_mbuf;
2097 * Try to conjure up a new mbuf cluster. If that
2098 * fails, it means we have an out of memory condition and
2099 * should leave the buffer in place and continue. This will
2100 * result in a lost packet, but there's little else we
2101 * can do in this situation.
2103 if (xl_newbuf(sc, cur_rx)) {
2105 cur_rx->xl_ptr->xl_status = 0;
2106 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2107 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2110 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2111 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2114 m->m_pkthdr.rcvif = ifp;
2115 m->m_pkthdr.len = m->m_len = total_len;
2117 if (ifp->if_capenable & IFCAP_RXCSUM) {
2118 /* Do IP checksum checking. */
2119 if (rxstat & XL_RXSTAT_IPCKOK)
2120 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2121 if (!(rxstat & XL_RXSTAT_IPCKERR))
2122 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2123 if ((rxstat & XL_RXSTAT_TCPCOK &&
2124 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2125 (rxstat & XL_RXSTAT_UDPCKOK &&
2126 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2127 m->m_pkthdr.csum_flags |=
2128 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2129 m->m_pkthdr.csum_data = 0xffff;
2133 ifp->if_input(ifp, m);
2136 if (sc->xl_type != XL_TYPE_905B) {
2138 * Handle the 'end of channel' condition. When the upload
2139 * engine hits the end of the RX ring, it will stall. This
2140 * is our cue to flush the RX ring, reload the uplist pointer
2141 * register and unstall the engine.
2142 * XXX This is actually a little goofy. With the ThunderLAN
2143 * chip, you get an interrupt when the receiver hits the end
2144 * of the receive ring, which tells you exactly when you
2145 * you need to reload the ring pointer. Here we have to
2146 * fake it. I'm mad at myself for not being clever enough
2147 * to avoid the use of a goto here.
2149 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2150 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2153 CSR_WRITE_4(sc, XL_UPLIST_PTR,
2154 sc->xl_ldata.xl_rx_dmaaddr);
2155 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2163 * A frame was downloaded to the chip. It's safe for us to clean up
2167 xl_txeof(struct xl_softc *sc)
2169 struct xl_chain *cur_tx;
2172 ifp = &sc->arpcom.ac_if;
2174 /* Clear the timeout timer. */
2178 * Go through our tx list and free mbufs for those
2179 * frames that have been uploaded. Note: the 3c905B
2180 * sets a special bit in the status word to let us
2181 * know that a frame has been downloaded, but the
2182 * original 3c900/3c905 adapters don't do that.
2183 * Consequently, we have to use a different test if
2184 * xl_type != XL_TYPE_905B.
2186 while(sc->xl_cdata.xl_tx_head != NULL) {
2187 cur_tx = sc->xl_cdata.xl_tx_head;
2189 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2192 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2193 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2194 BUS_DMASYNC_POSTWRITE);
2195 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2196 m_freem(cur_tx->xl_mbuf);
2197 cur_tx->xl_mbuf = NULL;
2200 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2201 sc->xl_cdata.xl_tx_free = cur_tx;
2204 if (sc->xl_cdata.xl_tx_head == NULL) {
2205 ifp->if_flags &= ~IFF_OACTIVE;
2206 sc->xl_cdata.xl_tx_tail = NULL;
2208 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2209 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2210 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2211 sc->xl_cdata.xl_tx_head->xl_phys);
2212 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2220 xl_txeof_90xB(struct xl_softc *sc)
2222 struct xl_chain *cur_tx = NULL;
2226 ifp = &sc->arpcom.ac_if;
2228 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2229 BUS_DMASYNC_POSTREAD);
2230 idx = sc->xl_cdata.xl_tx_cons;
2231 while(idx != sc->xl_cdata.xl_tx_prod) {
2233 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2235 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2236 XL_TXSTAT_DL_COMPLETE))
2239 if (cur_tx->xl_mbuf != NULL) {
2240 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2241 BUS_DMASYNC_POSTWRITE);
2242 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2243 m_freem(cur_tx->xl_mbuf);
2244 cur_tx->xl_mbuf = NULL;
2249 sc->xl_cdata.xl_tx_cnt--;
2250 XL_INC(idx, XL_TX_LIST_CNT);
2254 sc->xl_cdata.xl_tx_cons = idx;
2257 ifp->if_flags &= ~IFF_OACTIVE;
2263 * TX 'end of channel' interrupt handler. Actually, we should
2264 * only get a 'TX complete' interrupt if there's a transmit error,
2265 * so this is really TX error handler.
2268 xl_txeoc(struct xl_softc *sc)
2270 struct ifnet *ifp = &sc->arpcom.ac_if;
2273 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2274 if (txstat & XL_TXSTATUS_UNDERRUN ||
2275 txstat & XL_TXSTATUS_JABBER ||
2276 txstat & XL_TXSTATUS_RECLAIM) {
2277 if_printf(ifp, "transmission error: %x\n", txstat);
2278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2280 if (sc->xl_type == XL_TYPE_905B) {
2281 if (sc->xl_cdata.xl_tx_cnt) {
2284 i = sc->xl_cdata.xl_tx_cons;
2285 c = &sc->xl_cdata.xl_tx_chain[i];
2286 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2288 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2291 if (sc->xl_cdata.xl_tx_head != NULL)
2292 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2293 sc->xl_cdata.xl_tx_head->xl_phys);
2296 * Remember to set this for the
2297 * first generation 3c90X chips.
2299 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2300 if (txstat & XL_TXSTATUS_UNDERRUN &&
2301 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2302 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2303 if_printf(ifp, "tx underrun, increasing tx start"
2304 " threshold to %d bytes\n",
2307 CSR_WRITE_2(sc, XL_COMMAND,
2308 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2309 if (sc->xl_type == XL_TYPE_905B) {
2310 CSR_WRITE_2(sc, XL_COMMAND,
2311 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2313 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2314 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2316 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2317 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2320 * Write an arbitrary byte to the TX_STATUS register
2321 * to clear this interrupt/error and advance to the next.
2323 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2329 #ifdef DEVICE_POLLING
2332 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2334 struct xl_softc *sc = ifp->if_softc;
2338 xl_enable_intrs(sc, 0);
2340 case POLL_DEREGISTER:
2341 xl_enable_intrs(sc, XL_INTRS);
2344 case POLL_AND_CHECK_STATUS:
2345 xl_rxeof(sc, count);
2346 if (sc->xl_type == XL_TYPE_905B)
2351 if (!ifq_is_empty(&ifp->if_snd)) {
2352 if (sc->xl_type == XL_TYPE_905B)
2355 xl_start_body(ifp, 0);
2358 if (cmd == POLL_AND_CHECK_STATUS) {
2361 /* XXX copy & pasted from xl_intr() */
2362 status = CSR_READ_2(sc, XL_STATUS);
2363 if ((status & XL_INTRS) && status != 0xFFFF) {
2364 CSR_WRITE_2(sc, XL_COMMAND,
2365 XL_CMD_INTR_ACK | (status & XL_INTRS));
2367 if (status & XL_STAT_TX_COMPLETE) {
2372 if (status & XL_STAT_ADFAIL) {
2377 if (status & XL_STAT_STATSOFLOW) {
2378 sc->xl_stats_no_timeout = 1;
2379 xl_stats_update_serialized(sc);
2380 sc->xl_stats_no_timeout = 0;
2388 #endif /* DEVICE_POLLING */
2393 struct xl_softc *sc;
2398 ifp = &sc->arpcom.ac_if;
2400 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) &&
2403 CSR_WRITE_2(sc, XL_COMMAND,
2404 XL_CMD_INTR_ACK|(status & XL_INTRS));
2406 if (status & XL_STAT_UP_COMPLETE) {
2409 curpkts = ifp->if_ipackets;
2411 if (curpkts == ifp->if_ipackets) {
2412 while (xl_rx_resync(sc))
2417 if (status & XL_STAT_DOWN_COMPLETE) {
2418 if (sc->xl_type == XL_TYPE_905B)
2424 if (status & XL_STAT_TX_COMPLETE) {
2429 if (status & XL_STAT_ADFAIL) {
2434 if (status & XL_STAT_STATSOFLOW) {
2435 sc->xl_stats_no_timeout = 1;
2436 xl_stats_update_serialized(sc);
2437 sc->xl_stats_no_timeout = 0;
2441 if (!ifq_is_empty(&ifp->if_snd))
2442 (*ifp->if_start)(ifp);
2448 xl_stats_update(void *xsc)
2450 struct xl_softc *sc = xsc;
2452 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2453 xl_stats_update_serialized(xsc);
2454 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2458 xl_stats_update_serialized(void *xsc)
2460 struct xl_softc *sc;
2462 struct xl_stats xl_stats;
2465 struct mii_data *mii = NULL;
2467 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2470 ifp = &sc->arpcom.ac_if;
2471 if (sc->xl_miibus != NULL)
2472 mii = device_get_softc(sc->xl_miibus);
2474 p = (u_int8_t *)&xl_stats;
2476 /* Read all the stats registers. */
2479 for (i = 0; i < 16; i++)
2480 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2482 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2484 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2485 xl_stats.xl_tx_single_collision +
2486 xl_stats.xl_tx_late_collision;
2489 * Boomerang and cyclone chips have an extra stats counter
2490 * in window 4 (BadSSD). We have to read this too in order
2491 * to clear out all the stats registers and avoid a statsoflow
2495 CSR_READ_1(sc, XL_W4_BADSSD);
2497 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2502 if (!sc->xl_stats_no_timeout)
2503 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2509 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2510 * pointers to the fragment pointers.
2513 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2519 ifp = &sc->arpcom.ac_if;
2522 * Start packing the mbufs in this chain into
2523 * the fragment pointers. Stop when we run out
2524 * of fragments or hit the end of the mbuf chain.
2526 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2527 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2529 if (error && error != EFBIG) {
2531 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2536 * Handle special case: we used up all 63 fragments,
2537 * but we have more mbufs left in the chain. Copy the
2538 * data into an mbuf cluster. Note that we don't
2539 * bother clearing the values in the other fragment
2540 * pointers/counters; it wouldn't gain us anything,
2541 * and would waste cycles.
2546 m_new = m_defrag(m_head, MB_DONTWAIT);
2547 if (m_new == NULL) {
2554 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2555 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2558 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2563 if (sc->xl_type == XL_TYPE_905B) {
2564 status = XL_TXSTAT_RND_DEFEAT;
2566 if (m_head->m_pkthdr.csum_flags) {
2567 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2568 status |= XL_TXSTAT_IPCKSUM;
2569 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2570 status |= XL_TXSTAT_TCPCKSUM;
2571 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2572 status |= XL_TXSTAT_UDPCKSUM;
2574 c->xl_ptr->xl_status = htole32(status);
2577 c->xl_mbuf = m_head;
2578 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2583 xl_start(struct ifnet *ifp)
2585 xl_start_body(ifp, 1);
2589 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2590 * to the mbuf data regions directly in the transmit lists. We also save a
2591 * copy of the pointers since the transmit list fragment pointers are
2592 * physical addresses.
2595 xl_start_body(struct ifnet *ifp, int proc_rx)
2597 struct xl_softc *sc;
2598 struct mbuf *m_head = NULL;
2599 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2600 struct xl_chain *prev_tx;
2606 * Check for an available queue slot. If there are none,
2609 if (sc->xl_cdata.xl_tx_free == NULL) {
2612 if (sc->xl_cdata.xl_tx_free == NULL) {
2613 ifp->if_flags |= IFF_OACTIVE;
2618 start_tx = sc->xl_cdata.xl_tx_free;
2620 while(sc->xl_cdata.xl_tx_free != NULL) {
2621 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2625 /* Pick a descriptor off the free list. */
2627 cur_tx = sc->xl_cdata.xl_tx_free;
2629 /* Pack the data into the descriptor. */
2630 error = xl_encap(sc, cur_tx, m_head);
2636 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2637 cur_tx->xl_next = NULL;
2639 /* Chain it together. */
2641 prev->xl_next = cur_tx;
2642 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2646 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2650 * If there are no packets queued, bail.
2656 * Place the request for the upload interrupt
2657 * in the last descriptor in the chain. This way, if
2658 * we're chaining several packets at once, we'll only
2659 * get an interupt once for the whole chain rather than
2660 * once for each packet.
2662 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2666 * Queue the packets. If the TX channel is clear, update
2667 * the downlist pointer register.
2669 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2672 if (sc->xl_cdata.xl_tx_head != NULL) {
2673 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2674 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2675 htole32(start_tx->xl_phys);
2676 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2677 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2678 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2679 sc->xl_cdata.xl_tx_tail = cur_tx;
2681 sc->xl_cdata.xl_tx_head = start_tx;
2682 sc->xl_cdata.xl_tx_tail = cur_tx;
2684 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2685 BUS_DMASYNC_PREWRITE);
2687 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2688 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2690 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2695 * Set a timeout in case the chip goes out to lunch.
2701 * XXX Under certain conditions, usually on slower machines
2702 * where interrupts may be dropped, it's possible for the
2703 * adapter to chew up all the buffers in the receive ring
2704 * and stall, without us being able to do anything about it.
2705 * To guard against this, we need to make a pass over the
2706 * RX queue to make sure there aren't any packets pending.
2707 * Doing it here means we can flush the receive ring at the
2708 * same time the chip is DMAing the transmit descriptors we
2711 * 3Com goes to some lengths to emphasize the Parallel
2712 * Tasking (tm) nature of their chips in all their marketing
2713 * literature; we may as well take advantage of it. :)
2720 xl_start_90xB(struct ifnet *ifp)
2722 struct xl_softc *sc;
2723 struct mbuf *m_head = NULL;
2724 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2725 struct xl_chain *prev_tx;
2730 if (ifp->if_flags & IFF_OACTIVE)
2733 idx = sc->xl_cdata.xl_tx_prod;
2734 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2736 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2738 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2739 ifp->if_flags |= IFF_OACTIVE;
2743 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2748 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2750 /* Pack the data into the descriptor. */
2751 error = xl_encap(sc, cur_tx, m_head);
2757 /* Chain it together. */
2759 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2762 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2764 XL_INC(idx, XL_TX_LIST_CNT);
2765 sc->xl_cdata.xl_tx_cnt++;
2769 * If there are no packets queued, bail.
2775 * Place the request for the upload interrupt
2776 * in the last descriptor in the chain. This way, if
2777 * we're chaining several packets at once, we'll only
2778 * get an interupt once for the whole chain rather than
2779 * once for each packet.
2781 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2784 /* Start transmission */
2785 sc->xl_cdata.xl_tx_prod = idx;
2786 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2788 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2789 BUS_DMASYNC_PREWRITE);
2792 * Set a timeout in case the chip goes out to lunch.
2800 struct xl_softc *sc = xsc;
2801 struct ifnet *ifp = &sc->arpcom.ac_if;
2803 u_int16_t rxfilt = 0;
2804 struct mii_data *mii = NULL;
2807 * Cancel pending I/O and free all RX/TX buffers.
2811 if (sc->xl_miibus == NULL) {
2812 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2819 if (sc->xl_miibus != NULL)
2820 mii = device_get_softc(sc->xl_miibus);
2822 /* Init our MAC address */
2824 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2825 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2826 sc->arpcom.ac_enaddr[i]);
2829 /* Clear the station mask. */
2830 for (i = 0; i < 3; i++)
2831 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2833 /* Reset TX and RX. */
2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2836 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2839 /* Init circular RX list. */
2840 error = xl_list_rx_init(sc);
2842 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2848 /* Init TX descriptors. */
2849 if (sc->xl_type == XL_TYPE_905B)
2850 xl_list_tx_init_90xB(sc);
2852 xl_list_tx_init(sc);
2855 * Set the TX freethresh value.
2856 * Note that this has no effect on 3c905B "cyclone"
2857 * cards but is required for 3c900/3c905 "boomerang"
2858 * cards in order to enable the download engine.
2860 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2862 /* Set the TX start threshold for best performance. */
2863 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2867 * If this is a 3c905B, also set the tx reclaim threshold.
2868 * This helps cut down on the number of tx reclaim errors
2869 * that could happen on a busy network. The chip multiplies
2870 * the register value by 16 to obtain the actual threshold
2871 * in bytes, so we divide by 16 when setting the value here.
2872 * The existing threshold value can be examined by reading
2873 * the register at offset 9 in window 5.
2875 if (sc->xl_type == XL_TYPE_905B) {
2876 CSR_WRITE_2(sc, XL_COMMAND,
2877 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2880 /* Set RX filter bits. */
2882 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2884 /* Set the individual bit to receive frames for this host only. */
2885 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2887 /* If we want promiscuous mode, set the allframes bit. */
2888 if (ifp->if_flags & IFF_PROMISC) {
2889 rxfilt |= XL_RXFILTER_ALLFRAMES;
2890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2892 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2893 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2897 * Set capture broadcast bit to capture broadcast frames.
2899 if (ifp->if_flags & IFF_BROADCAST) {
2900 rxfilt |= XL_RXFILTER_BROADCAST;
2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2903 rxfilt &= ~XL_RXFILTER_BROADCAST;
2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2908 * Program the multicast filter, if necessary.
2910 if (sc->xl_type == XL_TYPE_905B)
2911 xl_setmulti_hash(sc);
2915 if (sc->xl_type == XL_TYPE_905B) {
2916 /* Set UP polling interval */
2917 CSR_WRITE_1(sc, XL_UP_POLL, 64);
2921 * Load the address of the RX list. We have to
2922 * stall the upload engine before we can manipulate
2923 * the uplist pointer register, then unstall it when
2924 * we're finished. We also have to wait for the
2925 * stall command to complete before proceeding.
2926 * Note that we have to do this after any RX resets
2927 * have completed since the uplist register is cleared
2930 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2932 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2936 if (sc->xl_type == XL_TYPE_905B) {
2937 /* Set DN polling interval */
2938 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2940 /* Load the address of the TX list */
2941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2943 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2944 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2950 * If the coax transceiver is on, make sure to enable
2951 * the DC-DC converter.
2954 if (sc->xl_xcvr == XL_XCVR_COAX)
2955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2960 * increase packet size to allow reception of 802.1q or ISL packets.
2961 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2962 * control register. For 3c90xB/C chips, use the RX packet size
2966 if (sc->xl_type == XL_TYPE_905B) {
2967 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2970 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2971 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2972 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2975 /* Clear out the stats counters. */
2976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2977 sc->xl_stats_no_timeout = 1;
2978 xl_stats_update_serialized(sc);
2979 sc->xl_stats_no_timeout = 0;
2981 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2982 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2985 * Enable interrupts.
2987 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
2988 #ifdef DEVICE_POLLING
2989 /* Do not enable interrupt if polling(4) is enabled */
2990 if ((ifp->if_flags & IFF_POLLING) != 0)
2991 xl_enable_intrs(sc, 0);
2994 xl_enable_intrs(sc, XL_INTRS);
2996 /* Set the RX early threshold */
2997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2998 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
3000 /* Enable receiver and transmitter. */
3001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
3003 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3009 /* Select window 7 for normal operations. */
3012 ifp->if_flags |= IFF_RUNNING;
3013 ifp->if_flags &= ~IFF_OACTIVE;
3015 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
3019 * Set media options.
3022 xl_ifmedia_upd(struct ifnet *ifp)
3024 struct xl_softc *sc;
3025 struct ifmedia *ifm = NULL;
3026 struct mii_data *mii = NULL;
3029 if (sc->xl_miibus != NULL)
3030 mii = device_get_softc(sc->xl_miibus);
3034 ifm = &mii->mii_media;
3036 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3041 xl_setmode(sc, ifm->ifm_media);
3048 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
3049 || sc->xl_media & XL_MEDIAOPT_BT4) {
3052 xl_setmode(sc, ifm->ifm_media);
3059 * Report current media status.
3062 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3064 struct xl_softc *sc;
3066 struct mii_data *mii = NULL;
3069 if (sc->xl_miibus != NULL)
3070 mii = device_get_softc(sc->xl_miibus);
3073 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3074 icfg >>= XL_ICFG_CONNECTOR_BITS;
3076 ifmr->ifm_active = IFM_ETHER;
3080 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3081 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3082 ifmr->ifm_active |= IFM_FDX;
3084 ifmr->ifm_active |= IFM_HDX;
3087 if (sc->xl_type == XL_TYPE_905B &&
3088 sc->xl_media == XL_MEDIAOPT_10FL) {
3089 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3090 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3091 ifmr->ifm_active |= IFM_FDX;
3093 ifmr->ifm_active |= IFM_HDX;
3095 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3098 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3101 * XXX MII and BTX/AUTO should be separate cases.
3104 case XL_XCVR_100BTX:
3109 ifmr->ifm_active = mii->mii_media_active;
3110 ifmr->ifm_status = mii->mii_media_status;
3113 case XL_XCVR_100BFX:
3114 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3117 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3125 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3127 struct xl_softc *sc = ifp->if_softc;
3128 struct ifreq *ifr = (struct ifreq *) data;
3130 struct mii_data *mii = NULL;
3136 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3137 if (ifp->if_flags & IFF_UP) {
3138 if (ifp->if_flags & IFF_RUNNING &&
3139 ifp->if_flags & IFF_PROMISC &&
3140 !(sc->xl_if_flags & IFF_PROMISC)) {
3141 rxfilt |= XL_RXFILTER_ALLFRAMES;
3142 CSR_WRITE_2(sc, XL_COMMAND,
3143 XL_CMD_RX_SET_FILT|rxfilt);
3145 } else if (ifp->if_flags & IFF_RUNNING &&
3146 !(ifp->if_flags & IFF_PROMISC) &&
3147 sc->xl_if_flags & IFF_PROMISC) {
3148 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3149 CSR_WRITE_2(sc, XL_COMMAND,
3150 XL_CMD_RX_SET_FILT|rxfilt);
3155 if (ifp->if_flags & IFF_RUNNING)
3158 sc->xl_if_flags = ifp->if_flags;
3163 if (sc->xl_type == XL_TYPE_905B)
3164 xl_setmulti_hash(sc);
3171 if (sc->xl_miibus != NULL)
3172 mii = device_get_softc(sc->xl_miibus);
3174 error = ifmedia_ioctl(ifp, ifr,
3175 &sc->ifmedia, command);
3177 error = ifmedia_ioctl(ifp, ifr,
3178 &mii->mii_media, command);
3181 ifp->if_capenable = ifr->ifr_reqcap;
3182 if (ifp->if_capenable & IFCAP_TXCSUM)
3183 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3185 ifp->if_hwassist = 0;
3188 error = ether_ioctl(ifp, command, data);
3195 xl_watchdog(struct ifnet *ifp)
3197 struct xl_softc *sc;
3198 u_int16_t status = 0;
3204 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3205 if_printf(ifp, "watchdog timeout\n");
3207 if (status & XL_MEDIASTAT_CARRIER)
3208 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3215 if (!ifq_is_empty(&ifp->if_snd))
3216 (*ifp->if_start)(ifp);
3220 * Stop the adapter and free any mbufs allocated to the
3224 xl_stop(struct xl_softc *sc)
3229 ifp = &sc->arpcom.ac_if;
3232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3233 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3234 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3235 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3237 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3238 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3242 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3248 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3249 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3250 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3251 if (sc->xl_flags & XL_FLAG_FUNCREG)
3252 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3254 /* Stop the stats updater. */
3255 callout_stop(&sc->xl_stat_timer);
3258 * Free data in the RX lists.
3260 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3261 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3262 bus_dmamap_unload(sc->xl_mtag,
3263 sc->xl_cdata.xl_rx_chain[i].xl_map);
3264 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3265 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3268 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3271 * Free the TX list buffers.
3273 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3274 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3275 bus_dmamap_unload(sc->xl_mtag,
3276 sc->xl_cdata.xl_tx_chain[i].xl_map);
3277 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3278 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3281 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3283 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3287 * Stop all chip I/O so that the kernel's probe routines don't
3288 * get confused by errant DMAs when rebooting.
3291 xl_shutdown(device_t dev)
3293 struct xl_softc *sc = device_get_softc(dev);
3295 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3298 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3302 xl_suspend(device_t dev)
3304 struct xl_softc *sc = device_get_softc(dev);
3306 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3308 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3314 xl_resume(device_t dev)
3316 struct xl_softc *sc;
3319 sc = device_get_softc(dev);
3320 ifp = &sc->arpcom.ac_if;
3322 lwkt_serialize_enter(ifp->if_serializer);
3324 if (ifp->if_flags & IFF_UP)
3326 lwkt_serialize_exit(ifp->if_serializer);