sys/dev/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <uapi_drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "atom.h"
  32
  33 static u8
  34 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  35 {
  36         u8 backlight_level;
  37         u32 bios_2_scratch;
  38
  39         if (rdev->family >= CHIP_R600)
  40                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  41         else
  42                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  43
  44         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  45                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  46
  47         return backlight_level;
  48 }
  49
  50 static void
  51 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  52                                        u8 backlight_level)
  53 {
  54         u32 bios_2_scratch;
  55
  56         if (rdev->family >= CHIP_R600)
  57                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  58         else
  59                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  60
  61         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  62         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  63                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  64
  65         if (rdev->family >= CHIP_R600)
  66                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  67         else
  68                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  69 }
  70
  71 u8
  72 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  73 {
  74         struct drm_device *dev = radeon_encoder->base.dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76
  77         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  78                 return 0;
  79
  80         return radeon_atom_get_backlight_level_from_reg(rdev);
  81 }
  82
  83 void
  84 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  85 {
  86         struct drm_encoder *encoder = &radeon_encoder->base;
  87         struct drm_device *dev = radeon_encoder->base.dev;
  88         struct radeon_device *rdev = dev->dev_private;
  89         struct radeon_encoder_atom_dig *dig;
  90         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  91         int index;
  92
  93         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  94                 return;
  95
  96         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  97             radeon_encoder->enc_priv) {
  98                 dig = radeon_encoder->enc_priv;
  99                 dig->backlight_level = level;
 100                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 101
 102                 switch (radeon_encoder->encoder_id) {
 103                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 104                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 105                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 106                         if (dig->backlight_level == 0) {
 107                                 args.ucAction = ATOM_LCD_BLOFF;
 108                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 109                         } else {
 110                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 111                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 112                                 args.ucAction = ATOM_LCD_BLON;
 113                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114                         }
 115                         break;
 116                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 117                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 118                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 120                         if (dig->backlight_level == 0)
 121                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 122                         else {
 123                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 124                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 125                         }
 126                         break;
 127                 default:
 128                         break;
 129                 }
 130         }
 131 }
 132
 133 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 134
 135 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 136 {
 137         u8 level;
 138
 139         /* Convert brightness to hardware level */
 140         if (bd->props.brightness < 0)
 141                 level = 0;
 142         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 143                 level = RADEON_MAX_BL_LEVEL;
 144         else
 145                 level = bd->props.brightness;
 146
 147         return level;
 148 }
 149
 150 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 151 {
 152         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 153         struct radeon_encoder *radeon_encoder = pdata->encoder;
 154
 155         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 156
 157         return 0;
 158 }
 159
 160 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 161 {
 162         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 163         struct radeon_encoder *radeon_encoder = pdata->encoder;
 164         struct drm_device *dev = radeon_encoder->base.dev;
 165         struct radeon_device *rdev = dev->dev_private;
 166
 167         return radeon_atom_get_backlight_level_from_reg(rdev);
 168 }
 169
 170 static const struct backlight_ops radeon_atom_backlight_ops = {
 171         .get_brightness = radeon_atom_backlight_get_brightness,
 172         .update_status  = radeon_atom_backlight_update_status,
 173 };
 174
 175 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 176                                 struct drm_connector *drm_connector)
 177 {
 178         struct drm_device *dev = radeon_encoder->base.dev;
 179         struct radeon_device *rdev = dev->dev_private;
 180         struct backlight_device *bd;
 181         struct backlight_properties props;
 182         struct radeon_backlight_privdata *pdata;
 183         struct radeon_encoder_atom_dig *dig;
 184         char bl_name[16];
 185
 186         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 187          * so don't register a backlight device
 188          */
 189         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 190             (rdev->pdev->device == 0x6741))
 191                 return;
 192
 193         if (!radeon_encoder->enc_priv)
 194                 return;
 195
 196         if (!rdev->is_atom_bios)
 197                 return;
 198
 199         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 200                 return;
 201
 202         pdata = kmalloc(sizeof(struct radeon_backlight_privdata),
 203                         M_DRM, M_WAITOK);
 204         if (!pdata) {
 205                 DRM_ERROR("Memory allocation failed\n");
 206                 goto error;
 207         }
 208
 209         memset(&props, 0, sizeof(props));
 210         props.max_brightness = RADEON_MAX_BL_LEVEL;
 211         props.type = BACKLIGHT_RAW;
 212         snprintf(bl_name, sizeof(bl_name),
 213                  "radeon_bl%d", dev->primary->index);
 214         bd = backlight_device_register(bl_name, drm_connector->kdev,
 215                                        pdata, &radeon_atom_backlight_ops, &props);
 216         if (IS_ERR(bd)) {
 217                 DRM_ERROR("Backlight registration failed\n");
 218                 goto error;
 219         }
 220
 221         pdata->encoder = radeon_encoder;
 222
 223         dig = radeon_encoder->enc_priv;
 224         dig->bl_dev = bd;
 225
 226         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 227         /* Set a reasonable default here if the level is 0 otherwise
 228          * fbdev will attempt to turn the backlight on after console
 229          * unblanking and it will try and restore 0 which turns the backlight
 230          * off again.
 231          */
 232         if (bd->props.brightness == 0)
 233                 bd->props.brightness = RADEON_MAX_BL_LEVEL;
 234         bd->props.power = FB_BLANK_UNBLANK;
 235         backlight_update_status(bd);
 236
 237         DRM_INFO("radeon atom DIG backlight initialized\n");
 238
 239         return;
 240
 241 error:
 242         kfree(pdata);
 243         return;
 244 }
 245
 246 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 247 {
 248         struct drm_device *dev = radeon_encoder->base.dev;
 249         struct radeon_device *rdev = dev->dev_private;
 250         struct backlight_device *bd = NULL;
 251         struct radeon_encoder_atom_dig *dig;
 252
 253         if (!radeon_encoder->enc_priv)
 254                 return;
 255
 256         if (!rdev->is_atom_bios)
 257                 return;
 258
 259         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 260                 return;
 261
 262         dig = radeon_encoder->enc_priv;
 263         bd = dig->bl_dev;
 264         dig->bl_dev = NULL;
 265
 266         if (bd) {
 267                 struct radeon_legacy_backlight_privdata *pdata;
 268
 269                 pdata = bl_get_data(bd);
 270                 backlight_device_unregister(bd);
 271                 kfree(pdata);
 272
 273                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 274         }
 275 }
 276
 277 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 278
 279 /*
 280  * Read max backlight level
 281  */
 282 static int
 283 sysctl_backlight_max(SYSCTL_HANDLER_ARGS)
 284 {
 285         int err, val;
 286
 287         val = RADEON_MAX_BL_LEVEL;
 288         err = sysctl_handle_int(oidp, &val, 0, req);
 289         return(err);
 290 }
 291
 292 /*
 293  * Read/write backlight level
 294  */
 295 static int
 296 sysctl_backlight_handler(SYSCTL_HANDLER_ARGS)
 297 {
 298         struct radeon_encoder *encoder;
 299         struct radeon_encoder_atom_dig *dig;
 300         int err, val;
 301
 302         encoder = (struct radeon_encoder *)arg1;
 303         dig = encoder->enc_priv;
 304         val = dig->backlight_level;
 305
 306         err = sysctl_handle_int(oidp, &val, 0, req);
 307         if (err != 0 || req->newptr == NULL) {
 308                 return(err);
 309         }
 310         if (dig->backlight_level != val && val >= 0 &&
 311             val <= RADEON_MAX_BL_LEVEL) {
 312                 atombios_set_backlight_level(encoder, val);
 313         }
 314
 315         return(err);
 316 }
 317
 318 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 319                                 struct drm_connector *drm_connector)
 320 {
 321         struct drm_device *dev = radeon_encoder->base.dev;
 322         struct radeon_device *rdev = dev->dev_private;
 323         struct radeon_encoder_atom_dig *dig;
 324
 325         if (!radeon_encoder->enc_priv)
 326                 return;
 327
 328         if (!rdev->is_atom_bios)
 329                 return;
 330
 331         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 332                 return;
 333
 334         dig = radeon_encoder->enc_priv;
 335         dig->backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
 336
 337         DRM_INFO("radeon atom DIG backlight initialized\n");
 338
 339         SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children,
 340                         OID_AUTO, "backlight_max",
 341                         CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_ANYBODY,
 342                         radeon_encoder, sizeof(int),
 343                         sysctl_backlight_max,
 344                         "I", "Max backlight level");
 345         SYSCTL_ADD_PROC(&drm_connector->dev->sysctl->ctx, &sysctl__hw_children,
 346                         OID_AUTO, "backlight_level",
 347                         CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_ANYBODY,
 348                         radeon_encoder, sizeof(int),
 349                         sysctl_backlight_handler,
 350                         "I", "Backlight level");
 351         return;
 352 }
 353
 354 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 355 {
 356 }
 357
 358 #endif
 359
 360
 361 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 362                                    const struct drm_display_mode *mode,
 363                                    struct drm_display_mode *adjusted_mode)
 364 {
 365         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 366         struct drm_device *dev = encoder->dev;
 367         struct radeon_device *rdev = dev->dev_private;
 368
 369         /* set the active encoder to connector routing */
 370         radeon_encoder_set_active_device(encoder);
 371         drm_mode_set_crtcinfo(adjusted_mode, 0);
 372
 373         /* hw bug */
 374         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 375             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 376                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 377
 378         /* get the native mode for scaling */
 379         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 380                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 381         } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 382                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 383                 if (tv_dac) {
 384                         if (tv_dac->tv_std == TV_STD_NTSC ||
 385                             tv_dac->tv_std == TV_STD_NTSC_J ||
 386                             tv_dac->tv_std == TV_STD_PAL_M)
 387                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 388                         else
 389                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 390                 }
 391         } else if (radeon_encoder->rmx_type != RMX_OFF) {
 392                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 393         }
 394
 395         if (ASIC_IS_DCE3(rdev) &&
 396             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 397              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 398                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 399                 radeon_dp_set_link_config(connector, adjusted_mode);
 400         }
 401
 402         return true;
 403 }
 404
 405 static void
 406 atombios_dac_setup(struct drm_encoder *encoder, int action)
 407 {
 408         struct drm_device *dev = encoder->dev;
 409         struct radeon_device *rdev = dev->dev_private;
 410         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 411         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 412         int index = 0;
 413         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 414
 415         memset(&args, 0, sizeof(args));
 416
 417         switch (radeon_encoder->encoder_id) {
 418         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 419         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 420                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 421                 break;
 422         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 423         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 424                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 425                 break;
 426         }
 427
 428         args.ucAction = action;
 429
 430         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 431                 args.ucDacStandard = ATOM_DAC1_PS2;
 432         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 433                 args.ucDacStandard = ATOM_DAC1_CV;
 434         else {
 435                 switch (dac_info->tv_std) {
 436                 case TV_STD_PAL:
 437                 case TV_STD_PAL_M:
 438                 case TV_STD_SCART_PAL:
 439                 case TV_STD_SECAM:
 440                 case TV_STD_PAL_CN:
 441                         args.ucDacStandard = ATOM_DAC1_PAL;
 442                         break;
 443                 case TV_STD_NTSC:
 444                 case TV_STD_NTSC_J:
 445                 case TV_STD_PAL_60:
 446                 default:
 447                         args.ucDacStandard = ATOM_DAC1_NTSC;
 448                         break;
 449                 }
 450         }
 451         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 452
 453         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 454
 455 }
 456
 457 static void
 458 atombios_tv_setup(struct drm_encoder *encoder, int action)
 459 {
 460         struct drm_device *dev = encoder->dev;
 461         struct radeon_device *rdev = dev->dev_private;
 462         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 463         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 464         int index = 0;
 465         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 466
 467         memset(&args, 0, sizeof(args));
 468
 469         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 470
 471         args.sTVEncoder.ucAction = action;
 472
 473         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 474                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 475         else {
 476                 switch (dac_info->tv_std) {
 477                 case TV_STD_NTSC:
 478                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 479                         break;
 480                 case TV_STD_PAL:
 481                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 482                         break;
 483                 case TV_STD_PAL_M:
 484                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 485                         break;
 486                 case TV_STD_PAL_60:
 487                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 488                         break;
 489                 case TV_STD_NTSC_J:
 490                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 491                         break;
 492                 case TV_STD_SCART_PAL:
 493                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 494                         break;
 495                 case TV_STD_SECAM:
 496                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 497                         break;
 498                 case TV_STD_PAL_CN:
 499                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 500                         break;
 501                 default:
 502                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 503                         break;
 504                 }
 505         }
 506
 507         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 508
 509         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 510
 511 }
 512
 513 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 514 {
 515         int bpc = 8;
 516
 517         if (encoder->crtc) {
 518                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 519                 bpc = radeon_crtc->bpc;
 520         }
 521
 522         switch (bpc) {
 523         case 0:
 524                 return PANEL_BPC_UNDEFINE;
 525         case 6:
 526                 return PANEL_6BIT_PER_COLOR;
 527         case 8:
 528         default:
 529                 return PANEL_8BIT_PER_COLOR;
 530         case 10:
 531                 return PANEL_10BIT_PER_COLOR;
 532         case 12:
 533                 return PANEL_12BIT_PER_COLOR;
 534         case 16:
 535                 return PANEL_16BIT_PER_COLOR;
 536         }
 537 }
 538
 539 union dvo_encoder_control {
 540         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 541         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 542         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 543         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 544 };
 545
 546 void
 547 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 548 {
 549         struct drm_device *dev = encoder->dev;
 550         struct radeon_device *rdev = dev->dev_private;
 551         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 552         union dvo_encoder_control args;
 553         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 554         uint8_t frev, crev;
 555
 556         memset(&args, 0, sizeof(args));
 557
 558         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 559                 return;
 560
 561         /* some R4xx chips have the wrong frev */
 562         if (rdev->family <= CHIP_RV410)
 563                 frev = 1;
 564
 565         switch (frev) {
 566         case 1:
 567                 switch (crev) {
 568                 case 1:
 569                         /* R4xx, R5xx */
 570                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 571
 572                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 573                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 574
 575                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 576                         break;
 577                 case 2:
 578                         /* RS600/690/740 */
 579                         args.dvo.sDVOEncoder.ucAction = action;
 580                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 581                         /* DFP1, CRT1, TV1 depending on the type of port */
 582                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 583
 584                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 585                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 586                         break;
 587                 case 3:
 588                         /* R6xx */
 589                         args.dvo_v3.ucAction = action;
 590                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 591                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 592                         break;
 593                 case 4:
 594                         /* DCE8 */
 595                         args.dvo_v4.ucAction = action;
 596                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 597                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 598                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 599                         break;
 600                 default:
 601                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 602                         break;
 603                 }
 604                 break;
 605         default:
 606                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 607                 break;
 608         }
 609
 610         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 611 }
 612
 613 union lvds_encoder_control {
 614         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 615         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 616 };
 617
 618 void
 619 atombios_digital_setup(struct drm_encoder *encoder, int action)
 620 {
 621         struct drm_device *dev = encoder->dev;
 622         struct radeon_device *rdev = dev->dev_private;
 623         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 624         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 625         union lvds_encoder_control args;
 626         int index = 0;
 627         int hdmi_detected = 0;
 628         uint8_t frev, crev;
 629
 630         if (!dig)
 631                 return;
 632
 633         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 634                 hdmi_detected = 1;
 635
 636         memset(&args, 0, sizeof(args));
 637
 638         switch (radeon_encoder->encoder_id) {
 639         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 640                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 641                 break;
 642         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 643         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 644                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 645                 break;
 646         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 647                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 648                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 649                 else
 650                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 651                 break;
 652         }
 653
 654         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 655                 return;
 656
 657         switch (frev) {
 658         case 1:
 659         case 2:
 660                 switch (crev) {
 661                 case 1:
 662                         args.v1.ucMisc = 0;
 663                         args.v1.ucAction = action;
 664                         if (hdmi_detected)
 665                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 666                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 667                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 668                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 669                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 670                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 671                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 672                         } else {
 673                                 if (dig->linkb)
 674                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 675                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 676                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 677                                 /*if (pScrn->rgbBits == 8) */
 678                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 679                         }
 680                         break;
 681                 case 2:
 682                 case 3:
 683                         args.v2.ucMisc = 0;
 684                         args.v2.ucAction = action;
 685                         if (crev == 3) {
 686                                 if (dig->coherent_mode)
 687                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 688                         }
 689                         if (hdmi_detected)
 690                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 691                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 692                         args.v2.ucTruncate = 0;
 693                         args.v2.ucSpatial = 0;
 694                         args.v2.ucTemporal = 0;
 695                         args.v2.ucFRC = 0;
 696                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 697                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 698                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 699                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 700                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 701                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 702                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 703                                 }
 704                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 705                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 706                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 707                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 708                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 709                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 710                                 }
 711                         } else {
 712                                 if (dig->linkb)
 713                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 714                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 715                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 716                         }
 717                         break;
 718                 default:
 719                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 720                         break;
 721                 }
 722                 break;
 723         default:
 724                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 725                 break;
 726         }
 727
 728         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 729 }
 730
 731 int
 732 atombios_get_encoder_mode(struct drm_encoder *encoder)
 733 {
 734         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 735         struct drm_connector *connector;
 736         struct radeon_connector *radeon_connector;
 737         struct radeon_connector_atom_dig *dig_connector;
 738
 739         /* dp bridges are always DP */
 740         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 741                 return ATOM_ENCODER_MODE_DP;
 742
 743         /* DVO is always DVO */
 744         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 745             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 746                 return ATOM_ENCODER_MODE_DVO;
 747
 748         connector = radeon_get_connector_for_encoder(encoder);
 749         /* if we don't have an active device yet, just use one of
 750          * the connectors tied to the encoder.
 751          */
 752         if (!connector)
 753                 connector = radeon_get_connector_for_encoder_init(encoder);
 754         radeon_connector = to_radeon_connector(connector);
 755
 756         switch (connector->connector_type) {
 757         case DRM_MODE_CONNECTOR_DVII:
 758         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 759                 if (radeon_audio != 0) {
 760                         if (radeon_connector->use_digital &&
 761                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 762                                 return ATOM_ENCODER_MODE_HDMI;
 763                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 764                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 765                                 return ATOM_ENCODER_MODE_HDMI;
 766                         else if (radeon_connector->use_digital)
 767                                 return ATOM_ENCODER_MODE_DVI;
 768                         else
 769                                 return ATOM_ENCODER_MODE_CRT;
 770                 } else if (radeon_connector->use_digital) {
 771                         return ATOM_ENCODER_MODE_DVI;
 772                 } else {
 773                         return ATOM_ENCODER_MODE_CRT;
 774                 }
 775                 break;
 776         case DRM_MODE_CONNECTOR_DVID:
 777         case DRM_MODE_CONNECTOR_HDMIA:
 778         default:
 779                 if (radeon_audio != 0) {
 780                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 781                                 return ATOM_ENCODER_MODE_HDMI;
 782                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 783                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 784                                 return ATOM_ENCODER_MODE_HDMI;
 785                         else
 786                                 return ATOM_ENCODER_MODE_DVI;
 787                 } else {
 788                         return ATOM_ENCODER_MODE_DVI;
 789                 }
 790                 break;
 791         case DRM_MODE_CONNECTOR_LVDS:
 792                 return ATOM_ENCODER_MODE_LVDS;
 793                 break;
 794         case DRM_MODE_CONNECTOR_DisplayPort:
 795                 dig_connector = radeon_connector->con_priv;
 796                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 797                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 798                         return ATOM_ENCODER_MODE_DP;
 799                 } else if (radeon_audio != 0) {
 800                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 801                                 return ATOM_ENCODER_MODE_HDMI;
 802                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 803                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 804                                 return ATOM_ENCODER_MODE_HDMI;
 805                         else
 806                                 return ATOM_ENCODER_MODE_DVI;
 807                 } else {
 808                         return ATOM_ENCODER_MODE_DVI;
 809                 }
 810                 break;
 811         case DRM_MODE_CONNECTOR_eDP:
 812                 return ATOM_ENCODER_MODE_DP;
 813         case DRM_MODE_CONNECTOR_DVIA:
 814         case DRM_MODE_CONNECTOR_VGA:
 815                 return ATOM_ENCODER_MODE_CRT;
 816                 break;
 817         case DRM_MODE_CONNECTOR_Composite:
 818         case DRM_MODE_CONNECTOR_SVIDEO:
 819         case DRM_MODE_CONNECTOR_9PinDIN:
 820                 /* fix me */
 821                 return ATOM_ENCODER_MODE_TV;
 822                 /*return ATOM_ENCODER_MODE_CV;*/
 823                 break;
 824         }
 825 }
 826
 827 /*
 828  * DIG Encoder/Transmitter Setup
 829  *
 830  * DCE 3.0/3.1
 831  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 832  * Supports up to 3 digital outputs
 833  * - 2 DIG encoder blocks.
 834  * DIG1 can drive UNIPHY link A or link B
 835  * DIG2 can drive UNIPHY link B or LVTMA
 836  *
 837  * DCE 3.2
 838  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 839  * Supports up to 5 digital outputs
 840  * - 2 DIG encoder blocks.
 841  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 842  *
 843  * DCE 4.0/5.0/6.0
 844  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 845  * Supports up to 6 digital outputs
 846  * - 6 DIG encoder blocks.
 847  * - DIG to PHY mapping is hardcoded
 848  * DIG1 drives UNIPHY0 link A, A+B
 849  * DIG2 drives UNIPHY0 link B
 850  * DIG3 drives UNIPHY1 link A, A+B
 851  * DIG4 drives UNIPHY1 link B
 852  * DIG5 drives UNIPHY2 link A, A+B
 853  * DIG6 drives UNIPHY2 link B
 854  *
 855  * DCE 4.1
 856  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 857  * Supports up to 6 digital outputs
 858  * - 2 DIG encoder blocks.
 859  * llano
 860  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 861  * ontario
 862  * DIG1 drives UNIPHY0/1/2 link A
 863  * DIG2 drives UNIPHY0/1/2 link B
 864  *
 865  * Routing
 866  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 867  * Examples:
 868  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 869  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 870  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 871  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 872  */
 873
 874 union dig_encoder_control {
 875         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 876         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 877         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 878         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 879 };
 880
 881 void
 882 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 883 {
 884         struct drm_device *dev = encoder->dev;
 885         struct radeon_device *rdev = dev->dev_private;
 886         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 887         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 888         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 889         union dig_encoder_control args;
 890         int index = 0;
 891         uint8_t frev, crev;
 892         int dp_clock = 0;
 893         int dp_lane_count = 0;
 894         int hpd_id = RADEON_HPD_NONE;
 895
 896         if (connector) {
 897                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 898                 struct radeon_connector_atom_dig *dig_connector =
 899                         radeon_connector->con_priv;
 900
 901                 dp_clock = dig_connector->dp_clock;
 902                 dp_lane_count = dig_connector->dp_lane_count;
 903                 hpd_id = radeon_connector->hpd.hpd;
 904         }
 905
 906         /* no dig encoder assigned */
 907         if (dig->dig_encoder == -1)
 908                 return;
 909
 910         memset(&args, 0, sizeof(args));
 911
 912         if (ASIC_IS_DCE4(rdev))
 913                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 914         else {
 915                 if (dig->dig_encoder)
 916                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 917                 else
 918                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 919         }
 920
 921         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 922                 return;
 923
 924         switch (frev) {
 925         case 1:
 926                 switch (crev) {
 927                 case 1:
 928                         args.v1.ucAction = action;
 929                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 930                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 931                                 args.v3.ucPanelMode = panel_mode;
 932                         else
 933                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 934
 935                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 936                                 args.v1.ucLaneNum = dp_lane_count;
 937                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 938                                 args.v1.ucLaneNum = 8;
 939                         else
 940                                 args.v1.ucLaneNum = 4;
 941
 942                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 943                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 944                         switch (radeon_encoder->encoder_id) {
 945                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 946                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 947                                 break;
 948                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 949                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 950                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 951                                 break;
 952                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 953                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 954                                 break;
 955                         }
 956                         if (dig->linkb)
 957                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 958                         else
 959                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 960                         break;
 961                 case 2:
 962                 case 3:
 963                         args.v3.ucAction = action;
 964                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 965                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 966                                 args.v3.ucPanelMode = panel_mode;
 967                         else
 968                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 969
 970                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 971                                 args.v3.ucLaneNum = dp_lane_count;
 972                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 973                                 args.v3.ucLaneNum = 8;
 974                         else
 975                                 args.v3.ucLaneNum = 4;
 976
 977                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 978                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 979                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 980                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 981                         break;
 982                 case 4:
 983                         args.v4.ucAction = action;
 984                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 985                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 986                                 args.v4.ucPanelMode = panel_mode;
 987                         else
 988                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 989
 990                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 991                                 args.v4.ucLaneNum = dp_lane_count;
 992                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 993                                 args.v4.ucLaneNum = 8;
 994                         else
 995                                 args.v4.ucLaneNum = 4;
 996
 997                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 998                                 if (dp_clock == 540000)
 999                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
1000                                 else if (dp_clock == 324000)
1001                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
1002                                 else if (dp_clock == 270000)
1003                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
1004                                 else
1005                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
1006                         }
1007                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
1008                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
1009                         if (hpd_id == RADEON_HPD_NONE)
1010                                 args.v4.ucHPD_ID = 0;
1011                         else
1012                                 args.v4.ucHPD_ID = hpd_id + 1;
1013                         break;
1014                 default:
1015                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1016                         break;
1017                 }
1018                 break;
1019         default:
1020                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1021                 break;
1022         }
1023
1024         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1025
1026 }
1027
1028 union dig_transmitter_control {
1029         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1030         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1031         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1032         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1033         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1034 };
1035
1036 void
1037 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1038 {
1039         struct drm_device *dev = encoder->dev;
1040         struct radeon_device *rdev = dev->dev_private;
1041         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1042         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1043         struct drm_connector *connector;
1044         union dig_transmitter_control args;
1045         int index = 0;
1046         uint8_t frev, crev;
1047         bool is_dp = false;
1048         int pll_id = 0;
1049         int dp_clock = 0;
1050         int dp_lane_count = 0;
1051         int connector_object_id = 0;
1052         int igp_lane_info = 0;
1053         int dig_encoder = dig->dig_encoder;
1054         int hpd_id = RADEON_HPD_NONE;
1055
1056         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1057                 connector = radeon_get_connector_for_encoder_init(encoder);
1058                 /* just needed to avoid bailing in the encoder check.  the encoder
1059                  * isn't used for init
1060                  */
1061                 dig_encoder = 0;
1062         } else
1063                 connector = radeon_get_connector_for_encoder(encoder);
1064
1065         if (connector) {
1066                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1067                 struct radeon_connector_atom_dig *dig_connector =
1068                         radeon_connector->con_priv;
1069
1070                 hpd_id = radeon_connector->hpd.hpd;
1071                 dp_clock = dig_connector->dp_clock;
1072                 dp_lane_count = dig_connector->dp_lane_count;
1073                 connector_object_id =
1074                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1075                 igp_lane_info = dig_connector->igp_lane_info;
1076         }
1077
1078         if (encoder->crtc) {
1079                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1080                 pll_id = radeon_crtc->pll_id;
1081         }
1082
1083         /* no dig encoder assigned */
1084         if (dig_encoder == -1)
1085                 return;
1086
1087         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1088                 is_dp = true;
1089
1090         memset(&args, 0, sizeof(args));
1091
1092         switch (radeon_encoder->encoder_id) {
1093         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1094                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1095                 break;
1096         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1097         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1098         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1099         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1100                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1101                 break;
1102         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1103                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1104                 break;
1105         }
1106
1107         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1108                 return;
1109
1110         switch (frev) {
1111         case 1:
1112                 switch (crev) {
1113                 case 1:
1114                         args.v1.ucAction = action;
1115                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1116                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1117                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1118                                 args.v1.asMode.ucLaneSel = lane_num;
1119                                 args.v1.asMode.ucLaneSet = lane_set;
1120                         } else {
1121                                 if (is_dp)
1122                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1123                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1124                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1125                                 else
1126                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1127                         }
1128
1129                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1130
1131                         if (dig_encoder)
1132                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1133                         else
1134                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1135
1136                         if ((rdev->flags & RADEON_IS_IGP) &&
1137                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1138                                 if (is_dp ||
1139                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1140                                         if (igp_lane_info & 0x1)
1141                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1142                                         else if (igp_lane_info & 0x2)
1143                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1144                                         else if (igp_lane_info & 0x4)
1145                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1146                                         else if (igp_lane_info & 0x8)
1147                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1148                                 } else {
1149                                         if (igp_lane_info & 0x3)
1150                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1151                                         else if (igp_lane_info & 0xc)
1152                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1153                                 }
1154                         }
1155
1156                         if (dig->linkb)
1157                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1158                         else
1159                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1160
1161                         if (is_dp)
1162                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1163                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1164                                 if (dig->coherent_mode)
1165                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1166                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1167                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1168                         }
1169                         break;
1170                 case 2:
1171                         args.v2.ucAction = action;
1172                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1173                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1174                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1175                                 args.v2.asMode.ucLaneSel = lane_num;
1176                                 args.v2.asMode.ucLaneSet = lane_set;
1177                         } else {
1178                                 if (is_dp)
1179                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1180                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1181                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1182                                 else
1183                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1184                         }
1185
1186                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1187                         if (dig->linkb)
1188                                 args.v2.acConfig.ucLinkSel = 1;
1189
1190                         switch (radeon_encoder->encoder_id) {
1191                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1192                                 args.v2.acConfig.ucTransmitterSel = 0;
1193                                 break;
1194                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1195                                 args.v2.acConfig.ucTransmitterSel = 1;
1196                                 break;
1197                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1198                                 args.v2.acConfig.ucTransmitterSel = 2;
1199                                 break;
1200                         }
1201
1202                         if (is_dp) {
1203                                 args.v2.acConfig.fCoherentMode = 1;
1204                                 args.v2.acConfig.fDPConnector = 1;
1205                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1206                                 if (dig->coherent_mode)
1207                                         args.v2.acConfig.fCoherentMode = 1;
1208                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1209                                         args.v2.acConfig.fDualLinkConnector = 1;
1210                         }
1211                         break;
1212                 case 3:
1213                         args.v3.ucAction = action;
1214                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1215                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1216                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1217                                 args.v3.asMode.ucLaneSel = lane_num;
1218                                 args.v3.asMode.ucLaneSet = lane_set;
1219                         } else {
1220                                 if (is_dp)
1221                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1222                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1223                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1224                                 else
1225                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1226                         }
1227
1228                         if (is_dp)
1229                                 args.v3.ucLaneNum = dp_lane_count;
1230                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1231                                 args.v3.ucLaneNum = 8;
1232                         else
1233                                 args.v3.ucLaneNum = 4;
1234
1235                         if (dig->linkb)
1236                                 args.v3.acConfig.ucLinkSel = 1;
1237                         if (dig_encoder & 1)
1238                                 args.v3.acConfig.ucEncoderSel = 1;
1239
1240                         /* Select the PLL for the PHY
1241                          * DP PHY should be clocked from external src if there is
1242                          * one.
1243                          */
1244                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1245                         if (is_dp && rdev->clock.dp_extclk)
1246                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1247                         else
1248                                 args.v3.acConfig.ucRefClkSource = pll_id;
1249
1250                         switch (radeon_encoder->encoder_id) {
1251                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1252                                 args.v3.acConfig.ucTransmitterSel = 0;
1253                                 break;
1254                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1255                                 args.v3.acConfig.ucTransmitterSel = 1;
1256                                 break;
1257                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1258                                 args.v3.acConfig.ucTransmitterSel = 2;
1259                                 break;
1260                         }
1261
1262                         if (is_dp)
1263                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1264                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1265                                 if (dig->coherent_mode)
1266                                         args.v3.acConfig.fCoherentMode = 1;
1267                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1268                                         args.v3.acConfig.fDualLinkConnector = 1;
1269                         }
1270                         break;
1271                 case 4:
1272                         args.v4.ucAction = action;
1273                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1274                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1275                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1276                                 args.v4.asMode.ucLaneSel = lane_num;
1277                                 args.v4.asMode.ucLaneSet = lane_set;
1278                         } else {
1279                                 if (is_dp)
1280                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1281                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1282                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1283                                 else
1284                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1285                         }
1286
1287                         if (is_dp)
1288                                 args.v4.ucLaneNum = dp_lane_count;
1289                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1290                                 args.v4.ucLaneNum = 8;
1291                         else
1292                                 args.v4.ucLaneNum = 4;
1293
1294                         if (dig->linkb)
1295                                 args.v4.acConfig.ucLinkSel = 1;
1296                         if (dig_encoder & 1)
1297                                 args.v4.acConfig.ucEncoderSel = 1;
1298
1299                         /* Select the PLL for the PHY
1300                          * DP PHY should be clocked from external src if there is
1301                          * one.
1302                          */
1303                         /* On DCE5 DCPLL usually generates the DP ref clock */
1304                         if (is_dp) {
1305                                 if (rdev->clock.dp_extclk)
1306                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1307                                 else
1308                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1309                         } else
1310                                 args.v4.acConfig.ucRefClkSource = pll_id;
1311
1312                         switch (radeon_encoder->encoder_id) {
1313                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1314                                 args.v4.acConfig.ucTransmitterSel = 0;
1315                                 break;
1316                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1317                                 args.v4.acConfig.ucTransmitterSel = 1;
1318                                 break;
1319                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1320                                 args.v4.acConfig.ucTransmitterSel = 2;
1321                                 break;
1322                         }
1323
1324                         if (is_dp)
1325                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1326                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1327                                 if (dig->coherent_mode)
1328                                         args.v4.acConfig.fCoherentMode = 1;
1329                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1330                                         args.v4.acConfig.fDualLinkConnector = 1;
1331                         }
1332                         break;
1333                 case 5:
1334                         args.v5.ucAction = action;
1335                         if (is_dp)
1336                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1337                         else
1338                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1339
1340                         switch (radeon_encoder->encoder_id) {
1341                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1342                                 if (dig->linkb)
1343                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1344                                 else
1345                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1346                                 break;
1347                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1348                                 if (dig->linkb)
1349                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1350                                 else
1351                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1352                                 break;
1353                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1354                                 if (dig->linkb)
1355                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1356                                 else
1357                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1358                                 break;
1359                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1360                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1361                                 break;
1362                         }
1363                         if (is_dp)
1364                                 args.v5.ucLaneNum = dp_lane_count;
1365                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1366                                 args.v5.ucLaneNum = 8;
1367                         else
1368                                 args.v5.ucLaneNum = 4;
1369                         args.v5.ucConnObjId = connector_object_id;
1370                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1371
1372                         if (is_dp && rdev->clock.dp_extclk)
1373                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1374                         else
1375                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1376
1377                         if (is_dp)
1378                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1379                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1380                                 if (dig->coherent_mode)
1381                                         args.v5.asConfig.ucCoherentMode = 1;
1382                         }
1383                         if (hpd_id == RADEON_HPD_NONE)
1384                                 args.v5.asConfig.ucHPDSel = 0;
1385                         else
1386                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1387                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1388                         args.v5.ucDPLaneSet = lane_set;
1389                         break;
1390                 default:
1391                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1392                         break;
1393                 }
1394                 break;
1395         default:
1396                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1397                 break;
1398         }
1399
1400         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1401 }
1402
1403 bool
1404 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1405 {
1406         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1407         struct drm_device *dev = radeon_connector->base.dev;
1408         struct radeon_device *rdev = dev->dev_private;
1409         union dig_transmitter_control args;
1410         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1411         uint8_t frev, crev;
1412
1413         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1414                 goto done;
1415
1416         if (!ASIC_IS_DCE4(rdev))
1417                 goto done;
1418
1419         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1420             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1421                 goto done;
1422
1423         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1424                 goto done;
1425
1426         memset(&args, 0, sizeof(args));
1427
1428         args.v1.ucAction = action;
1429
1430         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1431
1432         /* wait for the panel to power up */
1433         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1434                 int i;
1435
1436                 for (i = 0; i < 300; i++) {
1437                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1438                                 return true;
1439                         mdelay(1);
1440                 }
1441                 return false;
1442         }
1443 done:
1444         return true;
1445 }
1446
1447 union external_encoder_control {
1448         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1449         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1450 };
1451
1452 static void
1453 atombios_external_encoder_setup(struct drm_encoder *encoder,
1454                                 struct drm_encoder *ext_encoder,
1455                                 int action)
1456 {
1457         struct drm_device *dev = encoder->dev;
1458         struct radeon_device *rdev = dev->dev_private;
1459         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1460         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1461         union external_encoder_control args;
1462         struct drm_connector *connector;
1463         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1464         u8 frev, crev;
1465         int dp_clock = 0;
1466         int dp_lane_count = 0;
1467         int connector_object_id = 0;
1468         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1469
1470         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1471                 connector = radeon_get_connector_for_encoder_init(encoder);
1472         else
1473                 connector = radeon_get_connector_for_encoder(encoder);
1474
1475         if (connector) {
1476                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1477                 struct radeon_connector_atom_dig *dig_connector =
1478                         radeon_connector->con_priv;
1479
1480                 dp_clock = dig_connector->dp_clock;
1481                 dp_lane_count = dig_connector->dp_lane_count;
1482                 connector_object_id =
1483                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1484         }
1485
1486         memset(&args, 0, sizeof(args));
1487
1488         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1489                 return;
1490
1491         switch (frev) {
1492         case 1:
1493                 /* no params on frev 1 */
1494                 break;
1495         case 2:
1496                 switch (crev) {
1497                 case 1:
1498                 case 2:
1499                         args.v1.sDigEncoder.ucAction = action;
1500                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1501                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1502
1503                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1504                                 if (dp_clock == 270000)
1505                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1506                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1507                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1508                                 args.v1.sDigEncoder.ucLaneNum = 8;
1509                         else
1510                                 args.v1.sDigEncoder.ucLaneNum = 4;
1511                         break;
1512                 case 3:
1513                         args.v3.sExtEncoder.ucAction = action;
1514                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1515                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1516                         else
1517                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1518                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1519
1520                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1521                                 if (dp_clock == 270000)
1522                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1523                                 else if (dp_clock == 540000)
1524                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1525                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1526                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1527                                 args.v3.sExtEncoder.ucLaneNum = 8;
1528                         else
1529                                 args.v3.sExtEncoder.ucLaneNum = 4;
1530                         switch (ext_enum) {
1531                         case GRAPH_OBJECT_ENUM_ID1:
1532                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1533                                 break;
1534                         case GRAPH_OBJECT_ENUM_ID2:
1535                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1536                                 break;
1537                         case GRAPH_OBJECT_ENUM_ID3:
1538                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1539                                 break;
1540                         }
1541                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1542                         break;
1543                 default:
1544                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1545                         return;
1546                 }
1547                 break;
1548         default:
1549                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1550                 return;
1551         }
1552         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1553 }
1554
1555 static void
1556 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1557 {
1558         struct drm_device *dev = encoder->dev;
1559         struct radeon_device *rdev = dev->dev_private;
1560         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1561         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1562         ENABLE_YUV_PS_ALLOCATION args;
1563         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1564         uint32_t temp, reg;
1565
1566         memset(&args, 0, sizeof(args));
1567
1568         if (rdev->family >= CHIP_R600)
1569                 reg = R600_BIOS_3_SCRATCH;
1570         else
1571                 reg = RADEON_BIOS_3_SCRATCH;
1572
1573         /* XXX: fix up scratch reg handling */
1574         temp = RREG32(reg);
1575         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1576                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1577                              (radeon_crtc->crtc_id << 18)));
1578         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1579                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1580         else
1581                 WREG32(reg, 0);
1582
1583         if (enable)
1584                 args.ucEnable = ATOM_ENABLE;
1585         args.ucCRTC = radeon_crtc->crtc_id;
1586
1587         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1588
1589         WREG32(reg, temp);
1590 }
1591
1592 static void
1593 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1594 {
1595         struct drm_device *dev = encoder->dev;
1596         struct radeon_device *rdev = dev->dev_private;
1597         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1598         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1599         int index = 0;
1600
1601         memset(&args, 0, sizeof(args));
1602
1603         switch (radeon_encoder->encoder_id) {
1604         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1605         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1606                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1607                 break;
1608         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1609         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1610         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1611                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1612                 break;
1613         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1614                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1615                 break;
1616         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1617                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1618                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1619                 else
1620                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1621                 break;
1622         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1623         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1624                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1625                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1626                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1627                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1628                 else
1629                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1630                 break;
1631         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1632         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1633                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1634                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1635                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1636                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1637                 else
1638                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1639                 break;
1640         default:
1641                 return;
1642         }
1643
1644         switch (mode) {
1645         case DRM_MODE_DPMS_ON:
1646                 args.ucAction = ATOM_ENABLE;
1647                 /* workaround for DVOOutputControl on some RS690 systems */
1648                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1649                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1650                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1651                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1652                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1653                 } else
1654                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1655                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1656                         args.ucAction = ATOM_LCD_BLON;
1657                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1658                 }
1659                 break;
1660         case DRM_MODE_DPMS_STANDBY:
1661         case DRM_MODE_DPMS_SUSPEND:
1662         case DRM_MODE_DPMS_OFF:
1663                 args.ucAction = ATOM_DISABLE;
1664                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1665                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1666                         args.ucAction = ATOM_LCD_BLOFF;
1667                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1668                 }
1669                 break;
1670         }
1671 }
1672
1673 static void
1674 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1675 {
1676         struct drm_device *dev = encoder->dev;
1677         struct radeon_device *rdev = dev->dev_private;
1678         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1679         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1680         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1681         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1682         struct radeon_connector *radeon_connector = NULL;
1683         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1684         bool travis_quirk = false;
1685
1686         if (connector) {
1687                 radeon_connector = to_radeon_connector(connector);
1688                 radeon_dig_connector = radeon_connector->con_priv;
1689                 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1690                      ENCODER_OBJECT_ID_TRAVIS) &&
1691                     (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1692                     !ASIC_IS_DCE5(rdev))
1693                         travis_quirk = true;
1694         }
1695
1696         switch (mode) {
1697         case DRM_MODE_DPMS_ON:
1698                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1699                         if (!connector)
1700                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1701                         else
1702                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1703
1704                         /* setup and enable the encoder */
1705                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1706                         atombios_dig_encoder_setup(encoder,
1707                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1708                                                    dig->panel_mode);
1709                         if (ext_encoder) {
1710                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1711                                         atombios_external_encoder_setup(encoder, ext_encoder,
1712                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1713                         }
1714                 } else if (ASIC_IS_DCE4(rdev)) {
1715                         /* setup and enable the encoder */
1716                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1717                 } else {
1718                         /* setup and enable the encoder and transmitter */
1719                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1720                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1721                 }
1722                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1723                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1724                                 atombios_set_edp_panel_power(connector,
1725                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1726                                 radeon_dig_connector->edp_on = true;
1727                         }
1728                 }
1729                 /* enable the transmitter */
1730                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1731                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1732                         /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1733                         radeon_dp_link_train(encoder, connector);
1734                         if (ASIC_IS_DCE4(rdev))
1735                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1736                 }
1737                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1738                         atombios_dig_transmitter_setup(encoder,
1739                                                        ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1740                 if (ext_encoder)
1741                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1742                 break;
1743         case DRM_MODE_DPMS_STANDBY:
1744         case DRM_MODE_DPMS_SUSPEND:
1745         case DRM_MODE_DPMS_OFF:
1746                 if (ASIC_IS_DCE4(rdev)) {
1747                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1748                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1749                 }
1750                 if (ext_encoder)
1751                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1752                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1753                         atombios_dig_transmitter_setup(encoder,
1754                                                        ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1755
1756                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1757                     connector && !travis_quirk)
1758                         radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1759                 if (ASIC_IS_DCE4(rdev)) {
1760                         /* disable the transmitter */
1761                         atombios_dig_transmitter_setup(encoder,
1762                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1763                 } else {
1764                         /* disable the encoder and transmitter */
1765                         atombios_dig_transmitter_setup(encoder,
1766                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1767                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1768                 }
1769                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1770                         if (travis_quirk)
1771                                 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1772                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1773                                 atombios_set_edp_panel_power(connector,
1774                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1775                                 radeon_dig_connector->edp_on = false;
1776                         }
1777                 }
1778                 break;
1779         }
1780 }
1781
1782 static void
1783 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1784 {
1785         struct drm_device *dev = encoder->dev;
1786         struct radeon_device *rdev = dev->dev_private;
1787         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1788
1789         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1790                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1791                   radeon_encoder->active_device);
1792         switch (radeon_encoder->encoder_id) {
1793         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1794         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1795         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1796         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1797         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1798         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1799         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1800         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1801                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1802                 break;
1803         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1804         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1805         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1806         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1807         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1808                 radeon_atom_encoder_dpms_dig(encoder, mode);
1809                 break;
1810         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1811                 if (ASIC_IS_DCE5(rdev)) {
1812                         switch (mode) {
1813                         case DRM_MODE_DPMS_ON:
1814                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1815                                 break;
1816                         case DRM_MODE_DPMS_STANDBY:
1817                         case DRM_MODE_DPMS_SUSPEND:
1818                         case DRM_MODE_DPMS_OFF:
1819                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1820                                 break;
1821                         }
1822                 } else if (ASIC_IS_DCE3(rdev))
1823                         radeon_atom_encoder_dpms_dig(encoder, mode);
1824                 else
1825                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1826                 break;
1827         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1828         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1829                 if (ASIC_IS_DCE5(rdev)) {
1830                         switch (mode) {
1831                         case DRM_MODE_DPMS_ON:
1832                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1833                                 break;
1834                         case DRM_MODE_DPMS_STANDBY:
1835                         case DRM_MODE_DPMS_SUSPEND:
1836                         case DRM_MODE_DPMS_OFF:
1837                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1838                                 break;
1839                         }
1840                 } else
1841                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1842                 break;
1843         default:
1844                 return;
1845         }
1846
1847         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1848
1849 }
1850
1851 union crtc_source_param {
1852         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1853         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1854 };
1855
1856 static void
1857 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1858 {
1859         struct drm_device *dev = encoder->dev;
1860         struct radeon_device *rdev = dev->dev_private;
1861         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1862         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1863         union crtc_source_param args;
1864         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1865         uint8_t frev, crev;
1866         struct radeon_encoder_atom_dig *dig;
1867
1868         memset(&args, 0, sizeof(args));
1869
1870         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1871                 return;
1872
1873         switch (frev) {
1874         case 1:
1875                 switch (crev) {
1876                 case 1:
1877                 default:
1878                         if (ASIC_IS_AVIVO(rdev))
1879                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1880                         else {
1881                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1882                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1883                                 } else {
1884                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1885                                 }
1886                         }
1887                         switch (radeon_encoder->encoder_id) {
1888                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1889                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1890                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1891                                 break;
1892                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1893                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1894                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1895                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1896                                 else
1897                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1898                                 break;
1899                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1900                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1901                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1902                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1903                                 break;
1904                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1905                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1906                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1907                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1908                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1909                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1910                                 else
1911                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1912                                 break;
1913                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1914                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1915                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1916                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1917                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1918                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1919                                 else
1920                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1921                                 break;
1922                         }
1923                         break;
1924                 case 2:
1925                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1926                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1927                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1928
1929                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1930                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1931                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1932                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1933                                 else
1934                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1935                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1936                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1937                         } else {
1938                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1939                         }
1940                         switch (radeon_encoder->encoder_id) {
1941                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1942                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1943                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1944                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1945                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1946                                 dig = radeon_encoder->enc_priv;
1947                                 switch (dig->dig_encoder) {
1948                                 case 0:
1949                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1950                                         break;
1951                                 case 1:
1952                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1953                                         break;
1954                                 case 2:
1955                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1956                                         break;
1957                                 case 3:
1958                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1959                                         break;
1960                                 case 4:
1961                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1962                                         break;
1963                                 case 5:
1964                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1965                                         break;
1966                                 case 6:
1967                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1968                                         break;
1969                                 }
1970                                 break;
1971                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1972                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1973                                 break;
1974                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1975                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1976                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1977                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1978                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1979                                 else
1980                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1981                                 break;
1982                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1983                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1984                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1985                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1986                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1987                                 else
1988                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1989                                 break;
1990                         }
1991                         break;
1992                 }
1993                 break;
1994         default:
1995                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1996                 return;
1997         }
1998
1999         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2000
2001         /* update scratch regs with new routing */
2002         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2003 }
2004
2005 static void
2006 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2007                               struct drm_display_mode *mode)
2008 {
2009         struct drm_device *dev = encoder->dev;
2010         struct radeon_device *rdev = dev->dev_private;
2011         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2012         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2013
2014         /* Funky macbooks */
2015         if ((dev->pdev->device == 0x71C5) &&
2016             (dev->pdev->subsystem_vendor == 0x106b) &&
2017             (dev->pdev->subsystem_device == 0x0080)) {
2018                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2019                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2020
2021                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2022                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2023
2024                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2025                 }
2026         }
2027
2028         /* set scaler clears this on some chips */
2029         if (ASIC_IS_AVIVO(rdev) &&
2030             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2031                 if (ASIC_IS_DCE8(rdev)) {
2032                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2033                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2034                                        CIK_INTERLEAVE_EN);
2035                         else
2036                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2037                 } else if (ASIC_IS_DCE4(rdev)) {
2038                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2039                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2040                                        EVERGREEN_INTERLEAVE_EN);
2041                         else
2042                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2043                 } else {
2044                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2045                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2046                                        AVIVO_D1MODE_INTERLEAVE_EN);
2047                         else
2048                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2049                 }
2050         }
2051 }
2052
2053 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2054 {
2055         struct drm_device *dev = encoder->dev;
2056         struct radeon_device *rdev = dev->dev_private;
2057         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2058         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2059         struct drm_encoder *test_encoder;
2060         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2061         uint32_t dig_enc_in_use = 0;
2062
2063         if (ASIC_IS_DCE6(rdev)) {
2064                 /* DCE6 */
2065                 switch (radeon_encoder->encoder_id) {
2066                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2067                         if (dig->linkb)
2068                                 return 1;
2069                         else
2070                                 return 0;
2071                         break;
2072                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2073                         if (dig->linkb)
2074                                 return 3;
2075                         else
2076                                 return 2;
2077                         break;
2078                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2079                         if (dig->linkb)
2080                                 return 5;
2081                         else
2082                                 return 4;
2083                         break;
2084                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2085                         return 6;
2086                         break;
2087                 }
2088         } else if (ASIC_IS_DCE4(rdev)) {
2089                 /* DCE4/5 */
2090                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2091                         /* ontario follows DCE4 */
2092                         if (rdev->family == CHIP_PALM) {
2093                                 if (dig->linkb)
2094                                         return 1;
2095                                 else
2096                                         return 0;
2097                         } else
2098                                 /* llano follows DCE3.2 */
2099                                 return radeon_crtc->crtc_id;
2100                 } else {
2101                         switch (radeon_encoder->encoder_id) {
2102                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2103                                 if (dig->linkb)
2104                                         return 1;
2105                                 else
2106                                         return 0;
2107                                 break;
2108                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2109                                 if (dig->linkb)
2110                                         return 3;
2111                                 else
2112                                         return 2;
2113                                 break;
2114                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2115                                 if (dig->linkb)
2116                                         return 5;
2117                                 else
2118                                         return 4;
2119                                 break;
2120                         }
2121                 }
2122         }
2123
2124         /* on DCE32 and encoder can driver any block so just crtc id */
2125         if (ASIC_IS_DCE32(rdev)) {
2126                 return radeon_crtc->crtc_id;
2127         }
2128
2129         /* on DCE3 - LVTMA can only be driven by DIGB */
2130         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2131                 struct radeon_encoder *radeon_test_encoder;
2132
2133                 if (encoder == test_encoder)
2134                         continue;
2135
2136                 if (!radeon_encoder_is_digital(test_encoder))
2137                         continue;
2138
2139                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2140                 dig = radeon_test_encoder->enc_priv;
2141
2142                 if (dig->dig_encoder >= 0)
2143                         dig_enc_in_use |= (1 << dig->dig_encoder);
2144         }
2145
2146         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2147                 if (dig_enc_in_use & 0x2)
2148                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2149                 return 1;
2150         }
2151         if (!(dig_enc_in_use & 1))
2152                 return 0;
2153         return 1;
2154 }
2155
2156 /* This only needs to be called once at startup */
2157 void
2158 radeon_atom_encoder_init(struct radeon_device *rdev)
2159 {
2160         struct drm_device *dev = rdev->ddev;
2161         struct drm_encoder *encoder;
2162
2163         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2164                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2165                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2166
2167                 switch (radeon_encoder->encoder_id) {
2168                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2169                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2170                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2171                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2172                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2173                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2174                         break;
2175                 default:
2176                         break;
2177                 }
2178
2179                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2180                         atombios_external_encoder_setup(encoder, ext_encoder,
2181                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2182         }
2183 }
2184
2185 static void
2186 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2187                              struct drm_display_mode *mode,
2188                              struct drm_display_mode *adjusted_mode)
2189 {
2190         struct drm_device *dev = encoder->dev;
2191         struct radeon_device *rdev = dev->dev_private;
2192         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2193
2194         radeon_encoder->pixel_clock = adjusted_mode->clock;
2195
2196         /* need to call this here rather than in prepare() since we need some crtc info */
2197         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2198
2199         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2200                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2201                         atombios_yuv_setup(encoder, true);
2202                 else
2203                         atombios_yuv_setup(encoder, false);
2204         }
2205
2206         switch (radeon_encoder->encoder_id) {
2207         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2208         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2209         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2210         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2211                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2212                 break;
2213         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2214         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2215         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2216         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2217         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2218                 /* handled in dpms */
2219                 break;
2220         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2221         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2222         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2223                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2224                 break;
2225         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2226         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2227         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2228         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2229                 atombios_dac_setup(encoder, ATOM_ENABLE);
2230                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2231                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2232                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2233                         else
2234                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2235                 }
2236                 break;
2237         }
2238
2239         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2240
2241         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2242                 if (rdev->asic->display.hdmi_enable)
2243                         radeon_hdmi_enable(rdev, encoder, true);
2244                 if (rdev->asic->display.hdmi_setmode)
2245                         radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2246         }
2247 }
2248
2249 static bool
2250 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2251 {
2252         struct drm_device *dev = encoder->dev;
2253         struct radeon_device *rdev = dev->dev_private;
2254         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2255         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2256
2257         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2258                                        ATOM_DEVICE_CV_SUPPORT |
2259                                        ATOM_DEVICE_CRT_SUPPORT)) {
2260                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2261                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2262                 uint8_t frev, crev;
2263
2264                 memset(&args, 0, sizeof(args));
2265
2266                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2267                         return false;
2268
2269                 args.sDacload.ucMisc = 0;
2270
2271                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2272                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2273                         args.sDacload.ucDacType = ATOM_DAC_A;
2274                 else
2275                         args.sDacload.ucDacType = ATOM_DAC_B;
2276
2277                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2278                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2279                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2280                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2281                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2282                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2283                         if (crev >= 3)
2284                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2285                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2286                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2287                         if (crev >= 3)
2288                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2289                 }
2290
2291                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2292
2293                 return true;
2294         } else
2295                 return false;
2296 }
2297
2298 static enum drm_connector_status
2299 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2300 {
2301         struct drm_device *dev = encoder->dev;
2302         struct radeon_device *rdev = dev->dev_private;
2303         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2304         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2305         uint32_t bios_0_scratch;
2306
2307         if (!atombios_dac_load_detect(encoder, connector)) {
2308                 DRM_DEBUG_KMS("detect returned false \n");
2309                 return connector_status_unknown;
2310         }
2311
2312         if (rdev->family >= CHIP_R600)
2313                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2314         else
2315                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2316
2317         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2318         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2319                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2320                         return connector_status_connected;
2321         }
2322         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2323                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2324                         return connector_status_connected;
2325         }
2326         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2327                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2328                         return connector_status_connected;
2329         }
2330         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2331                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2332                         return connector_status_connected; /* CTV */
2333                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2334                         return connector_status_connected; /* STV */
2335         }
2336         return connector_status_disconnected;
2337 }
2338
2339 static enum drm_connector_status
2340 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2341 {
2342         struct drm_device *dev = encoder->dev;
2343         struct radeon_device *rdev = dev->dev_private;
2344         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2345         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2346         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2347         u32 bios_0_scratch;
2348
2349         if (!ASIC_IS_DCE4(rdev))
2350                 return connector_status_unknown;
2351
2352         if (!ext_encoder)
2353                 return connector_status_unknown;
2354
2355         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2356                 return connector_status_unknown;
2357
2358         /* load detect on the dp bridge */
2359         atombios_external_encoder_setup(encoder, ext_encoder,
2360                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2361
2362         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2363
2364         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2365         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2366                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2367                         return connector_status_connected;
2368         }
2369         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2370                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2371                         return connector_status_connected;
2372         }
2373         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2374                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2375                         return connector_status_connected;
2376         }
2377         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2378                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2379                         return connector_status_connected; /* CTV */
2380                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2381                         return connector_status_connected; /* STV */
2382         }
2383         return connector_status_disconnected;
2384 }
2385
2386 void
2387 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2388 {
2389         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2390
2391         if (ext_encoder)
2392                 /* ddc_setup on the dp bridge */
2393                 atombios_external_encoder_setup(encoder, ext_encoder,
2394                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2395
2396 }
2397
2398 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2399 {
2400         struct radeon_device *rdev = encoder->dev->dev_private;
2401         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2402         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2403
2404         if ((radeon_encoder->active_device &
2405              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2406             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2407              ENCODER_OBJECT_ID_NONE)) {
2408                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2409                 if (dig) {
2410                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2411                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2412                                 if (rdev->family >= CHIP_R600)
2413                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2414                                 else
2415                                         /* RS600/690/740 have only 1 afmt block */
2416                                         dig->afmt = rdev->mode_info.afmt[0];
2417                         }
2418                 }
2419         }
2420
2421         radeon_atom_output_lock(encoder, true);
2422
2423         if (connector) {
2424                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2425
2426                 /* select the clock/data port if it uses a router */
2427                 if (radeon_connector->router.cd_valid)
2428                         radeon_router_select_cd_port(radeon_connector);
2429
2430                 /* turn eDP panel on for mode set */
2431                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2432                         atombios_set_edp_panel_power(connector,
2433                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2434         }
2435
2436         /* this is needed for the pll/ss setup to work correctly in some cases */
2437         atombios_set_encoder_crtc_source(encoder);
2438         /* set up the FMT blocks */
2439         if (ASIC_IS_DCE8(rdev))
2440                 dce8_program_fmt(encoder);
2441         else if (ASIC_IS_DCE4(rdev))
2442                 dce4_program_fmt(encoder);
2443         else if (ASIC_IS_DCE3(rdev))
2444                 dce3_program_fmt(encoder);
2445         else if (ASIC_IS_AVIVO(rdev))
2446                 avivo_program_fmt(encoder);
2447 }
2448
2449 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2450 {
2451         /* need to call this here as we need the crtc set up */
2452         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2453         radeon_atom_output_lock(encoder, false);
2454 }
2455
2456 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2457 {
2458         struct drm_device *dev = encoder->dev;
2459         struct radeon_device *rdev = dev->dev_private;
2460         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2461         struct radeon_encoder_atom_dig *dig;
2462
2463         /* check for pre-DCE3 cards with shared encoders;
2464          * can't really use the links individually, so don't disable
2465          * the encoder if it's in use by another connector
2466          */
2467         if (!ASIC_IS_DCE3(rdev)) {
2468                 struct drm_encoder *other_encoder;
2469                 struct radeon_encoder *other_radeon_encoder;
2470
2471                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2472                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2473                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2474                             drm_helper_encoder_in_use(other_encoder))
2475                                 goto disable_done;
2476                 }
2477         }
2478
2479         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2480
2481         switch (radeon_encoder->encoder_id) {
2482         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2483         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2484         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2485         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2486                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2487                 break;
2488         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2489         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2490         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2491         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2492         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2493                 /* handled in dpms */
2494                 break;
2495         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2496         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2497         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2498                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2499                 break;
2500         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2501         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2502         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2503         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2504                 atombios_dac_setup(encoder, ATOM_DISABLE);
2505                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2506                         atombios_tv_setup(encoder, ATOM_DISABLE);
2507                 break;
2508         }
2509
2510 disable_done:
2511         if (radeon_encoder_is_digital(encoder)) {
2512                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2513                         if (rdev->asic->display.hdmi_enable)
2514                                 radeon_hdmi_enable(rdev, encoder, false);
2515                 }
2516                 dig = radeon_encoder->enc_priv;
2517                 dig->dig_encoder = -1;
2518         }
2519         radeon_encoder->active_device = 0;
2520 }
2521
2522 /* these are handled by the primary encoders */
2523 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2524 {
2525
2526 }
2527
2528 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2529 {
2530
2531 }
2532
2533 static void
2534 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2535                          struct drm_display_mode *mode,
2536                          struct drm_display_mode *adjusted_mode)
2537 {
2538
2539 }
2540
2541 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2542 {
2543
2544 }
2545
2546 static void
2547 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2548 {
2549
2550 }
2551
2552 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2553                                        const struct drm_display_mode *mode,
2554                                        struct drm_display_mode *adjusted_mode)
2555 {
2556         return true;
2557 }
2558
2559 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2560         .dpms = radeon_atom_ext_dpms,
2561         .mode_fixup = radeon_atom_ext_mode_fixup,
2562         .prepare = radeon_atom_ext_prepare,
2563         .mode_set = radeon_atom_ext_mode_set,
2564         .commit = radeon_atom_ext_commit,
2565         .disable = radeon_atom_ext_disable,
2566         /* no detect for TMDS/LVDS yet */
2567 };
2568
2569 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2570         .dpms = radeon_atom_encoder_dpms,
2571         .mode_fixup = radeon_atom_mode_fixup,
2572         .prepare = radeon_atom_encoder_prepare,
2573         .mode_set = radeon_atom_encoder_mode_set,
2574         .commit = radeon_atom_encoder_commit,
2575         .disable = radeon_atom_encoder_disable,
2576         .detect = radeon_atom_dig_detect,
2577 };
2578
2579 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2580         .dpms = radeon_atom_encoder_dpms,
2581         .mode_fixup = radeon_atom_mode_fixup,
2582         .prepare = radeon_atom_encoder_prepare,
2583         .mode_set = radeon_atom_encoder_mode_set,
2584         .commit = radeon_atom_encoder_commit,
2585         .detect = radeon_atom_dac_detect,
2586 };
2587
2588 void radeon_enc_destroy(struct drm_encoder *encoder)
2589 {
2590         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2591         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2592                 radeon_atom_backlight_exit(radeon_encoder);
2593         kfree(radeon_encoder->enc_priv);
2594         drm_encoder_cleanup(encoder);
2595         kfree(radeon_encoder);
2596 }
2597
2598 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2599         .destroy = radeon_enc_destroy,
2600 };
2601
2602 static struct radeon_encoder_atom_dac *
2603 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2604 {
2605         struct drm_device *dev = radeon_encoder->base.dev;
2606         struct radeon_device *rdev = dev->dev_private;
2607         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2608
2609         if (!dac)
2610                 return NULL;
2611
2612         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2613         return dac;
2614 }
2615
2616 static struct radeon_encoder_atom_dig *
2617 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2618 {
2619         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2620         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2621
2622         if (!dig)
2623                 return NULL;
2624
2625         /* coherent mode by default */
2626         dig->coherent_mode = true;
2627         dig->dig_encoder = -1;
2628
2629         if (encoder_enum == 2)
2630                 dig->linkb = true;
2631         else
2632                 dig->linkb = false;
2633
2634         return dig;
2635 }
2636
2637 void
2638 radeon_add_atom_encoder(struct drm_device *dev,
2639                         uint32_t encoder_enum,
2640                         uint32_t supported_device,
2641                         u16 caps)
2642 {
2643         struct radeon_device *rdev = dev->dev_private;
2644         struct drm_encoder *encoder;
2645         struct radeon_encoder *radeon_encoder;
2646
2647         /* see if we already added it */
2648         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2649                 radeon_encoder = to_radeon_encoder(encoder);
2650                 if (radeon_encoder->encoder_enum == encoder_enum) {
2651                         radeon_encoder->devices |= supported_device;
2652                         return;
2653                 }
2654
2655         }
2656
2657         /* add a new one */
2658         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2659         if (!radeon_encoder)
2660                 return;
2661
2662         encoder = &radeon_encoder->base;
2663         switch (rdev->num_crtc) {
2664         case 1:
2665                 encoder->possible_crtcs = 0x1;
2666                 break;
2667         case 2:
2668         default:
2669                 encoder->possible_crtcs = 0x3;
2670                 break;
2671         case 4:
2672                 encoder->possible_crtcs = 0xf;
2673                 break;
2674         case 6:
2675                 encoder->possible_crtcs = 0x3f;
2676                 break;
2677         }
2678
2679         radeon_encoder->enc_priv = NULL;
2680
2681         radeon_encoder->encoder_enum = encoder_enum;
2682         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2683         radeon_encoder->devices = supported_device;
2684         radeon_encoder->rmx_type = RMX_OFF;
2685         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2686         radeon_encoder->is_ext_encoder = false;
2687         radeon_encoder->caps = caps;
2688
2689         switch (radeon_encoder->encoder_id) {
2690         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2691         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2692         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2693         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2694                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2695                         radeon_encoder->rmx_type = RMX_FULL;
2696                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2697                                          DRM_MODE_ENCODER_LVDS, NULL);
2698                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2699                 } else {
2700                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2701                                          DRM_MODE_ENCODER_TMDS, NULL);
2702                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2703                 }
2704                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2705                 break;
2706         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2707                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2708                                  DRM_MODE_ENCODER_DAC, NULL);
2709                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2710                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2711                 break;
2712         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2713         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2714         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2715                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2716                                  DRM_MODE_ENCODER_TVDAC, NULL);
2717                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2718                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2719                 break;
2720         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2721         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2722         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2723         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2724         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2725         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2726         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2727         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2728                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2729                         radeon_encoder->rmx_type = RMX_FULL;
2730                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2731                                          DRM_MODE_ENCODER_LVDS, NULL);
2732                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2733                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2734                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2735                                          DRM_MODE_ENCODER_DAC, NULL);
2736                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2737                 } else {
2738                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2739                                          DRM_MODE_ENCODER_TMDS, NULL);
2740                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2741                 }
2742                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2743                 break;
2744         case ENCODER_OBJECT_ID_SI170B:
2745         case ENCODER_OBJECT_ID_CH7303:
2746         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2747         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2748         case ENCODER_OBJECT_ID_TITFP513:
2749         case ENCODER_OBJECT_ID_VT1623:
2750         case ENCODER_OBJECT_ID_HDMI_SI1930:
2751         case ENCODER_OBJECT_ID_TRAVIS:
2752         case ENCODER_OBJECT_ID_NUTMEG:
2753                 /* these are handled by the primary encoders */
2754                 radeon_encoder->is_ext_encoder = true;
2755                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2756                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2757                                          DRM_MODE_ENCODER_LVDS, NULL);
2758                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2759                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2760                                          DRM_MODE_ENCODER_DAC, NULL);
2761                 else
2762                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2763                                          DRM_MODE_ENCODER_TMDS, NULL);
2764                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2765                 break;
2766         }
2767 }