2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
19 #if defined(__DragonFly__)
20 #include "ahci_dragonfly.h"
22 #error "build for OS unknown"
26 /* change to AHCI_DEBUG for dmesg spam */
30 #define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \
32 #define AHCI_D_TIMEOUT 0x00
33 #define AHCI_D_VERBOSE 0x01
34 #define AHCI_D_INTR 0x02
35 #define AHCI_D_XFER 0x08
36 int ahcidebug = AHCI_D_VERBOSE;
38 #define DPRINTF(m, f...)
41 #define AHCI_PCI_BAR 0x24
42 #define AHCI_PCI_ATI_SB600_MAGIC 0x40
43 #define AHCI_PCI_ATI_SB600_LOCKED 0x01
44 #define AHCI_PCI_INTERFACE 0x01
46 #define AHCI_REG_CAP 0x000 /* HBA Capabilities */
47 #define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */
48 #define AHCI_REG_CAP_SXS (1<<5) /* External SATA */
49 #define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */
50 #define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */
51 #define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/
52 #define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */
53 #define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */
54 #define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */
55 #define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching */
56 #define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */
57 #define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */
58 #define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */
59 #define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */
60 #define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */
61 #define AHCI_REG_CAP_ISS_G1_2 (0x2<<20) /* Gen 1 and 2 (3 Gbps) */
62 #define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */
63 #define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */
64 #define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */
65 #define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */
66 #define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */
67 #define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */
68 #define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */
69 #define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */
70 #define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \
71 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \
72 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \
73 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \
74 "\010CCCS" "\007EMS" "\006SXS"
76 #define AHCI_REG_GHC 0x004 /* Global HBA Control */
77 #define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */
78 #define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */
79 #define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */
80 #define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */
81 #define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR"
83 #define AHCI_REG_IS 0x008 /* Interrupt Status */
84 #define AHCI_REG_PI 0x00c /* Ports Implemented */
86 #define AHCI_REG_VS 0x010 /* AHCI Version */
87 #define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */
88 #define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */
89 #define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */
90 #define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */
92 #define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */
93 #define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */
95 #define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */
96 #define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */
97 #define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */
99 #define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80))
100 #define AHCI_PORT_SIZE 0x80
102 #define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */
103 #define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */
104 #define AHCI_PREG_FB 0x08 /* FIS Base Addr */
105 #define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */
107 #define AHCI_PREG_IS 0x10 /* Interrupt Status */
108 #define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */
109 #define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */
110 #define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */
111 #define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */
112 #define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */
113 #define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */
114 #define AHCI_PREG_IS_PCS (1<<6) /* Port Change */
115 #define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */
116 #define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */
117 #define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */
118 #define AHCI_PREG_IS_OFS (1<<24) /* Overflow */
119 #define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */
120 #define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */
121 #define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */
122 #define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */
123 #define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */
124 #define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */
125 #define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \
126 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \
127 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \
128 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \
131 #define AHCI_PREG_IE 0x14 /* Interrupt Enable */
132 #define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */
133 #define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */
134 #define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */
135 #define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */
136 #define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */
137 #define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */
138 #define AHCI_PREG_IE_PCE (1<<6) /* Port Change */
139 #define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */
140 #define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */
141 #define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */
142 #define AHCI_PREG_IE_OFE (1<<24) /* Overflow */
143 #define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */
144 #define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */
145 #define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */
146 #define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */
147 #define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */
148 #define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */
149 #define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \
150 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \
151 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \
152 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \
155 #define AHCI_PREG_CMD 0x18 /* Command and Status */
156 #define AHCI_PREG_CMD_ST (1<<0) /* Start */
157 #define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */
158 #define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */
159 #define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */
160 #define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */
161 #define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */
162 #define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */
163 #define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */
164 #define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */
165 #define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */
166 #define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */
167 #define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */
168 #define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */
169 #define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */
170 #define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */
171 #define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */
172 #define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */
173 #define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */
174 #define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */
175 #define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */
176 #define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000
177 #define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000
178 #define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000
179 #define AHCI_PREG_CMD_ICC_IDLE 0x00000000
180 #define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \
181 "\031ATAPI" "\026ESP" "\025CPD" "\024MPSP" \
182 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \
183 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \
184 "\003POD" "\002SUD" "\001ST"
186 #define AHCI_PREG_TFD 0x20 /* Task File Data*/
187 #define AHCI_PREG_TFD_STS 0xff
188 #define AHCI_PREG_TFD_STS_ERR (1<<0)
189 #define AHCI_PREG_TFD_STS_DRQ (1<<3)
190 #define AHCI_PREG_TFD_STS_BSY (1<<7)
191 #define AHCI_PREG_TFD_ERR 0xff00
193 #define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR"
194 #define AHCI_PREG_SIG 0x24 /* Signature */
196 #define AHCI_PREG_SSTS 0x28 /* SATA Status */
197 #define AHCI_PREG_SSTS_DET 0xf /* Device Detection */
198 #define AHCI_PREG_SSTS_DET_NONE 0x0
199 #define AHCI_PREG_SSTS_DET_DEV_NE 0x1
200 #define AHCI_PREG_SSTS_DET_DEV 0x3
201 #define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4
202 #define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */
203 #define AHCI_PREG_SSTS_SPD_NONE 0x00
204 #define AHCI_PREG_SSTS_SPD_GEN1 0x10
205 #define AHCI_PREG_SSTS_SPD_GEN2 0x20
206 #define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */
207 #define AHCI_PREG_SSTS_IPM_NONE 0x000
208 #define AHCI_PREG_SSTS_IPM_ACTIVE 0x100
209 #define AHCI_PREG_SSTS_IPM_PARTIAL 0x200
210 #define AHCI_PREG_SSTS_IPM_SLUMBER 0x600
212 #define AHCI_PREG_SCTL 0x2c /* SATA Control */
213 #define AHCI_PREG_SCTL_DET 0xf /* Device Detection */
214 #define AHCI_PREG_SCTL_DET_NONE 0x0
215 #define AHCI_PREG_SCTL_DET_INIT 0x1
216 #define AHCI_PREG_SCTL_DET_DISABLE 0x4
217 #define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */
218 #define AHCI_PREG_SCTL_SPD_ANY 0x00
219 #define AHCI_PREG_SCTL_SPD_GEN1 0x10
220 #define AHCI_PREG_SCTL_SPD_GEN2 0x20
221 #define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */
222 #define AHCI_PREG_SCTL_IPM_NONE 0x000
223 #define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100
224 #define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200
225 #define AHCI_PREG_SCTL_IPM_DISABLED 0x300
227 #define AHCI_PREG_SERR 0x30 /* SATA Error */
228 #define AHCI_PREG_SERR_ERR(_r) ((_r) & 0xffff)
229 #define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */
230 #define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */
231 #define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */
232 #define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */
233 #define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */
234 #define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */
235 #define AHCI_PFMT_SERR_ERR "\020" "\014E" "\013P" "\012C" "\011T" "\002M" \
237 #define AHCI_PREG_SERR_DIAG(_r) (((_r) >> 16) & 0xffff)
238 #define AHCI_PREG_SERR_DIAG_N (1<<0) /* PhyRdy Change */
239 #define AHCI_PREG_SERR_DIAG_I (1<<1) /* Phy Internal Error */
240 #define AHCI_PREG_SERR_DIAG_W (1<<2) /* Comm Wake */
241 #define AHCI_PREG_SERR_DIAG_B (1<<3) /* 10B to 8B Decode Error */
242 #define AHCI_PREG_SERR_DIAG_D (1<<4) /* Disparity Error */
243 #define AHCI_PREG_SERR_DIAG_C (1<<5) /* CRC Error */
244 #define AHCI_PREG_SERR_DIAG_H (1<<6) /* Handshake Error */
245 #define AHCI_PREG_SERR_DIAG_S (1<<7) /* Link Sequence Error */
246 #define AHCI_PREG_SERR_DIAG_T (1<<8) /* Transport State Trans Err */
247 #define AHCI_PREG_SERR_DIAG_F (1<<9) /* Unknown FIS Type */
248 #define AHCI_PREG_SERR_DIAG_X (1<<10) /* Exchanged */
249 #define AHCI_PFMT_SERR_DIAG "\020" "\013X" "\012F" "\011T" "\010S" "\007H" \
250 "\006C" "\005D" "\004B" "\003W" "\002I" \
253 #define AHCI_PREG_SACT 0x34 /* SATA Active */
254 #define AHCI_PREG_CI 0x38 /* Command Issue */
255 #define AHCI_PREG_CI_ALL_SLOTS 0xffffffff
256 #define AHCI_PREG_SNTF 0x3c /* SNotification */
258 struct ahci_cmd_hdr {
260 #define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */
261 #define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */
262 #define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */
263 #define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */
264 #define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */
265 #define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */
266 #define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */
267 #define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */
268 u_int16_t prdtl; /* sgl len */
270 u_int32_t prdbc; /* transferred byte count */
275 u_int32_t reserved[4];
280 u_int8_t reserved1[4];
282 u_int8_t reserved2[8];
284 u_int8_t reserved3[4];
287 u_int8_t reserved4[96];
295 #define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */
299 * The base command table structure is 128 bytes. Each prdt is 16 bytes.
300 * We need to accomodate MAXPHYS (128K) which is at least 32 entries,
301 * plus one for page slop.
303 * Making the ahci_cmd_table 1024 bytes (a reasonable power of 2)
304 * thus requires MAX_PRDT to be set to 56.
306 #define AHCI_MAX_PRDT 56
308 #if MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT
309 #error "AHCI_MAX_PRDT is not big enough"
312 struct ahci_cmd_table {
313 u_int8_t cfis[64]; /* Command FIS */
314 u_int8_t acmd[16]; /* ATAPI Command */
315 u_int8_t reserved[48];
317 struct ahci_prdt prdt[AHCI_MAX_PRDT];
320 #define AHCI_MAX_PORTS 32
323 bus_dma_tag_t adm_tag;
324 bus_dmamap_t adm_map;
325 bus_dma_segment_t adm_seg;
326 bus_addr_t adm_busaddr;
329 #define AHCI_DMA_MAP(_adm) ((_adm)->adm_map)
330 #define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr)
331 #define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva)
338 /* ATA xfer associated with this CCB. Must be 1st struct member. */
339 struct ata_xfer ccb_xa;
340 struct callout ccb_timeout;
343 struct ahci_port *ccb_port;
345 bus_dmamap_t ccb_dmamap;
346 struct ahci_cmd_hdr *ccb_cmd_hdr;
347 struct ahci_cmd_table *ccb_cmd_table;
349 void (*ccb_done)(struct ahci_ccb *);
351 TAILQ_ENTRY(ahci_ccb) ccb_entry;
355 struct ahci_softc *ap_sc;
356 bus_space_handle_t ap_ioh;
360 #define AP_F_BUS_REGISTERED 0x0001
361 #define AP_F_CAM_ATTACHED 0x0002
362 struct cam_sim *ap_sim;
363 struct cam_path *ap_path;
365 struct ahci_rfis *ap_rfis;
366 struct ahci_dmamem *ap_dmamem_rfis;
368 struct ahci_dmamem *ap_dmamem_cmd_list;
369 struct ahci_dmamem *ap_dmamem_cmd_table;
371 volatile u_int32_t ap_active;
372 volatile u_int32_t ap_active_cnt;
373 volatile u_int32_t ap_sactive;
374 struct ahci_ccb *ap_ccbs;
376 TAILQ_HEAD(, ahci_ccb) ap_ccb_free;
377 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending;
378 struct lock ap_ccb_lock;
380 struct ata_port ap_ata;
383 #define AP_S_NORMAL 0
384 #define AP_S_FATAL_ERROR 1
386 /* For error recovery. */
390 u_int32_t ap_err_saved_sactive;
391 u_int32_t ap_err_saved_active;
392 u_int32_t ap_err_saved_active_cnt;
394 u_int8_t ap_err_scratch[512];
399 #define PORTNAME(_ap) ((_ap)->ap_name)
403 const struct ahci_device *sc_ad; /* special casing */
404 struct lwkt_serialize sc_serializer;
406 struct resource *sc_irq; /* bus resources */
407 struct resource *sc_regs; /* bus resources */
408 bus_space_tag_t sc_iot; /* split from sc_regs */
409 bus_space_handle_t sc_ioh; /* split from sc_regs */
411 int sc_rid_irq; /* saved bus RIDs */
413 u_int32_t sc_cap; /* capabilities */
415 void *sc_irq_handle; /* installed irq vector */
417 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */
418 bus_dma_tag_t sc_tag_cmdh;
419 bus_dma_tag_t sc_tag_cmdt;
420 bus_dma_tag_t sc_tag_data;
423 #define AHCI_F_NO_NCQ (1<<0)
424 #define AHCI_F_IGN_FR (1<<1)
428 struct ahci_port *sc_ports[AHCI_MAX_PORTS];
431 u_int32_t sc_ccc_mask;
432 u_int32_t sc_ccc_ports;
433 u_int32_t sc_ccc_ports_cur;
436 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname)
439 pci_vendor_id_t ad_vendor;
440 pci_product_id_t ad_product;
441 int (*ad_attach)(device_t dev);
442 int (*ad_detach)(device_t dev);
446 const struct ahci_device *ahci_lookup_device(device_t dev);
447 int ahci_init(struct ahci_softc *);
448 int ahci_port_alloc(struct ahci_softc *, u_int);
449 void ahci_port_free(struct ahci_softc *, u_int);
450 int ahci_port_softreset(struct ahci_port *);
451 int ahci_port_portreset(struct ahci_port *);
453 u_int32_t ahci_read(struct ahci_softc *, bus_size_t);
454 void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t);
455 int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t);
456 u_int32_t ahci_pread(struct ahci_port *, bus_size_t);
457 void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t);
458 int ahci_pwait_eq(struct ahci_port *, int, bus_size_t,
459 u_int32_t, u_int32_t);
460 void ahci_intr(void *);
462 int ahci_cam_attach(struct ahci_port *ap);
463 void ahci_cam_changed(struct ahci_port *ap, int found);
464 void ahci_cam_detach(struct ahci_port *ap);
466 struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap);
467 void ahci_ata_put_xfer(struct ata_xfer *xa);
468 int ahci_ata_cmd(struct ata_xfer *xa);
470 extern u_int32_t AhciForceGen1;