2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/md_var.h>
35 #include <machine/pmap.h>
36 #include <machine_base/apic/mpapic.h>
37 #include <machine/segments.h>
38 #include <sys/thread2.h>
40 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
44 /* EISA Edge/Level trigger control registers */
45 #define ELCR0 0x4d0 /* eisa irq 0-7 */
46 #define ELCR1 0x4d1 /* eisa irq 8-15 */
48 volatile lapic_t *lapic;
50 static void lapic_timer_calibrate(void);
51 static void lapic_timer_set_divisor(int);
52 static void lapic_timer_fixup_handler(void *);
53 static void lapic_timer_restart_handler(void *);
55 void lapic_timer_process(void);
56 void lapic_timer_process_frame(struct intrframe *);
57 void lapic_timer_always(struct intrframe *);
59 static int lapic_timer_enable = 1;
60 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
62 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
63 static void lapic_timer_intr_enable(struct cputimer_intr *);
64 static void lapic_timer_intr_restart(struct cputimer_intr *);
65 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
67 static struct cputimer_intr lapic_cputimer_intr = {
69 .reload = lapic_timer_intr_reload,
70 .enable = lapic_timer_intr_enable,
71 .config = cputimer_intr_default_config,
72 .restart = lapic_timer_intr_restart,
73 .pmfixup = lapic_timer_intr_pmfixup,
74 .initclock = cputimer_intr_default_initclock,
75 .next = SLIST_ENTRY_INITIALIZER,
77 .type = CPUTIMER_INTR_LAPIC,
78 .prio = CPUTIMER_INTR_PRIO_LAPIC,
79 .caps = CPUTIMER_INTR_CAP_NONE
83 * pointers to pmapped apic hardware.
86 volatile ioapic_t **ioapic;
88 static int lapic_timer_divisor_idx = -1;
89 static const uint32_t lapic_timer_divisors[] = {
90 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
91 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
93 #define APIC_TIMER_NDIVISORS \
94 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
105 * Enable APIC, configure interrupts.
108 apic_initialize(boolean_t bsp)
114 * setup LVT1 as ExtINT on the BSP. This is theoretically an
115 * aggregate interrupt input from the 8259. The INTA cycle
116 * will be routed to the external controller (the 8259) which
117 * is expected to supply the vector.
119 * Must be setup edge triggered, active high.
121 * Disable LVT1 on the APs. It doesn't matter what delivery
122 * mode we use because we leave it masked.
124 temp = lapic->lvt_lint0;
125 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
126 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
127 if (mycpu->gd_cpuid == 0)
128 temp |= APIC_LVT_DM_EXTINT;
130 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
131 lapic->lvt_lint0 = temp;
134 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
136 temp = lapic->lvt_lint1;
137 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
138 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
139 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
140 lapic->lvt_lint1 = temp;
143 * Mask the apic error interrupt, apic performance counter
146 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
147 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
149 /* Set apic timer vector and mask the apic timer interrupt. */
150 timer = lapic->lvt_timer;
151 timer &= ~APIC_LVTT_VECTOR;
152 timer |= XTIMER_OFFSET;
153 timer |= APIC_LVTT_MASKED;
154 lapic->lvt_timer = timer;
157 * Set the Task Priority Register as needed. At the moment allow
158 * interrupts on all cpus (the APs will remain CLId until they are
159 * ready to deal). We could disable all but IPIs by setting
160 * temp |= TPR_IPI for cpu != 0.
163 temp &= ~APIC_TPR_PRIO; /* clear priority field */
164 #ifdef SMP /* APIC-IO */
165 if (!apic_io_enable) {
168 * If we are NOT running the IO APICs, the LAPIC will only be used
169 * for IPIs. Set the TPR to prevent any unintentional interrupts.
172 #ifdef SMP /* APIC-IO */
178 * enable the local APIC
181 temp |= APIC_SVR_ENABLE; /* enable the APIC */
182 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
185 * Set the spurious interrupt vector. The low 4 bits of the vector
188 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
189 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
190 temp &= ~APIC_SVR_VECTOR;
191 temp |= XSPURIOUSINT_OFFSET;
196 * Pump out a few EOIs to clean out interrupts that got through
197 * before we were able to set the TPR.
204 lapic_timer_calibrate();
205 if (lapic_timer_enable) {
206 cputimer_intr_register(&lapic_cputimer_intr);
207 cputimer_intr_select(&lapic_cputimer_intr, 0);
210 lapic_timer_set_divisor(lapic_timer_divisor_idx);
214 apic_dump("apic_initialize()");
219 lapic_timer_set_divisor(int divisor_idx)
221 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
222 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
226 lapic_timer_oneshot(u_int count)
230 value = lapic->lvt_timer;
231 value &= ~APIC_LVTT_PERIODIC;
232 lapic->lvt_timer = value;
233 lapic->icr_timer = count;
237 lapic_timer_oneshot_quick(u_int count)
239 lapic->icr_timer = count;
243 lapic_timer_calibrate(void)
247 /* Try to calibrate the local APIC timer. */
248 for (lapic_timer_divisor_idx = 0;
249 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
250 lapic_timer_divisor_idx++) {
251 lapic_timer_set_divisor(lapic_timer_divisor_idx);
252 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
254 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
255 if (value != APIC_TIMER_MAX_COUNT)
258 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
259 panic("lapic: no proper timer divisor?!\n");
260 lapic_cputimer_intr.freq = value / 2;
262 kprintf("lapic: divisor index %d, frequency %u Hz\n",
263 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
267 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
271 gd->gd_timer_running = 0;
273 count = sys_cputimer->count();
274 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
275 systimer_intr(&count, 0, frame);
279 lapic_timer_process(void)
281 lapic_timer_process_oncpu(mycpu, NULL);
285 lapic_timer_process_frame(struct intrframe *frame)
287 lapic_timer_process_oncpu(mycpu, frame);
291 * This manual debugging code is called unconditionally from Xtimer
292 * (the lapic timer interrupt) whether the current thread is in a
293 * critical section or not) and can be useful in tracking down lockups.
295 * NOTE: MANUAL DEBUG CODE
298 static int saveticks[SMP_MAXCPU];
299 static int savecounts[SMP_MAXCPU];
303 lapic_timer_always(struct intrframe *frame)
306 globaldata_t gd = mycpu;
307 int cpu = gd->gd_cpuid;
313 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
314 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
317 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
318 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
320 for (i = 0; buf[i]; ++i) {
321 gptr[i] = 0x0700 | (unsigned char)buf[i];
325 if (saveticks[gd->gd_cpuid] != ticks) {
326 saveticks[gd->gd_cpuid] = ticks;
327 savecounts[gd->gd_cpuid] = 0;
329 ++savecounts[gd->gd_cpuid];
330 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
331 panic("cpud %d panicing on ticks failure",
334 for (i = 0; i < ncpus; ++i) {
336 if (saveticks[i] && panicstr == NULL) {
337 delta = saveticks[i] - ticks;
338 if (delta < -10 || delta > 10) {
339 panic("cpu %d panicing on cpu %d watchdog",
349 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
351 struct globaldata *gd = mycpu;
353 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
357 if (gd->gd_timer_running) {
358 if (reload < lapic->ccr_timer)
359 lapic_timer_oneshot_quick(reload);
361 gd->gd_timer_running = 1;
362 lapic_timer_oneshot_quick(reload);
367 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
371 timer = lapic->lvt_timer;
372 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
373 lapic->lvt_timer = timer;
375 lapic_timer_fixup_handler(NULL);
379 lapic_timer_fixup_handler(void *arg)
386 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
388 * Detect the presence of C1E capability mostly on latest
389 * dual-cores (or future) k8 family. This feature renders
390 * the local APIC timer dead, so we disable it by reading
391 * the Interrupt Pending Message register and clearing both
392 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
395 * "BIOS and Kernel Developer's Guide for AMD NPT
396 * Family 0Fh Processors"
397 * #32559 revision 3.00
399 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
400 (cpu_id & 0x0fff0000) >= 0x00040000) {
403 msr = rdmsr(0xc0010055);
404 if (msr & 0x18000000) {
405 struct globaldata *gd = mycpu;
407 kprintf("cpu%d: AMD C1E detected\n",
409 wrmsr(0xc0010055, msr & ~0x18000000ULL);
412 * We are kinda stalled;
415 gd->gd_timer_running = 1;
416 lapic_timer_oneshot_quick(2);
426 lapic_timer_restart_handler(void *dummy __unused)
430 lapic_timer_fixup_handler(&started);
432 struct globaldata *gd = mycpu;
434 gd->gd_timer_running = 1;
435 lapic_timer_oneshot_quick(2);
440 * This function is called only by ACPI-CA code currently:
441 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
442 * module controls PM. So once ACPI-CA is attached, we try
443 * to apply the fixup to prevent LAPIC timer from hanging.
446 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
448 lwkt_send_ipiq_mask(smp_active_mask,
449 lapic_timer_fixup_handler, NULL);
453 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
455 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
460 * dump contents of local APIC registers
465 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
466 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
467 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
471 #ifdef SMP /* APIC-IO */
477 #define IOAPIC_ISA_INTS 16
478 #define REDIRCNT_IOAPIC(A) \
479 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
481 static int trigger (int apic, int pin, u_int32_t * flags);
482 static void polarity (int apic, int pin, u_int32_t * flags, int level);
484 #define DEFAULT_FLAGS \
490 #define DEFAULT_ISA_FLAGS \
499 io_apic_set_id(int apic, int id)
503 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
504 if (((ux & APIC_ID_MASK) >> 24) != id) {
505 kprintf("Changing APIC ID for IO APIC #%d"
506 " from %d to %d on chip\n",
507 apic, ((ux & APIC_ID_MASK) >> 24), id);
508 ux &= ~APIC_ID_MASK; /* clear the ID field */
510 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
511 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
512 if (((ux & APIC_ID_MASK) >> 24) != id)
513 panic("can't control IO APIC #%d ID, reg: 0x%08x",
520 io_apic_get_id(int apic)
522 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
531 io_apic_setup_intpin(int apic, int pin)
533 int bus, bustype, irq;
534 u_char select; /* the select register is 8 bits */
535 u_int32_t flags; /* the window register is 32 bits */
536 u_int32_t target; /* the window register is 32 bits */
537 u_int32_t vector; /* the window register is 32 bits */
542 select = pin * 2 + IOAPIC_REDTBL0; /* register */
545 * Always clear an IO APIC pin before [re]programming it. This is
546 * particularly important if the pin is set up for a level interrupt
547 * as the IOART_REM_IRR bit might be set. When we reprogram the
548 * vector any EOI from pending ints on this pin could be lost and
549 * IRR might never get reset.
551 * To fix this problem, clear the vector and make sure it is
552 * programmed as an edge interrupt. This should theoretically
553 * clear IRR so we can later, safely program it as a level
558 flags = io_apic_read(apic, select) & IOART_RESV;
559 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
560 flags |= IOART_DESTPHY | IOART_DELFIXED;
562 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
563 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
567 io_apic_write(apic, select, flags | vector);
568 io_apic_write(apic, select + 1, target);
573 * We only deal with vectored interrupts here. ? documentation is
574 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
577 * This test also catches unconfigured pins.
579 if (apic_int_type(apic, pin) != 0)
583 * Leave the pin unprogrammed if it does not correspond to
586 irq = apic_irq(apic, pin);
590 /* determine the bus type for this pin */
591 bus = apic_src_bus_id(apic, pin);
594 bustype = apic_bus_type(bus);
596 if ((bustype == ISA) &&
597 (pin < IOAPIC_ISA_INTS) &&
599 (apic_polarity(apic, pin) == 0x1) &&
600 (apic_trigger(apic, pin) == 0x3)) {
602 * A broken BIOS might describe some ISA
603 * interrupts as active-high level-triggered.
604 * Use default ISA flags for those interrupts.
606 flags = DEFAULT_ISA_FLAGS;
609 * Program polarity and trigger mode according to
612 flags = DEFAULT_FLAGS;
613 level = trigger(apic, pin, &flags);
615 int_to_apicintpin[irq].flags |= AIMI_FLAG_LEVEL;
616 polarity(apic, pin, &flags, level);
620 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
621 kgetenv_int(envpath, &cpuid);
623 /* ncpus may not be available yet */
628 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
629 apic, pin, irq, cpuid);
633 * Program the appropriate registers. This routing may be
634 * overridden when an interrupt handler for a device is
635 * actually added (see register_int(), which calls through
636 * the MACHINTR ABI to set up an interrupt handler/vector).
638 * The order in which we must program the two registers for
639 * safety is unclear! XXX
643 vector = IDT_OFFSET + irq; /* IDT vec */
644 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
645 /* Deliver all interrupts to CPU0 (BSP) */
646 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
648 flags |= io_apic_read(apic, select) & IOART_RESV;
649 io_apic_write(apic, select, flags | vector);
650 io_apic_write(apic, select + 1, target);
656 io_apic_setup(int apic)
661 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
662 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
664 for (pin = 0; pin < maxpin; ++pin) {
665 io_apic_setup_intpin(apic, pin);
668 if (apic_int_type(apic, pin) >= 0) {
669 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
670 " cannot program!\n", apic, pin);
675 /* return GOOD status */
678 #undef DEFAULT_ISA_FLAGS
682 #define DEFAULT_EXTINT_FLAGS \
691 * XXX this function is only used by 8254 setup
692 * Setup the source of External INTerrupts.
695 ext_int_setup(int apic, int intr)
697 u_char select; /* the select register is 8 bits */
698 u_int32_t flags; /* the window register is 32 bits */
699 u_int32_t target; /* the window register is 32 bits */
700 u_int32_t vector; /* the window register is 32 bits */
704 if (apic_int_type(apic, intr) != 3)
708 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
709 kgetenv_int(envpath, &cpuid);
711 /* ncpus may not be available yet */
715 /* Deliver interrupts to CPU0 (BSP) */
716 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
718 select = IOAPIC_REDTBL0 + (2 * intr);
719 vector = IDT_OFFSET + intr;
720 flags = DEFAULT_EXTINT_FLAGS;
722 io_apic_write(apic, select, flags | vector);
723 io_apic_write(apic, select + 1, target);
727 #undef DEFAULT_EXTINT_FLAGS
731 * Set the trigger level for an IO APIC pin.
734 trigger(int apic, int pin, u_int32_t * flags)
739 static int intcontrol = -1;
741 switch (apic_trigger(apic, pin)) {
747 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
751 *flags |= IOART_TRGRLVL;
759 if ((id = apic_src_bus_id(apic, pin)) == -1)
762 switch (apic_bus_type(id)) {
764 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
768 eirq = apic_src_bus_irq(apic, pin);
770 if (eirq < 0 || eirq > 15) {
771 kprintf("EISA IRQ %d?!?!\n", eirq);
775 if (intcontrol == -1) {
776 intcontrol = inb(ELCR1) << 8;
777 intcontrol |= inb(ELCR0);
778 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
781 /* Use ELCR settings to determine level or edge mode */
782 level = (intcontrol >> eirq) & 1;
785 * Note that on older Neptune chipset based systems, any
786 * pci interrupts often show up here and in the ELCR as well
787 * as level sensitive interrupts attributed to the EISA bus.
791 *flags |= IOART_TRGRLVL;
793 *flags &= ~IOART_TRGRLVL;
798 *flags |= IOART_TRGRLVL;
807 panic("bad APIC IO INT flags");
812 * Set the polarity value for an IO APIC pin.
815 polarity(int apic, int pin, u_int32_t * flags, int level)
819 switch (apic_polarity(apic, pin)) {
825 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
829 *flags |= IOART_INTALO;
837 if ((id = apic_src_bus_id(apic, pin)) == -1)
840 switch (apic_bus_type(id)) {
842 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
846 /* polarity converter always gives active high */
847 *flags &= ~IOART_INTALO;
851 *flags |= IOART_INTALO;
860 panic("bad APIC IO INT flags");
865 * Print contents of unmasked IRQs.
872 kprintf("SMP: enabled INTs: ");
873 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
874 if ((int_to_apicintpin[x].flags & AIMI_FLAG_MASKED) == 0)
882 * Inter Processor Interrupt functions.
885 #endif /* SMP APIC-IO */
888 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
890 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
891 * vector is any valid SYSTEM INT vector
892 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
894 * A backlog of requests can create a deadlock between cpus. To avoid this
895 * we have to be able to accept IPIs at the same time we are trying to send
896 * them. The critical section prevents us from attempting to send additional
897 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
898 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
899 * to occur but fortunately it does not happen too often.
902 apic_ipi(int dest_type, int vector, int delivery_mode)
907 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
908 unsigned long rflags = read_rflags();
910 DEBUG_PUSH_INFO("apic_ipi");
911 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
915 write_rflags(rflags);
918 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
919 delivery_mode | vector;
920 lapic->icr_lo = icr_lo;
926 single_apic_ipi(int cpu, int vector, int delivery_mode)
932 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
933 unsigned long rflags = read_rflags();
935 DEBUG_PUSH_INFO("single_apic_ipi");
936 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
940 write_rflags(rflags);
942 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
943 icr_hi |= (CPU_TO_ID(cpu) << 24);
944 lapic->icr_hi = icr_hi;
947 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
948 | APIC_DEST_DESTFLD | delivery_mode | vector;
951 lapic->icr_lo = icr_lo;
958 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
960 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
961 * to the target, and the scheduler does not 'poll' for IPI messages.
964 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
970 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
974 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
975 icr_hi |= (CPU_TO_ID(cpu) << 24);
976 lapic->icr_hi = icr_hi;
979 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
980 | APIC_DEST_DESTFLD | delivery_mode | vector;
983 lapic->icr_lo = icr_lo;
991 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
993 * target is a bitmask of destination cpus. Vector is any
994 * valid system INT vector. Delivery mode may be either
995 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
998 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
1002 int n = BSFCPUMASK(target);
1003 target &= ~CPUMASK(n);
1004 single_apic_ipi(n, vector, delivery_mode);
1010 * Timer code, in development...
1011 * - suggested by rgrimes@gndrsh.aac.dev.com
1014 get_apic_timer_frequency(void)
1016 return(lapic_cputimer_intr.freq);
1020 * Load a 'downcount time' in uSeconds.
1023 set_apic_timer(int us)
1028 * When we reach here, lapic timer's frequency
1029 * must have been calculated as well as the
1030 * divisor (lapic->dcr_timer is setup during the
1031 * divisor calculation).
1033 KKASSERT(lapic_cputimer_intr.freq != 0 &&
1034 lapic_timer_divisor_idx >= 0);
1036 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
1037 lapic_timer_oneshot(count);
1042 * Read remaining time in timer.
1045 read_apic_timer(void)
1048 /** XXX FIXME: we need to return the actual remaining time,
1049 * for now we just return the remaining count.
1052 return lapic->ccr_timer;
1058 * Spin-style delay, set delay time in uS, spin till it drains.
1063 set_apic_timer(count);
1064 while (read_apic_timer())
1069 * XXX: Hack: Used by pmap_init
1071 vm_offset_t cpu_apic_addr;
1074 lapic_init(vm_offset_t lapic_addr)
1077 * lapic not mapped yet (pmap_init is called too late)
1079 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
1081 cpu_apic_addr = lapic_addr;
1083 kprintf("lapic: at 0x%08lx\n", lapic_addr);
1086 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1087 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1092 struct lapic_enumerator *e;
1095 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1096 error = e->lapic_probe(e);
1101 panic("can't config lapic\n");
1103 e->lapic_enumerate(e);
1107 lapic_enumerator_register(struct lapic_enumerator *ne)
1109 struct lapic_enumerator *e;
1111 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1112 if (e->lapic_prio < ne->lapic_prio) {
1113 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1117 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);