2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.42 2006/08/01 18:11:20 swildner Exp $
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * The Rhine has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #include "opt_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/sockio.h>
69 #include <sys/malloc.h>
70 #include <sys/kernel.h>
71 #include <sys/socket.h>
72 #include <sys/serialize.h>
73 #include <sys/thread2.h>
76 #include <net/ifq_var.h>
77 #include <net/if_arp.h>
78 #include <net/ethernet.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
84 #include <vm/vm.h> /* for vtophys */
85 #include <vm/pmap.h> /* for vtophys */
86 #include <machine/bus_pio.h>
87 #include <machine/bus_memio.h>
88 #include <machine/bus.h>
89 #include <machine/resource.h>
93 #include <dev/netif/mii_layer/mii.h>
94 #include <dev/netif/mii_layer/miivar.h>
96 #include <bus/pci/pcidevs.h>
97 #include <bus/pci/pcireg.h>
98 #include <bus/pci/pcivar.h>
100 #define VR_USEIOSPACE
102 #include <dev/netif/vr/if_vrreg.h>
104 /* "controller miibus0" required. See GENERIC if you get errors here. */
105 #include "miibus_if.h"
110 * Various supported device vendors/types and their names.
112 static struct vr_type vr_devs[] = {
113 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043,
114 "VIA VT3043 Rhine I 10/100BaseTX" },
115 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A,
116 "VIA VT86C100A Rhine II 10/100BaseTX" },
117 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102,
118 "VIA VT6102 Rhine II 10/100BaseTX" },
119 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105,
120 "VIA VT6105 Rhine III 10/100BaseTX" },
121 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M,
122 "VIA VT6105M Rhine III 10/100BaseTX" },
123 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_RHINEII,
124 "Delta Electronics Rhine II 10/100BaseTX" },
125 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_RHINEII,
126 "Addtron Technology Rhine II 10/100BaseTX" },
130 static int vr_probe(device_t);
131 static int vr_attach(device_t);
132 static int vr_detach(device_t);
134 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *,
136 static int vr_encap(struct vr_softc *, int, struct mbuf * );
138 static void vr_rxeof(struct vr_softc *);
139 static void vr_rxeoc(struct vr_softc *);
140 static void vr_txeof(struct vr_softc *);
141 static void vr_txeoc(struct vr_softc *);
142 static void vr_tick(void *);
143 static void vr_intr(void *);
144 static void vr_start(struct ifnet *);
145 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
146 static void vr_init(void *);
147 static void vr_stop(struct vr_softc *);
148 static void vr_watchdog(struct ifnet *);
149 static void vr_shutdown(device_t);
150 static int vr_ifmedia_upd(struct ifnet *);
151 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
154 static void vr_mii_sync(struct vr_softc *);
155 static void vr_mii_send(struct vr_softc *, uint32_t, int);
157 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
158 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
159 static int vr_miibus_readreg(device_t, int, int);
160 static int vr_miibus_writereg(device_t, int, int, int);
161 static void vr_miibus_statchg(device_t);
163 static void vr_setcfg(struct vr_softc *, int);
164 static void vr_setmulti(struct vr_softc *);
165 static void vr_reset(struct vr_softc *);
166 static int vr_list_rx_init(struct vr_softc *);
167 static int vr_list_tx_init(struct vr_softc *);
168 #ifdef DEVICE_POLLING
169 static void vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
173 #define VR_RES SYS_RES_IOPORT
174 #define VR_RID VR_PCI_LOIO
176 #define VR_RES SYS_RES_MEMORY
177 #define VR_RID VR_PCI_LOMEM
180 static device_method_t vr_methods[] = {
181 /* Device interface */
182 DEVMETHOD(device_probe, vr_probe),
183 DEVMETHOD(device_attach, vr_attach),
184 DEVMETHOD(device_detach, vr_detach),
185 DEVMETHOD(device_shutdown, vr_shutdown),
188 DEVMETHOD(bus_print_child, bus_generic_print_child),
189 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
192 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
193 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
194 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
199 static driver_t vr_driver = {
202 sizeof(struct vr_softc)
205 static devclass_t vr_devclass;
207 DECLARE_DUMMY_MODULE(if_vr);
208 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
209 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
211 #define VR_SETBIT(sc, reg, x) \
212 CSR_WRITE_1(sc, reg, \
213 CSR_READ_1(sc, reg) | (x))
215 #define VR_CLRBIT(sc, reg, x) \
216 CSR_WRITE_1(sc, reg, \
217 CSR_READ_1(sc, reg) & ~(x))
219 #define VR_SETBIT16(sc, reg, x) \
220 CSR_WRITE_2(sc, reg, \
221 CSR_READ_2(sc, reg) | (x))
223 #define VR_CLRBIT16(sc, reg, x) \
224 CSR_WRITE_2(sc, reg, \
225 CSR_READ_2(sc, reg) & ~(x))
227 #define VR_SETBIT32(sc, reg, x) \
228 CSR_WRITE_4(sc, reg, \
229 CSR_READ_4(sc, reg) | (x))
231 #define VR_CLRBIT32(sc, reg, x) \
232 CSR_WRITE_4(sc, reg, \
233 CSR_READ_4(sc, reg) & ~(x))
236 CSR_WRITE_1(sc, VR_MIICMD, \
237 CSR_READ_1(sc, VR_MIICMD) | (x))
240 CSR_WRITE_1(sc, VR_MIICMD, \
241 CSR_READ_1(sc, VR_MIICMD) & ~(x))
245 * Sync the PHYs by setting data bit and strobing the clock 32 times.
248 vr_mii_sync(struct vr_softc *sc)
252 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
254 for (i = 0; i < 32; i++) {
255 SIO_SET(VR_MIICMD_CLK);
257 SIO_CLR(VR_MIICMD_CLK);
263 * Clock a series of bits through the MII.
266 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
270 SIO_CLR(VR_MIICMD_CLK);
272 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
274 SIO_SET(VR_MIICMD_DATAIN);
276 SIO_CLR(VR_MIICMD_DATAIN);
278 SIO_CLR(VR_MIICMD_CLK);
280 SIO_SET(VR_MIICMD_CLK);
286 * Read an PHY register through the MII.
289 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame)
294 /* Set up frame for RX. */
295 frame->mii_stdelim = VR_MII_STARTDELIM;
296 frame->mii_opcode = VR_MII_READOP;
297 frame->mii_turnaround = 0;
300 CSR_WRITE_1(sc, VR_MIICMD, 0);
301 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
303 /* Turn on data xmit. */
304 SIO_SET(VR_MIICMD_DIR);
308 /* Send command/address info. */
309 vr_mii_send(sc, frame->mii_stdelim, 2);
310 vr_mii_send(sc, frame->mii_opcode, 2);
311 vr_mii_send(sc, frame->mii_phyaddr, 5);
312 vr_mii_send(sc, frame->mii_regaddr, 5);
315 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
317 SIO_SET(VR_MIICMD_CLK);
321 SIO_CLR(VR_MIICMD_DIR);
324 SIO_CLR(VR_MIICMD_CLK);
326 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
327 SIO_SET(VR_MIICMD_CLK);
331 * Now try reading data bits. If the ack failed, we still
332 * need to clock through 16 cycles to keep the PHY(s) in sync.
335 for(i = 0; i < 16; i++) {
336 SIO_CLR(VR_MIICMD_CLK);
338 SIO_SET(VR_MIICMD_CLK);
344 for (i = 0x8000; i; i >>= 1) {
345 SIO_CLR(VR_MIICMD_CLK);
348 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
349 frame->mii_data |= i;
352 SIO_SET(VR_MIICMD_CLK);
357 SIO_CLR(VR_MIICMD_CLK);
359 SIO_SET(VR_MIICMD_CLK);
370 /* Set the PHY address. */
371 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
374 /* Set the register address. */
375 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
376 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
378 for (i = 0; i < 10000; i++) {
379 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
383 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
391 * Write to a PHY register through the MII.
394 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame)
397 CSR_WRITE_1(sc, VR_MIICMD, 0);
398 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
400 /* Set up frame for TX. */
401 frame->mii_stdelim = VR_MII_STARTDELIM;
402 frame->mii_opcode = VR_MII_WRITEOP;
403 frame->mii_turnaround = VR_MII_TURNAROUND;
405 /* Turn on data output. */
406 SIO_SET(VR_MIICMD_DIR);
410 vr_mii_send(sc, frame->mii_stdelim, 2);
411 vr_mii_send(sc, frame->mii_opcode, 2);
412 vr_mii_send(sc, frame->mii_phyaddr, 5);
413 vr_mii_send(sc, frame->mii_regaddr, 5);
414 vr_mii_send(sc, frame->mii_turnaround, 2);
415 vr_mii_send(sc, frame->mii_data, 16);
418 SIO_SET(VR_MIICMD_CLK);
420 SIO_CLR(VR_MIICMD_CLK);
424 SIO_CLR(VR_MIICMD_DIR);
432 /* Set the PHY-adress */
433 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
436 /* Set the register address and data to write. */
437 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
438 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
440 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
442 for (i = 0; i < 10000; i++) {
443 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
452 vr_miibus_readreg(device_t dev, int phy, int reg)
454 struct vr_mii_frame frame;
457 sc = device_get_softc(dev);
459 switch (sc->vr_revid) {
460 case REV_ID_VT6102_APOLLO:
468 bzero(&frame, sizeof(frame));
470 frame.mii_phyaddr = phy;
471 frame.mii_regaddr = reg;
472 vr_mii_readreg(sc, &frame);
474 return(frame.mii_data);
478 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
480 struct vr_mii_frame frame;
483 sc = device_get_softc(dev);
485 switch (sc->vr_revid) {
486 case REV_ID_VT6102_APOLLO:
494 bzero(&frame, sizeof(frame));
496 frame.mii_phyaddr = phy;
497 frame.mii_regaddr = reg;
498 frame.mii_data = data;
500 vr_mii_writereg(sc, &frame);
506 vr_miibus_statchg(device_t dev)
508 struct mii_data *mii;
511 sc = device_get_softc(dev);
512 mii = device_get_softc(sc->vr_miibus);
513 vr_setcfg(sc, mii->mii_media_active);
517 * Program the 64-bit multicast hash filter.
520 vr_setmulti(struct vr_softc *sc)
523 uint32_t hashes[2] = { 0, 0 };
524 struct ifmultiaddr *ifma;
528 ifp = &sc->arpcom.ac_if;
530 rxfilt = CSR_READ_1(sc, VR_RXCFG);
532 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
533 rxfilt |= VR_RXCFG_RX_MULTI;
534 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
535 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
536 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
540 /* First, zero out all the existing hash bits. */
541 CSR_WRITE_4(sc, VR_MAR0, 0);
542 CSR_WRITE_4(sc, VR_MAR1, 0);
544 /* Now program new ones. */
545 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
548 if (ifma->ifma_addr->sa_family != AF_LINK)
551 /* use the lower 6 bits */
553 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
554 ETHER_ADDR_LEN) >> 26) & 0x0000003F;
556 hashes[0] |= (1 << h);
558 hashes[1] |= (1 << (h - 32));
563 rxfilt |= VR_RXCFG_RX_MULTI;
565 rxfilt &= ~VR_RXCFG_RX_MULTI;
567 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
568 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
569 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
573 * In order to fiddle with the
574 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
575 * first have to put the transmit and/or receive logic in the idle state.
578 vr_setcfg(struct vr_softc *sc, int media)
582 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
584 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
587 if ((media & IFM_GMASK) == IFM_FDX)
588 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
590 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
593 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
597 vr_reset(struct vr_softc *sc)
601 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
603 for (i = 0; i < VR_TIMEOUT; i++) {
605 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
608 if (i == VR_TIMEOUT) {
609 struct ifnet *ifp = &sc->arpcom.ac_if;
611 if (sc->vr_revid < REV_ID_VT3065_A) {
612 if_printf(ifp, "reset never completed!\n");
614 /* Use newer force reset command */
615 if_printf(ifp, "Using force reset command.\n");
616 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
620 /* Wait a little while for the chip to get its brains in order. */
625 * Probe for a VIA Rhine chip. Check the PCI vendor and device
626 * IDs against our list and return a device name if we find a match.
629 vr_probe(device_t dev)
634 vid = pci_get_vendor(dev);
635 did = pci_get_device(dev);
637 for (t = vr_devs; t->vr_name != NULL; ++t) {
638 if (vid == t->vr_vid && did == t->vr_did) {
639 device_set_desc(dev, t->vr_name);
648 * Attach the interface. Allocate softc structures, do ifmedia
649 * setup and ethernet/BPF attach.
652 vr_attach(device_t dev)
655 uint8_t eaddr[ETHER_ADDR_LEN];
660 sc = device_get_softc(dev);
661 callout_init(&sc->vr_stat_timer);
664 * Handle power management nonsense.
666 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
667 uint32_t iobase, membase, irq;
669 /* Save important PCI config data. */
670 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
671 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
672 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
674 /* Reset the power state. */
675 device_printf(dev, "chip is in D%d power mode "
676 "-- setting to D0\n", pci_get_powerstate(dev));
677 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
679 /* Restore PCI config data. */
680 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
681 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
682 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
685 pci_enable_busmaster(dev);
687 sc->vr_revid = pci_get_revid(dev);
690 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE);
692 if (sc->vr_res == NULL) {
693 device_printf(dev, "couldn't map ports/memory\n");
697 sc->vr_btag = rman_get_bustag(sc->vr_res);
698 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
700 /* Allocate interrupt */
702 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
703 RF_SHAREABLE | RF_ACTIVE);
705 if (sc->vr_irq == NULL) {
706 device_printf(dev, "couldn't map interrupt\n");
712 * Windows may put the chip in suspend mode when it
713 * shuts down. Be sure to kick it in the head to wake it
716 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
718 ifp = &sc->arpcom.ac_if;
719 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
721 /* Reset the adapter. */
725 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
726 * initialization and disable AUTOPOLL.
728 pci_write_config(dev, VR_PCI_MODE,
729 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
730 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
733 * Get station address. The way the Rhine chips work,
734 * you're not allowed to directly access the EEPROM once
735 * they've been programmed a special way. Consequently,
736 * we need to read the node address from the PAR0 and PAR1
739 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
741 for (i = 0; i < ETHER_ADDR_LEN; i++)
742 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
744 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
745 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
747 if (sc->vr_ldata == NULL) {
748 device_printf(dev, "no memory for list buffers!\n");
753 /* Initialize TX buffer */
754 sc->vr_cdata.vr_tx_buf = contigmalloc(VR_TX_BUF_SIZE, M_DEVBUF,
755 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
756 if (sc->vr_cdata.vr_tx_buf == NULL) {
757 device_printf(dev, "can't allocate tx buffer!\n");
762 /* Set various TX indexes to invalid value */
763 sc->vr_cdata.vr_tx_free_idx = -1;
764 sc->vr_cdata.vr_tx_tail_idx = -1;
765 sc->vr_cdata.vr_tx_head_idx = -1;
769 ifp->if_mtu = ETHERMTU;
770 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
771 ifp->if_ioctl = vr_ioctl;
772 ifp->if_start = vr_start;
773 #ifdef DEVICE_POLLING
774 ifp->if_poll = vr_poll;
776 ifp->if_watchdog = vr_watchdog;
777 ifp->if_init = vr_init;
778 ifp->if_baudrate = 10000000;
779 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1);
780 ifq_set_ready(&ifp->if_snd);
785 if (mii_phy_probe(dev, &sc->vr_miibus,
786 vr_ifmedia_upd, vr_ifmedia_sts)) {
787 if_printf(ifp, "MII without any phy!\n");
792 /* Call MI attach routine. */
793 ether_ifattach(ifp, eaddr, NULL);
795 error = bus_setup_intr(dev, sc->vr_irq, INTR_NETSAFE,
796 vr_intr, sc, &sc->vr_intrhand,
800 device_printf(dev, "couldn't set up irq\n");
812 vr_detach(device_t dev)
814 struct vr_softc *sc = device_get_softc(dev);
815 struct ifnet *ifp = &sc->arpcom.ac_if;
817 if (device_is_attached(dev)) {
818 lwkt_serialize_enter(ifp->if_serializer);
820 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
821 lwkt_serialize_exit(ifp->if_serializer);
825 if (sc->vr_miibus != NULL)
826 device_delete_child(dev, sc->vr_miibus);
827 bus_generic_detach(dev);
829 if (sc->vr_irq != NULL)
830 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
831 if (sc->vr_res != NULL)
832 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
833 if (sc->vr_ldata != NULL)
834 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
835 if (sc->vr_cdata.vr_tx_buf != NULL)
836 contigfree(sc->vr_cdata.vr_tx_buf, VR_TX_BUF_SIZE, M_DEVBUF);
842 * Initialize the transmit descriptors.
845 vr_list_tx_init(struct vr_softc *sc)
847 struct vr_chain_data *cd;
848 struct vr_list_data *ld;
849 struct vr_chain *tx_chain;
854 tx_chain = cd->vr_tx_chain;
856 for (i = 0; i < VR_TX_LIST_CNT; i++) {
857 tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
858 if (i == (VR_TX_LIST_CNT - 1))
859 tx_chain[i].vr_next_idx = 0;
861 tx_chain[i].vr_next_idx = i + 1;
864 for (i = 0; i < VR_TX_LIST_CNT; ++i) {
868 tx_buf = VR_TX_BUF(sc, i);
869 next_idx = tx_chain[i].vr_next_idx;
871 tx_chain[i].vr_next_desc_paddr =
872 vtophys(tx_chain[next_idx].vr_ptr);
873 tx_chain[i].vr_buf_paddr = vtophys(tx_buf);
876 cd->vr_tx_free_idx = 0;
877 cd->vr_tx_tail_idx = cd->vr_tx_head_idx = -1;
884 * Initialize the RX descriptors and allocate mbufs for them. Note that
885 * we arrange the descriptors in a closed ring, so that the last descriptor
886 * points back to the first.
889 vr_list_rx_init(struct vr_softc *sc)
891 struct vr_chain_data *cd;
892 struct vr_list_data *ld;
898 for (i = 0; i < VR_RX_LIST_CNT; i++) {
899 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i];
900 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
902 if (i == (VR_RX_LIST_CNT - 1))
906 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti];
907 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]);
910 cd->vr_rx_head = &cd->vr_rx_chain[0];
916 * Initialize an RX descriptor and attach an MBUF cluster.
917 * Note: the length fields are only 11 bits wide, which means the
918 * largest size we can specify is 2047. This is important because
919 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
920 * overflow the field and make a mess.
923 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m)
925 struct mbuf *m_new = NULL;
928 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
931 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
934 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
935 m_new->m_data = m_new->m_ext.ext_buf;
938 m_adj(m_new, sizeof(uint64_t));
941 c->vr_ptr->vr_status = VR_RXSTAT;
942 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
943 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
949 * A frame has been uploaded: pass the resulting mbuf chain up to
950 * the higher level protocols.
953 vr_rxeof(struct vr_softc *sc)
957 struct vr_chain_onefrag *cur_rx;
961 ifp = &sc->arpcom.ac_if;
963 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
965 struct mbuf *m0 = NULL;
967 cur_rx = sc->vr_cdata.vr_rx_head;
968 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
972 * If an error occurs, update stats, clear the
973 * status word and leave the mbuf cluster in place:
974 * it should simply get re-used next time this descriptor
975 * comes up in the ring.
977 if (rxstat & VR_RXSTAT_RXERR) {
979 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff);
980 if (rxstat & VR_RXSTAT_CRCERR)
981 printf(" crc error");
982 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
983 printf(" frame alignment error\n");
984 if (rxstat & VR_RXSTAT_FIFOOFLOW)
985 printf(" FIFO overflow");
986 if (rxstat & VR_RXSTAT_GIANT)
987 printf(" received giant packet");
988 if (rxstat & VR_RXSTAT_RUNT)
989 printf(" received runt packet");
990 if (rxstat & VR_RXSTAT_BUSERR)
991 printf(" system bus error");
992 if (rxstat & VR_RXSTAT_BUFFERR)
993 printf("rx buffer error");
995 vr_newbuf(sc, cur_rx, m);
999 /* No errors; receive the packet. */
1000 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1003 * XXX The VIA Rhine chip includes the CRC with every
1004 * received frame, and there's no way to turn this
1005 * behavior off (at least, I can't find anything in
1006 * the manual that explains how to do it) so we have
1007 * to trim off the CRC manually.
1009 total_len -= ETHER_CRC_LEN;
1011 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1012 total_len + ETHER_ALIGN, 0, ifp, NULL);
1013 vr_newbuf(sc, cur_rx, m);
1018 m_adj(m0, ETHER_ALIGN);
1022 ifp->if_input(ifp, m);
1027 vr_rxeoc(struct vr_softc *sc)
1032 ifp = &sc->arpcom.ac_if;
1036 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1039 /* Wait for receiver to stop */
1041 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1043 ; /* Wait for receiver to stop */
1046 if_printf(ifp, "rx shutdown error!\n");
1047 sc->vr_flags |= VR_F_RESTART;
1053 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1054 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1055 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1059 * A frame was downloaded to the chip. It's safe for us to clean up
1063 vr_txeof(struct vr_softc *sc)
1065 struct vr_chain_data *cd;
1066 struct vr_chain *tx_chain;
1069 ifp = &sc->arpcom.ac_if;
1072 /* Reset the timeout timer; if_txeoc will clear it. */
1076 if (cd->vr_tx_head_idx == -1)
1079 tx_chain = cd->vr_tx_chain;
1082 * Go through our tx list and free mbufs for those
1083 * frames that have been transmitted.
1085 while(tx_chain[cd->vr_tx_head_idx].vr_buf != NULL) {
1086 struct vr_chain *cur_tx;
1090 cur_tx = &tx_chain[cd->vr_tx_head_idx];
1091 txstat = cur_tx->vr_ptr->vr_status;
1093 if ((txstat & VR_TXSTAT_ABRT) ||
1094 (txstat & VR_TXSTAT_UDF)) {
1096 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1098 ; /* Wait for chip to shutdown */
1100 if_printf(ifp, "tx shutdown timeout\n");
1101 sc->vr_flags |= VR_F_RESTART;
1104 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1105 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1109 if (txstat & VR_TXSTAT_OWN)
1112 if (txstat & VR_TXSTAT_ERRSUM) {
1114 if (txstat & VR_TXSTAT_DEFER)
1115 ifp->if_collisions++;
1116 if (txstat & VR_TXSTAT_LATECOLL)
1117 ifp->if_collisions++;
1120 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3;
1123 cur_tx->vr_buf = NULL;
1125 if (cd->vr_tx_head_idx == cd->vr_tx_tail_idx) {
1126 cd->vr_tx_head_idx = -1;
1127 cd->vr_tx_tail_idx = -1;
1131 cd->vr_tx_head_idx = cur_tx->vr_next_idx;
1136 * TX 'end of channel' interrupt handler.
1139 vr_txeoc(struct vr_softc *sc)
1143 ifp = &sc->arpcom.ac_if;
1145 if (sc->vr_cdata.vr_tx_head_idx == -1) {
1146 ifp->if_flags &= ~IFF_OACTIVE;
1147 sc->vr_cdata.vr_tx_tail_idx = -1;
1155 struct vr_softc *sc = xsc;
1156 struct ifnet *ifp = &sc->arpcom.ac_if;
1157 struct mii_data *mii;
1159 lwkt_serialize_enter(ifp->if_serializer);
1161 if (sc->vr_flags & VR_F_RESTART) {
1162 if_printf(&sc->arpcom.ac_if, "restarting\n");
1166 sc->vr_flags &= ~VR_F_RESTART;
1169 mii = device_get_softc(sc->vr_miibus);
1172 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1174 lwkt_serialize_exit(ifp->if_serializer);
1180 struct vr_softc *sc;
1185 ifp = &sc->arpcom.ac_if;
1187 /* Supress unwanted interrupts. */
1188 if (!(ifp->if_flags & IFF_UP)) {
1193 /* Disable interrupts. */
1194 if ((ifp->if_flags & IFF_POLLING) == 0)
1195 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1198 status = CSR_READ_2(sc, VR_ISR);
1200 CSR_WRITE_2(sc, VR_ISR, status);
1202 if ((status & VR_INTRS) == 0)
1205 if (status & VR_ISR_RX_OK)
1208 if (status & VR_ISR_RX_DROPPED) {
1209 if_printf(ifp, "rx packet lost\n");
1213 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1214 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1215 if_printf(ifp, "receive error (%04x)", status);
1216 if (status & VR_ISR_RX_NOBUF)
1217 printf(" no buffers");
1218 if (status & VR_ISR_RX_OFLOW)
1219 printf(" overflow");
1220 if (status & VR_ISR_RX_DROPPED)
1221 printf(" packet lost");
1226 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1232 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1233 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1235 if ((status & VR_ISR_UDFI) ||
1236 (status & VR_ISR_TX_ABRT2) ||
1237 (status & VR_ISR_TX_ABRT)) {
1239 if (sc->vr_cdata.vr_tx_head_idx != -1) {
1240 VR_SETBIT16(sc, VR_COMMAND,
1242 VR_SETBIT16(sc, VR_COMMAND,
1252 /* Re-enable interrupts. */
1253 if ((ifp->if_flags & IFF_POLLING) == 0)
1254 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1256 if (!ifq_is_empty(&ifp->if_snd))
1261 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1262 * pointers to the fragment pointers.
1265 vr_encap(struct vr_softc *sc, int chain_idx, struct mbuf *m_head)
1272 KASSERT(chain_idx >= 0 && chain_idx < VR_TX_LIST_CNT,
1273 ("%s: chain idx(%d) out of range 0-%d",
1274 sc->arpcom.ac_if.if_xname, chain_idx, VR_TX_LIST_CNT));
1277 * The VIA Rhine wants packet buffers to be longword
1278 * aligned, but very often our mbufs aren't. Rather than
1279 * waste time trying to decide when to copy and when not
1280 * to copy, just do it all the time.
1282 tx_buf = VR_TX_BUF(sc, chain_idx);
1283 m_copydata(m_head, 0, m_head->m_pkthdr.len, tx_buf);
1284 len = m_head->m_pkthdr.len;
1287 * The Rhine chip doesn't auto-pad, so we have to make
1288 * sure to pad short frames out to the minimum frame length
1291 if (len < VR_MIN_FRAMELEN) {
1292 bzero(tx_buf + len, VR_MIN_FRAMELEN - len);
1293 len = VR_MIN_FRAMELEN;
1296 c = &sc->vr_cdata.vr_tx_chain[chain_idx];
1300 f->vr_data = c->vr_buf_paddr;
1302 f->vr_ctl |= (VR_TXCTL_TLINK | VR_TXCTL_FIRSTFRAG);
1303 f->vr_ctl |= (VR_TXCTL_LASTFRAG | VR_TXCTL_FINT);
1305 f->vr_next = c->vr_next_desc_paddr;
1311 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1312 * to the mbuf data regions directly in the transmit lists. We also save a
1313 * copy of the pointers since the transmit list fragment pointers are
1314 * physical addresses.
1317 vr_start(struct ifnet *ifp)
1319 struct vr_softc *sc;
1320 struct vr_chain_data *cd;
1321 struct vr_chain *tx_chain;
1322 int cur_tx_idx, start_tx_idx, prev_tx_idx;
1324 if (ifp->if_flags & IFF_OACTIVE)
1329 tx_chain = cd->vr_tx_chain;
1331 start_tx_idx = cd->vr_tx_free_idx;
1332 cur_tx_idx = prev_tx_idx = -1;
1334 /* Check for an available queue slot. If there are none, punt. */
1335 if (tx_chain[start_tx_idx].vr_buf != NULL) {
1336 ifp->if_flags |= IFF_OACTIVE;
1340 while(tx_chain[cd->vr_tx_free_idx].vr_buf == NULL) {
1341 struct mbuf *m_head;
1342 struct vr_chain *cur_tx;
1344 m_head = ifq_poll(&ifp->if_snd);
1348 /* Pick a descriptor off the free list. */
1349 cur_tx_idx = cd->vr_tx_free_idx;
1350 cur_tx = &tx_chain[cur_tx_idx];
1352 /* Pack the data into the descriptor. */
1353 if (vr_encap(sc, cur_tx_idx, m_head)) {
1354 ifp->if_flags |= IFF_OACTIVE;
1355 cur_tx_idx = prev_tx_idx;
1359 ifq_dequeue(&ifp->if_snd, m_head);
1362 if (cur_tx_idx != start_tx_idx)
1363 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1365 BPF_MTAP(ifp, m_head);
1368 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1369 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1371 /* Iff everything went OK, we bump up free index. */
1372 prev_tx_idx = cur_tx_idx;
1373 cd->vr_tx_free_idx = cur_tx->vr_next_idx;
1376 /* If there are no frames queued, bail. */
1377 if (cur_tx_idx == -1)
1380 sc->vr_cdata.vr_tx_tail_idx = cur_tx_idx;
1382 if (sc->vr_cdata.vr_tx_head_idx == -1)
1383 sc->vr_cdata.vr_tx_head_idx = start_tx_idx;
1386 * Set a timeout in case the chip goes out to lunch.
1394 struct vr_softc *sc = xsc;
1395 struct ifnet *ifp = &sc->arpcom.ac_if;
1396 struct mii_data *mii;
1399 mii = device_get_softc(sc->vr_miibus);
1401 /* Cancel pending I/O and free all RX/TX buffers. */
1405 /* Set our station address. */
1406 for (i = 0; i < ETHER_ADDR_LEN; i++)
1407 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1410 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1411 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1414 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1415 * so we must set both.
1417 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1418 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1420 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1421 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1423 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1424 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1426 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1427 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1429 /* Init circular RX list. */
1430 if (vr_list_rx_init(sc) == ENOBUFS) {
1432 if_printf(ifp, "initialization failed: no memory for rx buffers\n");
1436 /* Init tx descriptors. */
1437 vr_list_tx_init(sc);
1439 /* If we want promiscuous mode, set the allframes bit. */
1440 if (ifp->if_flags & IFF_PROMISC)
1441 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1443 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1445 /* Set capture broadcast bit to capture broadcast frames. */
1446 if (ifp->if_flags & IFF_BROADCAST)
1447 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1449 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1452 * Program the multicast filter, if necessary.
1457 * Load the address of the RX list.
1459 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1461 /* Enable receiver and transmitter. */
1462 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1463 VR_CMD_TX_ON|VR_CMD_RX_ON|
1466 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1469 * Enable interrupts, unless we are polling.
1471 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1472 if ((ifp->if_flags & IFF_POLLING) == 0)
1473 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1477 ifp->if_flags |= IFF_RUNNING;
1478 ifp->if_flags &= ~IFF_OACTIVE;
1480 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1484 * Set media options.
1487 vr_ifmedia_upd(struct ifnet *ifp)
1489 struct vr_softc *sc;
1493 if (ifp->if_flags & IFF_UP)
1500 * Report current media status.
1503 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1505 struct vr_softc *sc;
1506 struct mii_data *mii;
1509 mii = device_get_softc(sc->vr_miibus);
1511 ifmr->ifm_active = mii->mii_media_active;
1512 ifmr->ifm_status = mii->mii_media_status;
1516 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1518 struct vr_softc *sc = ifp->if_softc;
1519 struct ifreq *ifr = (struct ifreq *) data;
1520 struct mii_data *mii;
1525 if (ifp->if_flags & IFF_UP) {
1528 if (ifp->if_flags & IFF_RUNNING)
1540 mii = device_get_softc(sc->vr_miibus);
1541 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1544 error = ether_ioctl(ifp, command, data);
1550 #ifdef DEVICE_POLLING
1553 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1555 struct vr_softc *sc = ifp->if_softc;
1559 /* disable interrupts */
1560 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1562 case POLL_DEREGISTER:
1563 /* enable interrupts */
1564 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1574 vr_watchdog(struct ifnet *ifp)
1576 struct vr_softc *sc;
1581 if_printf(ifp, "watchdog timeout\n");
1583 #ifdef DEVICE_POLLING
1584 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) {
1585 if_printf(ifp, "ints don't seem to be working, "
1586 "emergency switch to polling\n");
1587 emergency_poll_enable("if_vr");
1588 ether_poll_register(ifp); /* XXX illegal */
1597 if (!ifq_is_empty(&ifp->if_snd))
1602 * Stop the adapter and free any mbufs allocated to the
1606 vr_stop(struct vr_softc *sc)
1611 ifp = &sc->arpcom.ac_if;
1614 callout_stop(&sc->vr_stat_timer);
1616 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1617 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1618 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1619 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1620 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1623 * Free data in the RX lists.
1625 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1626 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1627 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1628 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1631 bzero(&sc->vr_ldata->vr_rx_list, sizeof(sc->vr_ldata->vr_rx_list));
1634 * Reset the TX list buffer pointers.
1636 for (i = 0; i < VR_TX_LIST_CNT; i++)
1637 sc->vr_cdata.vr_tx_chain[i].vr_buf = NULL;
1639 bzero(&sc->vr_ldata->vr_tx_list, sizeof(sc->vr_ldata->vr_tx_list));
1641 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1645 * Stop all chip I/O so that the kernel's probe routines don't
1646 * get confused by errant DMAs when rebooting.
1649 vr_shutdown(device_t dev)
1651 struct vr_softc *sc;
1653 sc = device_get_softc(dev);