sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_polling.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
 139 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
 140 static void     igb_add_sysctl(struct igb_softc *);
 141 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 142 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 143
 144 static void     igb_vf_init_stats(struct igb_softc *);
 145 static void     igb_reset(struct igb_softc *);
 146 static void     igb_update_stats_counters(struct igb_softc *);
 147 static void     igb_update_vf_stats_counters(struct igb_softc *);
 148 static void     igb_update_link_status(struct igb_softc *);
 149 static void     igb_init_tx_unit(struct igb_softc *);
 150 static void     igb_init_rx_unit(struct igb_softc *);
 151
 152 static void     igb_set_vlan(struct igb_softc *);
 153 static void     igb_set_multi(struct igb_softc *);
 154 static void     igb_set_promisc(struct igb_softc *);
 155 static void     igb_disable_promisc(struct igb_softc *);
 156
 157 static int      igb_alloc_rings(struct igb_softc *);
 158 static void     igb_free_rings(struct igb_softc *);
 159 static int      igb_create_tx_ring(struct igb_tx_ring *);
 160 static int      igb_create_rx_ring(struct igb_rx_ring *);
 161 static void     igb_free_tx_ring(struct igb_tx_ring *);
 162 static void     igb_free_rx_ring(struct igb_rx_ring *);
 163 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 164 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 165 static void     igb_init_tx_ring(struct igb_tx_ring *);
 166 static int      igb_init_rx_ring(struct igb_rx_ring *);
 167 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 168 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
 169
 170 static void     igb_stop(struct igb_softc *);
 171 static void     igb_init(void *);
 172 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 173 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 174 static int      igb_media_change(struct ifnet *);
 175 static void     igb_timer(void *);
 176 static void     igb_watchdog(struct ifnet *);
 177 static void     igb_start(struct ifnet *);
 178 #ifdef DEVICE_POLLING
 179 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
 180 #endif
 181 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 182 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 183 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 184 #ifdef INVARIANTS
 185 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 186                     boolean_t);
 187 #endif
 188
 189 static void     igb_intr(void *);
 190 static void     igb_shared_intr(void *);
 191 static void     igb_rxeof(struct igb_rx_ring *, int);
 192 static void     igb_txeof(struct igb_tx_ring *);
 193 static void     igb_set_eitr(struct igb_softc *);
 194 static void     igb_enable_intr(struct igb_softc *);
 195 static void     igb_disable_intr(struct igb_softc *);
 196 static void     igb_init_unshared_intr(struct igb_softc *);
 197 static void     igb_init_intr(struct igb_softc *);
 198 static int      igb_setup_intr(struct igb_softc *);
 199 static void     igb_setup_tx_intr(struct igb_tx_ring *, int *, int);
 200 static void     igb_setup_rx_intr(struct igb_rx_ring *, int *, int);
 201
 202 /* Management and WOL Support */
 203 static void     igb_get_mgmt(struct igb_softc *);
 204 static void     igb_rel_mgmt(struct igb_softc *);
 205 static void     igb_get_hw_control(struct igb_softc *);
 206 static void     igb_rel_hw_control(struct igb_softc *);
 207 static void     igb_enable_wol(device_t);
 208
 209 static device_method_t igb_methods[] = {
 210         /* Device interface */
 211         DEVMETHOD(device_probe,         igb_probe),
 212         DEVMETHOD(device_attach,        igb_attach),
 213         DEVMETHOD(device_detach,        igb_detach),
 214         DEVMETHOD(device_shutdown,      igb_shutdown),
 215         DEVMETHOD(device_suspend,       igb_suspend),
 216         DEVMETHOD(device_resume,        igb_resume),
 217         { 0, 0 }
 218 };
 219
 220 static driver_t igb_driver = {
 221         "igb",
 222         igb_methods,
 223         sizeof(struct igb_softc),
 224 };
 225
 226 static devclass_t igb_devclass;
 227
 228 DECLARE_DUMMY_MODULE(if_igb);
 229 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 230 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 231
 232 static int      igb_rxd = IGB_DEFAULT_RXD;
 233 static int      igb_txd = IGB_DEFAULT_TXD;
 234 static int      igb_rxr = 0;
 235 static int      igb_msi_enable = 1;
 236 static int      igb_msix_enable = 1;
 237 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 238 static int      igb_fc_setting = e1000_fc_full;
 239
 240 /*
 241  * DMA Coalescing, only for i350 - default to off,
 242  * this feature is for power savings
 243  */
 244 static int      igb_dma_coalesce = 0;
 245
 246 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 247 TUNABLE_INT("hw.igb.txd", &igb_txd);
 248 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 249 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 250 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 251 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 252
 253 /* i350 specific */
 254 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 255 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 256
 257 static __inline void
 258 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 259 {
 260         /* Ignore Checksum bit is set */
 261         if (staterr & E1000_RXD_STAT_IXSM)
 262                 return;
 263
 264         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 265             E1000_RXD_STAT_IPCS)
 266                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 267
 268         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 269                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 270                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 271                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 272                         mp->m_pkthdr.csum_data = htons(0xffff);
 273                 }
 274         }
 275 }
 276
 277 static __inline struct pktinfo *
 278 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 279     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 280 {
 281         switch (hashtype) {
 282         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 283                 pi->pi_netisr = NETISR_IP;
 284                 pi->pi_flags = 0;
 285                 pi->pi_l3proto = IPPROTO_TCP;
 286                 break;
 287
 288         case E1000_RXDADV_RSSTYPE_IPV4:
 289                 if (staterr & E1000_RXD_STAT_IXSM)
 290                         return NULL;
 291
 292                 if ((staterr &
 293                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 294                     E1000_RXD_STAT_TCPCS) {
 295                         pi->pi_netisr = NETISR_IP;
 296                         pi->pi_flags = 0;
 297                         pi->pi_l3proto = IPPROTO_UDP;
 298                         break;
 299                 }
 300                 /* FALL THROUGH */
 301         default:
 302                 return NULL;
 303         }
 304
 305         m->m_flags |= M_HASH;
 306         m->m_pkthdr.hash = toeplitz_hash(hash);
 307         return pi;
 308 }
 309
 310 static int
 311 igb_probe(device_t dev)
 312 {
 313         const struct igb_device *d;
 314         uint16_t vid, did;
 315
 316         vid = pci_get_vendor(dev);
 317         did = pci_get_device(dev);
 318
 319         for (d = igb_devices; d->desc != NULL; ++d) {
 320                 if (vid == d->vid && did == d->did) {
 321                         device_set_desc(dev, d->desc);
 322                         return 0;
 323                 }
 324         }
 325         return ENXIO;
 326 }
 327
 328 static int
 329 igb_attach(device_t dev)
 330 {
 331         struct igb_softc *sc = device_get_softc(dev);
 332         uint16_t eeprom_data;
 333         u_int intr_flags;
 334         int error = 0, i, j, ring_max;
 335
 336 #ifdef notyet
 337         /* SYSCTL stuff */
 338         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 339             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 340             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 341             igb_sysctl_nvm_info, "I", "NVM Information");
 342
 343         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 344             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 345             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
 346             &igb_enable_aim, 1, "Interrupt Moderation");
 347
 348         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 349             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 350             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 351             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 352 #endif
 353
 354         callout_init_mp(&sc->timer);
 355
 356         sc->dev = sc->osdep.dev = dev;
 357
 358         /*
 359          * Determine hardware and mac type
 360          */
 361         sc->hw.vendor_id = pci_get_vendor(dev);
 362         sc->hw.device_id = pci_get_device(dev);
 363         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 364         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 365         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 366
 367         if (e1000_set_mac_type(&sc->hw))
 368                 return ENXIO;
 369
 370         /* Are we a VF device? */
 371         if (sc->hw.mac.type == e1000_vfadapt ||
 372             sc->hw.mac.type == e1000_vfadapt_i350)
 373                 sc->vf_ifp = 1;
 374         else
 375                 sc->vf_ifp = 0;
 376
 377         /* Enable bus mastering */
 378         pci_enable_busmaster(dev);
 379
 380         /*
 381          * Allocate IO memory
 382          */
 383         sc->mem_rid = PCIR_BAR(0);
 384         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 385             RF_ACTIVE);
 386         if (sc->mem_res == NULL) {
 387                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 388                 error = ENXIO;
 389                 goto failed;
 390         }
 391         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 392         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 393
 394         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 395
 396         /*
 397          * Allocate interrupt
 398          */
 399         sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
 400             &sc->intr_rid, &intr_flags);
 401
 402         sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
 403             intr_flags);
 404         if (sc->intr_res == NULL) {
 405                 device_printf(dev, "Unable to allocate bus resource: "
 406                     "interrupt\n");
 407                 error = ENXIO;
 408                 goto failed;
 409         }
 410
 411         /* Save PCI command register for Shared Code */
 412         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 413         sc->hw.back = &sc->osdep;
 414
 415         switch (sc->hw.mac.type) {
 416         case e1000_82575:
 417                 ring_max = IGB_MAX_RING_82575;
 418                 break;
 419         case e1000_82580:
 420                 ring_max = IGB_MAX_RING_82580;
 421                 break;
 422         case e1000_i350:
 423                 ring_max = IGB_MAX_RING_I350;
 424                 break;
 425         case e1000_82576:
 426                 ring_max = IGB_MAX_RING_82576;
 427                 break;
 428         default:
 429                 ring_max = IGB_MIN_RING;
 430                 break;
 431         }
 432         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 433         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 434 #ifdef IGB_RSS_DEBUG
 435         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 436 #endif
 437         sc->tx_ring_cnt = 1; /* XXX */
 438
 439         sc->intr_rate = IGB_INTR_RATE;
 440
 441         /* Do Shared Code initialization */
 442         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 443                 device_printf(dev, "Setup of Shared code failed\n");
 444                 error = ENXIO;
 445                 goto failed;
 446         }
 447
 448         e1000_get_bus_info(&sc->hw);
 449
 450         sc->hw.mac.autoneg = DO_AUTO_NEG;
 451         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 452         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 453
 454         /* Copper options */
 455         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 456                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 457                 sc->hw.phy.disable_polarity_correction = FALSE;
 458                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 459         }
 460
 461         /* Set the frame limits assuming  standard ethernet sized frames. */
 462         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 463
 464         /* Allocate RX/TX rings */
 465         error = igb_alloc_rings(sc);
 466         if (error)
 467                 goto failed;
 468
 469         /*
 470          * Setup serializers
 471          */
 472         lwkt_serialize_init(&sc->main_serialize);
 473         i = 0;
 474         sc->serializes[i++] = &sc->main_serialize;
 475
 476         sc->tx_serialize = i;
 477         for (j = 0; j < sc->tx_ring_cnt; ++j)
 478                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 479
 480         sc->rx_serialize = i;
 481         for (j = 0; j < sc->rx_ring_cnt; ++j)
 482                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 483
 484         sc->serialize_cnt = i;
 485         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 486
 487         /* Allocate the appropriate stats memory */
 488         if (sc->vf_ifp) {
 489                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 490                     M_WAITOK | M_ZERO);
 491                 igb_vf_init_stats(sc);
 492         } else {
 493                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 494                     M_WAITOK | M_ZERO);
 495         }
 496
 497         /* Allocate multicast array memory. */
 498         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 499             M_DEVBUF, M_WAITOK);
 500
 501         /* Some adapter-specific advanced features */
 502         if (sc->hw.mac.type >= e1000_i350) {
 503 #ifdef notyet
 504                 igb_set_sysctl_value(adapter, "dma_coalesce",
 505                     "configure dma coalesce",
 506                     &adapter->dma_coalesce, igb_dma_coalesce);
 507                 igb_set_sysctl_value(adapter, "eee_disabled",
 508                     "enable Energy Efficient Ethernet",
 509                     &adapter->hw.dev_spec._82575.eee_disable,
 510                     igb_eee_disabled);
 511 #else
 512                 sc->dma_coalesce = igb_dma_coalesce;
 513                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 514 #endif
 515                 e1000_set_eee_i350(&sc->hw);
 516         }
 517
 518         /*
 519          * Start from a known state, this is important in reading the nvm and
 520          * mac from that.
 521          */
 522         e1000_reset_hw(&sc->hw);
 523
 524         /* Make sure we have a good EEPROM before we read from it */
 525         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 526                 /*
 527                  * Some PCI-E parts fail the first check due to
 528                  * the link being in sleep state, call it again,
 529                  * if it fails a second time its a real issue.
 530                  */
 531                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 532                         device_printf(dev,
 533                             "The EEPROM Checksum Is Not Valid\n");
 534                         error = EIO;
 535                         goto failed;
 536                 }
 537         }
 538
 539         /* Copy the permanent MAC address out of the EEPROM */
 540         if (e1000_read_mac_addr(&sc->hw) < 0) {
 541                 device_printf(dev, "EEPROM read error while reading MAC"
 542                     " address\n");
 543                 error = EIO;
 544                 goto failed;
 545         }
 546         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 547                 device_printf(dev, "Invalid MAC address\n");
 548                 error = EIO;
 549                 goto failed;
 550         }
 551
 552 #ifdef notyet
 553         /*
 554         ** Configure Interrupts
 555         */
 556         if ((adapter->msix > 1) && (igb_enable_msix))
 557                 error = igb_allocate_msix(adapter);
 558         else /* MSI or Legacy */
 559                 error = igb_allocate_legacy(adapter);
 560         if (error)
 561                 goto err_late;
 562 #endif
 563
 564         /* Setup OS specific network interface */
 565         igb_setup_ifp(sc);
 566
 567         /* Add sysctl tree, must after igb_setup_ifp() */
 568         igb_add_sysctl(sc);
 569
 570         /* Now get a good starting state */
 571         igb_reset(sc);
 572
 573         /* Initialize statistics */
 574         igb_update_stats_counters(sc);
 575
 576         sc->hw.mac.get_link_status = 1;
 577         igb_update_link_status(sc);
 578
 579         /* Indicate SOL/IDER usage */
 580         if (e1000_check_reset_block(&sc->hw)) {
 581                 device_printf(dev,
 582                     "PHY reset is blocked due to SOL/IDER session.\n");
 583         }
 584
 585         /* Determine if we have to control management hardware */
 586         if (e1000_enable_mng_pass_thru(&sc->hw))
 587                 sc->flags |= IGB_FLAG_HAS_MGMT;
 588
 589         /*
 590          * Setup Wake-on-Lan
 591          */
 592         /* APME bit in EEPROM is mapped to WUC.APME */
 593         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 594         if (eeprom_data)
 595                 sc->wol = E1000_WUFC_MAG;
 596         /* XXX disable WOL */
 597         sc->wol = 0;
 598
 599 #ifdef notyet
 600         /* Register for VLAN events */
 601         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 602              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 603         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 604              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 605 #endif
 606
 607 #ifdef notyet
 608         igb_add_hw_stats(adapter);
 609 #endif
 610
 611         error = igb_setup_intr(sc);
 612         if (error) {
 613                 ether_ifdetach(&sc->arpcom.ac_if);
 614                 goto failed;
 615         }
 616         return 0;
 617
 618 failed:
 619         igb_detach(dev);
 620         return error;
 621 }
 622
 623 static int
 624 igb_detach(device_t dev)
 625 {
 626         struct igb_softc *sc = device_get_softc(dev);
 627
 628         if (device_is_attached(dev)) {
 629                 struct ifnet *ifp = &sc->arpcom.ac_if;
 630
 631                 ifnet_serialize_all(ifp);
 632
 633                 igb_stop(sc);
 634
 635                 e1000_phy_hw_reset(&sc->hw);
 636
 637                 /* Give control back to firmware */
 638                 igb_rel_mgmt(sc);
 639                 igb_rel_hw_control(sc);
 640
 641                 if (sc->wol) {
 642                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 643                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 644                         igb_enable_wol(dev);
 645                 }
 646
 647                 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
 648
 649                 ifnet_deserialize_all(ifp);
 650
 651                 ether_ifdetach(ifp);
 652         } else if (sc->mem_res != NULL) {
 653                 igb_rel_hw_control(sc);
 654         }
 655         bus_generic_detach(dev);
 656
 657         if (sc->intr_res != NULL) {
 658                 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
 659                     sc->intr_res);
 660         }
 661         if (sc->intr_type == PCI_INTR_TYPE_MSI)
 662                 pci_release_msi(dev);
 663
 664         if (sc->mem_res != NULL) {
 665                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 666                     sc->mem_res);
 667         }
 668
 669         igb_free_rings(sc);
 670
 671         if (sc->mta != NULL)
 672                 kfree(sc->mta, M_DEVBUF);
 673         if (sc->stats != NULL)
 674                 kfree(sc->stats, M_DEVBUF);
 675
 676         if (sc->sysctl_tree != NULL)
 677                 sysctl_ctx_free(&sc->sysctl_ctx);
 678
 679         return 0;
 680 }
 681
 682 static int
 683 igb_shutdown(device_t dev)
 684 {
 685         return igb_suspend(dev);
 686 }
 687
 688 static int
 689 igb_suspend(device_t dev)
 690 {
 691         struct igb_softc *sc = device_get_softc(dev);
 692         struct ifnet *ifp = &sc->arpcom.ac_if;
 693
 694         ifnet_serialize_all(ifp);
 695
 696         igb_stop(sc);
 697
 698         igb_rel_mgmt(sc);
 699         igb_rel_hw_control(sc);
 700
 701         if (sc->wol) {
 702                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 703                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 704                 igb_enable_wol(dev);
 705         }
 706
 707         ifnet_deserialize_all(ifp);
 708
 709         return bus_generic_suspend(dev);
 710 }
 711
 712 static int
 713 igb_resume(device_t dev)
 714 {
 715         struct igb_softc *sc = device_get_softc(dev);
 716         struct ifnet *ifp = &sc->arpcom.ac_if;
 717
 718         ifnet_serialize_all(ifp);
 719
 720         igb_init(sc);
 721         igb_get_mgmt(sc);
 722
 723         if_devstart(ifp);
 724
 725         ifnet_deserialize_all(ifp);
 726
 727         return bus_generic_resume(dev);
 728 }
 729
 730 static int
 731 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 732 {
 733         struct igb_softc *sc = ifp->if_softc;
 734         struct ifreq *ifr = (struct ifreq *)data;
 735         int max_frame_size, mask, reinit;
 736         int error = 0;
 737
 738         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 739
 740         switch (command) {
 741         case SIOCSIFMTU:
 742                 max_frame_size = 9234;
 743                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 744                     ETHER_CRC_LEN) {
 745                         error = EINVAL;
 746                         break;
 747                 }
 748
 749                 ifp->if_mtu = ifr->ifr_mtu;
 750                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 751                     ETHER_CRC_LEN;
 752
 753                 if (ifp->if_flags & IFF_RUNNING)
 754                         igb_init(sc);
 755                 break;
 756
 757         case SIOCSIFFLAGS:
 758                 if (ifp->if_flags & IFF_UP) {
 759                         if (ifp->if_flags & IFF_RUNNING) {
 760                                 if ((ifp->if_flags ^ sc->if_flags) &
 761                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 762                                         igb_disable_promisc(sc);
 763                                         igb_set_promisc(sc);
 764                                 }
 765                         } else {
 766                                 igb_init(sc);
 767                         }
 768                 } else if (ifp->if_flags & IFF_RUNNING) {
 769                         igb_stop(sc);
 770                 }
 771                 sc->if_flags = ifp->if_flags;
 772                 break;
 773
 774         case SIOCADDMULTI:
 775         case SIOCDELMULTI:
 776                 if (ifp->if_flags & IFF_RUNNING) {
 777                         igb_disable_intr(sc);
 778                         igb_set_multi(sc);
 779 #ifdef DEVICE_POLLING
 780                         if (!(ifp->if_flags & IFF_POLLING))
 781 #endif
 782                                 igb_enable_intr(sc);
 783                 }
 784                 break;
 785
 786         case SIOCSIFMEDIA:
 787                 /*
 788                  * As the speed/duplex settings are being
 789                  * changed, we need toreset the PHY.
 790                  */
 791                 sc->hw.phy.reset_disable = FALSE;
 792
 793                 /* Check SOL/IDER usage */
 794                 if (e1000_check_reset_block(&sc->hw)) {
 795                         if_printf(ifp, "Media change is "
 796                             "blocked due to SOL/IDER session.\n");
 797                         break;
 798                 }
 799                 /* FALL THROUGH */
 800
 801         case SIOCGIFMEDIA:
 802                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 803                 break;
 804
 805         case SIOCSIFCAP:
 806                 reinit = 0;
 807                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 808                 if (mask & IFCAP_HWCSUM) {
 809                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
 810                         reinit = 1;
 811                 }
 812                 if (mask & IFCAP_VLAN_HWTAGGING) {
 813                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 814                         reinit = 1;
 815                 }
 816                 if (mask & IFCAP_RSS)
 817                         ifp->if_capenable ^= IFCAP_RSS;
 818                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 819                         igb_init(sc);
 820                 break;
 821
 822         default:
 823                 error = ether_ioctl(ifp, command, data);
 824                 break;
 825         }
 826         return error;
 827 }
 828
 829 static void
 830 igb_init(void *xsc)
 831 {
 832         struct igb_softc *sc = xsc;
 833         struct ifnet *ifp = &sc->arpcom.ac_if;
 834         int i;
 835
 836         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 837
 838         igb_stop(sc);
 839
 840         /* Get the latest mac address, User can use a LAA */
 841         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 842
 843         /* Put the address into the Receive Address Array */
 844         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 845
 846         igb_reset(sc);
 847         igb_update_link_status(sc);
 848
 849         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 850
 851         /* Set hardware offload abilities */
 852         if (ifp->if_capenable & IFCAP_TXCSUM)
 853                 ifp->if_hwassist = IGB_CSUM_FEATURES;
 854         else
 855                 ifp->if_hwassist = 0;
 856
 857         /* Configure for OS presence */
 858         igb_get_mgmt(sc);
 859
 860         /* Prepare transmit descriptors and buffers */
 861         for (i = 0; i < sc->tx_ring_cnt; ++i)
 862                 igb_init_tx_ring(&sc->tx_rings[i]);
 863         igb_init_tx_unit(sc);
 864
 865         /* Setup Multicast table */
 866         igb_set_multi(sc);
 867
 868 #if 0
 869         /*
 870          * Figure out the desired mbuf pool
 871          * for doing jumbo/packetsplit
 872          */
 873         if (adapter->max_frame_size <= 2048)
 874                 adapter->rx_mbuf_sz = MCLBYTES;
 875         else if (adapter->max_frame_size <= 4096)
 876                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 877         else
 878                 adapter->rx_mbuf_sz = MJUM9BYTES;
 879 #endif
 880
 881         /* Initialize interrupt */
 882         igb_init_intr(sc);
 883
 884         /* Prepare receive descriptors and buffers */
 885         for (i = 0; i < sc->rx_ring_cnt; ++i) {
 886                 int error;
 887
 888                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 889                 if (error) {
 890                         if_printf(ifp, "Could not setup receive structures\n");
 891                         igb_stop(sc);
 892                         return;
 893                 }
 894         }
 895         igb_init_rx_unit(sc);
 896
 897         /* Enable VLAN support */
 898         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 899                 igb_set_vlan(sc);
 900
 901         /* Don't lose promiscuous settings */
 902         igb_set_promisc(sc);
 903
 904         ifp->if_flags |= IFF_RUNNING;
 905         ifp->if_flags &= ~IFF_OACTIVE;
 906
 907         callout_reset(&sc->timer, hz, igb_timer, sc);
 908         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 909
 910 #if 0
 911         if (adapter->msix > 1) /* Set up queue routing */
 912                 igb_configure_queues(adapter);
 913 #endif
 914
 915         /* this clears any pending interrupts */
 916         E1000_READ_REG(&sc->hw, E1000_ICR);
 917 #ifdef DEVICE_POLLING
 918         /*
 919          * Only enable interrupts if we are not polling, make sure
 920          * they are off otherwise.
 921          */
 922         if (ifp->if_flags & IFF_POLLING)
 923                 igb_disable_intr(sc);
 924         else
 925 #endif /* DEVICE_POLLING */
 926         {
 927                 igb_enable_intr(sc);
 928                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
 929         }
 930
 931         /* Set Energy Efficient Ethernet */
 932         e1000_set_eee_i350(&sc->hw);
 933
 934         /* Don't reset the phy next time init gets called */
 935         sc->hw.phy.reset_disable = TRUE;
 936 }
 937
 938 static void
 939 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 940 {
 941         struct igb_softc *sc = ifp->if_softc;
 942         u_char fiber_type = IFM_1000_SX;
 943
 944         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 945
 946         igb_update_link_status(sc);
 947
 948         ifmr->ifm_status = IFM_AVALID;
 949         ifmr->ifm_active = IFM_ETHER;
 950
 951         if (!sc->link_active)
 952                 return;
 953
 954         ifmr->ifm_status |= IFM_ACTIVE;
 955
 956         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
 957             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
 958                 ifmr->ifm_active |= fiber_type | IFM_FDX;
 959         } else {
 960                 switch (sc->link_speed) {
 961                 case 10:
 962                         ifmr->ifm_active |= IFM_10_T;
 963                         break;
 964
 965                 case 100:
 966                         ifmr->ifm_active |= IFM_100_TX;
 967                         break;
 968
 969                 case 1000:
 970                         ifmr->ifm_active |= IFM_1000_T;
 971                         break;
 972                 }
 973                 if (sc->link_duplex == FULL_DUPLEX)
 974                         ifmr->ifm_active |= IFM_FDX;
 975                 else
 976                         ifmr->ifm_active |= IFM_HDX;
 977         }
 978 }
 979
 980 static int
 981 igb_media_change(struct ifnet *ifp)
 982 {
 983         struct igb_softc *sc = ifp->if_softc;
 984         struct ifmedia *ifm = &sc->media;
 985
 986         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 987
 988         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 989                 return EINVAL;
 990
 991         switch (IFM_SUBTYPE(ifm->ifm_media)) {
 992         case IFM_AUTO:
 993                 sc->hw.mac.autoneg = DO_AUTO_NEG;
 994                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 995                 break;
 996
 997         case IFM_1000_LX:
 998         case IFM_1000_SX:
 999         case IFM_1000_T:
1000                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1001                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1002                 break;
1003
1004         case IFM_100_TX:
1005                 sc->hw.mac.autoneg = FALSE;
1006                 sc->hw.phy.autoneg_advertised = 0;
1007                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1008                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1009                 else
1010                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1011                 break;
1012
1013         case IFM_10_T:
1014                 sc->hw.mac.autoneg = FALSE;
1015                 sc->hw.phy.autoneg_advertised = 0;
1016                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1017                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1018                 else
1019                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1020                 break;
1021
1022         default:
1023                 if_printf(ifp, "Unsupported media type\n");
1024                 break;
1025         }
1026
1027         igb_init(sc);
1028
1029         return 0;
1030 }
1031
1032 static void
1033 igb_set_promisc(struct igb_softc *sc)
1034 {
1035         struct ifnet *ifp = &sc->arpcom.ac_if;
1036         struct e1000_hw *hw = &sc->hw;
1037         uint32_t reg;
1038
1039         if (sc->vf_ifp) {
1040                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1041                 return;
1042         }
1043
1044         reg = E1000_READ_REG(hw, E1000_RCTL);
1045         if (ifp->if_flags & IFF_PROMISC) {
1046                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1047                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1048         } else if (ifp->if_flags & IFF_ALLMULTI) {
1049                 reg |= E1000_RCTL_MPE;
1050                 reg &= ~E1000_RCTL_UPE;
1051                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1052         }
1053 }
1054
1055 static void
1056 igb_disable_promisc(struct igb_softc *sc)
1057 {
1058         struct e1000_hw *hw = &sc->hw;
1059         uint32_t reg;
1060
1061         if (sc->vf_ifp) {
1062                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1063                 return;
1064         }
1065         reg = E1000_READ_REG(hw, E1000_RCTL);
1066         reg &= ~E1000_RCTL_UPE;
1067         reg &= ~E1000_RCTL_MPE;
1068         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1069 }
1070
1071 static void
1072 igb_set_multi(struct igb_softc *sc)
1073 {
1074         struct ifnet *ifp = &sc->arpcom.ac_if;
1075         struct ifmultiaddr *ifma;
1076         uint32_t reg_rctl = 0;
1077         uint8_t *mta;
1078         int mcnt = 0;
1079
1080         mta = sc->mta;
1081         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1082
1083         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1084                 if (ifma->ifma_addr->sa_family != AF_LINK)
1085                         continue;
1086
1087                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1088                         break;
1089
1090                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1091                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1092                 mcnt++;
1093         }
1094
1095         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1096                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1097                 reg_rctl |= E1000_RCTL_MPE;
1098                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1099         } else {
1100                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1101         }
1102 }
1103
1104 static void
1105 igb_timer(void *xsc)
1106 {
1107         struct igb_softc *sc = xsc;
1108
1109         lwkt_serialize_enter(&sc->main_serialize);
1110
1111         igb_update_link_status(sc);
1112         igb_update_stats_counters(sc);
1113
1114         callout_reset(&sc->timer, hz, igb_timer, sc);
1115
1116         lwkt_serialize_exit(&sc->main_serialize);
1117 }
1118
1119 static void
1120 igb_update_link_status(struct igb_softc *sc)
1121 {
1122         struct ifnet *ifp = &sc->arpcom.ac_if;
1123         struct e1000_hw *hw = &sc->hw;
1124         uint32_t link_check, thstat, ctrl;
1125
1126         link_check = thstat = ctrl = 0;
1127
1128         /* Get the cached link value or read for real */
1129         switch (hw->phy.media_type) {
1130         case e1000_media_type_copper:
1131                 if (hw->mac.get_link_status) {
1132                         /* Do the work to read phy */
1133                         e1000_check_for_link(hw);
1134                         link_check = !hw->mac.get_link_status;
1135                 } else {
1136                         link_check = TRUE;
1137                 }
1138                 break;
1139
1140         case e1000_media_type_fiber:
1141                 e1000_check_for_link(hw);
1142                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1143                 break;
1144
1145         case e1000_media_type_internal_serdes:
1146                 e1000_check_for_link(hw);
1147                 link_check = hw->mac.serdes_has_link;
1148                 break;
1149
1150         /* VF device is type_unknown */
1151         case e1000_media_type_unknown:
1152                 e1000_check_for_link(hw);
1153                 link_check = !hw->mac.get_link_status;
1154                 /* Fall thru */
1155         default:
1156                 break;
1157         }
1158
1159         /* Check for thermal downshift or shutdown */
1160         if (hw->mac.type == e1000_i350) {
1161                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1162                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1163         }
1164
1165         /* Now we check if a transition has happened */
1166         if (link_check && sc->link_active == 0) {
1167                 e1000_get_speed_and_duplex(hw,
1168                     &sc->link_speed, &sc->link_duplex);
1169                 if (bootverbose) {
1170                         if_printf(ifp, "Link is up %d Mbps %s\n",
1171                             sc->link_speed,
1172                             sc->link_duplex == FULL_DUPLEX ?
1173                             "Full Duplex" : "Half Duplex");
1174                 }
1175                 sc->link_active = 1;
1176
1177                 ifp->if_baudrate = sc->link_speed * 1000000;
1178                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1179                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1180                         if_printf(ifp, "Link: thermal downshift\n");
1181                 /* This can sleep */
1182                 ifp->if_link_state = LINK_STATE_UP;
1183                 if_link_state_change(ifp);
1184         } else if (!link_check && sc->link_active == 1) {
1185                 ifp->if_baudrate = sc->link_speed = 0;
1186                 sc->link_duplex = 0;
1187                 if (bootverbose)
1188                         if_printf(ifp, "Link is Down\n");
1189                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1190                     (thstat & E1000_THSTAT_PWR_DOWN))
1191                         if_printf(ifp, "Link: thermal shutdown\n");
1192                 sc->link_active = 0;
1193                 /* This can sleep */
1194                 ifp->if_link_state = LINK_STATE_DOWN;
1195                 if_link_state_change(ifp);
1196         }
1197 }
1198
1199 static void
1200 igb_stop(struct igb_softc *sc)
1201 {
1202         struct ifnet *ifp = &sc->arpcom.ac_if;
1203         int i;
1204
1205         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1206
1207         igb_disable_intr(sc);
1208
1209         callout_stop(&sc->timer);
1210
1211         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1212         ifp->if_timer = 0;
1213
1214         e1000_reset_hw(&sc->hw);
1215         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1216
1217         e1000_led_off(&sc->hw);
1218         e1000_cleanup_led(&sc->hw);
1219
1220         for (i = 0; i < sc->tx_ring_cnt; ++i)
1221                 igb_free_tx_ring(&sc->tx_rings[i]);
1222         for (i = 0; i < sc->rx_ring_cnt; ++i)
1223                 igb_free_rx_ring(&sc->rx_rings[i]);
1224 }
1225
1226 static void
1227 igb_reset(struct igb_softc *sc)
1228 {
1229         struct ifnet *ifp = &sc->arpcom.ac_if;
1230         struct e1000_hw *hw = &sc->hw;
1231         struct e1000_fc_info *fc = &hw->fc;
1232         uint32_t pba = 0;
1233         uint16_t hwm;
1234
1235         /* Let the firmware know the OS is in control */
1236         igb_get_hw_control(sc);
1237
1238         /*
1239          * Packet Buffer Allocation (PBA)
1240          * Writing PBA sets the receive portion of the buffer
1241          * the remainder is used for the transmit buffer.
1242          */
1243         switch (hw->mac.type) {
1244         case e1000_82575:
1245                 pba = E1000_PBA_32K;
1246                 break;
1247
1248         case e1000_82576:
1249         case e1000_vfadapt:
1250                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1251                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1252                 break;
1253
1254         case e1000_82580:
1255         case e1000_i350:
1256         case e1000_vfadapt_i350:
1257                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1258                 pba = e1000_rxpbs_adjust_82580(pba);
1259                 break;
1260                 /* XXX pba = E1000_PBA_35K; */
1261
1262         default:
1263                 break;
1264         }
1265
1266         /* Special needs in case of Jumbo frames */
1267         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1268                 uint32_t tx_space, min_tx, min_rx;
1269
1270                 pba = E1000_READ_REG(hw, E1000_PBA);
1271                 tx_space = pba >> 16;
1272                 pba &= 0xffff;
1273
1274                 min_tx = (sc->max_frame_size +
1275                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1276                 min_tx = roundup2(min_tx, 1024);
1277                 min_tx >>= 10;
1278                 min_rx = sc->max_frame_size;
1279                 min_rx = roundup2(min_rx, 1024);
1280                 min_rx >>= 10;
1281                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1282                         pba = pba - (min_tx - tx_space);
1283                         /*
1284                          * if short on rx space, rx wins
1285                          * and must trump tx adjustment
1286                          */
1287                         if (pba < min_rx)
1288                                 pba = min_rx;
1289                 }
1290                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1291         }
1292
1293         /*
1294          * These parameters control the automatic generation (Tx) and
1295          * response (Rx) to Ethernet PAUSE frames.
1296          * - High water mark should allow for at least two frames to be
1297          *   received after sending an XOFF.
1298          * - Low water mark works best when it is very near the high water mark.
1299          *   This allows the receiver to restart by sending XON when it has
1300          *   drained a bit.
1301          */
1302         hwm = min(((pba << 10) * 9 / 10),
1303             ((pba << 10) - 2 * sc->max_frame_size));
1304
1305         if (hw->mac.type < e1000_82576) {
1306                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1307                 fc->low_water = fc->high_water - 8;
1308         } else {
1309                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1310                 fc->low_water = fc->high_water - 16;
1311         }
1312         fc->pause_time = IGB_FC_PAUSE_TIME;
1313         fc->send_xon = TRUE;
1314
1315         /* Issue a global reset */
1316         e1000_reset_hw(hw);
1317         E1000_WRITE_REG(hw, E1000_WUC, 0);
1318
1319         if (e1000_init_hw(hw) < 0)
1320                 if_printf(ifp, "Hardware Initialization Failed\n");
1321
1322         /* Setup DMA Coalescing */
1323         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1324                 uint32_t reg;
1325
1326                 hwm = (pba - 4) << 10;
1327                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1328                     & E1000_DMACR_DMACTHR_MASK;
1329
1330                 /* transition to L0x or L1 if available..*/
1331                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1332
1333                 /* timer = +-1000 usec in 32usec intervals */
1334                 reg |= (1000 >> 5);
1335                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1336
1337                 /* No lower threshold */
1338                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1339
1340                 /* set hwm to PBA -  2 * max frame size */
1341                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1342
1343                 /* Set the interval before transition */
1344                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1345                 reg |= 0x800000FF; /* 255 usec */
1346                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1347
1348                 /* free space in tx packet buffer to wake from DMA coal */
1349                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1350                     (20480 - (2 * sc->max_frame_size)) >> 6);
1351
1352                 /* make low power state decision controlled by DMA coal */
1353                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1354                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1355                     reg | E1000_PCIEMISC_LX_DECISION);
1356                 if_printf(ifp, "DMA Coalescing enabled\n");
1357         }
1358
1359         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1360         e1000_get_phy_info(hw);
1361         e1000_check_for_link(hw);
1362 }
1363
1364 static void
1365 igb_setup_ifp(struct igb_softc *sc)
1366 {
1367         struct ifnet *ifp = &sc->arpcom.ac_if;
1368
1369         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1370         ifp->if_softc = sc;
1371         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1372         ifp->if_init =  igb_init;
1373         ifp->if_ioctl = igb_ioctl;
1374         ifp->if_start = igb_start;
1375         ifp->if_serialize = igb_serialize;
1376         ifp->if_deserialize = igb_deserialize;
1377         ifp->if_tryserialize = igb_tryserialize;
1378 #ifdef INVARIANTS
1379         ifp->if_serialize_assert = igb_serialize_assert;
1380 #endif
1381 #ifdef DEVICE_POLLING
1382         ifp->if_poll = igb_poll;
1383 #endif
1384         ifp->if_watchdog = igb_watchdog;
1385
1386         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1387         ifq_set_ready(&ifp->if_snd);
1388
1389         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1390
1391         ifp->if_capabilities =
1392             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1393         if (IGB_ENABLE_HWRSS(sc))
1394                 ifp->if_capabilities |= IFCAP_RSS;
1395         ifp->if_capenable = ifp->if_capabilities;
1396         ifp->if_hwassist = IGB_CSUM_FEATURES;
1397
1398         /*
1399          * Tell the upper layer(s) we support long frames
1400          */
1401         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1402
1403         /*
1404          * Specify the media types supported by this adapter and register
1405          * callbacks to update media and link information
1406          */
1407         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1408         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1409             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1410                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1411                     0, NULL);
1412                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1413         } else {
1414                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1415                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1416                     0, NULL);
1417                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1418                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1419                     0, NULL);
1420                 if (sc->hw.phy.type != e1000_phy_ife) {
1421                         ifmedia_add(&sc->media,
1422                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1423                         ifmedia_add(&sc->media,
1424                             IFM_ETHER | IFM_1000_T, 0, NULL);
1425                 }
1426         }
1427         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1428         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1429 }
1430
1431 static void
1432 igb_add_sysctl(struct igb_softc *sc)
1433 {
1434 #ifdef IGB_RSS_DEBUG
1435         char rx_pkt[32];
1436         int i;
1437 #endif
1438
1439         sysctl_ctx_init(&sc->sysctl_ctx);
1440         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1441             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1442             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1443         if (sc->sysctl_tree == NULL) {
1444                 device_printf(sc->dev, "can't add sysctl node\n");
1445                 return;
1446         }
1447
1448         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1449             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1450         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1451             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1452             "# of RX descs");
1453         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1454             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1455             "# of TX descs");
1456
1457         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1458             OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1459             sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1460
1461         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1462             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1463             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1464             "# of segments per TX interrupt");
1465
1466 #ifdef IGB_RSS_DEBUG
1467         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1468             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1469             "RSS debug level");
1470         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1471                 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
1472                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1473                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, rx_pkt,
1474                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1475         }
1476 #endif
1477 }
1478
1479 static int
1480 igb_alloc_rings(struct igb_softc *sc)
1481 {
1482         int error, i;
1483
1484         /*
1485          * Create top level busdma tag
1486          */
1487         error = bus_dma_tag_create(NULL, 1, 0,
1488             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1489             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1490             &sc->parent_tag);
1491         if (error) {
1492                 device_printf(sc->dev, "could not create top level DMA tag\n");
1493                 return error;
1494         }
1495
1496         /*
1497          * Allocate TX descriptor rings and buffers
1498          */
1499         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1500             M_DEVBUF, M_WAITOK | M_ZERO);
1501         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1502                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1503
1504                 /* Set up some basics */
1505                 txr->sc = sc;
1506                 txr->me = i;
1507                 lwkt_serialize_init(&txr->tx_serialize);
1508
1509                 error = igb_create_tx_ring(txr);
1510                 if (error)
1511                         return error;
1512         }
1513
1514         /*
1515          * Allocate RX descriptor rings and buffers
1516          */
1517         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1518             M_DEVBUF, M_WAITOK | M_ZERO);
1519         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1520                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1521
1522                 /* Set up some basics */
1523                 rxr->sc = sc;
1524                 rxr->me = i;
1525                 lwkt_serialize_init(&rxr->rx_serialize);
1526
1527                 error = igb_create_rx_ring(rxr);
1528                 if (error)
1529                         return error;
1530         }
1531
1532         return 0;
1533 }
1534
1535 static void
1536 igb_free_rings(struct igb_softc *sc)
1537 {
1538         int i;
1539
1540         if (sc->tx_rings != NULL) {
1541                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1542                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1543
1544                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1545                 }
1546                 kfree(sc->tx_rings, M_DEVBUF);
1547         }
1548
1549         if (sc->rx_rings != NULL) {
1550                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1551                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1552
1553                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1554                 }
1555                 kfree(sc->rx_rings, M_DEVBUF);
1556         }
1557 }
1558
1559 static int
1560 igb_create_tx_ring(struct igb_tx_ring *txr)
1561 {
1562         int tsize, error, i;
1563
1564         /*
1565          * Validate number of transmit descriptors. It must not exceed
1566          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1567          */
1568         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1569             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1570                 device_printf(txr->sc->dev,
1571                     "Using %d TX descriptors instead of %d!\n",
1572                     IGB_DEFAULT_TXD, igb_txd);
1573                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1574         } else {
1575                 txr->num_tx_desc = igb_txd;
1576         }
1577
1578         /*
1579          * Allocate TX descriptor ring
1580          */
1581         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1582             IGB_DBA_ALIGN);
1583         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1584             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1585             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1586         if (txr->txdma.dma_vaddr == NULL) {
1587                 device_printf(txr->sc->dev,
1588                     "Unable to allocate TX Descriptor memory\n");
1589                 return ENOMEM;
1590         }
1591         txr->tx_base = txr->txdma.dma_vaddr;
1592         bzero(txr->tx_base, tsize);
1593
1594         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1595             M_DEVBUF, M_WAITOK | M_ZERO);
1596
1597         /*
1598          * Allocate TX head write-back buffer
1599          */
1600         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1601             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1602             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1603         if (txr->tx_hdr == NULL) {
1604                 device_printf(txr->sc->dev,
1605                     "Unable to allocate TX head write-back buffer\n");
1606                 return ENOMEM;
1607         }
1608
1609         /*
1610          * Create DMA tag for TX buffers
1611          */
1612         error = bus_dma_tag_create(txr->sc->parent_tag,
1613             1, 0,               /* alignment, bounds */
1614             BUS_SPACE_MAXADDR,  /* lowaddr */
1615             BUS_SPACE_MAXADDR,  /* highaddr */
1616             NULL, NULL,         /* filter, filterarg */
1617             IGB_TSO_SIZE,       /* maxsize */
1618             IGB_MAX_SCATTER,    /* nsegments */
1619             PAGE_SIZE,          /* maxsegsize */
1620             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1621             BUS_DMA_ONEBPAGE,   /* flags */
1622             &txr->tx_tag);
1623         if (error) {
1624                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1625                 kfree(txr->tx_buf, M_DEVBUF);
1626                 txr->tx_buf = NULL;
1627                 return error;
1628         }
1629
1630         /*
1631          * Create DMA maps for TX buffers
1632          */
1633         for (i = 0; i < txr->num_tx_desc; ++i) {
1634                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1635
1636                 error = bus_dmamap_create(txr->tx_tag,
1637                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1638                 if (error) {
1639                         device_printf(txr->sc->dev,
1640                             "Unable to create TX DMA map\n");
1641                         igb_destroy_tx_ring(txr, i);
1642                         return error;
1643                 }
1644         }
1645
1646         /*
1647          * Initialize various watermark
1648          */
1649         txr->spare_desc = IGB_TX_SPARE;
1650         txr->intr_nsegs = txr->num_tx_desc / 16;
1651         txr->oact_hi_desc = txr->num_tx_desc / 2;
1652         txr->oact_lo_desc = txr->num_tx_desc / 8;
1653         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1654                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1655         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1656                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1657
1658         return 0;
1659 }
1660
1661 static void
1662 igb_free_tx_ring(struct igb_tx_ring *txr)
1663 {
1664         int i;
1665
1666         for (i = 0; i < txr->num_tx_desc; ++i) {
1667                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1668
1669                 if (txbuf->m_head != NULL) {
1670                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1671                         m_freem(txbuf->m_head);
1672                         txbuf->m_head = NULL;
1673                 }
1674         }
1675 }
1676
1677 static void
1678 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1679 {
1680         int i;
1681
1682         if (txr->txdma.dma_vaddr != NULL) {
1683                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1684                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1685                     txr->txdma.dma_map);
1686                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1687                 txr->txdma.dma_vaddr = NULL;
1688         }
1689
1690         if (txr->tx_hdr != NULL) {
1691                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1692                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1693                     txr->tx_hdr_dmap);
1694                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1695                 txr->tx_hdr = NULL;
1696         }
1697
1698         if (txr->tx_buf == NULL)
1699                 return;
1700
1701         for (i = 0; i < ndesc; ++i) {
1702                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1703
1704                 KKASSERT(txbuf->m_head == NULL);
1705                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1706         }
1707         bus_dma_tag_destroy(txr->tx_tag);
1708
1709         kfree(txr->tx_buf, M_DEVBUF);
1710         txr->tx_buf = NULL;
1711 }
1712
1713 static void
1714 igb_init_tx_ring(struct igb_tx_ring *txr)
1715 {
1716         /* Clear the old descriptor contents */
1717         bzero(txr->tx_base,
1718             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1719
1720         /* Clear TX head write-back buffer */
1721         *(txr->tx_hdr) = 0;
1722
1723         /* Reset indices */
1724         txr->next_avail_desc = 0;
1725         txr->next_to_clean = 0;
1726         txr->tx_nsegs = 0;
1727
1728         /* Set number of descriptors available */
1729         txr->tx_avail = txr->num_tx_desc;
1730 }
1731
1732 static void
1733 igb_init_tx_unit(struct igb_softc *sc)
1734 {
1735         struct e1000_hw *hw = &sc->hw;
1736         uint32_t tctl;
1737         int i;
1738
1739         /* Setup the Tx Descriptor Rings */
1740         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1741                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1742                 uint64_t bus_addr = txr->txdma.dma_paddr;
1743                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1744                 uint32_t txdctl = 0;
1745                 uint32_t dca_txctrl;
1746
1747                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1748                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1749                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1750                     (uint32_t)(bus_addr >> 32));
1751                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1752                     (uint32_t)bus_addr);
1753
1754                 /* Setup the HW Tx Head and Tail descriptor pointers */
1755                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1756                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1757
1758                 txdctl |= IGB_TX_PTHRESH;
1759                 txdctl |= IGB_TX_HTHRESH << 8;
1760                 txdctl |= IGB_TX_WTHRESH << 16;
1761                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1762                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1763
1764                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1765                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1766                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1767
1768                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1769                     (uint32_t)(hdr_paddr >> 32));
1770                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1771                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1772         }
1773
1774         if (sc->vf_ifp)
1775                 return;
1776
1777         e1000_config_collision_dist(hw);
1778
1779         /* Program the Transmit Control Register */
1780         tctl = E1000_READ_REG(hw, E1000_TCTL);
1781         tctl &= ~E1000_TCTL_CT;
1782         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1783             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1784
1785         /* This write will effectively turn on the transmit unit. */
1786         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1787 }
1788
1789 static boolean_t
1790 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1791 {
1792         struct e1000_adv_tx_context_desc *TXD;
1793         struct igb_tx_buf *txbuf;
1794         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1795         struct ether_vlan_header *eh;
1796         struct ip *ip = NULL;
1797         int ehdrlen, ctxd, ip_hlen = 0;
1798         uint16_t etype, vlantag = 0;
1799         boolean_t offload = TRUE;
1800
1801         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1802                 offload = FALSE;
1803
1804         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1805         ctxd = txr->next_avail_desc;
1806         txbuf = &txr->tx_buf[ctxd];
1807         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1808
1809         /*
1810          * In advanced descriptors the vlan tag must
1811          * be placed into the context descriptor, thus
1812          * we need to be here just for that setup.
1813          */
1814         if (mp->m_flags & M_VLANTAG) {
1815                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1816                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1817         } else if (!offload) {
1818                 return FALSE;
1819         }
1820
1821         /*
1822          * Determine where frame payload starts.
1823          * Jump over vlan headers if already present,
1824          * helpful for QinQ too.
1825          */
1826         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1827             ("igb_txctx_pullup is not called (eh)?\n"));
1828         eh = mtod(mp, struct ether_vlan_header *);
1829         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1830                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1831                     ("igb_txctx_pullup is not called (evh)?\n"));
1832                 etype = ntohs(eh->evl_proto);
1833                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1834         } else {
1835                 etype = ntohs(eh->evl_encap_proto);
1836                 ehdrlen = ETHER_HDR_LEN;
1837         }
1838
1839         /* Set the ether header length */
1840         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1841
1842         switch (etype) {
1843         case ETHERTYPE_IP:
1844                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1845                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1846
1847                 /* NOTE: We could only safely access ip.ip_vhl part */
1848                 ip = (struct ip *)(mp->m_data + ehdrlen);
1849                 ip_hlen = ip->ip_hl << 2;
1850
1851                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1852                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1853                 break;
1854
1855 #ifdef notyet
1856         case ETHERTYPE_IPV6:
1857                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1858                 ip_hlen = sizeof(struct ip6_hdr);
1859                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1860                 break;
1861 #endif
1862
1863         default:
1864                 offload = FALSE;
1865                 break;
1866         }
1867
1868         vlan_macip_lens |= ip_hlen;
1869         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1870
1871         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1872                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1873         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1874                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1875
1876         /* 82575 needs the queue index added */
1877         if (txr->sc->hw.mac.type == e1000_82575)
1878                 mss_l4len_idx = txr->me << 4;
1879
1880         /* Now copy bits into descriptor */
1881         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1882         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1883         TXD->seqnum_seed = htole32(0);
1884         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1885
1886         txbuf->m_head = NULL;
1887
1888         /* We've consumed the first desc, adjust counters */
1889         if (++ctxd == txr->num_tx_desc)
1890                 ctxd = 0;
1891         txr->next_avail_desc = ctxd;
1892         --txr->tx_avail;
1893
1894         return offload;
1895 }
1896
1897 static void
1898 igb_txeof(struct igb_tx_ring *txr)
1899 {
1900         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1901         int first, hdr, avail;
1902
1903         if (txr->tx_avail == txr->num_tx_desc)
1904                 return;
1905
1906         first = txr->next_to_clean;
1907         hdr = *(txr->tx_hdr);
1908
1909         if (first == hdr)
1910                 return;
1911
1912         avail = txr->tx_avail;
1913         while (first != hdr) {
1914                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1915
1916                 ++avail;
1917                 if (txbuf->m_head) {
1918                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1919                         m_freem(txbuf->m_head);
1920                         txbuf->m_head = NULL;
1921                         ++ifp->if_opackets;
1922                 }
1923                 if (++first == txr->num_tx_desc)
1924                         first = 0;
1925         }
1926         txr->next_to_clean = first;
1927         txr->tx_avail = avail;
1928
1929         /*
1930          * If we have a minimum free, clear IFF_OACTIVE
1931          * to tell the stack that it is OK to send packets.
1932          */
1933         if (IGB_IS_NOT_OACTIVE(txr)) {
1934                 ifp->if_flags &= ~IFF_OACTIVE;
1935
1936                 /*
1937                  * We have enough TX descriptors, turn off
1938                  * the watchdog.  We allow small amount of
1939                  * packets (roughly intr_nsegs) pending on
1940                  * the transmit ring.
1941                  */
1942                 ifp->if_timer = 0;
1943         }
1944 }
1945
1946 static int
1947 igb_create_rx_ring(struct igb_rx_ring *rxr)
1948 {
1949         int rsize, i, error;
1950
1951         /*
1952          * Validate number of receive descriptors. It must not exceed
1953          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1954          */
1955         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1956             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1957                 device_printf(rxr->sc->dev,
1958                     "Using %d RX descriptors instead of %d!\n",
1959                     IGB_DEFAULT_RXD, igb_rxd);
1960                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1961         } else {
1962                 rxr->num_rx_desc = igb_rxd;
1963         }
1964
1965         /*
1966          * Allocate RX descriptor ring
1967          */
1968         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1969             IGB_DBA_ALIGN);
1970         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1971             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1972             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1973             &rxr->rxdma.dma_paddr);
1974         if (rxr->rxdma.dma_vaddr == NULL) {
1975                 device_printf(rxr->sc->dev,
1976                     "Unable to allocate RxDescriptor memory\n");
1977                 return ENOMEM;
1978         }
1979         rxr->rx_base = rxr->rxdma.dma_vaddr;
1980         bzero(rxr->rx_base, rsize);
1981
1982         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
1983             M_DEVBUF, M_WAITOK | M_ZERO);
1984
1985         /*
1986          * Create DMA tag for RX buffers
1987          */
1988         error = bus_dma_tag_create(rxr->sc->parent_tag,
1989             1, 0,               /* alignment, bounds */
1990             BUS_SPACE_MAXADDR,  /* lowaddr */
1991             BUS_SPACE_MAXADDR,  /* highaddr */
1992             NULL, NULL,         /* filter, filterarg */
1993             MCLBYTES,           /* maxsize */
1994             1,                  /* nsegments */
1995             MCLBYTES,           /* maxsegsize */
1996             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1997             &rxr->rx_tag);
1998         if (error) {
1999                 device_printf(rxr->sc->dev,
2000                     "Unable to create RX payload DMA tag\n");
2001                 kfree(rxr->rx_buf, M_DEVBUF);
2002                 rxr->rx_buf = NULL;
2003                 return error;
2004         }
2005
2006         /*
2007          * Create spare DMA map for RX buffers
2008          */
2009         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2010             &rxr->rx_sparemap);
2011         if (error) {
2012                 device_printf(rxr->sc->dev,
2013                     "Unable to create spare RX DMA maps\n");
2014                 bus_dma_tag_destroy(rxr->rx_tag);
2015                 kfree(rxr->rx_buf, M_DEVBUF);
2016                 rxr->rx_buf = NULL;
2017                 return error;
2018         }
2019
2020         /*
2021          * Create DMA maps for RX buffers
2022          */
2023         for (i = 0; i < rxr->num_rx_desc; i++) {
2024                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2025
2026                 error = bus_dmamap_create(rxr->rx_tag,
2027                     BUS_DMA_WAITOK, &rxbuf->map);
2028                 if (error) {
2029                         device_printf(rxr->sc->dev,
2030                             "Unable to create RX DMA maps\n");
2031                         igb_destroy_rx_ring(rxr, i);
2032                         return error;
2033                 }
2034         }
2035         return 0;
2036 }
2037
2038 static void
2039 igb_free_rx_ring(struct igb_rx_ring *rxr)
2040 {
2041         int i;
2042
2043         for (i = 0; i < rxr->num_rx_desc; ++i) {
2044                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2045
2046                 if (rxbuf->m_head != NULL) {
2047                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2048                         m_freem(rxbuf->m_head);
2049                         rxbuf->m_head = NULL;
2050                 }
2051         }
2052
2053         if (rxr->fmp != NULL)
2054                 m_freem(rxr->fmp);
2055         rxr->fmp = NULL;
2056         rxr->lmp = NULL;
2057 }
2058
2059 static void
2060 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2061 {
2062         int i;
2063
2064         if (rxr->rxdma.dma_vaddr != NULL) {
2065                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2066                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2067                     rxr->rxdma.dma_map);
2068                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2069                 rxr->rxdma.dma_vaddr = NULL;
2070         }
2071
2072         if (rxr->rx_buf == NULL)
2073                 return;
2074
2075         for (i = 0; i < ndesc; ++i) {
2076                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2077
2078                 KKASSERT(rxbuf->m_head == NULL);
2079                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2080         }
2081         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2082         bus_dma_tag_destroy(rxr->rx_tag);
2083
2084         kfree(rxr->rx_buf, M_DEVBUF);
2085         rxr->rx_buf = NULL;
2086 }
2087
2088 static void
2089 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2090 {
2091         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2092         rxd->wb.upper.status_error = 0;
2093 }
2094
2095 static int
2096 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2097 {
2098         struct mbuf *m;
2099         bus_dma_segment_t seg;
2100         bus_dmamap_t map;
2101         struct igb_rx_buf *rxbuf;
2102         int error, nseg;
2103
2104         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2105         if (m == NULL) {
2106                 if (wait) {
2107                         if_printf(&rxr->sc->arpcom.ac_if,
2108                             "Unable to allocate RX mbuf\n");
2109                 }
2110                 return ENOBUFS;
2111         }
2112         m->m_len = m->m_pkthdr.len = MCLBYTES;
2113
2114         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2115                 m_adj(m, ETHER_ALIGN);
2116
2117         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2118             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2119         if (error) {
2120                 m_freem(m);
2121                 if (wait) {
2122                         if_printf(&rxr->sc->arpcom.ac_if,
2123                             "Unable to load RX mbuf\n");
2124                 }
2125                 return error;
2126         }
2127
2128         rxbuf = &rxr->rx_buf[i];
2129         if (rxbuf->m_head != NULL)
2130                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2131
2132         map = rxbuf->map;
2133         rxbuf->map = rxr->rx_sparemap;
2134         rxr->rx_sparemap = map;
2135
2136         rxbuf->m_head = m;
2137         rxbuf->paddr = seg.ds_addr;
2138
2139         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2140         return 0;
2141 }
2142
2143 static int
2144 igb_init_rx_ring(struct igb_rx_ring *rxr)
2145 {
2146         int i;
2147
2148         /* Clear the ring contents */
2149         bzero(rxr->rx_base,
2150             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2151
2152         /* Now replenish the ring mbufs */
2153         for (i = 0; i < rxr->num_rx_desc; ++i) {
2154                 int error;
2155
2156                 error = igb_newbuf(rxr, i, TRUE);
2157                 if (error)
2158                         return error;
2159         }
2160
2161         /* Setup our descriptor indices */
2162         rxr->next_to_check = 0;
2163
2164         rxr->fmp = NULL;
2165         rxr->lmp = NULL;
2166         rxr->discard = FALSE;
2167
2168         return 0;
2169 }
2170
2171 static void
2172 igb_init_rx_unit(struct igb_softc *sc)
2173 {
2174         struct ifnet *ifp = &sc->arpcom.ac_if;
2175         struct e1000_hw *hw = &sc->hw;
2176         uint32_t rctl, rxcsum, srrctl = 0;
2177         int i;
2178
2179         /*
2180          * Make sure receives are disabled while setting
2181          * up the descriptor ring
2182          */
2183         rctl = E1000_READ_REG(hw, E1000_RCTL);
2184         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2185
2186 #if 0
2187         /*
2188         ** Set up for header split
2189         */
2190         if (igb_header_split) {
2191                 /* Use a standard mbuf for the header */
2192                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2193                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2194         } else
2195 #endif
2196                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2197
2198         /*
2199         ** Set up for jumbo frames
2200         */
2201         if (ifp->if_mtu > ETHERMTU) {
2202                 rctl |= E1000_RCTL_LPE;
2203 #if 0
2204                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2205                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2206                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2207                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2208                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2209                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2210                 }
2211                 /* Set maximum packet len */
2212                 psize = adapter->max_frame_size;
2213                 /* are we on a vlan? */
2214                 if (adapter->ifp->if_vlantrunk != NULL)
2215                         psize += VLAN_TAG_SIZE;
2216                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2217 #else
2218                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2219                 rctl |= E1000_RCTL_SZ_2048;
2220 #endif
2221         } else {
2222                 rctl &= ~E1000_RCTL_LPE;
2223                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2224                 rctl |= E1000_RCTL_SZ_2048;
2225         }
2226
2227         /* Setup the Base and Length of the Rx Descriptor Rings */
2228         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2229                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2230                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2231                 uint32_t rxdctl;
2232
2233                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2234                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2235                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2236                     (uint32_t)(bus_addr >> 32));
2237                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2238                     (uint32_t)bus_addr);
2239                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2240                 /* Enable this Queue */
2241                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2242                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2243                 rxdctl &= 0xFFF00000;
2244                 rxdctl |= IGB_RX_PTHRESH;
2245                 rxdctl |= IGB_RX_HTHRESH << 8;
2246                 rxdctl |= IGB_RX_WTHRESH << 16;
2247                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2248         }
2249
2250         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2251         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2252
2253         /*
2254          * Receive Checksum Offload for TCP and UDP
2255          *
2256          * Checksum offloading is also enabled if multiple receive
2257          * queue is to be supported, since we need it to figure out
2258          * fragments.
2259          */
2260         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2261                 /*
2262                  * NOTE:
2263                  * PCSD must be enabled to enable multiple
2264                  * receive queues.
2265                  */
2266                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2267                     E1000_RXCSUM_PCSD;
2268         } else {
2269                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2270                     E1000_RXCSUM_PCSD);
2271         }
2272         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2273
2274         if (IGB_ENABLE_HWRSS(sc)) {
2275                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2276                 uint32_t reta_shift;
2277                 int j, r;
2278
2279                 /*
2280                  * NOTE:
2281                  * When we reach here, RSS has already been disabled
2282                  * in igb_stop(), so we could safely configure RSS key
2283                  * and redirect table.
2284                  */
2285
2286                 /*
2287                  * Configure RSS key
2288                  */
2289                 toeplitz_get_key(key, sizeof(key));
2290                 for (i = 0; i < IGB_NRSSRK; ++i) {
2291                         uint32_t rssrk;
2292
2293                         rssrk = IGB_RSSRK_VAL(key, i);
2294                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2295
2296                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2297                 }
2298
2299                 /*
2300                  * Configure RSS redirect table in following fashion:
2301                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2302                  */
2303                 reta_shift = IGB_RETA_SHIFT;
2304                 if (hw->mac.type == e1000_82575)
2305                         reta_shift = IGB_RETA_SHIFT_82575;
2306
2307                 r = 0;
2308                 for (j = 0; j < IGB_NRETA; ++j) {
2309                         uint32_t reta = 0;
2310
2311                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2312                                 uint32_t q;
2313
2314                                 q = (r % sc->rx_ring_cnt) << reta_shift;
2315                                 reta |= q << (8 * i);
2316                                 ++r;
2317                         }
2318                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2319                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2320                 }
2321
2322                 /*
2323                  * Enable multiple receive queues.
2324                  * Enable IPv4 RSS standard hash functions.
2325                  * Disable RSS interrupt on 82575
2326                  */
2327                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2328                                 E1000_MRQC_ENABLE_RSS_4Q |
2329                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2330                                 E1000_MRQC_RSS_FIELD_IPV4);
2331         }
2332
2333         /* Setup the Receive Control Register */
2334         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2335         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2336             E1000_RCTL_RDMTS_HALF |
2337             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2338         /* Strip CRC bytes. */
2339         rctl |= E1000_RCTL_SECRC;
2340         /* Make sure VLAN Filters are off */
2341         rctl &= ~E1000_RCTL_VFE;
2342         /* Don't store bad packets */
2343         rctl &= ~E1000_RCTL_SBP;
2344
2345         /* Enable Receives */
2346         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2347
2348         /*
2349          * Setup the HW Rx Head and Tail Descriptor Pointers
2350          *   - needs to be after enable
2351          */
2352         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2353                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2354
2355                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2356                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2357         }
2358 }
2359
2360 static void
2361 igb_rxeof(struct igb_rx_ring *rxr, int count)
2362 {
2363         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2364         union e1000_adv_rx_desc *cur;
2365         uint32_t staterr;
2366         int i;
2367
2368         i = rxr->next_to_check;
2369         cur = &rxr->rx_base[i];
2370         staterr = le32toh(cur->wb.upper.status_error);
2371
2372         if ((staterr & E1000_RXD_STAT_DD) == 0)
2373                 return;
2374
2375         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2376                 struct pktinfo *pi = NULL, pi0;
2377                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2378                 struct mbuf *m = NULL;
2379                 boolean_t eop;
2380
2381                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2382                 if (eop)
2383                         --count;
2384
2385                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2386                     !rxr->discard) {
2387                         struct mbuf *mp = rxbuf->m_head;
2388                         uint32_t hash, hashtype;
2389                         uint16_t vlan;
2390                         int len;
2391
2392                         len = le16toh(cur->wb.upper.length);
2393                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2394                             (staterr & E1000_RXDEXT_STATERR_LB))
2395                                 vlan = be16toh(cur->wb.upper.vlan);
2396                         else
2397                                 vlan = le16toh(cur->wb.upper.vlan);
2398
2399                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2400                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2401                             E1000_RXDADV_RSSTYPE_MASK;
2402
2403                         IGB_RSS_DPRINTF(rxr->sc, 10,
2404                             "ring%d, hash 0x%08x, hashtype %u\n",
2405                             rxr->me, hash, hashtype);
2406
2407                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2408                             BUS_DMASYNC_POSTREAD);
2409
2410                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2411                                 ifp->if_iqdrops++;
2412                                 goto discard;
2413                         }
2414
2415                         mp->m_len = len;
2416                         if (rxr->fmp == NULL) {
2417                                 mp->m_pkthdr.len = len;
2418                                 rxr->fmp = mp;
2419                                 rxr->lmp = mp;
2420                         } else {
2421                                 rxr->lmp->m_next = mp;
2422                                 rxr->lmp = rxr->lmp->m_next;
2423                                 rxr->fmp->m_pkthdr.len += len;
2424                         }
2425
2426                         if (eop) {
2427                                 m = rxr->fmp;
2428                                 rxr->fmp = NULL;
2429                                 rxr->lmp = NULL;
2430
2431                                 m->m_pkthdr.rcvif = ifp;
2432                                 ifp->if_ipackets++;
2433
2434                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2435                                         igb_rxcsum(staterr, m);
2436
2437                                 if (staterr & E1000_RXD_STAT_VP) {
2438                                         m->m_pkthdr.ether_vlantag = vlan;
2439                                         m->m_flags |= M_VLANTAG;
2440                                 }
2441
2442                                 if (ifp->if_capenable & IFCAP_RSS) {
2443                                         pi = igb_rssinfo(m, &pi0,
2444                                             hash, hashtype, staterr);
2445                                 }
2446 #ifdef IGB_RSS_DEBUG
2447                                 rxr->rx_packets++;
2448 #endif
2449                         }
2450                 } else {
2451                         ifp->if_ierrors++;
2452 discard:
2453                         igb_setup_rxdesc(cur, rxbuf);
2454                         if (!eop)
2455                                 rxr->discard = TRUE;
2456                         else
2457                                 rxr->discard = FALSE;
2458                         if (rxr->fmp != NULL) {
2459                                 m_freem(rxr->fmp);
2460                                 rxr->fmp = NULL;
2461                                 rxr->lmp = NULL;
2462                         }
2463                         m = NULL;
2464                 }
2465
2466                 if (m != NULL)
2467                         ether_input_pkt(ifp, m, pi);
2468
2469                 /* Advance our pointers to the next descriptor. */
2470                 if (++i == rxr->num_rx_desc)
2471                         i = 0;
2472
2473                 cur = &rxr->rx_base[i];
2474                 staterr = le32toh(cur->wb.upper.status_error);
2475         }
2476         rxr->next_to_check = i;
2477
2478         if (--i < 0)
2479                 i = rxr->num_rx_desc - 1;
2480         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2481 }
2482
2483
2484 static void
2485 igb_set_vlan(struct igb_softc *sc)
2486 {
2487         struct e1000_hw *hw = &sc->hw;
2488         uint32_t reg;
2489 #if 0
2490         struct ifnet *ifp = sc->arpcom.ac_if;
2491 #endif
2492
2493         if (sc->vf_ifp) {
2494                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2495                 return;
2496         }
2497
2498         reg = E1000_READ_REG(hw, E1000_CTRL);
2499         reg |= E1000_CTRL_VME;
2500         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2501
2502 #if 0
2503         /* Enable the Filter Table */
2504         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2505                 reg = E1000_READ_REG(hw, E1000_RCTL);
2506                 reg &= ~E1000_RCTL_CFIEN;
2507                 reg |= E1000_RCTL_VFE;
2508                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2509         }
2510 #endif
2511
2512         /* Update the frame size */
2513         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2514             sc->max_frame_size + VLAN_TAG_SIZE);
2515
2516 #if 0
2517         /* Don't bother with table if no vlans */
2518         if ((adapter->num_vlans == 0) ||
2519             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2520                 return;
2521         /*
2522         ** A soft reset zero's out the VFTA, so
2523         ** we need to repopulate it now.
2524         */
2525         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2526                 if (adapter->shadow_vfta[i] != 0) {
2527                         if (adapter->vf_ifp)
2528                                 e1000_vfta_set_vf(hw,
2529                                     adapter->shadow_vfta[i], TRUE);
2530                         else
2531                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2532                                  i, adapter->shadow_vfta[i]);
2533                 }
2534 #endif
2535 }
2536
2537 static void
2538 igb_enable_intr(struct igb_softc *sc)
2539 {
2540         lwkt_serialize_handler_enable(&sc->main_serialize);
2541
2542         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2543                 /* XXX MSI-X should use sc->intr_mask */
2544                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2545                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2546                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2547                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2548         } else {
2549                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2550         }
2551         E1000_WRITE_FLUSH(&sc->hw);
2552 }
2553
2554 static void
2555 igb_disable_intr(struct igb_softc *sc)
2556 {
2557         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2558                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2559                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2560         }
2561         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2562         E1000_WRITE_FLUSH(&sc->hw);
2563
2564         lwkt_serialize_handler_disable(&sc->main_serialize);
2565 }
2566
2567 /*
2568  * Bit of a misnomer, what this really means is
2569  * to enable OS management of the system... aka
2570  * to disable special hardware management features
2571  */
2572 static void
2573 igb_get_mgmt(struct igb_softc *sc)
2574 {
2575         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2576                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2577                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2578
2579                 /* disable hardware interception of ARP */
2580                 manc &= ~E1000_MANC_ARP_EN;
2581
2582                 /* enable receiving management packets to the host */
2583                 manc |= E1000_MANC_EN_MNG2HOST;
2584                 manc2h |= 1 << 5; /* Mng Port 623 */
2585                 manc2h |= 1 << 6; /* Mng Port 664 */
2586                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2587                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2588         }
2589 }
2590
2591 /*
2592  * Give control back to hardware management controller
2593  * if there is one.
2594  */
2595 static void
2596 igb_rel_mgmt(struct igb_softc *sc)
2597 {
2598         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2599                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2600
2601                 /* Re-enable hardware interception of ARP */
2602                 manc |= E1000_MANC_ARP_EN;
2603                 manc &= ~E1000_MANC_EN_MNG2HOST;
2604
2605                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2606         }
2607 }
2608
2609 /*
2610  * Sets CTRL_EXT:DRV_LOAD bit.
2611  *
2612  * For ASF and Pass Through versions of f/w this means that
2613  * the driver is loaded.
2614  */
2615 static void
2616 igb_get_hw_control(struct igb_softc *sc)
2617 {
2618         uint32_t ctrl_ext;
2619
2620         if (sc->vf_ifp)
2621                 return;
2622
2623         /* Let firmware know the driver has taken over */
2624         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2625         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2626             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2627 }
2628
2629 /*
2630  * Resets CTRL_EXT:DRV_LOAD bit.
2631  *
2632  * For ASF and Pass Through versions of f/w this means that the
2633  * driver is no longer loaded.
2634  */
2635 static void
2636 igb_rel_hw_control(struct igb_softc *sc)
2637 {
2638         uint32_t ctrl_ext;
2639
2640         if (sc->vf_ifp)
2641                 return;
2642
2643         /* Let firmware taken over control of h/w */
2644         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2645         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2646             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2647 }
2648
2649 static int
2650 igb_is_valid_ether_addr(const uint8_t *addr)
2651 {
2652         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2653
2654         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2655                 return FALSE;
2656         return TRUE;
2657 }
2658
2659 /*
2660  * Enable PCI Wake On Lan capability
2661  */
2662 static void
2663 igb_enable_wol(device_t dev)
2664 {
2665         uint16_t cap, status;
2666         uint8_t id;
2667
2668         /* First find the capabilities pointer*/
2669         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2670
2671         /* Read the PM Capabilities */
2672         id = pci_read_config(dev, cap, 1);
2673         if (id != PCIY_PMG)     /* Something wrong */
2674                 return;
2675
2676         /*
2677          * OK, we have the power capabilities,
2678          * so now get the status register
2679          */
2680         cap += PCIR_POWER_STATUS;
2681         status = pci_read_config(dev, cap, 2);
2682         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2683         pci_write_config(dev, cap, status, 2);
2684 }
2685
2686 static void
2687 igb_update_stats_counters(struct igb_softc *sc)
2688 {
2689         struct e1000_hw *hw = &sc->hw;
2690         struct e1000_hw_stats *stats;
2691         struct ifnet *ifp = &sc->arpcom.ac_if;
2692
2693         /*
2694          * The virtual function adapter has only a
2695          * small controlled set of stats, do only
2696          * those and return.
2697          */
2698         if (sc->vf_ifp) {
2699                 igb_update_vf_stats_counters(sc);
2700                 return;
2701         }
2702         stats = sc->stats;
2703
2704         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2705             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2706                 stats->symerrs +=
2707                     E1000_READ_REG(hw,E1000_SYMERRS);
2708                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2709         }
2710
2711         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2712         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2713         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2714         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2715
2716         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2717         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2718         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2719         stats->dc += E1000_READ_REG(hw, E1000_DC);
2720         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2721         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2722         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2723
2724         /*
2725          * For watchdog management we need to know if we have been
2726          * paused during the last interval, so capture that here.
2727          */
2728         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2729         stats->xoffrxc += sc->pause_frames;
2730         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2731         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2732         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2733         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2734         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2735         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2736         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2737         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2738         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2739         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2740         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2741         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2742
2743         /* For the 64-bit byte counters the low dword must be read first. */
2744         /* Both registers clear on the read of the high dword */
2745
2746         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2747             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2748         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2749             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2750
2751         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2752         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2753         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2754         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2755         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2756
2757         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2758         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2759
2760         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2761         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2762         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2763         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2764         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2765         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2766         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2767         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2768         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2769         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2770
2771         /* Interrupt Counts */
2772
2773         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2774         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2775         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2776         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2777         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2778         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2779         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2780         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2781         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2782
2783         /* Host to Card Statistics */
2784
2785         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2786         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2787         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2788         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2789         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2790         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2791         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2792         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2793             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2794         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2795             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2796         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2797         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2798         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2799
2800         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2801         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2802         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2803         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2804         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2805         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2806
2807         ifp->if_collisions = stats->colc;
2808
2809         /* Rx Errors */
2810         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2811             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2812
2813         /* Tx Errors */
2814         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2815
2816         /* Driver specific counters */
2817         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2818         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2819         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2820         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2821         sc->packet_buf_alloc_tx =
2822             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2823         sc->packet_buf_alloc_rx =
2824             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2825 }
2826
2827 static void
2828 igb_vf_init_stats(struct igb_softc *sc)
2829 {
2830         struct e1000_hw *hw = &sc->hw;
2831         struct e1000_vf_stats *stats;
2832
2833         stats = sc->stats;
2834         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2835         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2836         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2837         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2838         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2839 }
2840
2841 static void
2842 igb_update_vf_stats_counters(struct igb_softc *sc)
2843 {
2844         struct e1000_hw *hw = &sc->hw;
2845         struct e1000_vf_stats *stats;
2846
2847         if (sc->link_speed == 0)
2848                 return;
2849
2850         stats = sc->stats;
2851         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2852         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2853         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2854         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2855         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2856 }
2857
2858 #ifdef DEVICE_POLLING
2859
2860 static void
2861 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2862 {
2863         struct igb_softc *sc = ifp->if_softc;
2864         uint32_t reg_icr;
2865
2866         ASSERT_SERIALIZED(&sc->main_serialize);
2867
2868         switch (cmd) {
2869         case POLL_REGISTER:
2870                 igb_disable_intr(sc);
2871                 break;
2872
2873         case POLL_DEREGISTER:
2874                 igb_enable_intr(sc);
2875                 break;
2876
2877         case POLL_AND_CHECK_STATUS:
2878                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2879                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2880                         sc->hw.mac.get_link_status = 1;
2881                         igb_update_link_status(sc);
2882                 }
2883                 /* FALL THROUGH */
2884         case POLL_ONLY:
2885                 if (ifp->if_flags & IFF_RUNNING) {
2886                         struct igb_tx_ring *txr;
2887                         int i;
2888
2889                         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2890                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2891
2892                                 lwkt_serialize_enter(&rxr->rx_serialize);
2893                                 igb_rxeof(rxr, count);
2894                                 lwkt_serialize_exit(&rxr->rx_serialize);
2895                         }
2896
2897                         txr = &sc->tx_rings[0];
2898                         lwkt_serialize_enter(&txr->tx_serialize);
2899                         igb_txeof(txr);
2900                         if (!ifq_is_empty(&ifp->if_snd))
2901                                 if_devstart(ifp);
2902                         lwkt_serialize_exit(&txr->tx_serialize);
2903                 }
2904                 break;
2905         }
2906 }
2907
2908 #endif /* DEVICE_POLLING */
2909
2910 static void
2911 igb_intr(void *xsc)
2912 {
2913         struct igb_softc *sc = xsc;
2914         struct ifnet *ifp = &sc->arpcom.ac_if;
2915         uint32_t eicr;
2916
2917         ASSERT_SERIALIZED(&sc->main_serialize);
2918
2919         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2920
2921         if (eicr == 0)
2922                 return;
2923
2924         if (ifp->if_flags & IFF_RUNNING) {
2925                 struct igb_tx_ring *txr;
2926                 int i;
2927
2928                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2929                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2930
2931                         if (eicr & rxr->rx_intr_mask) {
2932                                 lwkt_serialize_enter(&rxr->rx_serialize);
2933                                 igb_rxeof(rxr, -1);
2934                                 lwkt_serialize_exit(&rxr->rx_serialize);
2935                         }
2936                 }
2937
2938                 txr = &sc->tx_rings[0];
2939                 if (eicr & txr->tx_intr_mask) {
2940                         lwkt_serialize_enter(&txr->tx_serialize);
2941                         igb_txeof(txr);
2942                         if (!ifq_is_empty(&ifp->if_snd))
2943                                 if_devstart(ifp);
2944                         lwkt_serialize_exit(&txr->tx_serialize);
2945                 }
2946         }
2947
2948         if (eicr & E1000_EICR_OTHER) {
2949                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2950
2951                 /* Link status change */
2952                 if (icr & E1000_ICR_LSC) {
2953                         sc->hw.mac.get_link_status = 1;
2954                         igb_update_link_status(sc);
2955                 }
2956         }
2957
2958         /*
2959          * Reading EICR has the side effect to clear interrupt mask,
2960          * so all interrupts need to be enabled here.
2961          */
2962         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2963 }
2964
2965 static void
2966 igb_shared_intr(void *xsc)
2967 {
2968         struct igb_softc *sc = xsc;
2969         struct ifnet *ifp = &sc->arpcom.ac_if;
2970         uint32_t reg_icr;
2971
2972         ASSERT_SERIALIZED(&sc->main_serialize);
2973
2974         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2975
2976         /* Hot eject?  */
2977         if (reg_icr == 0xffffffff)
2978                 return;
2979
2980         /* Definitely not our interrupt.  */
2981         if (reg_icr == 0x0)
2982                 return;
2983
2984         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
2985                 return;
2986
2987         if (ifp->if_flags & IFF_RUNNING) {
2988                 struct igb_tx_ring *txr;
2989                 int i;
2990
2991                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2992                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2993
2994                         lwkt_serialize_enter(&rxr->rx_serialize);
2995                         igb_rxeof(rxr, -1);
2996                         lwkt_serialize_exit(&rxr->rx_serialize);
2997                 }
2998
2999                 txr = &sc->tx_rings[0];
3000                 lwkt_serialize_enter(&txr->tx_serialize);
3001                 igb_txeof(txr);
3002                 if (!ifq_is_empty(&ifp->if_snd))
3003                         if_devstart(ifp);
3004                 lwkt_serialize_exit(&txr->tx_serialize);
3005         }
3006
3007         /* Link status change */
3008         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3009                 sc->hw.mac.get_link_status = 1;
3010                 igb_update_link_status(sc);
3011         }
3012
3013         if (reg_icr & E1000_ICR_RXO)
3014                 sc->rx_overruns++;
3015 }
3016
3017 static int
3018 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
3019 {
3020         struct mbuf *m = *m0;
3021         struct ether_header *eh;
3022         int len;
3023
3024         txr->ctx_try_pullup++;
3025
3026         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
3027
3028         if (__predict_false(!M_WRITABLE(m))) {
3029                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3030                         txr->ctx_drop1++;
3031                         m_freem(m);
3032                         *m0 = NULL;
3033                         return ENOBUFS;
3034                 }
3035                 eh = mtod(m, struct ether_header *);
3036
3037                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
3038                         len += EVL_ENCAPLEN;
3039
3040                 if (m->m_len < len) {
3041                         txr->ctx_drop2++;
3042                         m_freem(m);
3043                         *m0 = NULL;
3044                         return ENOBUFS;
3045                 }
3046                 return 0;
3047         }
3048
3049         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3050                 txr->ctx_pullup1++;
3051                 m = m_pullup(m, ETHER_HDR_LEN);
3052                 if (m == NULL) {
3053                         txr->ctx_pullup1_failed++;
3054                         *m0 = NULL;
3055                         return ENOBUFS;
3056                 }
3057                 *m0 = m;
3058         }
3059         eh = mtod(m, struct ether_header *);
3060
3061         if (eh->ether_type == htons(ETHERTYPE_VLAN))
3062                 len += EVL_ENCAPLEN;
3063
3064         if (m->m_len < len) {
3065                 txr->ctx_pullup2++;
3066                 m = m_pullup(m, len);
3067                 if (m == NULL) {
3068                         txr->ctx_pullup2_failed++;
3069                         *m0 = NULL;
3070                         return ENOBUFS;
3071                 }
3072                 *m0 = m;
3073         }
3074         return 0;
3075 }
3076
3077 static int
3078 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3079 {
3080         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3081         bus_dmamap_t map;
3082         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3083         union e1000_adv_tx_desc *txd = NULL;
3084         struct mbuf *m_head = *m_headp;
3085         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3086         int maxsegs, nsegs, i, j, error, last = 0;
3087         uint32_t hdrlen = 0;
3088
3089         if (m_head->m_len < IGB_TXCSUM_MINHL &&
3090             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
3091              (m_head->m_flags & M_VLANTAG))) {
3092                 /*
3093                  * Make sure that ethernet header and ip.ip_hl are in
3094                  * contiguous memory, since if TXCSUM or VLANTAG is
3095                  * enabled, later TX context descriptor's setup need
3096                  * to access ip.ip_hl.
3097                  */
3098                 error = igb_txctx_pullup(txr, m_headp);
3099                 if (error) {
3100                         KKASSERT(*m_headp == NULL);
3101                         return error;
3102                 }
3103                 m_head = *m_headp;
3104         }
3105
3106         /* Set basic descriptor constants */
3107         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3108         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3109         if (m_head->m_flags & M_VLANTAG)
3110                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3111
3112         /*
3113          * Map the packet for DMA.
3114          */
3115         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3116         tx_buf_mapped = tx_buf;
3117         map = tx_buf->map;
3118
3119         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3120         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3121         if (maxsegs > IGB_MAX_SCATTER)
3122                 maxsegs = IGB_MAX_SCATTER;
3123
3124         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3125             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3126         if (error) {
3127                 if (error == ENOBUFS)
3128                         txr->sc->mbuf_defrag_failed++;
3129                 else
3130                         txr->sc->no_tx_dma_setup++;
3131
3132                 m_freem(*m_headp);
3133                 *m_headp = NULL;
3134                 return error;
3135         }
3136         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3137
3138         m_head = *m_headp;
3139
3140 #if 0
3141         /*
3142          * Set up the context descriptor:
3143          * used when any hardware offload is done.
3144          * This includes CSUM, VLAN, and TSO. It
3145          * will use the first descriptor.
3146          */
3147         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3148                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3149                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3150                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3151                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3152                 } else
3153                         return (ENXIO);
3154         } else if (igb_tx_ctx_setup(txr, m_head))
3155                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3156 #else
3157         if (igb_txctx(txr, m_head)) {
3158                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3159                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3160                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3161                 txr->tx_nsegs++;
3162         }
3163 #endif
3164
3165         txr->tx_nsegs += nsegs;
3166         if (txr->tx_nsegs >= txr->intr_nsegs) {
3167                 /*
3168                  * Report Status (RS) is turned on every intr_nsegs
3169                  * descriptors (roughly).
3170                  */
3171                 txr->tx_nsegs = 0;
3172                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3173         }
3174
3175         /* Calculate payload length */
3176         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3177             << E1000_ADVTXD_PAYLEN_SHIFT);
3178
3179         /* 82575 needs the queue index added */
3180         if (txr->sc->hw.mac.type == e1000_82575)
3181                 olinfo_status |= txr->me << 4;
3182
3183         /* Set up our transmit descriptors */
3184         i = txr->next_avail_desc;
3185         for (j = 0; j < nsegs; j++) {
3186                 bus_size_t seg_len;
3187                 bus_addr_t seg_addr;
3188
3189                 tx_buf = &txr->tx_buf[i];
3190                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3191                 seg_addr = segs[j].ds_addr;
3192                 seg_len = segs[j].ds_len;
3193
3194                 txd->read.buffer_addr = htole64(seg_addr);
3195                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3196                 txd->read.olinfo_status = htole32(olinfo_status);
3197                 last = i;
3198                 if (++i == txr->num_tx_desc)
3199                         i = 0;
3200                 tx_buf->m_head = NULL;
3201         }
3202
3203         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3204         txr->next_avail_desc = i;
3205         txr->tx_avail -= nsegs;
3206
3207         tx_buf->m_head = m_head;
3208         tx_buf_mapped->map = tx_buf->map;
3209         tx_buf->map = map;
3210
3211         /*
3212          * Last Descriptor of Packet needs End Of Packet (EOP)
3213          */
3214         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3215
3216         /*
3217          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3218          * that this frame is available to transmit.
3219          */
3220         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3221         ++txr->tx_packets;
3222
3223         return 0;
3224 }
3225
3226 static void
3227 igb_start(struct ifnet *ifp)
3228 {
3229         struct igb_softc *sc = ifp->if_softc;
3230         struct igb_tx_ring *txr = &sc->tx_rings[0];
3231         struct mbuf *m_head;
3232
3233         ASSERT_SERIALIZED(&txr->tx_serialize);
3234
3235         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3236                 return;
3237
3238         if (!sc->link_active) {
3239                 ifq_purge(&ifp->if_snd);
3240                 return;
3241         }
3242
3243         if (!IGB_IS_NOT_OACTIVE(txr))
3244                 igb_txeof(txr);
3245
3246         while (!ifq_is_empty(&ifp->if_snd)) {
3247                 if (IGB_IS_OACTIVE(txr)) {
3248                         ifp->if_flags |= IFF_OACTIVE;
3249                         /* Set watchdog on */
3250                         ifp->if_timer = 5;
3251                         break;
3252                 }
3253
3254                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3255                 if (m_head == NULL)
3256                         break;
3257
3258                 if (igb_encap(txr, &m_head)) {
3259                         ifp->if_oerrors++;
3260                         continue;
3261                 }
3262
3263                 /* Send a copy of the frame to the BPF listener */
3264                 ETHER_BPF_MTAP(ifp, m_head);
3265         }
3266 }
3267
3268 static void
3269 igb_watchdog(struct ifnet *ifp)
3270 {
3271         struct igb_softc *sc = ifp->if_softc;
3272         struct igb_tx_ring *txr = &sc->tx_rings[0];
3273
3274         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3275
3276         /*
3277          * If flow control has paused us since last checking
3278          * it invalidates the watchdog timing, so dont run it.
3279          */
3280         if (sc->pause_frames) {
3281                 sc->pause_frames = 0;
3282                 ifp->if_timer = 5;
3283                 return;
3284         }
3285
3286         if_printf(ifp, "Watchdog timeout -- resetting\n");
3287         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3288             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3289             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3290         if_printf(ifp, "TX(%d) desc avail = %d, "
3291             "Next TX to Clean = %d\n",
3292             txr->me, txr->tx_avail, txr->next_to_clean);
3293
3294         ifp->if_oerrors++;
3295         sc->watchdog_events++;
3296
3297         igb_init(sc);
3298         if (!ifq_is_empty(&ifp->if_snd))
3299                 if_devstart(ifp);
3300 }
3301
3302 static void
3303 igb_set_eitr(struct igb_softc *sc)
3304 {
3305         uint32_t itr = 0;
3306
3307         if (sc->intr_rate > 0) {
3308                 if (sc->hw.mac.type == e1000_82575) {
3309                         itr = 1000000000 / 256 / sc->intr_rate;
3310                         /*
3311                          * NOTE:
3312                          * Document is wrong on the 2 bits left shift
3313                          */
3314                 } else {
3315                         itr = 1000000 / sc->intr_rate;
3316                         itr <<= 2;
3317                 }
3318                 itr &= 0x7FFC;
3319         }
3320         if (sc->hw.mac.type == e1000_82575)
3321                 itr |= itr << 16;
3322         else
3323                 itr |= E1000_EITR_CNT_IGNR;
3324         E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3325 }
3326
3327 static int
3328 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3329 {
3330         struct igb_softc *sc = (void *)arg1;
3331         struct ifnet *ifp = &sc->arpcom.ac_if;
3332         int error, intr_rate;
3333
3334         intr_rate = sc->intr_rate;
3335         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3336         if (error || req->newptr == NULL)
3337                 return error;
3338         if (intr_rate < 0)
3339                 return EINVAL;
3340
3341         ifnet_serialize_all(ifp);
3342
3343         sc->intr_rate = intr_rate;
3344         if (ifp->if_flags & IFF_RUNNING)
3345                 igb_set_eitr(sc);
3346
3347         ifnet_deserialize_all(ifp);
3348
3349         if (bootverbose)
3350                 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3351         return 0;
3352 }
3353
3354 static int
3355 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3356 {
3357         struct igb_softc *sc = (void *)arg1;
3358         struct ifnet *ifp = &sc->arpcom.ac_if;
3359         struct igb_tx_ring *txr = &sc->tx_rings[0];
3360         int error, nsegs;
3361
3362         nsegs = txr->intr_nsegs;
3363         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3364         if (error || req->newptr == NULL)
3365                 return error;
3366         if (nsegs <= 0)
3367                 return EINVAL;
3368
3369         ifnet_serialize_all(ifp);
3370
3371         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3372             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3373                 error = EINVAL;
3374         } else {
3375                 error = 0;
3376                 txr->intr_nsegs = nsegs;
3377         }
3378
3379         ifnet_deserialize_all(ifp);
3380
3381         return error;
3382 }
3383
3384 static void
3385 igb_init_intr(struct igb_softc *sc)
3386 {
3387         if (sc->flags & IGB_FLAG_SHARED_INTR)
3388                 igb_set_eitr(sc);
3389         else
3390                 igb_init_unshared_intr(sc);
3391 }
3392
3393 static void
3394 igb_init_unshared_intr(struct igb_softc *sc)
3395 {
3396         struct e1000_hw *hw = &sc->hw;
3397         const struct igb_rx_ring *rxr;
3398         const struct igb_tx_ring *txr;
3399         uint32_t ivar, index;
3400         int i;
3401
3402         /*
3403          * Enable extended mode
3404          */
3405         if (sc->hw.mac.type != e1000_82575) {
3406                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_NSICR);
3407         } else {
3408                 uint32_t tmp;
3409
3410                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3411                 tmp |= E1000_CTRL_EXT_IRCA;
3412                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3413         }
3414
3415         /*
3416          * Map TX/RX interrupts to EICR
3417          */
3418         switch (sc->hw.mac.type) {
3419         case e1000_82580:
3420         case e1000_i350:
3421         case e1000_vfadapt:
3422         case e1000_vfadapt_i350:
3423                 /* RX entries */
3424                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3425                         rxr = &sc->rx_rings[i];
3426
3427                         index = i >> 1;
3428                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3429
3430                         if (i & 1) {
3431                                 ivar &= 0xff00ffff;
3432                                 ivar |=
3433                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3434                         } else {
3435                                 ivar &= 0xffffff00;
3436                                 ivar |=
3437                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3438                         }
3439                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3440                 }
3441                 /* TX entries */
3442                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3443                         txr = &sc->tx_rings[i];
3444
3445                         index = i >> 1;
3446                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3447
3448                         if (i & 1) {
3449                                 ivar &= 0x00ffffff;
3450                                 ivar |=
3451                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3452                         } else {
3453                                 ivar &= 0xffff00ff;
3454                                 ivar |=
3455                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3456                         }
3457                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3458                 }
3459                 /* Clear unused IVAR_MISC */
3460                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3461                 break;
3462
3463         case e1000_82576:
3464                 /* RX entries */
3465                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3466                         rxr = &sc->rx_rings[i];
3467
3468                         index = i & 0x7; /* Each IVAR has two entries */
3469                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3470
3471                         if (i < 8) {
3472                                 ivar &= 0xffffff00;
3473                                 ivar |=
3474                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3475                         } else {
3476                                 ivar &= 0xff00ffff;
3477                                 ivar |=
3478                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3479                         }
3480                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3481                 }
3482                 /* TX entries */
3483                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3484                         txr = &sc->tx_rings[i];
3485
3486                         index = i & 0x7; /* Each IVAR has two entries */
3487                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3488
3489                         if (i < 8) {
3490                                 ivar &= 0xffff00ff;
3491                                 ivar |=
3492                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3493                         } else {
3494                                 ivar &= 0x00ffffff;
3495                                 ivar |=
3496                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3497                         }
3498                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3499                 }
3500                 /* Clear unused IVAR_MISC */
3501                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3502                 break;
3503
3504         case e1000_82575:
3505                 /*
3506                  * Enable necessary interrupt bits.
3507                  *
3508                  * The name of the register is confusing; in addition to
3509                  * configuring the first vector of MSI-X, it also configures
3510                  * which bits of EICR could be set by the hardware even when
3511                  * MSI or line interrupt is used; it thus controls interrupt
3512                  * generation.  It MUST be configured explicitly; the default
3513                  * value mentioned in the datasheet is wrong: RX queue0 and
3514                  * TX queue0 are NOT enabled by default.
3515                  */
3516                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3517                 break;
3518
3519         default:
3520                 break;
3521         }
3522
3523         /*
3524          * Configure interrupt moderation
3525          */
3526         igb_set_eitr(sc);
3527 }
3528
3529 static int
3530 igb_setup_intr(struct igb_softc *sc)
3531 {
3532         struct ifnet *ifp = &sc->arpcom.ac_if;
3533         int error, i, intr_bit, intr_bitmax;
3534
3535         /*
3536          * Setup interrupt mask
3537          */
3538         switch (sc->hw.mac.type) {
3539         case e1000_82575:
3540                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3541                 break;
3542         case e1000_82580:
3543                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3544                 break;
3545         case e1000_i350:
3546                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3547                 break;
3548         case e1000_82576:
3549                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3550                 break;
3551         default:
3552                 intr_bitmax = IGB_MIN_TXRXINT;
3553                 break;
3554         }
3555         intr_bit = 0;
3556         for (i = 0; i < sc->tx_ring_cnt; ++i)
3557                 igb_setup_tx_intr(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3558         for (i = 0; i < sc->rx_ring_cnt; ++i)
3559                 igb_setup_rx_intr(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3560
3561         sc->intr_mask = E1000_EICR_OTHER;
3562         for (i = 0; i < sc->rx_ring_cnt; ++i)
3563                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3564         for (i = 0; i < sc->tx_ring_cnt; ++i)
3565                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3566
3567         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3568                 int unshared;
3569
3570                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3571                 if (!unshared) {
3572                         sc->flags |= IGB_FLAG_SHARED_INTR;
3573                         if (bootverbose)
3574                                 device_printf(sc->dev, "IRQ shared\n");
3575                 } else if (bootverbose) {
3576                         device_printf(sc->dev, "IRQ unshared\n");
3577                 }
3578         }
3579
3580         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3581             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_shared_intr : igb_intr,
3582             sc, &sc->intr_tag, &sc->main_serialize);
3583         if (error) {
3584                 device_printf(sc->dev, "Failed to register interrupt handler");
3585                 return error;
3586         }
3587
3588         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3589         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3590
3591         return 0;
3592 }
3593
3594 static void
3595 igb_setup_tx_intr(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3596 {
3597         if (txr->sc->hw.mac.type == e1000_82575) {
3598                 txr->tx_intr_bit = 0;   /* unused */
3599                 switch (txr->me) {
3600                 case 0:
3601                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3602                         break;
3603                 case 1:
3604                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3605                         break;
3606                 case 2:
3607                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3608                         break;
3609                 case 3:
3610                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3611                         break;
3612                 default:
3613                         panic("unsupported # of TX ring, %d\n", txr->me);
3614                 }
3615         } else {
3616                 int intr_bit = *intr_bit0;
3617
3618                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3619                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3620
3621                 *intr_bit0 = intr_bit + 1;
3622         }
3623 }
3624
3625 static void
3626 igb_setup_rx_intr(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3627 {
3628         if (rxr->sc->hw.mac.type == e1000_82575) {
3629                 rxr->rx_intr_bit = 0;   /* unused */
3630                 switch (rxr->me) {
3631                 case 0:
3632                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3633                         break;
3634                 case 1:
3635                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3636                         break;
3637                 case 2:
3638                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3639                         break;
3640                 case 3:
3641                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3642                         break;
3643                 default:
3644                         panic("unsupported # of RX ring, %d\n", rxr->me);
3645                 }
3646         } else {
3647                 int intr_bit = *intr_bit0;
3648
3649                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3650                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3651
3652                 *intr_bit0 = intr_bit + 1;
3653         }
3654 }
3655
3656 static void
3657 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3658 {
3659         struct igb_softc *sc = ifp->if_softc;
3660
3661         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3662             sc->tx_serialize, sc->rx_serialize, slz);
3663 }
3664
3665 static void
3666 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3667 {
3668         struct igb_softc *sc = ifp->if_softc;
3669
3670         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3671             sc->tx_serialize, sc->rx_serialize, slz);
3672 }
3673
3674 static int
3675 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3676 {
3677         struct igb_softc *sc = ifp->if_softc;
3678
3679         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3680             sc->tx_serialize, sc->rx_serialize, slz);
3681 }
3682
3683 #ifdef INVARIANTS
3684
3685 static void
3686 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3687     boolean_t serialized)
3688 {
3689         struct igb_softc *sc = ifp->if_softc;
3690
3691         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3692             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3693 }
3694
3695 #endif  /* INVARIANTS */