sys/dev/disk/aic7xxx/aic79xx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      aic7901 and aic7902 SCSI controllers
   4  *
   5  * Copyright (c) 1994-2001 Justin T. Gibbs.
   6  * Copyright (c) 2000-2002 Adaptec Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16  *    substantially similar to the "NO WARRANTY" disclaimer below
  17  *    ("Disclaimer") and any redistribution must be conditioned upon
  18  *    including a substantially similar Disclaimer requirement for further
  19  *    binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39  * POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $
  42  *
  43  * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.24 2005/12/04 02:12:40 ru Exp $
  44  * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx_pci.c,v 1.16 2008/02/09 18:13:13 pavalos Exp $
  45  */
  46
  47 #ifdef __linux__
  48 #include "aic79xx_osm.h"
  49 #include "aic79xx_inline.h"
  50 #else
  51 #include "aic79xx_osm.h"
  52 #include "aic79xx_inline.h"
  53 #endif
  54
  55 static __inline uint64_t
  56 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  57 {
  58         uint64_t id;
  59
  60         id = subvendor
  61            | (subdevice << 16)
  62            | ((uint64_t)vendor << 32)
  63            | ((uint64_t)device << 48);
  64
  65         return (id);
  66 }
  67
  68 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  69 #define ID_ALL_IROC_MASK                0xFF7FFFFFFFFFFFFFull
  70 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  71 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  72 #define ID_9005_GENERIC_IROC_MASK       0xFF70FFFF00000000ull
  73
  74 #define ID_AIC7901                      0x800F9005FFFF9005ull
  75 #define ID_AHA_29320A                   0x8000900500609005ull
  76 #define ID_AHA_29320ALP                 0x8017900500449005ull
  77
  78 #define ID_AIC7901A                     0x801E9005FFFF9005ull
  79 #define ID_AHA_29320LP                  0x8014900500449005ull
  80
  81 #define ID_AIC7902                      0x801F9005FFFF9005ull
  82 #define ID_AIC7902_B                    0x801D9005FFFF9005ull
  83 #define ID_AHA_39320                    0x8010900500409005ull
  84 #define ID_AHA_29320                    0x8012900500429005ull
  85 #define ID_AHA_29320B                   0x8013900500439005ull
  86 #define ID_AHA_39320_B                  0x8015900500409005ull
  87 #define ID_AHA_39320_B_DELL             0x8015900501681028ull
  88 #define ID_AHA_39320A                   0x8016900500409005ull
  89 #define ID_AHA_39320D                   0x8011900500419005ull
  90 #define ID_AHA_39320D_B                 0x801C900500419005ull
  91 #define ID_AHA_39320D_HP                0x8011900500AC0E11ull
  92 #define ID_AHA_39320D_B_HP              0x801C900500AC0E11ull
  93 #define ID_AIC7902_PCI_REV_A4           0x3
  94 #define ID_AIC7902_PCI_REV_B0           0x10
  95 #define SUBID_HP                        0x0E11
  96
  97 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
  98
  99 #define DEVID_9005_TYPE(id) ((id) & 0xF)
 100 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
 101 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
 102 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 103
 104 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
 105
 106 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
 107
 108 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 109 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
 110 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 111
 112 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
 113
 114 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
 115
 116 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
 117 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 118 #define         SUBID_9005_SEEPTYPE_4K          0x1
 119
 120 static ahd_device_setup_t ahd_aic7901_setup;
 121 static ahd_device_setup_t ahd_aic7901A_setup;
 122 static ahd_device_setup_t ahd_aic7902_setup;
 123 static ahd_device_setup_t ahd_aic790X_setup;
 124
 125 struct ahd_pci_identity ahd_pci_ident_table [] =
 126 {
 127         /* aic7901 based controllers */
 128         {
 129                 ID_AHA_29320A,
 130                 ID_ALL_MASK,
 131                 "Adaptec 29320A Ultra320 SCSI adapter",
 132                 ahd_aic7901_setup
 133         },
 134         {
 135                 ID_AHA_29320ALP,
 136                 ID_ALL_MASK,
 137                 "Adaptec 29320ALP Ultra320 SCSI adapter",
 138                 ahd_aic7901_setup
 139         },
 140         /* aic7901A based controllers */
 141         {
 142                 ID_AHA_29320LP,
 143                 ID_ALL_MASK,
 144                 "Adaptec 29320LP Ultra320 SCSI adapter",
 145                 ahd_aic7901A_setup
 146         },
 147         /* aic7902 based controllers */
 148         {
 149                 ID_AHA_29320,
 150                 ID_ALL_MASK,
 151                 "Adaptec 29320 Ultra320 SCSI adapter",
 152                 ahd_aic7902_setup
 153         },
 154         {
 155                 ID_AHA_29320B,
 156                 ID_ALL_MASK,
 157                 "Adaptec 29320B Ultra320 SCSI adapter",
 158                 ahd_aic7902_setup
 159         },
 160         {
 161                 ID_AHA_39320,
 162                 ID_ALL_MASK,
 163                 "Adaptec 39320 Ultra320 SCSI adapter",
 164                 ahd_aic7902_setup
 165         },
 166         {
 167                 ID_AHA_39320_B,
 168                 ID_ALL_MASK,
 169                 "Adaptec 39320 Ultra320 SCSI adapter",
 170                 ahd_aic7902_setup
 171         },
 172         {
 173                 ID_AHA_39320_B_DELL,
 174                 ID_ALL_MASK,
 175                 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
 176                 ahd_aic7902_setup
 177         },
 178         {
 179                 ID_AHA_39320A,
 180                 ID_ALL_MASK,
 181                 "Adaptec 39320A Ultra320 SCSI adapter",
 182                 ahd_aic7902_setup
 183         },
 184         {
 185                 ID_AHA_39320D,
 186                 ID_ALL_MASK,
 187                 "Adaptec 39320D Ultra320 SCSI adapter",
 188                 ahd_aic7902_setup
 189         },
 190         {
 191                 ID_AHA_39320D_HP,
 192                 ID_ALL_MASK,
 193                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 194                 ahd_aic7902_setup
 195         },
 196         {
 197                 ID_AHA_39320D_B,
 198                 ID_ALL_MASK,
 199                 "Adaptec 39320D Ultra320 SCSI adapter",
 200                 ahd_aic7902_setup
 201         },
 202         {
 203                 ID_AHA_39320D_B_HP,
 204                 ID_ALL_MASK,
 205                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 206                 ahd_aic7902_setup
 207         },
 208         /* Generic chip probes for devices we don't know 'exactly' */
 209         {
 210                 ID_AIC7901 & ID_9005_GENERIC_MASK,
 211                 ID_9005_GENERIC_MASK,
 212                 "Adaptec AIC7901 Ultra320 SCSI adapter",
 213                 ahd_aic7901_setup
 214         },
 215         {
 216                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
 217                 ID_DEV_VENDOR_MASK,
 218                 "Adaptec AIC7901A Ultra320 SCSI adapter",
 219                 ahd_aic7901A_setup
 220         },
 221         {
 222                 ID_AIC7902 & ID_9005_GENERIC_MASK,
 223                 ID_9005_GENERIC_MASK,
 224                 "Adaptec AIC7902 Ultra320 SCSI adapter",
 225                 ahd_aic7902_setup
 226         }
 227 };
 228
 229 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
 230
 231 #define DEVCONFIG               0x40
 232 #define         PCIXINITPAT     0x0000E000ul
 233 #define                 PCIXINIT_PCI33_66       0x0000E000ul
 234 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
 235 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
 236 #define                 PCIXINIT_PCIX100_133    0x00008000ul
 237 #define PCI_BUS_MODES_INDEX(devconfig)  \
 238         (((devconfig) & PCIXINITPAT) >> 13)
 239 static const char *pci_bus_modes[] =
 240 {
 241         "PCI bus mode unknown",
 242         "PCI bus mode unknown",
 243         "PCI bus mode unknown",
 244         "PCI bus mode unknown",
 245         "PCI-X 101-133Mhz",
 246         "PCI-X 67-100Mhz",
 247         "PCI-X 50-66Mhz",
 248         "PCI 33 or 66Mhz"
 249 };
 250
 251 #define         TESTMODE        0x00000800ul
 252 #define         IRDY_RST        0x00000200ul
 253 #define         FRAME_RST       0x00000100ul
 254 #define         PCI64BIT        0x00000080ul
 255 #define         MRDCEN          0x00000040ul
 256 #define         ENDIANSEL       0x00000020ul
 257 #define         MIXQWENDIANEN   0x00000008ul
 258 #define         DACEN           0x00000004ul
 259 #define         STPWLEVEL       0x00000002ul
 260 #define         QWENDIANSEL     0x00000001ul
 261
 262 #define DEVCONFIG1              0x44
 263 #define         PREQDIS         0x01
 264
 265 #define CSIZE_LATTIME           0x0c
 266 #define         CACHESIZE       0x000000fful
 267 #define         LATTIME         0x0000ff00ul
 268
 269 static int      ahd_check_extport(struct ahd_softc *ahd);
 270 static void     ahd_configure_termination(struct ahd_softc *ahd,
 271                                           u_int adapter_control);
 272 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
 273
 274 struct ahd_pci_identity *
 275 ahd_find_pci_device(aic_dev_softc_t pci)
 276 {
 277         uint64_t  full_id;
 278         uint16_t  device;
 279         uint16_t  vendor;
 280         uint16_t  subdevice;
 281         uint16_t  subvendor;
 282         struct    ahd_pci_identity *entry;
 283         u_int     i;
 284
 285         vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 286         device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 287         subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 288         subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 289         full_id = ahd_compose_id(device,
 290                                  vendor,
 291                                  subdevice,
 292                                  subvendor);
 293
 294         /*
 295          * If we are configured to attach to HostRAID
 296          * controllers, mask out the IROC/HostRAID bit
 297          * in the
 298          */
 299         if (ahd_attach_to_HostRAID_controllers)
 300                 full_id &= ID_ALL_IROC_MASK;
 301
 302         for (i = 0; i < ahd_num_pci_devs; i++) {
 303                 entry = &ahd_pci_ident_table[i];
 304                 if (entry->full_id == (full_id & entry->id_mask)) {
 305                         /* Honor exclusion entries. */
 306                         if (entry->name == NULL)
 307                                 return (NULL);
 308                         return (entry);
 309                 }
 310         }
 311         return (NULL);
 312 }
 313
 314 int
 315 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
 316 {
 317         struct scb_data *shared_scb_data;
 318         u_int            command;
 319         uint32_t         devconfig;
 320         uint16_t         device;
 321         uint16_t         subvendor;
 322         int              error;
 323
 324         shared_scb_data = NULL;
 325         ahd->description = entry->name;
 326         /*
 327          * Record if this is a HostRAID board.
 328          */
 329         device = aic_pci_read_config(ahd->dev_softc,
 330                                      PCIR_DEVICE, /*bytes*/2);
 331         if (DEVID_9005_HOSTRAID(device))
 332                 ahd->flags |= AHD_HOSTRAID_BOARD;
 333
 334         /*
 335          * Record if this is an HP board.
 336          */
 337         subvendor = aic_pci_read_config(ahd->dev_softc,
 338                                         PCIR_SUBVEND_0, /*bytes*/2);
 339         if (subvendor == SUBID_HP)
 340                 ahd->flags |= AHD_HP_BOARD;
 341
 342         error = entry->setup(ahd);
 343         if (error != 0)
 344                 return (error);
 345
 346         devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 347         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 348                 ahd->chip |= AHD_PCI;
 349                 /* Disable PCIX workarounds when running in PCI mode. */
 350                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 351         } else {
 352                 ahd->chip |= AHD_PCIX;
 353         }
 354         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 355
 356         aic_power_state_change(ahd, AIC_POWER_STATE_D0);
 357
 358         error = ahd_pci_map_registers(ahd);
 359         if (error != 0)
 360                 return (error);
 361
 362         /*
 363          * If we need to support high memory, enable dual
 364          * address cycles.  This bit must be set to enable
 365          * high address bit generation even if we are on a
 366          * 64bit bus (PCI64BIT set in devconfig).
 367          */
 368         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
 369                 uint32_t devconfig;
 370
 371                 if (bootverbose)
 372                         kprintf("%s: Enabling 39Bit Addressing\n",
 373                                ahd_name(ahd));
 374                 devconfig = aic_pci_read_config(ahd->dev_softc,
 375                                                 DEVCONFIG, /*bytes*/4);
 376                 devconfig |= DACEN;
 377                 aic_pci_write_config(ahd->dev_softc, DEVCONFIG,
 378                                      devconfig, /*bytes*/4);
 379         }
 380
 381         /* Ensure busmastering is enabled */
 382         command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 383         command |= PCIM_CMD_BUSMASTEREN;
 384         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 385
 386         error = ahd_softc_init(ahd);
 387         if (error != 0)
 388                 return (error);
 389
 390         ahd->bus_intr = ahd_pci_intr;
 391
 392         error = ahd_reset(ahd, /*reinit*/FALSE);
 393         if (error != 0)
 394                 return (ENXIO);
 395
 396         ahd->pci_cachesize =
 397             aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
 398                                 /*bytes*/1) & CACHESIZE;
 399         ahd->pci_cachesize *= 4;
 400
 401         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 402         /* See if we have a SEEPROM and perform auto-term */
 403         error = ahd_check_extport(ahd);
 404         if (error != 0)
 405                 return (error);
 406
 407         /* Core initialization */
 408         error = ahd_init(ahd);
 409         if (error != 0)
 410                 return (error);
 411
 412         /*
 413          * Allow interrupts now that we are completely setup.
 414          */
 415         error = ahd_pci_map_int(ahd);
 416         if (error != 0)
 417                 return (error);
 418
 419         ahd_lock(ahd);
 420         /*
 421          * Link this softc in with all other ahd instances.
 422          */
 423         ahd_softc_insert(ahd);
 424         ahd_unlock(ahd);
 425         return (0);
 426 }
 427
 428 /*
 429  * Perform some simple tests that should catch situations where
 430  * our registers are invalidly mapped.
 431  */
 432 int
 433 ahd_pci_test_register_access(struct ahd_softc *ahd)
 434 {
 435         uint32_t cmd;
 436         u_int    targpcistat;
 437         u_int    pci_status1;
 438         int      error;
 439         uint8_t  hcntrl;
 440
 441         error = EIO;
 442
 443         /*
 444          * Enable PCI error interrupt status, but suppress NMIs
 445          * generated by SERR raised due to target aborts.
 446          */
 447         cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 448         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 449                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
 450
 451         /*
 452          * First a simple test to see if any
 453          * registers can be read.  Reading
 454          * HCNTRL has no side effects and has
 455          * at least one bit that is guaranteed to
 456          * be zero so it is a good register to
 457          * use for this test.
 458          */
 459         hcntrl = ahd_inb(ahd, HCNTRL);
 460         if (hcntrl == 0xFF)
 461                 goto fail;
 462
 463         /*
 464          * Next create a situation where write combining
 465          * or read prefetching could be initiated by the
 466          * CPU or host bridge.  Our device does not support
 467          * either, so look for data corruption and/or flaged
 468          * PCI errors.  First pause without causing another
 469          * chip reset.
 470          */
 471         hcntrl &= ~CHIPRST;
 472         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
 473         while (ahd_is_paused(ahd) == 0)
 474                 ;
 475
 476         /* Clear any PCI errors that occurred before our driver attached. */
 477         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 478         targpcistat = ahd_inb(ahd, TARGPCISTAT);
 479         ahd_outb(ahd, TARGPCISTAT, targpcistat);
 480         pci_status1 = aic_pci_read_config(ahd->dev_softc,
 481                                           PCIR_STATUS + 1, /*bytes*/1);
 482         aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 483                              pci_status1, /*bytes*/1);
 484         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 485         ahd_outb(ahd, CLRINT, CLRPCIINT);
 486
 487         ahd_outb(ahd, SEQCTL0, PERRORDIS);
 488         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
 489         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
 490                 goto fail;
 491
 492         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 493                 u_int targpcistat;
 494
 495                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 496                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 497                 if ((targpcistat & STA) != 0)
 498                         goto fail;
 499         }
 500
 501         error = 0;
 502
 503 fail:
 504         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 505
 506                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 507                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 508
 509                 /* Silently clear any latched errors. */
 510                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
 511                 pci_status1 = aic_pci_read_config(ahd->dev_softc,
 512                                                   PCIR_STATUS + 1, /*bytes*/1);
 513                 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 514                                      pci_status1, /*bytes*/1);
 515                 ahd_outb(ahd, CLRINT, CLRPCIINT);
 516         }
 517         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
 518         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 519         return (error);
 520 }
 521
 522 /*
 523  * Check the external port logic for a serial eeprom
 524  * and termination/cable detection contrls.
 525  */
 526 static int
 527 ahd_check_extport(struct ahd_softc *ahd)
 528 {
 529         struct  vpd_config vpd;
 530         struct  seeprom_config *sc;
 531         u_int   adapter_control;
 532         int     have_seeprom;
 533         int     error;
 534
 535         sc = ahd->seep_config;
 536         have_seeprom = ahd_acquire_seeprom(ahd);
 537         if (have_seeprom) {
 538                 u_int start_addr;
 539
 540                 /*
 541                  * Fetch VPD for this function and parse it.
 542                  */
 543                 if (bootverbose)
 544                         kprintf("%s: Reading VPD from SEEPROM...",
 545                                ahd_name(ahd));
 546
 547                 /* Address is always in units of 16bit words */
 548                 start_addr = ((2 * sizeof(*sc))
 549                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
 550
 551                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
 552                                          start_addr, sizeof(vpd)/2,
 553                                          /*bytestream*/TRUE);
 554                 if (error == 0)
 555                         error = ahd_parse_vpddata(ahd, &vpd);
 556                 if (bootverbose)
 557                         kprintf("%s: VPD parsing %s\n",
 558                                ahd_name(ahd),
 559                                error == 0 ? "successful" : "failed");
 560
 561                 if (bootverbose)
 562                         kprintf("%s: Reading SEEPROM...", ahd_name(ahd));
 563
 564                 /* Address is always in units of 16bit words */
 565                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
 566
 567                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
 568                                          start_addr, sizeof(*sc)/2,
 569                                          /*bytestream*/FALSE);
 570
 571                 if (error != 0) {
 572                         kprintf("Unable to read SEEPROM\n");
 573                         have_seeprom = 0;
 574                 } else {
 575                         have_seeprom = ahd_verify_cksum(sc);
 576
 577                         if (bootverbose) {
 578                                 if (have_seeprom == 0)
 579                                         kprintf ("checksum error\n");
 580                                 else
 581                                         kprintf ("done.\n");
 582                         }
 583                 }
 584                 ahd_release_seeprom(ahd);
 585         }
 586
 587         if (!have_seeprom) {
 588                 u_int     nvram_scb;
 589
 590                 /*
 591                  * Pull scratch ram settings and treat them as
 592                  * if they are the contents of an seeprom if
 593                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
 594                  * in SCB 0xFF.  We manually compose the data as 16bit
 595                  * values to avoid endian issues.
 596                  */
 597                 ahd_set_scbptr(ahd, 0xFF);
 598                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
 599                 if (nvram_scb != 0xFF
 600                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 601                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
 602                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 603                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
 604                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
 605                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
 606                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
 607                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
 608                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 609                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
 610                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 611                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
 612                         uint16_t *sc_data;
 613                         int       i;
 614
 615                         ahd_set_scbptr(ahd, nvram_scb);
 616                         sc_data = (uint16_t *)sc;
 617                         for (i = 0; i < 64; i += 2)
 618                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
 619                         have_seeprom = ahd_verify_cksum(sc);
 620                         if (have_seeprom)
 621                                 ahd->flags |= AHD_SCB_CONFIG_USED;
 622                 }
 623         }
 624
 625 #ifdef AHD_DEBUG
 626         if (have_seeprom != 0
 627          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 628                 uint16_t *sc_data;
 629                 int       i;
 630
 631                 kprintf("%s: Seeprom Contents:", ahd_name(ahd));
 632                 sc_data = (uint16_t *)sc;
 633                 for (i = 0; i < (sizeof(*sc)); i += 2)
 634                         kprintf("\n\t0x%.4x", sc_data[i]);
 635                 kprintf("\n");
 636         }
 637 #endif
 638
 639         if (!have_seeprom) {
 640                 if (bootverbose)
 641                         kprintf("%s: No SEEPROM available.\n", ahd_name(ahd));
 642                 ahd->flags |= AHD_USEDEFAULTS;
 643                 error = ahd_default_config(ahd);
 644                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
 645                 kfree(ahd->seep_config, M_DEVBUF);
 646                 ahd->seep_config = NULL;
 647         } else {
 648                 error = ahd_parse_cfgdata(ahd, sc);
 649                 adapter_control = sc->adapter_control;
 650         }
 651         if (error != 0)
 652                 return (error);
 653
 654         ahd_configure_termination(ahd, adapter_control);
 655
 656         return (0);
 657 }
 658
 659 static void
 660 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
 661 {
 662         int      error;
 663         u_int    sxfrctl1;
 664         uint8_t  termctl;
 665         uint32_t devconfig;
 666
 667         devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 668         devconfig &= ~STPWLEVEL;
 669         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
 670                 devconfig |= STPWLEVEL;
 671         if (bootverbose)
 672                 kprintf("%s: STPWLEVEL is %s\n",
 673                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
 674         aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 675
 676         /* Make sure current sensing is off. */
 677         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
 678                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
 679         }
 680
 681         /*
 682          * Read to sense.  Write to set.
 683          */
 684         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
 685         if ((adapter_control & CFAUTOTERM) == 0) {
 686                 if (bootverbose)
 687                         kprintf("%s: Manual Primary Termination\n",
 688                                ahd_name(ahd));
 689                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
 690                 if ((adapter_control & CFSTERM) != 0)
 691                         termctl |= FLX_TERMCTL_ENPRILOW;
 692                 if ((adapter_control & CFWSTERM) != 0)
 693                         termctl |= FLX_TERMCTL_ENPRIHIGH;
 694         } else if (error != 0) {
 695                 kprintf("%s: Primary Auto-Term Sensing failed! "
 696                        "Using Defaults.\n", ahd_name(ahd));
 697                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
 698         }
 699
 700         if ((adapter_control & CFSEAUTOTERM) == 0) {
 701                 if (bootverbose)
 702                         kprintf("%s: Manual Secondary Termination\n",
 703                                ahd_name(ahd));
 704                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
 705                 if ((adapter_control & CFSELOWTERM) != 0)
 706                         termctl |= FLX_TERMCTL_ENSECLOW;
 707                 if ((adapter_control & CFSEHIGHTERM) != 0)
 708                         termctl |= FLX_TERMCTL_ENSECHIGH;
 709         } else if (error != 0) {
 710                 kprintf("%s: Secondary Auto-Term Sensing failed! "
 711                        "Using Defaults.\n", ahd_name(ahd));
 712                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
 713         }
 714
 715         /*
 716          * Now set the termination based on what we found.
 717          */
 718         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
 719         ahd->flags &= ~AHD_TERM_ENB_A;
 720         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
 721                 ahd->flags |= AHD_TERM_ENB_A;
 722                 sxfrctl1 |= STPWEN;
 723         }
 724         /* Must set the latch once in order to be effective. */
 725         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
 726         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
 727
 728         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
 729         if (error != 0) {
 730                 kprintf("%s: Unable to set termination settings!\n",
 731                        ahd_name(ahd));
 732         } else if (bootverbose) {
 733                 kprintf("%s: Primary High byte termination %sabled\n",
 734                        ahd_name(ahd),
 735                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
 736
 737                 kprintf("%s: Primary Low byte termination %sabled\n",
 738                        ahd_name(ahd),
 739                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
 740
 741                 kprintf("%s: Secondary High byte termination %sabled\n",
 742                        ahd_name(ahd),
 743                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
 744
 745                 kprintf("%s: Secondary Low byte termination %sabled\n",
 746                        ahd_name(ahd),
 747                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
 748         }
 749         return;
 750 }
 751
 752 #define DPE     0x80
 753 #define SSE     0x40
 754 #define RMA     0x20
 755 #define RTA     0x10
 756 #define STA     0x08
 757 #define DPR     0x01
 758
 759 static const char *split_status_source[] =
 760 {
 761         "DFF0",
 762         "DFF1",
 763         "OVLY",
 764         "CMC",
 765 };
 766
 767 static const char *pci_status_source[] =
 768 {
 769         "DFF0",
 770         "DFF1",
 771         "SG",
 772         "CMC",
 773         "OVLY",
 774         "NONE",
 775         "MSI",
 776         "TARG"
 777 };
 778
 779 static const char *split_status_strings[] =
 780 {
 781         "%s: Received split response in %s.\n",
 782         "%s: Received split completion error message in %s\n",
 783         "%s: Receive overrun in %s\n",
 784         "%s: Count not complete in %s\n",
 785         "%s: Split completion data bucket in %s\n",
 786         "%s: Split completion address error in %s\n",
 787         "%s: Split completion byte count error in %s\n",
 788         "%s: Signaled Target-abort to early terminate a split in %s\n"
 789 };
 790
 791 static const char *pci_status_strings[] =
 792 {
 793         "%s: Data Parity Error has been reported via PERR# in %s\n",
 794         "%s: Target initial wait state error in %s\n",
 795         "%s: Split completion read data parity error in %s\n",
 796         "%s: Split completion address attribute parity error in %s\n",
 797         "%s: Received a Target Abort in %s\n",
 798         "%s: Received a Master Abort in %s\n",
 799         "%s: Signal System Error Detected in %s\n",
 800         "%s: Address or Write Phase Parity Error Detected in %s.\n"
 801 };
 802
 803 void
 804 ahd_pci_intr(struct ahd_softc *ahd)
 805 {
 806         uint8_t         pci_status[8];
 807         ahd_mode_state  saved_modes;
 808         u_int           pci_status1;
 809         u_int           intstat;
 810         u_int           i;
 811         u_int           reg;
 812
 813         intstat = ahd_inb(ahd, INTSTAT);
 814
 815         if ((intstat & SPLTINT) != 0)
 816                 ahd_pci_split_intr(ahd, intstat);
 817
 818         if ((intstat & PCIINT) == 0)
 819                 return;
 820
 821         kprintf("%s: PCI error Interrupt\n", ahd_name(ahd));
 822         saved_modes = ahd_save_modes(ahd);
 823         ahd_dump_card_state(ahd);
 824         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 825         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
 826
 827                 if (i == 5)
 828                         continue;
 829                 pci_status[i] = ahd_inb(ahd, reg);
 830                 /* Clear latched errors.  So our interrupt deasserts. */
 831                 ahd_outb(ahd, reg, pci_status[i]);
 832         }
 833
 834         for (i = 0; i < 8; i++) {
 835                 u_int bit;
 836
 837                 if (i == 5)
 838                         continue;
 839
 840                 for (bit = 0; bit < 8; bit++) {
 841
 842                         if ((pci_status[i] & (0x1 << bit)) != 0) {
 843                                 static const char *s;
 844
 845                                 s = pci_status_strings[bit];
 846                                 if (i == 7/*TARG*/ && bit == 3)
 847                                         s = "%s: Signaled Target Abort\n";
 848                                 kprintf(s, ahd_name(ahd), pci_status_source[i]);
 849                         }
 850                 }
 851         }
 852         pci_status1 = aic_pci_read_config(ahd->dev_softc,
 853                                           PCIR_STATUS + 1, /*bytes*/1);
 854         aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 855                              pci_status1, /*bytes*/1);
 856         ahd_restore_modes(ahd, saved_modes);
 857         ahd_outb(ahd, CLRINT, CLRPCIINT);
 858         ahd_unpause(ahd);
 859 }
 860
 861 static void
 862 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
 863 {
 864         uint8_t         split_status[4];
 865         uint8_t         split_status1[4];
 866         uint8_t         sg_split_status[2];
 867         uint8_t         sg_split_status1[2];
 868         ahd_mode_state  saved_modes;
 869         u_int           i;
 870         uint16_t        pcix_status;
 871
 872         /*
 873          * Check for splits in all modes.  Modes 0 and 1
 874          * additionally have SG engine splits to look at.
 875          */
 876         pcix_status = aic_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
 877                                           /*bytes*/2);
 878         kprintf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
 879                ahd_name(ahd), pcix_status);
 880         saved_modes = ahd_save_modes(ahd);
 881         for (i = 0; i < 4; i++) {
 882                 ahd_set_modes(ahd, i, i);
 883
 884                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
 885                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
 886                 /* Clear latched errors.  So our interrupt deasserts. */
 887                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
 888                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
 889                 if (i > 1)
 890                         continue;
 891                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
 892                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
 893                 /* Clear latched errors.  So our interrupt deasserts. */
 894                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
 895                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
 896         }
 897
 898         for (i = 0; i < 4; i++) {
 899                 u_int bit;
 900
 901                 for (bit = 0; bit < 8; bit++) {
 902
 903                         if ((split_status[i] & (0x1 << bit)) != 0) {
 904                                 static const char *s;
 905
 906                                 s = split_status_strings[bit];
 907                                 kprintf(s, ahd_name(ahd),
 908                                        split_status_source[i]);
 909                         }
 910
 911                         if (i > 1)
 912                                 continue;
 913
 914                         if ((sg_split_status[i] & (0x1 << bit)) != 0) {
 915                                 static const char *s;
 916
 917                                 s = split_status_strings[bit];
 918                                 kprintf(s, ahd_name(ahd), "SG");
 919                         }
 920                 }
 921         }
 922         /*
 923          * Clear PCI-X status bits.
 924          */
 925         aic_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
 926                              pcix_status, /*bytes*/2);
 927         ahd_outb(ahd, CLRINT, CLRSPLTINT);
 928         ahd_restore_modes(ahd, saved_modes);
 929 }
 930
 931 static int
 932 ahd_aic7901_setup(struct ahd_softc *ahd)
 933 {
 934
 935         ahd->chip = AHD_AIC7901;
 936         ahd->features = AHD_AIC7901_FE;
 937         return (ahd_aic790X_setup(ahd));
 938 }
 939
 940 static int
 941 ahd_aic7901A_setup(struct ahd_softc *ahd)
 942 {
 943
 944         ahd->chip = AHD_AIC7901A;
 945         ahd->features = AHD_AIC7901A_FE;
 946         return (ahd_aic790X_setup(ahd));
 947 }
 948
 949 static int
 950 ahd_aic7902_setup(struct ahd_softc *ahd)
 951 {
 952         ahd->chip = AHD_AIC7902;
 953         ahd->features = AHD_AIC7902_FE;
 954         return (ahd_aic790X_setup(ahd));
 955 }
 956
 957 static int
 958 ahd_aic790X_setup(struct ahd_softc *ahd)
 959 {
 960         aic_dev_softc_t pci;
 961         u_int rev;
 962
 963         pci = ahd->dev_softc;
 964         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
 965         if (rev < ID_AIC7902_PCI_REV_A4) {
 966                 kprintf("%s: Unable to attach to unsupported chip revision %d\n",
 967                        ahd_name(ahd), rev);
 968                 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
 969                 return (ENXIO);
 970         }
 971         ahd->channel = aic_get_pci_function(pci) + 'A';
 972         if (rev < ID_AIC7902_PCI_REV_B0) {
 973                 /*
 974                  * Enable A series workarounds.
 975                  */
 976                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
 977                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
 978                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
 979                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
 980                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
 981                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
 982                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
 983                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
 984                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
 985                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
 986                           |  AHD_FAINT_LED_BUG;
 987
 988                 /*
 989                  * IO Cell paramter setup.
 990                  */
 991                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 992
 993                 if ((ahd->flags & AHD_HP_BOARD) == 0)
 994                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
 995         } else {
 996                 u_int devconfig1;
 997
 998                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
 999                               |  AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY;
1000                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
1001
1002                 /*
1003                  * Some issues have been resolved in the 7901B.
1004                  */
1005                 if ((ahd->features & AHD_MULTI_FUNC) != 0)
1006                         ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG
1007                                   |  AHD_BUSFREEREV_BUG;
1008
1009                 /*
1010                  * IO Cell paramter setup.
1011                  */
1012                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1013                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
1014                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
1015
1016                 /*
1017                  * Set the PREQDIS bit for H2B which disables some workaround
1018                  * that doesn't work on regular PCI busses.
1019                  * XXX - Find out exactly what this does from the hardware
1020                  *       folks!
1021                  */
1022                 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1023                 aic_pci_write_config(pci, DEVCONFIG1,
1024                                      devconfig1|PREQDIS, /*bytes*/1);
1025                 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1026         }
1027
1028         return (0);
1029 }