sys/platform/pc32/i386/identcpu.c

   1 /*
   2  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   3  * Copyright (c) 1992 Terrence R. Lambert.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * Copyright (c) 2001 Tamotsu Hattori.
   6  * Copyright (c) 2001 Mitsuru IWASAKI.
   7  * All rights reserved.
   8  *
   9  * This code is derived from software contributed to Berkeley by
  10  * William Jolitz.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. All advertising materials mentioning features or use of this software
  21  *    must display the following acknowledgement:
  22  *      This product includes software developed by the University of
  23  *      California, Berkeley and its contributors.
  24  * 4. Neither the name of the University nor the names of its contributors
  25  *    may be used to endorse or promote products derived from this software
  26  *    without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  41  * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
  42  * $DragonFly: src/sys/platform/pc32/i386/identcpu.c,v 1.14 2006/12/07 13:33:04 tgen Exp $
  43  */
  44
  45 #include "opt_cpu.h"
  46
  47 #include <sys/param.h>
  48 #include <sys/systm.h>
  49 #include <sys/kernel.h>
  50 #include <sys/sysctl.h>
  51 #include <sys/lock.h>
  52
  53 #include <machine/asmacros.h>
  54 #include <machine/clock.h>
  55 #include <machine/cputypes.h>
  56 #include <machine/segments.h>
  57 #include <machine/specialreg.h>
  58 #include <machine/md_var.h>
  59
  60 #include <machine_base/isa/intr_machdep.h>
  61
  62 #define IDENTBLUE_CYRIX486      0
  63 #define IDENTBLUE_IBMCPU        1
  64 #define IDENTBLUE_CYRIXM2       2
  65
  66 /* XXX - should be in header file: */
  67 void printcpuinfo(void);
  68 void finishidentcpu(void);
  69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  70 void    enable_K5_wt_alloc(void);
  71 void    enable_K6_wt_alloc(void);
  72 void    enable_K6_2_wt_alloc(void);
  73 #endif
  74 void panicifcpuunsupported(void);
  75
  76 static void identifycyrix(void);
  77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
  78 static void print_AMD_features(void);
  79 #endif
  80 static void print_AMD_info(void);
  81 static void print_AMD_assoc(int i);
  82 static void print_transmeta_info(void);
  83 static void setup_tmx86_longrun(void);
  84
  85 int     cpu_class = CPUCLASS_386;
  86 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
  87 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
  88 char machine[] = MACHINE;
  89 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  90     machine, 0, "Machine class");
  91
  92 static char cpu_model[128];
  93 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  94     cpu_model, 0, "Machine model");
  95
  96 static char cpu_brand[48];
  97
  98 #define MAX_ADDITIONAL_INFO     16
  99
 100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
 101 static u_int additional_cpu_info_count;
 102
 103 #define MAX_BRAND_INDEX 23
 104
 105 /*
 106  * Brand ID's according to Intel document AP-485, number 241618-31, published
 107  * September 2006, page 42.
 108  */
 109 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 110         NULL,                   /* No brand */
 111         "Intel Celeron",
 112         "Intel Pentium III",
 113         "Intel Pentium III Xeon",
 114         "Intel Pentium III",
 115         NULL,                   /* Unspecified */
 116         "Mobile Intel Pentium III-M",
 117         "Mobile Intel Celeron",
 118         "Intel Pentium 4",
 119         "Intel Pentium 4",
 120         "Intel Celeron",
 121         "Intel Xeon",
 122         "Intel Xeon MP",
 123         NULL,                   /* Unspecified */
 124         "Mobile Intel Pentium 4-M",
 125         "Mobile Intel Celeron",
 126         NULL,                   /* Unspecified */
 127         "Mobile Genuine Intel",
 128         "Intel Celeron M",
 129         "Mobile Intel Celeron",
 130         "Intel Celeron",
 131         "Mobile Genuine Intel",
 132         "Intel Pentium M",
 133         "Mobile Intel Celeron"
 134 };
 135
 136 static struct cpu_nameclass i386_cpus[] = {
 137         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 138         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 139         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 140         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 141         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 142         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 143         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 144         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 145         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 146         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 147         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 148         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 149         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 150         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 151         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 152         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 153         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 154 };
 155
 156 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 157 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
 158 #endif
 159
 160 void
 161 printcpuinfo(void)
 162 {
 163 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
 164         u_int regs[4], i;
 165 #endif
 166         char *brand;
 167
 168         cpu_class = i386_cpus[cpu].cpu_class;
 169         printf("CPU: ");
 170         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
 171
 172 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
 173         /* Check for extended CPUID information and a processor name. */
 174         if (cpu_high > 0 &&
 175             (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
 176             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
 177             strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
 178             strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
 179                 do_cpuid(0x80000000, regs);
 180                 if (regs[0] >= 0x80000000) {
 181                         cpu_exthigh = regs[0];
 182                         if (cpu_exthigh >= 0x80000004) {
 183                                 brand = cpu_brand;
 184                                 for (i = 0x80000002; i < 0x80000005; i++) {
 185                                         do_cpuid(i, regs);
 186                                         memcpy(brand, regs, sizeof(regs));
 187                                         brand += sizeof(regs);
 188                                 }
 189                         }
 190                 }
 191         }
 192
 193         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
 194                 if ((cpu_id & 0xf00) > 0x300) {
 195                         u_int brand_index;
 196
 197                         cpu_model[0] = '\0';
 198
 199                         switch (cpu_id & 0x3000) {
 200                         case 0x1000:
 201                                 strcpy(cpu_model, "Overdrive ");
 202                                 break;
 203                         case 0x2000:
 204                                 strcpy(cpu_model, "Dual ");
 205                                 break;
 206                         }
 207
 208                         switch (cpu_id & 0xf00) {
 209                         case 0x400:
 210                                 strcat(cpu_model, "i486 ");
 211                                 /* Check the particular flavor of 486 */
 212                                 switch (cpu_id & 0xf0) {
 213                                 case 0x00:
 214                                 case 0x10:
 215                                         strcat(cpu_model, "DX");
 216                                         break;
 217                                 case 0x20:
 218                                         strcat(cpu_model, "SX");
 219                                         break;
 220                                 case 0x30:
 221                                         strcat(cpu_model, "DX2");
 222                                         break;
 223                                 case 0x40:
 224                                         strcat(cpu_model, "SL");
 225                                         break;
 226                                 case 0x50:
 227                                         strcat(cpu_model, "SX2");
 228                                         break;
 229                                 case 0x70:
 230                                         strcat(cpu_model,
 231                                             "DX2 Write-Back Enhanced");
 232                                         break;
 233                                 case 0x80:
 234                                         strcat(cpu_model, "DX4");
 235                                         break;
 236                                 }
 237                                 break;
 238                         case 0x500:
 239                                 /* Check the particular flavor of 586 */
 240                                 strcat(cpu_model, "Pentium");
 241                                 switch (cpu_id & 0xf0) {
 242                                 case 0x00:
 243                                         strcat(cpu_model, " A-step");
 244                                         break;
 245                                 case 0x10:
 246                                         strcat(cpu_model, "/P5");
 247                                         break;
 248                                 case 0x20:
 249                                         strcat(cpu_model, "/P54C");
 250                                         break;
 251                                 case 0x30:
 252                                         strcat(cpu_model, "/P54T Overdrive");
 253                                         break;
 254                                 case 0x40:
 255                                         strcat(cpu_model, "/P55C");
 256                                         break;
 257                                 case 0x70:
 258                                         strcat(cpu_model, "/P54C");
 259                                         break;
 260                                 case 0x80:
 261                                         strcat(cpu_model, "/P55C (quarter-micron)");
 262                                         break;
 263                                 default:
 264                                         /* nothing */
 265                                         break;
 266                                 }
 267 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 268                                 /*
 269                                  * XXX - If/when Intel fixes the bug, this
 270                                  * should also check the version of the
 271                                  * CPU, not just that it's a Pentium.
 272                                  */
 273                                 has_f00f_bug = 1;
 274 #endif
 275                                 break;
 276                         case 0x600:
 277                                 /* Check the particular flavor of 686 */
 278                                 switch (cpu_id & 0xf0) {
 279                                 case 0x00:
 280                                         strcat(cpu_model, "Pentium Pro A-step");
 281                                         break;
 282                                 case 0x10:
 283                                         strcat(cpu_model, "Pentium Pro");
 284                                         break;
 285                                 case 0x30:
 286                                 case 0x50:
 287                                 case 0x60:
 288                                         strcat(cpu_model,
 289                                 "Pentium II/Pentium II Xeon/Celeron");
 290                                         cpu = CPU_PII;
 291                                         break;
 292                                 case 0x70:
 293                                 case 0x80:
 294                                 case 0xa0:
 295                                 case 0xb0:
 296                                         strcat(cpu_model,
 297                                         "Pentium III/Pentium III Xeon/Celeron");
 298                                         cpu = CPU_PIII;
 299                                         break;
 300                                 default:
 301                                         strcat(cpu_model, "Unknown 80686");
 302                                         break;
 303                                 }
 304                                 break;
 305                         case 0xf00:
 306                                 strcat(cpu_model, "Pentium 4");
 307                                 cpu = CPU_P4;
 308                                 break;
 309                         default:
 310                                 strcat(cpu_model, "unknown");
 311                                 break;
 312                         }
 313
 314                         /*
 315                          * If we didn't get a brand name from the extended
 316                          * CPUID, try to look it up in the brand table.
 317                          */
 318                         if (cpu_high > 0 && *cpu_brand == '\0') {
 319                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 320                                 if (brand_index <= MAX_BRAND_INDEX &&
 321                                     cpu_brandtable[brand_index] != NULL)
 322                                         strcpy(cpu_brand,
 323                                             cpu_brandtable[brand_index]);
 324                         }
 325                 }
 326         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
 327                 /*
 328                  * Values taken from AMD Processor Recognition
 329                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 330                  * (also describes ``Features'' encodings.
 331                  */
 332                 strcpy(cpu_model, "AMD ");
 333                 switch (cpu_id & 0xFF0) {
 334                 case 0x410:
 335                         strcat(cpu_model, "Standard Am486DX");
 336                         break;
 337                 case 0x430:
 338                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 339                         break;
 340                 case 0x470:
 341                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 342                         break;
 343                 case 0x480:
 344                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 345                         break;
 346                 case 0x490:
 347                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 348                         break;
 349                 case 0x4E0:
 350                         strcat(cpu_model, "Am5x86 Write-Through");
 351                         break;
 352                 case 0x4F0:
 353                         strcat(cpu_model, "Am5x86 Write-Back");
 354                         break;
 355                 case 0x500:
 356                         strcat(cpu_model, "K5 model 0");
 357                         tsc_is_broken = 1;
 358                         break;
 359                 case 0x510:
 360                         strcat(cpu_model, "K5 model 1");
 361                         break;
 362                 case 0x520:
 363                         strcat(cpu_model, "K5 PR166 (model 2)");
 364                         break;
 365                 case 0x530:
 366                         strcat(cpu_model, "K5 PR200 (model 3)");
 367                         break;
 368                 case 0x560:
 369                         strcat(cpu_model, "K6");
 370                         break;
 371                 case 0x570:
 372                         strcat(cpu_model, "K6 266 (model 1)");
 373                         break;
 374                 case 0x580:
 375                         strcat(cpu_model, "K6-2");
 376                         break;
 377                 case 0x590:
 378                         strcat(cpu_model, "K6-III");
 379                         break;
 380                 default:
 381                         strcat(cpu_model, "Unknown");
 382                         break;
 383                 }
 384 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 385                 if ((cpu_id & 0xf00) == 0x500) {
 386                         if (((cpu_id & 0x0f0) > 0)
 387                             && ((cpu_id & 0x0f0) < 0x60)
 388                             && ((cpu_id & 0x00f) > 3))
 389                                 enable_K5_wt_alloc();
 390                         else if (((cpu_id & 0x0f0) > 0x80)
 391                                  || (((cpu_id & 0x0f0) == 0x80)
 392                                      && (cpu_id & 0x00f) > 0x07))
 393                                 enable_K6_2_wt_alloc();
 394                         else if ((cpu_id & 0x0f0) > 0x50)
 395                                 enable_K6_wt_alloc();
 396                 }
 397 #endif
 398         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
 399                 strcpy(cpu_model, "Cyrix ");
 400                 switch (cpu_id & 0xff0) {
 401                 case 0x440:
 402                         strcat(cpu_model, "MediaGX");
 403                         break;
 404                 case 0x520:
 405                         strcat(cpu_model, "6x86");
 406                         break;
 407                 case 0x540:
 408                         cpu_class = CPUCLASS_586;
 409                         strcat(cpu_model, "GXm");
 410                         break;
 411                 case 0x600:
 412                         strcat(cpu_model, "6x86MX");
 413                         break;
 414                 default:
 415                         /*
 416                          * Even though CPU supports the cpuid
 417                          * instruction, it can be disabled.
 418                          * Therefore, this routine supports all Cyrix
 419                          * CPUs.
 420                          */
 421                         switch (cyrix_did & 0xf0) {
 422                         case 0x00:
 423                                 switch (cyrix_did & 0x0f) {
 424                                 case 0x00:
 425                                         strcat(cpu_model, "486SLC");
 426                                         break;
 427                                 case 0x01:
 428                                         strcat(cpu_model, "486DLC");
 429                                         break;
 430                                 case 0x02:
 431                                         strcat(cpu_model, "486SLC2");
 432                                         break;
 433                                 case 0x03:
 434                                         strcat(cpu_model, "486DLC2");
 435                                         break;
 436                                 case 0x04:
 437                                         strcat(cpu_model, "486SRx");
 438                                         break;
 439                                 case 0x05:
 440                                         strcat(cpu_model, "486DRx");
 441                                         break;
 442                                 case 0x06:
 443                                         strcat(cpu_model, "486SRx2");
 444                                         break;
 445                                 case 0x07:
 446                                         strcat(cpu_model, "486DRx2");
 447                                         break;
 448                                 case 0x08:
 449                                         strcat(cpu_model, "486SRu");
 450                                         break;
 451                                 case 0x09:
 452                                         strcat(cpu_model, "486DRu");
 453                                         break;
 454                                 case 0x0a:
 455                                         strcat(cpu_model, "486SRu2");
 456                                         break;
 457                                 case 0x0b:
 458                                         strcat(cpu_model, "486DRu2");
 459                                         break;
 460                                 default:
 461                                         strcat(cpu_model, "Unknown");
 462                                         break;
 463                                 }
 464                                 break;
 465                         case 0x10:
 466                                 switch (cyrix_did & 0x0f) {
 467                                 case 0x00:
 468                                         strcat(cpu_model, "486S");
 469                                         break;
 470                                 case 0x01:
 471                                         strcat(cpu_model, "486S2");
 472                                         break;
 473                                 case 0x02:
 474                                         strcat(cpu_model, "486Se");
 475                                         break;
 476                                 case 0x03:
 477                                         strcat(cpu_model, "486S2e");
 478                                         break;
 479                                 case 0x0a:
 480                                         strcat(cpu_model, "486DX");
 481                                         break;
 482                                 case 0x0b:
 483                                         strcat(cpu_model, "486DX2");
 484                                         break;
 485                                 case 0x0f:
 486                                         strcat(cpu_model, "486DX4");
 487                                         break;
 488                                 default:
 489                                         strcat(cpu_model, "Unknown");
 490                                         break;
 491                                 }
 492                                 break;
 493                         case 0x20:
 494                                 if ((cyrix_did & 0x0f) < 8)
 495                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 496                                 else
 497                                         strcat(cpu_model, "5x86");
 498                                 break;
 499                         case 0x30:
 500                                 strcat(cpu_model, "6x86");
 501                                 break;
 502                         case 0x40:
 503                                 if ((cyrix_did & 0xf000) == 0x3000) {
 504                                         cpu_class = CPUCLASS_586;
 505                                         strcat(cpu_model, "GXm");
 506                                 } else
 507                                         strcat(cpu_model, "MediaGX");
 508                                 break;
 509                         case 0x50:
 510                                 strcat(cpu_model, "6x86MX");
 511                                 break;
 512                         case 0xf0:
 513                                 switch (cyrix_did & 0x0f) {
 514                                 case 0x0d:
 515                                         strcat(cpu_model, "Overdrive CPU");
 516                                 case 0x0e:
 517                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 518                                         break;
 519                                 case 0x0f:
 520                                         strcat(cpu_model, "486SLC/DLC");
 521                                         break;
 522                                 default:
 523                                         strcat(cpu_model, "Unknown");
 524                                         break;
 525                                 }
 526                                 break;
 527                         default:
 528                                 strcat(cpu_model, "Unknown");
 529                                 break;
 530                         }
 531                         break;
 532                 }
 533         } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
 534                 strcpy(cpu_model, "Rise ");
 535                 switch (cpu_id & 0xff0) {
 536                 case 0x500:
 537                         strcat(cpu_model, "mP6");
 538                         break;
 539                 default:
 540                         strcat(cpu_model, "Unknown");
 541                 }
 542         } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
 543                 switch (cpu_id & 0xff0) {
 544                 case 0x540:
 545                         strcpy(cpu_model, "IDT WinChip C6");
 546                         tsc_is_broken = 1;
 547                         break;
 548                 case 0x580:
 549                         strcpy(cpu_model, "IDT WinChip 2");
 550                         break;
 551                 case 0x660:
 552                         strcpy(cpu_model, "VIA C3 Samuel");
 553                         break;
 554                 case 0x670:
 555                         if (cpu_id & 0x8)
 556                                 strcpy(cpu_model, "VIA C3 Ezra");
 557                         else
 558                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 559                         break;
 560                 case 0x680:
 561                         strcpy(cpu_model, "VIA C3 Ezra-T");
 562                         break;
 563                 case 0x690:
 564                         strcpy(cpu_model, "VIA C3 Nehemiah");
 565                         do_cpuid(0xc0000000, regs);
 566                         if (regs[0] == 0xc0000001) {
 567                                 do_cpuid(0xc0000001, regs);
 568                                 if ((cpu_id & 0xf) >= 3)
 569                                         if ((regs[3] & 0x0c) == 0x0c)
 570                                                 strcat(cpu_model, "+RNG");
 571                                 if ((cpu_id & 0xf) >= 8)
 572                                         if ((regs[3] & 0xc0) == 0xc0)
 573                                                 strcat(cpu_model, "+ACE");
 574                         }
 575                         break;
 576                 default:
 577                         strcpy(cpu_model, "VIA/IDT Unknown");
 578                 }
 579         } else if (strcmp(cpu_vendor, "IBM") == 0) {
 580                 strcpy(cpu_model, "Blue Lightning CPU");
 581         }
 582
 583         /*
 584          * Replace cpu_model with cpu_brand minus leading spaces if
 585          * we have one.
 586          */
 587         brand = cpu_brand;
 588         while (*brand == ' ')
 589                 ++brand;
 590         if (*brand != '\0')
 591                 strcpy(cpu_model, brand);
 592
 593 #endif
 594
 595         printf("%s (", cpu_model);
 596         switch(cpu_class) {
 597         case CPUCLASS_286:
 598                 printf("286");
 599                 break;
 600 #if defined(I386_CPU)
 601         case CPUCLASS_386:
 602                 printf("386");
 603                 break;
 604 #endif
 605 #if defined(I486_CPU)
 606         case CPUCLASS_486:
 607                 printf("486");
 608                 /* bzero = i486_bzero; */
 609                 break;
 610 #endif
 611 #if defined(I586_CPU)
 612         case CPUCLASS_586:
 613                 printf("%d.%02d-MHz ",
 614                        (tsc_freq + 4999) / 1000000,
 615                        ((tsc_freq + 4999) / 10000) % 100);
 616                 printf("586");
 617                 break;
 618 #endif
 619 #if defined(I686_CPU)
 620         case CPUCLASS_686:
 621                 printf("%d.%02d-MHz ",
 622                        (tsc_freq + 4999) / 1000000,
 623                        ((tsc_freq + 4999) / 10000) % 100);
 624                 printf("686");
 625                 break;
 626 #endif
 627         default:
 628                 printf("Unknown");      /* will panic below... */
 629         }
 630         printf("-class CPU)\n");
 631 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
 632         if(*cpu_vendor)
 633                 printf("  Origin = \"%s\"",cpu_vendor);
 634         if(cpu_id)
 635                 printf("  Id = 0x%x", cpu_id);
 636
 637         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
 638             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
 639             strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
 640             strcmp(cpu_vendor, "CentaurHauls") == 0 ||
 641                 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
 642                  ((cpu_id & 0xf00) > 0x500))) {
 643                 printf("  Stepping = %u", cpu_id & 0xf);
 644                 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
 645                         printf("  DIR=0x%04x", cyrix_did);
 646                 if (cpu_high > 0) {
 647                         /*
 648                          * Here we should probably set up flags indicating
 649                          * whether or not various features are available.
 650                          * The interesting ones are probably VME, PSE, PAE,
 651                          * and PGE.  The code already assumes without bothering
 652                          * to check that all CPUs >= Pentium have a TSC and
 653                          * MSRs.
 654                          */
 655                         printf("\n  Features=0x%b", cpu_feature,
 656                         "\020"
 657                         "\001FPU"       /* Integral FPU */
 658                         "\002VME"       /* Extended VM86 mode support */
 659                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 660                         "\004PSE"       /* 4MByte page tables */
 661                         "\005TSC"       /* Timestamp counter */
 662                         "\006MSR"       /* Machine specific registers */
 663                         "\007PAE"       /* Physical address extension */
 664                         "\010MCE"       /* Machine Check support */
 665                         "\011CX8"       /* CMPEXCH8 instruction */
 666                         "\012APIC"      /* SMP local APIC */
 667                         "\013oldMTRR"   /* Previous implementation of MTRR */
 668                         "\014SEP"       /* Fast System Call */
 669                         "\015MTRR"      /* Memory Type Range Registers */
 670                         "\016PGE"       /* PG_G (global bit) support */
 671                         "\017MCA"       /* Machine Check Architecture */
 672                         "\020CMOV"      /* CMOV instruction */
 673                         "\021PAT"       /* Page attributes table */
 674                         "\022PSE36"     /* 36 bit address space support */
 675                         "\023PN"        /* Processor Serial number */
 676                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 677                         "\025<b20>"
 678                         "\026DTS"       /* Debug Trace Store */
 679                         "\027ACPI"      /* ACPI support */
 680                         "\030MMX"       /* MMX instructions */
 681                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 682                         "\032SSE"       /* Streaming SIMD Extensions */
 683                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 684                         "\034SS"        /* Self snoop */
 685                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 686                         "\036TM"        /* Thermal Monitor clock slowdown */
 687                         "\037IA64"      /* CPU can execute IA64 instructions */
 688                         "\040PBE"       /* Pending Break Enable */
 689                         );
 690
 691                         /*
 692                          * If this CPU supports hyperthreading then mention
 693                          * the number of logical CPU's it contains.
 694                          */
 695                         if (cpu_feature & CPUID_HTT &&
 696                             (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
 697                                 printf("\n  Hyperthreading: %d logical CPUs",
 698                                     (cpu_procinfo & CPUID_HTT_CORES) >> 16);
 699                 }
 700                 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
 701                     cpu_exthigh >= 0x80000001)
 702                         print_AMD_features();
 703         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
 704                 printf("  DIR=0x%04x", cyrix_did);
 705                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
 706                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
 707 #ifndef CYRIX_CACHE_REALLY_WORKS
 708                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
 709                         printf("\n  CPU cache: write-through mode");
 710 #endif
 711         }
 712         /* Avoid ugly blank lines: only print newline when we have to. */
 713         if (*cpu_vendor || cpu_id)
 714                 printf("\n");
 715
 716 #endif
 717         if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
 718             strcmp(cpu_vendor, "TransmetaCPU") == 0) {
 719                 setup_tmx86_longrun();
 720         }
 721
 722         for (i = 0; i < additional_cpu_info_count; ++i) {
 723                 printf("  %s\n", additional_cpu_info_ary[i]);
 724         }
 725
 726         if (!bootverbose)
 727                 return;
 728
 729         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
 730                 print_AMD_info();
 731         else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
 732                  strcmp(cpu_vendor, "TransmetaCPU") == 0)
 733                 print_transmeta_info();
 734
 735 #ifdef I686_CPU
 736         /*
 737          * XXX - Do PPro CPUID level=2 stuff here?
 738          *
 739          * No, but maybe in a print_Intel_info() function called from here.
 740          */
 741 #endif
 742 }
 743
 744 void
 745 panicifcpuunsupported(void)
 746 {
 747
 748 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
 749 #error This kernel is not configured for one of the supported CPUs
 750 #endif
 751         /*
 752          * Now that we have told the user what they have,
 753          * let them know if that machine type isn't configured.
 754          */
 755         switch (cpu_class) {
 756         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
 757 #if !defined(I386_CPU)
 758         case CPUCLASS_386:
 759 #endif
 760 #if !defined(I486_CPU)
 761         case CPUCLASS_486:
 762 #endif
 763 #if !defined(I586_CPU)
 764         case CPUCLASS_586:
 765 #endif
 766 #if !defined(I686_CPU)
 767         case CPUCLASS_686:
 768 #endif
 769                 panic("CPU class not configured");
 770         default:
 771                 break;
 772         }
 773 }
 774
 775
 776 static  volatile u_int trap_by_rdmsr;
 777
 778 /*
 779  * Special exception 6 handler.
 780  * The rdmsr instruction generates invalid opcodes fault on 486-class
 781  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
 782  * function identblue() when this handler is called.  Stacked eip should
 783  * be advanced.
 784  */
 785 inthand_t       bluetrap6;
 786
 787 __asm(
 788     "   .text                                                   \n"
 789     "   .p2align 2,0x90                                         \n"
 790     "   .type   " __XSTRING(CNAME(bluetrap6)) ",@function       \n"
 791     __XSTRING(CNAME(bluetrap6)) ":                              \n"
 792     "   ss                                                      \n"
 793     "   movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "    \n"
 794     "   addl    $2, (%esp)  # I know rdmsr is a 2-bytes instruction.    \n"
 795     "   iret                                                    \n"
 796 );
 797
 798 /*
 799  * Special exception 13 handler.
 800  * Accessing non-existent MSR generates general protection fault.
 801  */
 802 inthand_t       bluetrap13;
 803
 804 __asm(
 805     "   .text                                                   \n"
 806     "   .p2align 2,0x90                                         \n"
 807     "   .type " __XSTRING(CNAME(bluetrap13)) ",@function        \n"
 808     __XSTRING(CNAME(bluetrap13)) ":                             \n"
 809     "   ss                                                      \n"
 810     "   movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "    \n"
 811     "   popl    %eax                    # discard errorcode.    \n"
 812     "   addl    $2, (%esp) # I know rdmsr is a 2-bytes instruction.     \n"
 813     "   iret                                                    \n"
 814 );
 815
 816 /*
 817  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
 818  * support cpuid instruction.  This function should be called after
 819  * loading interrupt descriptor table register.
 820  *
 821  * I don't like this method that handles fault, but I couldn't get
 822  * information for any other methods.  Does blue giant know?
 823  */
 824 static int
 825 identblue(void)
 826 {
 827
 828         trap_by_rdmsr = 0;
 829
 830         /*
 831          * Cyrix 486-class CPU does not support rdmsr instruction.
 832          * The rdmsr instruction generates invalid opcode fault, and exception
 833          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
 834          * bluetrap6() set the magic number to trap_by_rdmsr.
 835          */
 836         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 837
 838         /*
 839          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
 840          * In this case, rdmsr generates general protection fault, and
 841          * exception will be trapped by bluetrap13().
 842          */
 843         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 844
 845         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
 846
 847         if (trap_by_rdmsr == 0xa8c1d)
 848                 return IDENTBLUE_CYRIX486;
 849         else if (trap_by_rdmsr == 0xa89c4)
 850                 return IDENTBLUE_CYRIXM2;
 851         return IDENTBLUE_IBMCPU;
 852 }
 853
 854
 855 /*
 856  * identifycyrix() set lower 16 bits of cyrix_did as follows:
 857  *
 858  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
 859  * +-------+-------+---------------+
 860  * |  SID  |  RID  |   Device ID   |
 861  * |    (DIR 1)    |    (DIR 0)    |
 862  * +-------+-------+---------------+
 863  */
 864 static void
 865 identifycyrix(void)
 866 {
 867         int     ccr2_test = 0, dir_test = 0;
 868         u_char  ccr2, ccr3;
 869
 870         mpintr_lock();
 871
 872         ccr2 = read_cyrix_reg(CCR2);
 873         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
 874         read_cyrix_reg(CCR2);
 875         if (read_cyrix_reg(CCR2) != ccr2)
 876                 ccr2_test = 1;
 877         write_cyrix_reg(CCR2, ccr2);
 878
 879         ccr3 = read_cyrix_reg(CCR3);
 880         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
 881         read_cyrix_reg(CCR3);
 882         if (read_cyrix_reg(CCR3) != ccr3)
 883                 dir_test = 1;                                   /* CPU supports DIRs. */
 884         write_cyrix_reg(CCR3, ccr3);
 885
 886         if (dir_test) {
 887                 /* Device ID registers are available. */
 888                 cyrix_did = read_cyrix_reg(DIR1) << 8;
 889                 cyrix_did += read_cyrix_reg(DIR0);
 890         } else if (ccr2_test)
 891                 cyrix_did = 0x0010;             /* 486S A-step */
 892         else
 893                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
 894
 895         mpintr_unlock();
 896 }
 897
 898 /*
 899  * Final stage of CPU identification. -- Should I check TI?
 900  */
 901 void
 902 finishidentcpu(void)
 903 {
 904         int     isblue = 0;
 905         u_char  ccr3;
 906         u_int   regs[4];
 907
 908         if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
 909                 if (cpu == CPU_486) {
 910                         /*
 911                          * These conditions are equivalent to:
 912                          *     - CPU does not support cpuid instruction.
 913                          *     - Cyrix/IBM CPU is detected.
 914                          */
 915                         isblue = identblue();
 916                         if (isblue == IDENTBLUE_IBMCPU) {
 917                                 strcpy(cpu_vendor, "IBM");
 918                                 cpu = CPU_BLUE;
 919                                 return;
 920                         }
 921                 }
 922                 switch (cpu_id & 0xf00) {
 923                 case 0x600:
 924                         /*
 925                          * Cyrix's datasheet does not describe DIRs.
 926                          * Therefor, I assume it does not have them
 927                          * and use the result of the cpuid instruction.
 928                          * XXX they seem to have it for now at least. -Peter
 929                          */
 930                         identifycyrix();
 931                         cpu = CPU_M2;
 932                         break;
 933                 default:
 934                         identifycyrix();
 935                         /*
 936                          * This routine contains a trick.
 937                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
 938                          */
 939                         switch (cyrix_did & 0x00f0) {
 940                         case 0x00:
 941                         case 0xf0:
 942                                 cpu = CPU_486DLC;
 943                                 break;
 944                         case 0x10:
 945                                 cpu = CPU_CY486DX;
 946                                 break;
 947                         case 0x20:
 948                                 if ((cyrix_did & 0x000f) < 8)
 949                                         cpu = CPU_M1;
 950                                 else
 951                                         cpu = CPU_M1SC;
 952                                 break;
 953                         case 0x30:
 954                                 cpu = CPU_M1;
 955                                 break;
 956                         case 0x40:
 957                                 /* MediaGX CPU */
 958                                 cpu = CPU_M1SC;
 959                                 break;
 960                         default:
 961                                 /* M2 and later CPUs are treated as M2. */
 962                                 cpu = CPU_M2;
 963
 964                                 /*
 965                                  * enable cpuid instruction.
 966                                  */
 967                                 ccr3 = read_cyrix_reg(CCR3);
 968                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
 969                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
 970                                 write_cyrix_reg(CCR3, ccr3);
 971
 972                                 do_cpuid(0, regs);
 973                                 cpu_high = regs[0];     /* eax */
 974                                 do_cpuid(1, regs);
 975                                 cpu_id = regs[0];       /* eax */
 976                                 cpu_feature = regs[3];  /* edx */
 977                                 break;
 978                         }
 979                 }
 980         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
 981                 /*
 982                  * There are BlueLightning CPUs that do not change
 983                  * undefined flags by dividing 5 by 2.  In this case,
 984                  * the CPU identification routine in locore.s leaves
 985                  * cpu_vendor null string and puts CPU_486 into the
 986                  * cpu.
 987                  */
 988                 isblue = identblue();
 989                 if (isblue == IDENTBLUE_IBMCPU) {
 990                         strcpy(cpu_vendor, "IBM");
 991                         cpu = CPU_BLUE;
 992                         return;
 993                 }
 994         }
 995 }
 996
 997 static void
 998 print_AMD_assoc(int i)
 999 {
1000         if (i == 255)
1001                 printf(", fully associative\n");
1002         else
1003                 printf(", %d-way associative\n", i);
1004 }
1005
1006 static void
1007 print_AMD_info(void)
1008 {
1009         quad_t amd_whcr;
1010
1011         if (cpu_exthigh >= 0x80000005) {
1012                 u_int regs[4];
1013
1014                 do_cpuid(0x80000005, regs);
1015                 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1016                 print_AMD_assoc(regs[1] >> 24);
1017                 printf("Instruction TLB: %d entries", regs[1] & 0xff);
1018                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1019                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1020                 printf(", %d bytes/line", regs[2] & 0xff);
1021                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1022                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1023                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1024                 printf(", %d bytes/line", regs[3] & 0xff);
1025                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1026                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1027                 if (cpu_exthigh >= 0x80000006) {        /* K6-III, or later */
1028                         do_cpuid(0x80000006, regs);
1029                         /*
1030                          * Report right L2 cache size on Duron rev. A0.
1031                          */
1032                         if ((cpu_id & 0xFF0) == 0x630)
1033                                 printf("L2 internal cache: 64 kbytes");
1034                         else
1035                                 printf("L2 internal cache: %d kbytes",
1036                                         regs[2] >> 16);
1037
1038                         printf(", %d bytes/line", regs[2] & 0xff);
1039                         printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1040                         print_AMD_assoc((regs[2] >> 12) & 0x0f);
1041                 }
1042         }
1043         if (((cpu_id & 0xf00) == 0x500)
1044             && (((cpu_id & 0x0f0) > 0x80)
1045                 || (((cpu_id & 0x0f0) == 0x80)
1046                     && (cpu_id & 0x00f) > 0x07))) {
1047                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1048                 amd_whcr = rdmsr(0xc0000082);
1049                 if (!(amd_whcr & (0x3ff << 22))) {
1050                         printf("Write Allocate Disable\n");
1051                 } else {
1052                         printf("Write Allocate Enable Limit: %dM bytes\n",
1053                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1054                         printf("Write Allocate 15-16M bytes: %s\n",
1055                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1056                 }
1057         } else if (((cpu_id & 0xf00) == 0x500)
1058                    && ((cpu_id & 0x0f0) > 0x50)) {
1059                 /* K6, K6-2(old core) */
1060                 amd_whcr = rdmsr(0xc0000082);
1061                 if (!(amd_whcr & (0x7f << 1))) {
1062                         printf("Write Allocate Disable\n");
1063                 } else {
1064                         printf("Write Allocate Enable Limit: %dM bytes\n",
1065                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1066                         printf("Write Allocate 15-16M bytes: %s\n",
1067                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1068                         printf("Hardware Write Allocate Control: %s\n",
1069                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1070                 }
1071         }
1072 }
1073
1074 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1075 static void
1076 print_AMD_features(void)
1077 {
1078         u_int regs[4];
1079
1080         /*
1081          * Values taken from AMD Processor Recognition
1082          * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1083          */
1084         do_cpuid(0x80000001, regs);
1085         printf("\n  AMD Features=0x%b", regs[3] &~ cpu_feature,
1086                 "\020"          /* in hex */
1087                 "\001FPU"       /* Integral FPU */
1088                 "\002VME"       /* Extended VM86 mode support */
1089                 "\003DE"        /* Debug extensions */
1090                 "\004PSE"       /* 4MByte page tables */
1091                 "\005TSC"       /* Timestamp counter */
1092                 "\006MSR"       /* Machine specific registers */
1093                 "\007PAE"       /* Physical address extension */
1094                 "\010MCE"       /* Machine Check support */
1095                 "\011CX8"       /* CMPEXCH8 instruction */
1096                 "\012APIC"      /* SMP local APIC */
1097                 "\013<b10>"
1098                 "\014SYSCALL"   /* SYSENTER/SYSEXIT instructions */
1099                 "\015MTRR"      /* Memory Type Range Registers */
1100                 "\016PGE"       /* PG_G (global bit) support */
1101                 "\017MCA"       /* Machine Check Architecture */
1102                 "\020ICMOV"     /* CMOV instruction */
1103                 "\021PAT"       /* Page attributes table */
1104                 "\022PGE36"     /* 36 bit address space support */
1105                 "\023RSVD"      /* Reserved, unknown */
1106                 "\024MP"        /* Multiprocessor Capable */
1107                 "\025<b20>"
1108                 "\026<b21>"
1109                 "\027AMIE"      /* AMD MMX Instruction Extensions */
1110                 "\030MMX"
1111                 "\031FXSAVE"    /* FXSAVE/FXRSTOR */
1112                 "\032<b25>"
1113                 "\033<b26>"
1114                 "\034<b27>"
1115                 "\035<b28>"
1116                 "\036<b29>"
1117                 "\037DSP"       /* AMD 3DNow! Instruction Extensions */
1118                 "\0403DNow!"
1119                 );
1120 }
1121 #endif
1122
1123 /*
1124  * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1125  */
1126
1127 #define MSR_TMx86_LONGRUN               0x80868010
1128 #define MSR_TMx86_LONGRUN_FLAGS         0x80868011
1129
1130 #define LONGRUN_MODE_MASK(x)            ((x) & 0x000000007f)
1131 #define LONGRUN_MODE_RESERVED(x)        ((x) & 0xffffff80)
1132 #define LONGRUN_MODE_WRITE(x, y)        (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1133
1134 #define LONGRUN_MODE_MINFREQUENCY       0x00
1135 #define LONGRUN_MODE_ECONOMY            0x01
1136 #define LONGRUN_MODE_PERFORMANCE        0x02
1137 #define LONGRUN_MODE_MAXFREQUENCY       0x03
1138 #define LONGRUN_MODE_UNKNOWN            0x04
1139 #define LONGRUN_MODE_MAX                0x04
1140
1141 union msrinfo {
1142         u_int64_t       msr;
1143         u_int32_t       regs[2];
1144 };
1145
1146 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1147         /*  MSR low, MSR high, flags bit0 */
1148         {         0,      0,            0},     /* LONGRUN_MODE_MINFREQUENCY */
1149         {         0,    100,            0},     /* LONGRUN_MODE_ECONOMY */
1150         {         0,    100,            1},     /* LONGRUN_MODE_PERFORMANCE */
1151         {       100,    100,            1},     /* LONGRUN_MODE_MAXFREQUENCY */
1152 };
1153
1154 static u_int
1155 tmx86_get_longrun_mode(void)
1156 {
1157         union msrinfo   msrinfo;
1158         u_int           low, high, flags, mode;
1159
1160         mpintr_lock();
1161
1162         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1163         low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1164         high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1165         flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1166
1167         for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1168                 if (low   == longrun_modes[mode][0] &&
1169                     high  == longrun_modes[mode][1] &&
1170                     flags == longrun_modes[mode][2]) {
1171                         goto out;
1172                 }
1173         }
1174         mode = LONGRUN_MODE_UNKNOWN;
1175 out:
1176         mpintr_unlock();
1177         return (mode);
1178 }
1179
1180 static u_int
1181 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1182 {
1183         u_int           regs[4];
1184
1185         mpintr_lock();
1186
1187         do_cpuid(0x80860007, regs);
1188         *frequency = regs[0];
1189         *voltage = regs[1];
1190         *percentage = regs[2];
1191
1192         mpintr_unlock();
1193         return (1);
1194 }
1195
1196 static u_int
1197 tmx86_set_longrun_mode(u_int mode)
1198 {
1199         union msrinfo   msrinfo;
1200
1201         if (mode >= LONGRUN_MODE_UNKNOWN) {
1202                 return (0);
1203         }
1204
1205         mpintr_lock();
1206
1207         /* Write LongRun mode values to Model Specific Register. */
1208         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1209         msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1210                                              longrun_modes[mode][0]);
1211         msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1212                                              longrun_modes[mode][1]);
1213         wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1214
1215         /* Write LongRun mode flags to Model Specific Register. */
1216         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1217         msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1218         wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1219
1220         mpintr_unlock();
1221         return (1);
1222 }
1223
1224 static u_int                     crusoe_longrun;
1225 static u_int                     crusoe_frequency;
1226 static u_int                     crusoe_voltage;
1227 static u_int                     crusoe_percentage;
1228 static struct sysctl_ctx_list    crusoe_sysctl_ctx;
1229 static struct sysctl_oid        *crusoe_sysctl_tree;
1230
1231 static int
1232 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1233 {
1234         u_int   mode;
1235         int     error;
1236
1237         crusoe_longrun = tmx86_get_longrun_mode();
1238         mode = crusoe_longrun;
1239         error = sysctl_handle_int(oidp, &mode, 0, req);
1240         if (error || !req->newptr) {
1241                 return (error);
1242         }
1243         if (mode >= LONGRUN_MODE_UNKNOWN) {
1244                 error = EINVAL;
1245                 return (error);
1246         }
1247         if (crusoe_longrun != mode) {
1248                 crusoe_longrun = mode;
1249                 tmx86_set_longrun_mode(crusoe_longrun);
1250         }
1251
1252         return (error);
1253 }
1254
1255 static int
1256 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1257 {
1258         u_int   val;
1259         int     error;
1260
1261         tmx86_get_longrun_status(&crusoe_frequency,
1262                                  &crusoe_voltage, &crusoe_percentage);
1263         val = *(u_int *)oidp->oid_arg1;
1264         error = sysctl_handle_int(oidp, &val, 0, req);
1265         return (error);
1266 }
1267
1268 static void
1269 setup_tmx86_longrun(void)
1270 {
1271         static int      done = 0;
1272
1273         if (done)
1274                 return;
1275         done++;
1276
1277         sysctl_ctx_init(&crusoe_sysctl_ctx);
1278         crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1279                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1280                                 "crusoe", CTLFLAG_RD, 0,
1281                                 "Transmeta Crusoe LongRun support");
1282         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1283                 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1284                 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1285                 "LongRun mode [0-3]");
1286         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1287                 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1288                 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1289                 "Current frequency (MHz)");
1290         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1291                 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1292                 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1293                 "Current voltage (mV)");
1294         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1295                 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1296                 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1297                 "Processing performance (%)");
1298 }
1299
1300 static void
1301 print_transmeta_info(void)
1302 {
1303         u_int regs[4], nreg = 0;
1304
1305         do_cpuid(0x80860000, regs);
1306         nreg = regs[0];
1307         if (nreg >= 0x80860001) {
1308                 do_cpuid(0x80860001, regs);
1309                 printf("  Processor revision %u.%u.%u.%u\n",
1310                        (regs[1] >> 24) & 0xff,
1311                        (regs[1] >> 16) & 0xff,
1312                        (regs[1] >> 8) & 0xff,
1313                        regs[1] & 0xff);
1314         }
1315         if (nreg >= 0x80860002) {
1316                 do_cpuid(0x80860002, regs);
1317                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1318                        (regs[1] >> 24) & 0xff,
1319                        (regs[1] >> 16) & 0xff,
1320                        (regs[1] >> 8) & 0xff,
1321                        regs[1] & 0xff,
1322                        regs[2]);
1323         }
1324         if (nreg >= 0x80860006) {
1325                 char info[65];
1326                 do_cpuid(0x80860003, (u_int*) &info[0]);
1327                 do_cpuid(0x80860004, (u_int*) &info[16]);
1328                 do_cpuid(0x80860005, (u_int*) &info[32]);
1329                 do_cpuid(0x80860006, (u_int*) &info[48]);
1330                 info[64] = 0;
1331                 printf("  %s\n", info);
1332         }
1333
1334         crusoe_longrun = tmx86_get_longrun_mode();
1335         tmx86_get_longrun_status(&crusoe_frequency,
1336                                  &crusoe_voltage, &crusoe_percentage);
1337         printf("  LongRun mode: %d  <%dMHz %dmV %d%%>\n", crusoe_longrun,
1338                crusoe_frequency, crusoe_voltage, crusoe_percentage);
1339 }
1340
1341 void
1342 additional_cpu_info(const char *line)
1343 {
1344         int i;
1345
1346         if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1347                 additional_cpu_info_ary[i] = line;
1348                 ++additional_cpu_info_count;
1349         }
1350 }
1351