sys/dev/netif/sr/if_sr.c

   1 /*
   2  * Copyright (c) 1996 - 2001 John Hay.
   3  * Copyright (c) 1996 SDL Communications, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the author nor the names of any co-contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
  31  */
  32
  33 /*
  34  * Programming assumptions and other issues.
  35  *
  36  * Only a 16K window will be used.
  37  *
  38  * The descriptors of a DMA channel will fit in a 16K memory window.
  39  *
  40  * The buffers of a transmit DMA channel will fit in a 16K memory window.
  41  *
  42  * When interface is going up, handshaking is set and it is only cleared
  43  * when the interface is down'ed.
  44  *
  45  * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
  46  * internal/external clock, etc.....
  47  *
  48  */
  49
  50 #include "opt_netgraph.h"
  51 #ifdef NETGRAPH
  52 #include "if_sr.h"
  53 #endif  /* NETGRAPH */
  54
  55 #include <sys/param.h>
  56 #include <sys/systm.h>
  57 #include <sys/kernel.h>
  58 #include <sys/malloc.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/sockio.h>
  61 #include <sys/socket.h>
  62 #include <sys/thread2.h>
  63 #include <sys/bus.h>
  64 #include <sys/rman.h>
  65
  66 #include <net/if.h>
  67 #include <net/ifq_var.h>
  68 #ifdef NETGRAPH
  69 #include <sys/syslog.h>
  70 #else /* NETGRAPH */
  71 #include <net/if_arp.h>
  72 #include <net/sppp/if_sppp.h>
  73
  74 #include <net/bpf.h>
  75 #endif  /* NETGRAPH */
  76
  77 #include <machine/md_var.h>
  78
  79 #include "../ic_layer/hd64570.h"
  80 #include "if_srregs.h"
  81
  82 #ifdef NETGRAPH
  83 #include <netgraph/ng_message.h>
  84 #include <netgraph/netgraph.h>
  85 #endif /* NETGRAPH */
  86 /* #define USE_MODEMCK */
  87
  88 #ifndef BUGGY
  89 #define BUGGY           0
  90 #endif
  91
  92 #ifndef NETGRAPH
  93 #define PPP_HEADER_LEN  4
  94 #endif /* NETGRAPH */
  95
  96 static int      next_sc_unit = 0;
  97 #ifndef NETGRAPH
  98 #ifdef USE_MODEMCK
  99 static int      sr_watcher = 0;
 100 #endif
 101 #endif /* NETGRAPH */
 102
 103 /*
 104  * Define the software interface for the card... There is one for
 105  * every channel (port).
 106  */
 107 struct sr_softc {
 108 #ifndef NETGRAPH
 109         struct  sppp ifsppp;    /* PPP service w/in system */
 110 #endif /* NETGRAPH */
 111         struct  sr_hardc *hc;   /* card-level information */
 112
 113         int     unit;           /* With regard to all sr devices */
 114         int     subunit;        /* With regard to this card */
 115
 116         struct  buf_block {
 117                 u_int   txdesc; /* DPRAM offset */
 118                 u_int   txstart;/* DPRAM offset */
 119                 u_int   txend;  /* DPRAM offset */
 120                 u_int   txtail; /* # of 1st free gran */
 121                 u_int   txmax;  /* # of free grans */
 122                 u_int   txeda;  /* err descr addr */
 123         } block[SR_TX_BLOCKS];
 124
 125         char    xmit_busy;      /* Transmitter is busy */
 126         char    txb_inuse;      /* # of tx grans in use */
 127         u_int   txb_new;        /* ndx to new buffer */
 128         u_int   txb_next_tx;    /* ndx to next gran rdy tx */
 129
 130         u_int   rxdesc;         /* DPRAM offset */
 131         u_int   rxstart;        /* DPRAM offset */
 132         u_int   rxend;          /* DPRAM offset */
 133         u_int   rxhind;         /* ndx to the hd of rx bufrs */
 134         u_int   rxmax;          /* # of avail grans */
 135
 136         u_int   clk_cfg;        /* Clock configuration */
 137
 138         int     scachan;        /* channel # on card */
 139 #ifdef NETGRAPH
 140         int     running;        /* something is attached so we are running */
 141         int     dcd;            /* do we have dcd? */
 142         /* ---netgraph bits --- */
 143         char            nodename[NG_NODESIZ]; /* store our node name */
 144         int             datahooks;      /* number of data hooks attached */
 145         node_p          node;           /* netgraph node */
 146         hook_p          hook;           /* data hook */
 147         hook_p          debug_hook;
 148         struct ifqueue  xmitq_hipri;    /* hi-priority transmit queue */
 149         struct ifqueue  xmitq;          /* transmit queue */
 150         int             flags;          /* state */
 151 #define SCF_RUNNING     0x01            /* board is active */
 152 #define SCF_OACTIVE     0x02            /* output is active */
 153         int             out_dog;        /* watchdog cycles output count-down */
 154         struct callout  sr_timer;       /* timeout(9) handle */
 155         u_long          inbytes, outbytes;      /* stats */
 156         u_long          lastinbytes, lastoutbytes; /* a second ago */
 157         u_long          inrate, outrate;        /* highest rate seen */
 158         u_long          inlast;         /* last input N secs ago */
 159         u_long          out_deficit;    /* output since last input */
 160         u_long          oerrors, ierrors[6];
 161         u_long          opackets, ipackets;
 162 #endif /* NETGRAPH */
 163 };
 164
 165 #ifdef NETGRAPH
 166 #define DOG_HOLDOFF     6       /* dog holds off for 6 secs */
 167 #define QUITE_A_WHILE   300     /* 5 MINUTES */
 168 #define LOTS_OF_PACKETS 100
 169 #endif /* NETGRAPH */
 170
 171 /*
 172  * Baud Rate table for Sync Mode.
 173  * Each entry consists of 3 elements:
 174  * Baud Rate (x100) , TMC, BR
 175  *
 176  * Baud Rate = FCLK / TMC / 2^BR
 177  * Baud table for Crystal freq. of 9.8304 Mhz
 178  */
 179 #ifdef N2_TEST_SPEED
 180 struct rate_line {
 181         int     target;         /* target rate/100 */
 182         int     tmc_reg;        /* TMC register value */
 183         int     br_reg;         /* BR (BaudRateClk) selector */
 184 } n2_rates[] = {
 185         /* Baudx100     TMC             BR */
 186         { 3,            128,            8 },
 187         { 6,            128,            7 },
 188         { 12,           128,            6 },
 189         { 24,           128,            5 },
 190         { 48,           128,            4 },
 191         { 96,           128,            3 },
 192         { 192,          128,            2 },
 193         { 384,          128,            1 },
 194         { 560,          88,             1 },
 195         { 640,          77,             1 },
 196         { 1280,         38,             1 },
 197         { 2560,         19,             1 },
 198         { 5120,         10,             1 },
 199         { 10000,        5,              1 },
 200         { 15000,        3,              1 },
 201         { 25000,        2,              1 },
 202         { 50000,        1,              1 },
 203         { 0,            0,              0 }
 204 };
 205
 206 int     sr_test_speed[] = {
 207         N2_TEST_SPEED,
 208         N2_TEST_SPEED
 209 };
 210
 211 int     etc0vals[] = {
 212         SR_MCR_ETC0,            /* ISA channel 0 */
 213         SR_MCR_ETC1,            /* ISA channel 1 */
 214         SR_FECR_ETC0,           /* PCI channel 0 */
 215         SR_FECR_ETC1            /* PCI channel 1 */
 216 };
 217 #endif
 218
 219 devclass_t sr_devclass;
 220 #ifndef NETGRAPH
 221 DECLARE_DUMMY_MODULE(if_sr);
 222 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
 223 #else
 224 MODULE_DEPEND(ng_sync_sr, netgraph, NG_ABI_VERSION, NG_ABI_VERSION, NG_ABI_VERSION);
 225 #endif
 226
 227 static void     srintr(void *arg);
 228 static void     sr_xmit(struct sr_softc *sc);
 229 #ifndef NETGRAPH
 230 static void     srstart(struct ifnet *ifp, struct ifaltq_subque *);
 231 static int      srioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
 232                         struct ucred *);
 233 static void     srwatchdog(struct ifnet *ifp);
 234 #else
 235 static void     srstart(struct sr_softc *sc);
 236 static void     srwatchdog(struct sr_softc *sc);
 237 #endif /* NETGRAPH */
 238 static int      sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
 239 static void     sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
 240 static void     sr_eat_packet(struct sr_softc *sc, int single);
 241 static void     sr_get_packets(struct sr_softc *sc);
 242
 243 static void     sr_up(struct sr_softc *sc);
 244 static void     sr_down(struct sr_softc *sc);
 245 static void     src_init(struct sr_hardc *hc);
 246 static void     sr_init_sca(struct sr_hardc *hc);
 247 static void     sr_init_msci(struct sr_softc *sc);
 248 static void     sr_init_rx_dmac(struct sr_softc *sc);
 249 static void     sr_init_tx_dmac(struct sr_softc *sc);
 250 static void     sr_dmac_intr(struct sr_hardc *hc, u_char isr);
 251 static void     sr_msci_intr(struct sr_hardc *hc, u_char isr);
 252 static void     sr_timer_intr(struct sr_hardc *hc, u_char isr);
 253 #ifndef NETGRAPH
 254 #ifdef USE_MODEMCK
 255 static void     sr_modemck(void *x);
 256 #endif
 257 #else
 258 static void     sr_modemck(struct sr_softc *x);
 259 #endif /* NETGRAPH */
 260
 261 #ifdef NETGRAPH
 262 static  void    ngsr_watchdog_frame(void * arg);
 263 static  void    ngsr_init(void* ignored);
 264
 265 static ng_constructor_t ngsr_constructor;
 266 static ng_rcvmsg_t      ngsr_rcvmsg;
 267 static ng_shutdown_t    ngsr_rmnode;
 268 static ng_newhook_t     ngsr_newhook;
 269 /*static ng_findhook_t  ngsr_findhook; */
 270 static ng_connect_t     ngsr_connect;
 271 static ng_rcvdata_t     ngsr_rcvdata;
 272 static ng_disconnect_t  ngsr_disconnect;
 273
 274 static struct ng_type typestruct = {
 275         NG_VERSION,
 276         NG_SR_NODE_TYPE,
 277         NULL,
 278         ngsr_constructor,
 279         ngsr_rcvmsg,
 280         ngsr_rmnode,
 281         ngsr_newhook,
 282         NULL,
 283         ngsr_connect,
 284         ngsr_rcvdata,
 285         ngsr_rcvdata,
 286         ngsr_disconnect,
 287         NULL
 288 };
 289
 290 static int      ngsr_done_init = 0;
 291 #endif /* NETGRAPH */
 292
 293 /*
 294  * Register the ports on the adapter.
 295  * Fill in the info for each port.
 296 #ifndef NETGRAPH
 297  * Attach each port to sppp and bpf.
 298 #endif
 299  */
 300 int
 301 sr_attach(device_t device)
 302 {
 303         int intf_sw, pndx;
 304         u_int32_t flags;
 305         u_int fecr, *fecrp;
 306         struct sr_hardc *hc;
 307         struct sr_softc *sc;
 308 #ifndef NETGRAPH
 309         struct ifnet *ifp;
 310 #endif /* NETGRAPH */
 311         int unit;               /* index: channel w/in card */
 312
 313         hc = (struct sr_hardc *)device_get_softc(device);
 314         sc = kmalloc(hc->numports * sizeof(struct sr_softc), M_DEVBUF,
 315                      M_WAITOK | M_ZERO);
 316         hc->sc = sc;
 317
 318         /*
 319          * Get the TX clock direction and configuration. The default is a
 320          * single external clock which is used by RX and TX.
 321          */
 322         switch(hc->cardtype) {
 323         case SR_CRD_N2:
 324                 flags = device_get_flags(device);
 325 #ifdef N2_TEST_SPEED
 326                 if (sr_test_speed[0] > 0)
 327                         hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 328                 else
 329 #endif
 330                 if (flags & SR_FLAGS_0_CLK_MSK)
 331                         hc->sc[0].clk_cfg =
 332                             (flags & SR_FLAGS_0_CLK_MSK)
 333                             >> SR_FLAGS_CLK_SHFT;
 334
 335                 if (hc->numports == 2)
 336 #ifdef N2_TEST_SPEED
 337                         if (sr_test_speed[1] > 0)
 338                                 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 339                         else
 340 #endif
 341                         if (flags & SR_FLAGS_1_CLK_MSK)
 342                                 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
 343                                     >> (SR_FLAGS_CLK_SHFT +
 344                                     SR_FLAGS_CLK_CHAN_SHFT);
 345                 break;
 346         case SR_CRD_N2PCI:
 347                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
 348                 fecr = *fecrp;
 349                 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
 350                         switch (pndx) {
 351                         case 1:
 352                                 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
 353                                 break;
 354                         case 0:
 355                         default:
 356                                 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
 357                         }
 358
 359 #ifdef N2_TEST_SPEED
 360                         if (sr_test_speed[pndx] > 0)
 361                                 sc->clk_cfg = SR_FLAGS_INT_CLK;
 362                         else
 363 #endif
 364                                 switch (intf_sw) {
 365                                 default:
 366                                 case SR_FE_ID_RS232:
 367                                 case SR_FE_ID_HSSI:
 368                                 case SR_FE_ID_RS422:
 369                                 case SR_FE_ID_TEST:
 370                                         break;
 371
 372                                 case SR_FE_ID_V35:
 373                                         sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
 374                                         break;
 375
 376                                 case SR_FE_ID_X21:
 377                                         sc->clk_cfg = SR_FLAGS_EXT_CLK;
 378                                         break;
 379                                 }
 380                 }
 381                 sc = hc->sc;
 382                 break;
 383         }
 384
 385         /*
 386          * Report Card configuration information before we start configuring
 387          * each channel on the card...
 388          */
 389         kprintf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
 390                hc->cunit, hc->memsize / 1024, hc->mempages,
 391                (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
 392
 393         src_init(hc);
 394         sr_init_sca(hc);
 395
 396         if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
 397                            0, srintr, hc,
 398                            &hc->intr_cookie, NULL, NULL) != 0)
 399                 goto errexit;
 400
 401         /*
 402          * Now configure each port on the card.
 403          */
 404         for (unit = 0; unit < hc->numports; sc++, unit++) {
 405                 sc->hc = hc;
 406                 sc->subunit = unit;
 407                 sc->unit = next_sc_unit;
 408                 next_sc_unit++;
 409                 sc->scachan = unit % NCHAN;
 410
 411                 sr_init_rx_dmac(sc);
 412                 sr_init_tx_dmac(sc);
 413                 sr_init_msci(sc);
 414
 415                 kprintf("sr%d: Adapter %d, port %d.\n",
 416                        sc->unit, hc->cunit, sc->subunit);
 417
 418 #ifndef NETGRAPH
 419                 ifp = &sc->ifsppp.pp_if;
 420                 ifp->if_softc = sc;
 421                 if_initname(ifp, "sr", sc->unit);
 422                 ifp->if_mtu = PP_MTU;
 423                 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
 424                 ifp->if_ioctl = srioctl;
 425                 ifp->if_start = srstart;
 426                 ifp->if_watchdog = srwatchdog;
 427
 428                 sc->ifsppp.pp_flags = PP_KEEPALIVE;
 429                 sppp_attach((struct ifnet *)&sc->ifsppp);
 430                 if_attach(ifp, NULL);
 431
 432                 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
 433 #else   /* NETGRAPH */
 434                 /*
 435                  * we have found a node, make sure our 'type' is availabe.
 436                  */
 437                 if (ngsr_done_init == 0) ngsr_init(NULL);
 438                 if (ng_make_node_common(&typestruct, &sc->node) != 0)
 439                         goto errexit;
 440                 sc->node->private = sc;
 441                 callout_init(&sc->sr_timer);
 442                 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
 443                 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
 444                 ksprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
 445                 if (ng_name_node(sc->node, sc->nodename)) {
 446                         ng_rmnode(sc->node);
 447                         ng_unref(sc->node);
 448                         return (0);
 449                 }
 450                 sc->running = 0;
 451 #endif  /* NETGRAPH */
 452         }
 453
 454         return (0);
 455
 456 errexit:
 457         sr_deallocate_resources(device);
 458         return (ENXIO);
 459 }
 460
 461 int
 462 sr_detach(device_t device)
 463 {
 464         device_t parent = device_get_parent(device);
 465         struct sr_hardc *hc = device_get_softc(device);
 466
 467         if (hc->intr_cookie != NULL) {
 468                 if (BUS_TEARDOWN_INTR(parent, device,
 469                         hc->res_irq, hc->intr_cookie) != 0) {
 470                                 kprintf("intr teardown failed.. continuing\n");
 471                 }
 472                 hc->intr_cookie = NULL;
 473         }
 474
 475         /* XXX Stop the DMA. */
 476
 477         /*
 478          * deallocate any system resources we may have
 479          * allocated on behalf of this driver.
 480          */
 481         kfree(hc->sc, M_DEVBUF);
 482         hc->sc = NULL;
 483         hc->mem_start = NULL;
 484         return (sr_deallocate_resources(device));
 485 }
 486
 487 int
 488 sr_allocate_irq(device_t device, int rid, u_long size)
 489 {
 490         struct sr_hardc *hc = device_get_softc(device);
 491
 492         hc->rid_irq = rid;
 493         hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
 494             &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
 495         if (hc->res_irq == NULL) {
 496                 goto errexit;
 497         }
 498         return (0);
 499
 500 errexit:
 501         sr_deallocate_resources(device);
 502         return (ENXIO);
 503 }
 504
 505 int
 506 sr_allocate_memory(device_t device, int rid, u_long size)
 507 {
 508         struct sr_hardc *hc = device_get_softc(device);
 509
 510         hc->rid_memory = rid;
 511         hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 512                         &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
 513         if (hc->res_memory == NULL) {
 514                 goto errexit;
 515         }
 516         return (0);
 517
 518 errexit:
 519         sr_deallocate_resources(device);
 520         return (ENXIO);
 521 }
 522
 523 int
 524 sr_allocate_plx_memory(device_t device, int rid, u_long size)
 525 {
 526         struct sr_hardc *hc = device_get_softc(device);
 527
 528         hc->rid_plx_memory = rid;
 529         hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 530                         &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
 531         if (hc->res_plx_memory == NULL) {
 532                 goto errexit;
 533         }
 534         return (0);
 535
 536 errexit:
 537         sr_deallocate_resources(device);
 538         return (ENXIO);
 539 }
 540
 541 int
 542 sr_deallocate_resources(device_t device)
 543 {
 544         struct sr_hardc *hc = device_get_softc(device);
 545
 546         if (hc->res_irq != 0) {
 547                 bus_deactivate_resource(device, SYS_RES_IRQ,
 548                         hc->rid_irq, hc->res_irq);
 549                 bus_release_resource(device, SYS_RES_IRQ,
 550                         hc->rid_irq, hc->res_irq);
 551                 hc->res_irq = 0;
 552         }
 553         if (hc->res_memory != 0) {
 554                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 555                         hc->rid_memory, hc->res_memory);
 556                 bus_release_resource(device, SYS_RES_MEMORY,
 557                         hc->rid_memory, hc->res_memory);
 558                 hc->res_memory = 0;
 559         }
 560         if (hc->res_plx_memory != 0) {
 561                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 562                         hc->rid_plx_memory, hc->res_plx_memory);
 563                 bus_release_resource(device, SYS_RES_MEMORY,
 564                         hc->rid_plx_memory, hc->res_plx_memory);
 565                 hc->res_plx_memory = 0;
 566         }
 567         return (0);
 568 }
 569
 570 /*
 571  * N2 Interrupt Service Routine
 572  *
 573  * First figure out which SCA gave the interrupt.
 574  * Process it.
 575  * See if there is other interrupts pending.
 576  * Repeat until there no interrupts remain.
 577  */
 578 static void
 579 srintr(void *arg)
 580 {
 581         struct sr_hardc *hc = (struct sr_hardc *)arg;
 582         sca_regs *sca = hc->sca;        /* MSCI register tree */
 583         u_char  isr0, isr1, isr2;       /* interrupt statii captured */
 584
 585 #if BUGGY > 1
 586         kprintf("sr: srintr_hc(hc=%08x)\n", hc);
 587 #endif
 588
 589         /*
 590          * Since multiple interfaces may share this interrupt, we must loop
 591          * until no interrupts are still pending service.
 592          */
 593         while (1) {
 594                 /*
 595                  * Read all three interrupt status registers from the N2
 596                  * card...
 597                  */
 598                 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
 599                 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
 600                 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
 601
 602                 /*
 603                  * If all three registers returned 0, we've finished
 604                  * processing interrupts from this device, so we can quit
 605                  * this loop...
 606                  */
 607                 if ((isr0 | isr1 | isr2) == 0)
 608                         break;
 609
 610 #if BUGGY > 2
 611                 kprintf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
 612 #ifndef NETGRAPH
 613                         unit, isr0, isr1, isr2);
 614 #else
 615                         hc->cunit, isr0, isr1, isr2);
 616 #endif /* NETGRAPH */
 617 #endif
 618
 619                 /*
 620                  * Now we can dispatch the interrupts. Since we don't expect
 621                  * either MSCI or timer interrupts, we'll test for DMA
 622                  * interrupts first...
 623                  */
 624                 if (isr1)       /* DMA-initiated interrupt */
 625                         sr_dmac_intr(hc, isr1);
 626
 627                 if (isr0)       /* serial part IRQ? */
 628                         sr_msci_intr(hc, isr0);
 629
 630                 if (isr2)       /* timer-initiated interrupt */
 631                         sr_timer_intr(hc, isr2);
 632         }
 633 }
 634
 635 /*
 636  * This will only start the transmitter. It is assumed that the data
 637  * is already there.
 638  * It is normally called from srstart() or sr_dmac_intr().
 639  */
 640 static void
 641 sr_xmit(struct sr_softc *sc)
 642 {
 643         u_short cda_value;      /* starting descriptor */
 644         u_short eda_value;      /* ending descriptor */
 645         struct sr_hardc *hc;
 646 #ifndef NETGRAPH
 647         struct ifnet *ifp;      /* O/S Network Services */
 648 #endif /* NETGRAPH */
 649         dmac_channel *dmac;     /* DMA channel registers */
 650
 651 #if BUGGY > 0
 652         kprintf("sr: sr_xmit( sc=%08x)\n", sc);
 653 #endif
 654
 655         hc = sc->hc;
 656 #ifndef NETGRAPH
 657         ifp = &sc->ifsppp.pp_if;
 658 #endif /* NETGRAPH */
 659         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
 660
 661         /*
 662          * Get the starting and ending addresses of the chain to be
 663          * transmitted and pass these on to the DMA engine on-chip.
 664          */
 665         cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
 666         cda_value &= 0x00ffff;
 667         eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
 668         eda_value &= 0x00ffff;
 669
 670         SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
 671         SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
 672
 673         /*
 674          * Now we'll let the DMA status register know about this change
 675          */
 676         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
 677
 678         sc->xmit_busy = 1;      /* mark transmitter busy */
 679
 680 #if BUGGY > 2
 681         kprintf("sr%d: XMIT  cda=%04x, eda=%4x, rcda=%08lx\n",
 682                sc->unit, cda_value, eda_value,
 683                sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
 684 #endif
 685
 686         sc->txb_next_tx++;      /* update next transmit seq# */
 687
 688         if (sc->txb_next_tx == SR_TX_BLOCKS)    /* handle wrap... */
 689                 sc->txb_next_tx = 0;
 690
 691 #ifndef NETGRAPH
 692         /*
 693          * Finally, we'll set a timout (which will start srwatchdog())
 694          * within the O/S network services layer...
 695          */
 696         ifp->if_timer = 2;      /* Value in seconds. */
 697 #else
 698         /*
 699          * Don't time out for a while.
 700          */
 701         sc->out_dog = DOG_HOLDOFF;      /* give ourself some breathing space*/
 702 #endif /* NETGRAPH */
 703 }
 704
 705 /*
 706  * This function will be called from the upper level when a user add a
 707  * packet to be send, and from the interrupt handler after a finished
 708  * transmit.
 709  *
 710  * This function only place the data in the oncard buffers. It does not
 711  * start the transmition. sr_xmit() does that.
 712  *
 713  * Transmitter idle state is indicated by the OACTIVE flag.
 714  * The function that clears that should ensure that the transmitter
 715  * and its DMA is in a "good" idle state.
 716  */
 717 #ifndef NETGRAPH
 718 static void
 719 srstart(struct ifnet *ifp, struct ifaltq_subque *ifsq)
 720 {
 721         struct sr_softc *sc;    /* channel control structure */
 722 #else
 723 static void
 724 srstart(struct sr_softc *sc)
 725 {
 726 #endif /* NETGRAPH */
 727         struct sr_hardc *hc;    /* card control/config block */
 728         int len;                /* total length of a packet */
 729         int pkts;               /* packets placed in DPRAM */
 730         int tlen;               /* working length of pkt */
 731         u_int i;
 732         struct mbuf *mtx;       /* message buffer from O/S */
 733         u_char *txdata;         /* buffer address in DPRAM */
 734         sca_descriptor *txdesc; /* working descriptor pointr */
 735         struct buf_block *blkp;
 736
 737 #ifndef NETGRAPH
 738 #if BUGGY > 0
 739         kprintf("sr: srstart( ifp=%08x)\n", ifp);
 740 #endif
 741         sc = ifp->if_softc;
 742         if ((ifp->if_flags & IFF_RUNNING) == 0)
 743                 return;
 744 #endif /* NETGRAPH */
 745         hc = sc->hc;
 746         /*
 747          * It is OK to set the memory window outside the loop because all tx
 748          * buffers and descriptors are assumed to be in the same 16K window.
 749          */
 750
 751         /*
 752          * Loop to place packets into DPRAM.
 753          *
 754          * We stay in this loop until there is nothing in
 755          * the TX queue left or the tx buffers are full.
 756          */
 757 top_srstart:
 758
 759         /*
 760          * See if we have space for more packets.
 761          */
 762         if (sc->txb_inuse == SR_TX_BLOCKS) {    /* out of space? */
 763 #ifndef NETGRAPH
 764                 ifq_set_oactive(&ifp->if_snd);  /* yes, mark active */
 765 #else
 766                 /*ifq_set_oactive(&ifp->if_snd);*/      /* yes, mark active */
 767 #endif /* NETGRAPH */
 768
 769 #if BUGGY > 9
 770                 kprintf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
 771                        sc->unit, sc->txb_inuse);
 772 #endif
 773                 return;
 774         }
 775         /*
 776          * OK, the card can take more traffic.  Let's see if there's any
 777          * pending from the system...
 778          *
 779          * NOTE:
 780          * The architecture of the networking interface doesn't
 781          * actually call us like 'write()', providing an address.  We get
 782          * started, a lot like a disk strategy routine, and we actually call
 783          * back out to the system to get traffic to send...
 784          *
 785          * NOTE:
 786          * If we were gonna run through another layer, we would use a
 787          * dispatch table to select the service we're getting a packet
 788          * from...
 789          */
 790 #ifndef NETGRAPH
 791         mtx = sppp_dequeue(ifp);
 792 #else /* NETGRAPH */
 793         IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 794         if (mtx == NULL) {
 795                 IF_DEQUEUE(&sc->xmitq, mtx);
 796         }
 797 #endif /* NETGRAPH */
 798         if (!mtx) {
 799                 return;
 800         }
 801         /*
 802          * OK, we got a packet from the network services of the O/S. Now we
 803          * can move it into the DPRAM (under control of the descriptors) and
 804          * fire it off...
 805          */
 806         pkts = 0;
 807         i = 0;                  /* counts # of granules used */
 808
 809         blkp = &sc->block[sc->txb_new]; /* address of free granule */
 810         txdesc = (sca_descriptor *)
 811             (hc->mem_start + (blkp->txdesc & hc->winmsk));
 812
 813         txdata = (u_char *)(hc->mem_start
 814                             + (blkp->txstart & hc->winmsk));
 815
 816         /*
 817          * Now we'll try to install as many packets as possible into the
 818          * card's DP RAM buffers.
 819          */
 820         for (;;) {              /* perform actual copy of packet */
 821                 len = mtx->m_pkthdr.len;        /* length of message */
 822
 823 #if BUGGY > 1
 824                 kprintf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
 825                            sc->unit, mtx, len);
 826 #endif
 827
 828 #ifndef NETGRAPH
 829                 BPF_MTAP(ifp, mtx);
 830 #else   /* NETGRAPH */
 831                 sc->outbytes += len;
 832 #endif  /* NETGRAPH */
 833
 834                 /*
 835                  * We can perform a straight copy because the tranmit
 836                  * buffers won't wrap.
 837                  */
 838                 m_copydata(mtx, 0, len, txdata);
 839
 840                 /*
 841                  * Now we know how big the message is gonna be.  We must now
 842                  * construct the descriptors to drive this message out...
 843                  */
 844                 tlen = len;
 845                 while (tlen > SR_BUF_SIZ) {     /* loop for full granules */
 846                         txdesc->stat = 0;       /* reset bits */
 847                         txdesc->len = SR_BUF_SIZ;       /* size of granule */
 848                         tlen -= SR_BUF_SIZ;
 849
 850                         txdesc++;       /* move to next dscr */
 851                         txdata += SR_BUF_SIZ;   /* adjust data addr */
 852                         i++;
 853                 }
 854
 855                 /*
 856                  * This section handles the setting of the final piece of a
 857                  * message.
 858                  */
 859                 txdesc->stat = SCA_DESC_EOM;
 860                 txdesc->len = tlen;
 861                 pkts++;
 862
 863                 /*
 864                  * prepare for subsequent packets (if any)
 865                  */
 866                 txdesc++;
 867                 txdata += SR_BUF_SIZ;   /* next mem granule */
 868                 i++;            /* count of granules */
 869
 870                 /*
 871                  * OK, we've now placed the message into the DPRAM where it
 872                  * can be transmitted.  We'll now release the message memory
 873                  * and update the statistics...
 874                  */
 875                 m_freem(mtx);
 876 #ifndef NETGRAPH
 877                 IFNET_STAT_INC(&sc->ifsppp.pp_if, opackets, 1);
 878 #else   /* NETGRAPH */
 879                 sc->opackets++;
 880 #endif /* NETGRAPH */
 881
 882                 /*
 883                  * Check if we have space for another packet. XXX This is
 884                  * hardcoded.  A packet can't be larger than 3 buffers (3 x
 885                  * 512).
 886                  */
 887                 if ((i + 3) >= blkp->txmax) {   /* enough remains? */
 888 #if BUGGY > 9
 889                         kprintf("sr%d.srstart: i=%d (%d pkts); card full.\n",
 890                                sc->unit, i, pkts);
 891 #endif
 892                         break;
 893                 }
 894                 /*
 895                  * We'll pull the next message to be sent (if any)
 896                  */
 897 #ifndef NETGRAPH
 898                 mtx = sppp_dequeue(ifp);
 899 #else /* NETGRAPH */
 900                 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 901                 if (mtx == NULL) {
 902                         IF_DEQUEUE(&sc->xmitq, mtx);
 903                 }
 904 #endif /* NETGRAPH */
 905                 if (!mtx) {     /* no message?  We're done! */
 906 #if BUGGY > 9
 907                         kprintf("sr%d.srstart: pending=0, pkts=%d\n",
 908                                sc->unit, pkts);
 909 #endif
 910                         break;
 911                 }
 912         }
 913
 914         blkp->txtail = i;       /* record next free granule */
 915
 916         /*
 917          * Mark the last descriptor, so that the SCA know where to stop.
 918          */
 919         txdesc--;               /* back up to last descriptor in list */
 920         txdesc->stat |= SCA_DESC_EOT;   /* mark as end of list */
 921
 922         /*
 923          * Now we'll reset the transmit granule's descriptor address so we
 924          * can record this in the structure and fire it off w/ the DMA
 925          * processor of the serial chip...
 926          */
 927         txdesc = (sca_descriptor *)blkp->txdesc;
 928         blkp->txeda = (u_short)((u_int)&txdesc[i]);
 929
 930         sc->txb_inuse++;        /* update inuse status */
 931         sc->txb_new++;          /* new traffic wuz added */
 932
 933         if (sc->txb_new == SR_TX_BLOCKS)
 934                 sc->txb_new = 0;
 935
 936         /*
 937          * If the tranmitter wasn't marked as "busy" we will force it to be
 938          * started...
 939          */
 940         if (sc->xmit_busy == 0) {
 941                 sr_xmit(sc);
 942 #if BUGGY > 9
 943                 kprintf("sr%d.srstart: called sr_xmit()\n", sc->unit);
 944 #endif
 945         }
 946         goto top_srstart;
 947 }
 948
 949 #ifndef NETGRAPH
 950 /*
 951  * Handle ioctl's at the device level, though we *will* call up
 952  * a layer...
 953  */
 954 #if BUGGY > 2
 955 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
 956 #endif
 957
 958 static int
 959 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
 960 {
 961         int error, was_up, should_be_up;
 962         struct sr_softc *sc = ifp->if_softc;
 963
 964 #if BUGGY > 0
 965         kprintf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
 966                ifp->if_xname, ifp, cmd, data);
 967 #endif
 968
 969         was_up = ifp->if_flags & IFF_RUNNING;
 970
 971         error = sppp_ioctl(ifp, cmd, data);
 972
 973 #if BUGGY > 1
 974         kprintf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
 975               ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
 976 #endif
 977
 978         if (error)
 979                 return error;
 980
 981         if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
 982 #if BUGGY > 2
 983                 if (bug_splats[sc->unit]++ < 2) {
 984                         kprintf("sr(%d).if_addrheads = %08x\n",
 985                                sc->unit, ifp->if_addrheads);
 986                         kprintf("sr(%d).if_bpf = %08x\n",
 987                                sc->unit, ifp->if_bpf);
 988                         kprintf("sr(%d).if_init = %08x\n",
 989                                sc->unit, ifp->if_init);
 990                         kprintf("sr(%d).if_output = %08x\n",
 991                                sc->unit, ifp->if_output);
 992                         kprintf("sr(%d).if_start = %08x\n",
 993                                sc->unit, ifp->if_start);
 994                         kprintf("sr(%d).if_done = %08x\n",
 995                                sc->unit, ifp->if_done);
 996                         kprintf("sr(%d).if_ioctl = %08x\n",
 997                                sc->unit, ifp->if_ioctl);
 998                         kprintf("sr(%d).if_reset = %08x\n",
 999                                sc->unit, ifp->if_reset);
1000                         kprintf("sr(%d).if_watchdog = %08x\n",
1001                                sc->unit, ifp->if_watchdog);
1002                 }
1003 #endif
1004                 return 0;
1005         }
1006
1007         crit_enter();
1008
1009         should_be_up = ifp->if_flags & IFF_RUNNING;
1010
1011         if (!was_up && should_be_up) {
1012                 /*
1013                  * Interface should be up -- start it.
1014                  */
1015                 sr_up(sc);
1016                 srstart(ifp, ifq_get_subq_default(&ifp->if_snd));
1017
1018                 /*
1019                  * XXX Clear the IFF_UP flag so that the link will only go
1020                  * up after sppp lcp and ipcp negotiation.
1021                  */
1022                 /* ifp->if_flags &= ~IFF_UP; */
1023         } else if (was_up && !should_be_up) {
1024                 /*
1025                  * Interface should be down -- stop it.
1026                  */
1027                 sr_down(sc);
1028                 sppp_flush(ifp);
1029         }
1030
1031         crit_exit();
1032
1033         return 0;
1034 }
1035 #endif /* NETGRAPH */
1036
1037 /*
1038  * This is to catch lost tx interrupts.
1039  */
1040 static void
1041 #ifndef NETGRAPH
1042 srwatchdog(struct ifnet *ifp)
1043 #else
1044 srwatchdog(struct sr_softc *sc)
1045 #endif /* NETGRAPH */
1046 {
1047         int     got_st0, got_st1, got_st3, got_dsr;
1048 #ifndef NETGRAPH
1049         struct sr_softc *sc = ifp->if_softc;
1050 #endif /* NETGRAPH */
1051         struct sr_hardc *hc = sc->hc;
1052         msci_channel *msci = &hc->sca->msci[sc->scachan];
1053         dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1054
1055 #if BUGGY > 0
1056 #ifndef NETGRAPH
1057         kprintf("srwatchdog(unit=%d)\n", unit);
1058 #else
1059         kprintf("srwatchdog(unit=%d)\n", sc->unit);
1060 #endif /* NETGRAPH */
1061 #endif
1062
1063 #ifndef NETGRAPH
1064         if (!(ifp->if_flags & IFF_RUNNING))
1065                 return;
1066
1067         IFNET_STAT_INC(ifp, oerrors, 1);        /* update output error count */
1068 #else   /* NETGRAPH */
1069         sc->oerrors++;  /* update output error count */
1070 #endif /* NETGRAPH */
1071
1072         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1073         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1074         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1075         got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1076
1077 #ifndef NETGRAPH
1078 #if     0
1079         if (ifp->if_flags & IFF_DEBUG)
1080 #endif
1081                 kprintf("sr%d: transmit failed, "
1082 #else   /* NETGRAPH */
1083         kprintf("sr%d: transmit failed, "
1084 #endif /* NETGRAPH */
1085                        "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1086                        sc->unit,
1087                        got_st0, got_st1, got_st3, got_dsr);
1088
1089         if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1090                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1091                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1092                 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1093         }
1094         sc->xmit_busy = 0;
1095 #ifndef NETGRAPH
1096         ifq_clr_oactive(&ifp->if_snd);
1097 #else
1098         /*ifq_clr_oactive(&ifp->if_snd) */
1099 #endif /* NETGRAPH */
1100
1101         if (sc->txb_inuse && --sc->txb_inuse)
1102                 sr_xmit(sc);
1103
1104 #ifndef NETGRAPH
1105         srstart(ifp, ifq_get_subq_default(&ifp->if_snd));
1106                         /* restart transmitter */
1107 #else
1108         srstart(sc);    /* restart transmitter */
1109 #endif /* NETGRAPH */
1110 }
1111
1112 static void
1113 sr_up(struct sr_softc *sc)
1114 {
1115         u_int *fecrp;
1116         struct sr_hardc *hc = sc->hc;
1117         sca_regs *sca = hc->sca;
1118         msci_channel *msci = &sca->msci[sc->scachan];
1119
1120 #if BUGGY > 0
1121         kprintf("sr_up(sc=%08x)\n", sc);
1122 #endif
1123
1124         /*
1125          * Enable transmitter and receiver. Raise DTR and RTS. Enable
1126          * interrupts.
1127          *
1128          * XXX What about using AUTO mode in msci->md0 ???
1129          */
1130         SRC_PUT8(hc->sca_base, msci->ctl,
1131                  SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1132
1133         if (sc->scachan == 0)
1134                 switch (hc->cardtype) {
1135                 case SR_CRD_N2PCI:
1136                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1137                         *fecrp &= ~SR_FECR_DTR0;
1138                         break;
1139                 }
1140         else
1141                 switch (hc->cardtype) {
1142                 case SR_CRD_N2PCI:
1143                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1144                         *fecrp &= ~SR_FECR_DTR1;
1145                         break;
1146                 }
1147
1148         if (sc->scachan == 0) {
1149                 SRC_PUT8(hc->sca_base, sca->ier0,
1150                          SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1151                 SRC_PUT8(hc->sca_base, sca->ier1,
1152                          SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1153         } else {
1154                 SRC_PUT8(hc->sca_base, sca->ier0,
1155                          SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1156                 SRC_PUT8(hc->sca_base, sca->ier1,
1157                          SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1158         }
1159
1160         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1161         DELAY(1000);    /* XXX slow it down a bit. */
1162         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1163
1164 #ifndef NETGRAPH
1165 #ifdef USE_MODEMCK
1166         if (sr_watcher == 0)
1167                 sr_modemck(NULL);
1168 #endif
1169 #else   /* NETGRAPH */
1170         callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
1171         sc->running = 1;
1172 #endif /* NETGRAPH */
1173 }
1174
1175 static void
1176 sr_down(struct sr_softc *sc)
1177 {
1178         u_int *fecrp;
1179         struct sr_hardc *hc = sc->hc;
1180         sca_regs *sca = hc->sca;
1181         msci_channel *msci = &sca->msci[sc->scachan];
1182
1183 #if BUGGY > 0
1184         kprintf("sr_down(sc=%08x)\n", sc);
1185 #endif
1186 #ifdef NETGRAPH
1187         callout_stop(&sc->sr_timer);
1188         sc->running = 0;
1189 #endif /* NETGRAPH */
1190
1191         /*
1192          * Disable transmitter and receiver. Lower DTR and RTS. Disable
1193          * interrupts.
1194          */
1195         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1196         DELAY(1000);    /* XXX slow it down a bit. */
1197         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1198
1199         SRC_PUT8(hc->sca_base, msci->ctl,
1200                  SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1201
1202         if (sc->scachan == 0)
1203                 switch (hc->cardtype) {
1204                 case SR_CRD_N2PCI:
1205                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1206                         *fecrp |= SR_FECR_DTR0;
1207                         break;
1208                 }
1209         else
1210                 switch (hc->cardtype) {
1211                 case SR_CRD_N2PCI:
1212                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1213                         *fecrp |= SR_FECR_DTR1;
1214                         break;
1215                 }
1216
1217         if (sc->scachan == 0) {
1218                 SRC_PUT8(hc->sca_base, sca->ier0,
1219                          SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1220                 SRC_PUT8(hc->sca_base, sca->ier1,
1221                          SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1222         } else {
1223                 SRC_PUT8(hc->sca_base, sca->ier0,
1224                          SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1225                 SRC_PUT8(hc->sca_base, sca->ier1,
1226                          SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1227         }
1228 }
1229
1230 /*
1231  * Initialize the card, allocate memory for the sr_softc structures
1232  * and fill in the pointers.
1233  */
1234 static void
1235 src_init(struct sr_hardc *hc)
1236 {
1237         struct sr_softc *sc = hc->sc;
1238         int x;
1239         u_int chanmem;
1240         u_int bufmem;
1241         u_int next;
1242         u_int descneeded;
1243
1244 #if BUGGY > 0
1245         kprintf("src_init(hc=%08x)\n", hc);
1246 #endif
1247
1248         chanmem = hc->memsize / hc->numports;
1249         next = 0;
1250
1251         for (x = 0; x < hc->numports; x++, sc++) {
1252                 int blk;
1253
1254                 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1255                         sc->block[blk].txdesc = next;
1256                         bufmem = (16 * 1024) / SR_TX_BLOCKS;
1257                         descneeded = bufmem / SR_BUF_SIZ;
1258
1259                         sc->block[blk].txstart = sc->block[blk].txdesc
1260                             + ((((descneeded * sizeof(sca_descriptor))
1261                                  / SR_BUF_SIZ) + 1)
1262                                * SR_BUF_SIZ);
1263
1264                         sc->block[blk].txend = next + bufmem;
1265                         sc->block[blk].txmax =
1266                             (sc->block[blk].txend - sc->block[blk].txstart)
1267                             / SR_BUF_SIZ;
1268                         next += bufmem;
1269
1270 #if BUGGY > 2
1271                         kprintf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1272                                sc->unit, blk,
1273                                sc->block[blk].txdesc, sc->block[blk].txstart);
1274 #endif
1275                 }
1276
1277                 sc->rxdesc = next;
1278                 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1279                 descneeded = bufmem / SR_BUF_SIZ;
1280                 sc->rxstart = sc->rxdesc +
1281                     ((((descneeded * sizeof(sca_descriptor)) /
1282                        SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1283                 sc->rxend = next + bufmem;
1284                 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1285                 next += bufmem;
1286         }
1287 }
1288
1289 /*
1290  * The things done here are channel independent.
1291  *
1292  * Configure the sca waitstates.
1293  * Configure the global interrupt registers.
1294  * Enable master dma enable.
1295  */
1296 static void
1297 sr_init_sca(struct sr_hardc *hc)
1298 {
1299         sca_regs *sca = hc->sca;
1300
1301 #if BUGGY > 0
1302         kprintf("sr_init_sca(hc=%08x)\n", hc);
1303 #endif
1304
1305         /*
1306          * Do the wait registers. Set everything to 0 wait states.
1307          */
1308         SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1309         SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1310         SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1311         SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1312         SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1313
1314         /*
1315          * Configure the interrupt registers. Most are cleared until the
1316          * interface is configured.
1317          */
1318         SRC_PUT8(hc->sca_base, sca->ier0, 0x00);        /* MSCI interrupts. */
1319         SRC_PUT8(hc->sca_base, sca->ier1, 0x00);        /* DMAC interrupts */
1320         SRC_PUT8(hc->sca_base, sca->ier2, 0x00);        /* TIMER interrupts. */
1321         SRC_PUT8(hc->sca_base, sca->itcr, 0x00);        /* Use ivr and no intr
1322                                                          * ack */
1323         SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1324         SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1325
1326         /*
1327          * Configure the timers. XXX Later
1328          */
1329
1330         /*
1331          * Set the DMA channel priority to rotate between all four channels.
1332          *
1333          * Enable all dma channels.
1334          */
1335         SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1336         SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1337 }
1338
1339 /*
1340  * Configure the msci
1341  *
1342  * NOTE: The serial port configuration is hardcoded at the moment.
1343  */
1344 static void
1345 sr_init_msci(struct sr_softc *sc)
1346 {
1347         int portndx;            /* on-board port number */
1348         u_int *fecrp;           /* pointer for PCI's MCR i/o */
1349         struct sr_hardc *hc = sc->hc;
1350         msci_channel *msci = &hc->sca->msci[sc->scachan];
1351 #ifdef N2_TEST_SPEED
1352         int br_v;               /* contents for BR divisor */
1353         int etcndx;             /* index into ETC table */
1354         int fifo_v, gotspeed;   /* final tabled speed found */
1355         int tmc_v;              /* timer control register */
1356         int wanted;             /* speed (bitrate) wanted... */
1357         struct rate_line *rtp;
1358 #endif
1359
1360         portndx = sc->scachan;
1361
1362 #if BUGGY > 0
1363         kprintf("sr: sr_init_msci( sc=%08x)\n", sc);
1364 #endif
1365
1366         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1367         SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1368                  SCA_MD0_CRC_CCITT |
1369                  SCA_MD0_CRC_ENABLE |
1370                  SCA_MD0_MODE_HDLC);
1371         SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1372         SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1373
1374         /*
1375          * According to the manual I should give a reset after changing the
1376          * mode registers.
1377          */
1378         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1379         SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1380                  SCA_CTL_UDRNC |
1381                  SCA_CTL_RTS);
1382
1383         /*
1384          * XXX Later we will have to support different clock settings.
1385          */
1386         switch (sc->clk_cfg) {
1387         default:
1388 #if BUGGY > 0
1389                 kprintf("sr%: clk_cfg=%08x, selected default clock.\n",
1390                        portndx, sc->clk_cfg);
1391 #endif
1392                 /* FALLTHROUGH */
1393         case SR_FLAGS_EXT_CLK:
1394                 /*
1395                  * For now all interfaces are programmed to use the RX clock
1396                  * for the TX clock.
1397                  */
1398
1399 #if BUGGY > 0
1400                 kprintf("sr%d: External Clock Selected.\n", portndx);
1401 #endif
1402
1403                 SRC_PUT8(hc->sca_base, msci->rxs,
1404                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1405                 SRC_PUT8(hc->sca_base, msci->txs,
1406                          SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1407                 break;
1408
1409         case SR_FLAGS_EXT_SEP_CLK:
1410 #if BUGGY > 0
1411                 kprintf("sr%d: Split Clocking Selected.\n", portndx);
1412 #endif
1413
1414                 SRC_PUT8(hc->sca_base, msci->rxs,
1415                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1416                 SRC_PUT8(hc->sca_base, msci->txs,
1417                          SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1418                 break;
1419
1420         case SR_FLAGS_INT_CLK:
1421 #if BUGGY > 0
1422                 kprintf("sr%d: Internal Clocking selected.\n", portndx);
1423 #endif
1424
1425                 /*
1426                  * XXX I do need some code to set the baud rate here!
1427                  */
1428 #ifdef N2_TEST_SPEED
1429                 switch (hc->cardtype) {
1430                 case SR_CRD_N2PCI:
1431                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1432                         mcr_v = *fecrp;
1433                         etcndx = 2;
1434                         break;
1435                 }
1436
1437                 fifo_v = 0x10;  /* stolen from Linux version */
1438
1439                 /*
1440                  * search for appropriate speed in table, don't calc it:
1441                  */
1442                 wanted = sr_test_speed[portndx];
1443                 rtp = &n2_rates[0];     /* point to first table item */
1444
1445                 while ((rtp->target > 0)        /* search table for speed */
1446                        &&(rtp->target != wanted))
1447                         rtp++;
1448
1449                 /*
1450                  * We've searched the table for a matching speed.  If we've
1451                  * found the correct rate line, we'll get the pre-calc'd
1452                  * values for the TMC and baud rate divisor for subsequent
1453                  * use...
1454                  */
1455                 if (rtp->target > 0) {  /* use table-provided values */
1456                         gotspeed = wanted;
1457                         tmc_v = rtp->tmc_reg;
1458                         br_v = rtp->br_reg;
1459                 } else {        /* otherwise assume 1MBit comm rate */
1460                         gotspeed = 10000;
1461                         tmc_v = 5;
1462                         br_v = 1;
1463                 }
1464
1465                 /*
1466                  * Now we mask in the enable clock output for the MCR:
1467                  */
1468                 mcr_v |= etc0vals[etcndx + portndx];
1469
1470                 /*
1471                  * Now we'll program the registers with these speed- related
1472                  * contents...
1473                  */
1474                 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1475                 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1476                 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1477                 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1478
1479                 switch (hc->cardtype) {
1480                 case SR_CRD_N2PCI:
1481                         *fecrp = mcr_v;
1482                         break;
1483                 }
1484
1485 #if BUGGY > 0
1486                 if (wanted != gotspeed)
1487                         kprintf("sr%d: Speed wanted=%d, found=%d\n",
1488                                wanted, gotspeed);
1489
1490                 kprintf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1491                        portndx, gotspeed, tmc_v, br_v);
1492 #endif
1493 #else
1494                 SRC_PUT8(hc->sca_base, msci->rxs,
1495                          SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1496                 SRC_PUT8(hc->sca_base, msci->txs,
1497                          SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1498
1499                 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1500
1501                 if (portndx == 0)
1502                         switch (hc->cardtype) {
1503                         case SR_CRD_N2PCI:
1504                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1505                                 *fecrp |= SR_FECR_ETC0;
1506                                 break;
1507                         }
1508                 else
1509                         switch (hc->cardtype) {
1510                         case SR_CRD_N2PCI:
1511                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1512                                 *fecrp |= SR_FECR_ETC1;
1513                                 break;
1514                         }
1515 #endif
1516         }
1517
1518         /*
1519          * XXX Disable all interrupts for now. I think if you are using the
1520          * dmac you don't use these interrupts.
1521          */
1522         SRC_PUT8(hc->sca_base, msci->ie0, 0);
1523         SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1524         SRC_PUT8(hc->sca_base, msci->ie2, 0);
1525         SRC_PUT8(hc->sca_base, msci->fie, 0);
1526
1527         SRC_PUT8(hc->sca_base, msci->sa0, 0);
1528         SRC_PUT8(hc->sca_base, msci->sa1, 0);
1529
1530         SRC_PUT8(hc->sca_base, msci->idl, 0x7E);        /* set flags value */
1531
1532         SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1533         SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1534         SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1535 }
1536
1537 /*
1538  * Configure the rx dma controller.
1539  */
1540 static void
1541 sr_init_rx_dmac(struct sr_softc *sc)
1542 {
1543         struct sr_hardc *hc;
1544         dmac_channel *dmac;
1545         sca_descriptor *rxd;
1546         u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1547
1548 #if BUGGY > 0
1549         kprintf("sr_init_rx_dmac(sc=%08x)\n", sc);
1550 #endif
1551
1552         hc = sc->hc;
1553         dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1554
1555         /*
1556          * This phase initializes the contents of the descriptor table
1557          * needed to construct a circular buffer...
1558          */
1559         rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1560         rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1561
1562         for (rxbuf = sc->rxstart;
1563              rxbuf < sc->rxend;
1564              rxbuf += SR_BUF_SIZ, rxd++) {
1565                 /*
1566                  * construct the circular chain...
1567                  */
1568                 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1569                 rxd->cp = (u_short)(rxda & 0xffff);
1570
1571                 /*
1572                  * set the on-card buffer address...
1573                  */
1574                 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1575                 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1576
1577                 rxd->len = 0;   /* bytes resident w/in granule */
1578                 rxd->stat = 0xff;       /* The sca write here when finished */
1579         }
1580
1581         /*
1582          * heal the chain so that the last entry points to the first...
1583          */
1584         rxd--;
1585         rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1586
1587         /*
1588          * reset the reception handler's index...
1589          */
1590         sc->rxhind = 0;
1591
1592         /*
1593          * We'll now configure the receiver's DMA logic...
1594          */
1595         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA transfer */
1596         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1597
1598         /* XXX maybe also SCA_DMR_CNTE */
1599         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1600         SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1601
1602         cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1603         sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1604
1605         SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1606         SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1607
1608         rxd = (sca_descriptor *)sc->rxstart;
1609
1610         SRC_PUT16(hc->sca_base, dmac->eda,
1611                   (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1612
1613         SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1614
1615
1616         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);  /* Enable DMA */
1617 }
1618
1619 /*
1620  * Configure the TX DMA descriptors.
1621  * Initialize the needed values and chain the descriptors.
1622  */
1623 static void
1624 sr_init_tx_dmac(struct sr_softc *sc)
1625 {
1626         int blk;
1627         u_int txbuf, txda, txda_d;
1628         struct sr_hardc *hc;
1629         sca_descriptor *txd;
1630         dmac_channel *dmac;
1631         struct buf_block *blkp;
1632         u_int x;
1633         u_int sarb_v;
1634
1635 #if BUGGY > 0
1636         kprintf("sr_init_tx_dmac(sc=%08x)\n", sc);
1637 #endif
1638
1639         hc = sc->hc;
1640         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1641
1642         /*
1643          * Initialize the array of descriptors for transmission
1644          */
1645         for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1646                 blkp = &sc->block[blk];
1647                 txd = (sca_descriptor *)(hc->mem_start
1648                                          + (blkp->txdesc & hc->winmsk));
1649                 txda_d = (u_int) hc->mem_start
1650                     - (blkp->txdesc & ~hc->winmsk);
1651
1652                 x = 0;
1653                 txbuf = blkp->txstart;
1654                 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1655                         txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1656                         txd->cp = (u_short)(txda & 0xffff);
1657
1658                         txd->bp = (u_short)((txbuf + hc->mem_pstart)
1659                                             & 0xffff);
1660                         txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1661                                             & 0xff);
1662                         txd->len = 0;
1663                         txd->stat = 0;
1664                         x++;
1665                 }
1666
1667                 txd--;
1668                 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1669                                     & 0xffff);
1670
1671                 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1672         }
1673
1674         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA */
1675         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1676         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1677         SRC_PUT8(hc->sca_base, dmac->dir,
1678                  SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1679
1680         sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1681         sarb_v &= 0x00ff;
1682
1683         SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1684 }
1685
1686 /*
1687  * Look through the descriptors to see if there is a complete packet
1688  * available. Stop if we get to where the sca is busy.
1689  *
1690  * Return the length and status of the packet.
1691  * Return nonzero if there is a packet available.
1692  *
1693  * NOTE:
1694  * It seems that we get the interrupt a bit early. The updateing of
1695  * descriptor values is not always completed when this is called.
1696  */
1697 static int
1698 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1699 {
1700         int granules;   /* count of granules in pkt */
1701         int wki, wko;
1702         struct sr_hardc *hc;
1703         sca_descriptor *rxdesc; /* current descriptor */
1704         sca_descriptor *endp;   /* ending descriptor */
1705         sca_descriptor *cda;    /* starting descriptor */
1706
1707         hc = sc->hc;            /* get card's information */
1708
1709         /*
1710          * set up starting descriptor by pulling that info from the DMA half
1711          * of the HD chip...
1712          */
1713         wki = DMAC_RXCH(sc->scachan);
1714         wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1715
1716         cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1717
1718 #if BUGGY > 1
1719         kprintf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1720                wki, wko, cda);
1721 #endif
1722
1723         /*
1724          * open the appropriate memory window and set our expectations...
1725          */
1726         rxdesc = (sca_descriptor *)
1727             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1728         endp = rxdesc;
1729         rxdesc = &rxdesc[sc->rxhind];
1730         endp = &endp[sc->rxmax];
1731
1732         *len = 0;               /* reset result total length */
1733         granules = 0;           /* reset count of granules */
1734
1735         /*
1736          * This loop will scan descriptors, but it *will* puke up if we wrap
1737          * around to our starting point...
1738          */
1739         while (rxdesc != cda) {
1740                 *len += rxdesc->len;    /* increment result length */
1741                 granules++;
1742
1743                 /*
1744                  * If we hit a valid packet's completion we'll know we've
1745                  * got a live one, and that we can deliver the packet.
1746                  * Since we're only allowed to report a packet available,
1747                  * somebody else does that...
1748                  */
1749                 if (rxdesc->stat & SCA_DESC_EOM) {      /* End Of Message */
1750                         *rxstat = rxdesc->stat; /* return closing */
1751 #if BUGGY > 0
1752                         kprintf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1753                                sc->unit, *len, *rxstat, granules);
1754 #endif
1755                         return 1;       /* indicate success */
1756                 }
1757                 /*
1758                  * OK, this packet take up multiple granules.  Move on to
1759                  * the next descriptor so we can consider it...
1760                  */
1761                 rxdesc++;
1762
1763                 if (rxdesc == endp)     /* recognize & act on wrap point */
1764                         rxdesc = (sca_descriptor *)
1765                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1766         }
1767
1768         /*
1769          * Nothing found in the DPRAM.  Let the caller know...
1770          */
1771         *len = 0;
1772         *rxstat = 0;
1773
1774         return 0;
1775 }
1776
1777 /*
1778  * Copy a packet from the on card memory into a provided mbuf.
1779  * Take into account that buffers wrap and that a packet may
1780  * be larger than a buffer.
1781  */
1782 static void
1783 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1784 {
1785         struct sr_hardc *hc;
1786         sca_descriptor *rxdesc;
1787         u_int rxdata;
1788         u_int rxmax;
1789         u_int off = 0;
1790         u_int tlen;
1791
1792 #if BUGGY > 0
1793         kprintf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1794                m, sc, len);
1795 #endif
1796
1797         hc = sc->hc;
1798
1799         rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1800         rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1801
1802         rxdesc = (sca_descriptor *)
1803             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1804         rxdesc = &rxdesc[sc->rxhind];
1805
1806         /*
1807          * Using the count of bytes in the received packet, we decrement it
1808          * for each granule (controller by an SCA descriptor) to control the
1809          * looping...
1810          */
1811         while (len) {
1812                 /*
1813                  * tlen gets the length of *this* granule... ...which is
1814                  * then copied to the target buffer.
1815                  */
1816                 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1817
1818                 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1819                       mtod(m, caddr_t) +off,
1820                       tlen);
1821
1822                 off += tlen;
1823                 len -= tlen;
1824
1825                 /*
1826                  * now, return to the descriptor's window in DPRAM and reset
1827                  * the descriptor we've just suctioned...
1828                  */
1829
1830                 rxdesc->len = 0;
1831                 rxdesc->stat = 0xff;
1832
1833                 /*
1834                  * Move on to the next granule.  If we've any remaining
1835                  * bytes to process we'll just continue in our loop...
1836                  */
1837                 rxdata += SR_BUF_SIZ;
1838                 rxdesc++;
1839
1840                 if (rxdata == rxmax) {  /* handle the wrap point */
1841                         rxdata = sc->rxstart;
1842                         rxdesc = (sca_descriptor *)
1843                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1844                 }
1845         }
1846 }
1847
1848 /*
1849  * If single is set, just eat a packet. Otherwise eat everything up to
1850  * where cda points. Update pointers to point to the next packet.
1851  *
1852  * This handles "flushing" of a packet as received...
1853  *
1854  * If the "single" parameter is zero, all pending reeceive traffic will
1855  * be flushed out of existence.  A non-zero value will only drop the
1856  * *next* (currently) pending packet...
1857  */
1858 static void
1859 sr_eat_packet(struct sr_softc *sc, int single)
1860 {
1861         struct sr_hardc *hc;
1862         sca_descriptor *rxdesc; /* current descriptor being eval'd */
1863         sca_descriptor *endp;   /* last descriptor in chain */
1864         sca_descriptor *cda;    /* current start point */
1865         u_int loopcnt = 0;      /* count of packets flushed ??? */
1866         u_char stat;            /* captured status byte from descr */
1867
1868         hc = sc->hc;
1869         cda = (sca_descriptor *)(hc->mem_start +
1870                                  (SRC_GET16(hc->sca_base,
1871                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1872                                   hc->winmsk));
1873
1874         /*
1875          * loop until desc->stat == (0xff || EOM) Clear the status and
1876          * length in the descriptor. Increment the descriptor.
1877          */
1878
1879         rxdesc = (sca_descriptor *)
1880             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1881         endp = rxdesc;
1882         rxdesc = &rxdesc[sc->rxhind];
1883         endp = &endp[sc->rxmax];
1884
1885         /*
1886          * allow loop, but abort it if we wrap completely...
1887          */
1888         while (rxdesc != cda) {
1889                 loopcnt++;
1890
1891                 if (loopcnt > sc->rxmax) {
1892                         kprintf("sr%d: eat pkt %d loop, cda %x, "
1893                                "rxdesc %x, stat %x.\n",
1894                                sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1895                                rxdesc->stat);
1896                         break;
1897                 }
1898                 stat = rxdesc->stat;
1899
1900                 rxdesc->len = 0;
1901                 rxdesc->stat = 0xff;
1902
1903                 rxdesc++;
1904                 sc->rxhind++;
1905
1906                 if (rxdesc == endp) {
1907                         rxdesc = (sca_descriptor *)
1908                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1909                         sc->rxhind = 0;
1910                 }
1911                 if (single && (stat == SCA_DESC_EOM))
1912                         break;
1913         }
1914
1915         /*
1916          * Update the eda to the previous descriptor.
1917          */
1918         rxdesc = (sca_descriptor *)sc->rxdesc;
1919         rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
1920
1921         SRC_PUT16(hc->sca_base,
1922                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
1923                   (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
1924 }
1925
1926 /*
1927  * While there is packets available in the rx buffer, read them out
1928  * into mbufs and ship them off.
1929  */
1930 static void
1931 sr_get_packets(struct sr_softc *sc)
1932 {
1933         u_char rxstat;          /* acquired status byte */
1934         int i;
1935         int pkts;               /* count of packets found */
1936         int rxndx;              /* rcv buffer index */
1937         int tries;              /* settling time counter */
1938         u_int len;              /* length of pending packet */
1939         struct sr_hardc *hc;    /* card-level information */
1940         sca_descriptor *rxdesc; /* descriptor in memory */
1941 #ifndef NETGRAPH
1942         struct ifnet *ifp;      /* network intf ctl table */
1943 #endif /* NETGRAPH */
1944         struct mbuf *m = NULL;  /* message buffer */
1945
1946 #if BUGGY > 0
1947         kprintf("sr_get_packets(sc=%08x)\n", sc);
1948 #endif
1949
1950         hc = sc->hc;
1951 #ifndef NETGRAPH
1952         ifp = &sc->ifsppp.pp_if;
1953 #endif /* NETGRAPH */
1954
1955         pkts = 0;               /* reset count of found packets */
1956
1957         /*
1958          * for each complete packet in the receiving pool, process each
1959          * packet...
1960          */
1961         while (sr_packet_avail(sc, &len, &rxstat)) {    /* packet pending? */
1962                 /*
1963                  * I have seen situations where we got the interrupt but the
1964                  * status value wasn't deposited.  This code should allow
1965                  * the status byte's value to settle...
1966                  */
1967
1968                 tries = 5;
1969
1970                 while ((rxstat == 0x00ff)
1971                        && --tries)
1972                         sr_packet_avail(sc, &len, &rxstat);
1973
1974 #if BUGGY > 1
1975                 kprintf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
1976                        len, rxstat);
1977 #endif
1978
1979                 pkts++;
1980 #ifdef NETGRAPH
1981                 sc->inbytes += len;
1982                 sc->inlast = 0;
1983 #endif /* NETGRAPH */
1984
1985                 /*
1986                  * OK, we've settled the incoming message status. We can now
1987                  * process it...
1988                  */
1989                 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1990 #if BUGGY > 1
1991                         kprintf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
1992                                sc->unit, rxstat, len);
1993 #endif
1994
1995                         MGETHDR(m, MB_DONTWAIT, MT_DATA);
1996                         if (m == NULL) {
1997                                 /*
1998                                  * eat (flush) packet if get mbuf fail!!
1999                                  */
2000                                 sr_eat_packet(sc, 1);
2001                                 continue;
2002                         }
2003                         /*
2004                          * construct control information for pass-off
2005                          */
2006 #ifndef NETGRAPH
2007                         m->m_pkthdr.rcvif = ifp;
2008 #else
2009                         m->m_pkthdr.rcvif = NULL;
2010 #endif /* NETGRAPH */
2011                         m->m_pkthdr.len = m->m_len = len;
2012                         if (len > MHLEN) {
2013                                 MCLGET(m, MB_DONTWAIT);
2014                                 if ((m->m_flags & M_EXT) == 0) {
2015                                         /*
2016                                          * We couldn't get a big enough
2017                                          * message packet, so we'll send the
2018                                          * packet to /dev/null...
2019                                          */
2020                                         m_freem(m);
2021                                         sr_eat_packet(sc, 1);
2022                                         continue;
2023                                 }
2024                         }
2025                         /*
2026                          * OK, we've got a good message buffer.  Now we can
2027                          * copy the received message into it
2028                          */
2029                         sr_copy_rxbuf(m, sc, len);      /* copy from DPRAM */
2030
2031 #ifndef NETGRAPH
2032                         BPF_MTAP(ifp, m);
2033
2034 #if BUGGY > 3
2035                         {
2036                                 u_char *bp;
2037
2038                                 bp = (u_char *)m;
2039                                 kprintf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2040                                        sc->unit,
2041                                        bp[0], bp[1], bp[2],
2042                                        bp[4], bp[5], bp[6]);
2043                         }
2044 #endif
2045                         sppp_input(ifp, m);
2046                         IFNET_STAT_INC(ifp, ipackets, 1);
2047
2048 #else   /* NETGRAPH */
2049 #if BUGGY > 3
2050                         {
2051                                 u_char *bp;
2052
2053                                 bp = mtod(m,u_char *);
2054                                 kprintf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2055                                        sc->unit,
2056                                        bp[0], bp[1], bp[2],
2057                                        bp[4], bp[5], bp[6]);
2058                                 kprintf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2059                                        bp[6], bp[7], bp[8],
2060                                        bp[9], bp[10], bp[11]);
2061                         }
2062 #endif
2063                         ng_queue_data(sc->hook, m, NULL);
2064                         sc->ipackets++;
2065 #endif /* NETGRAPH */
2066                         /*
2067                          * Update the eda to the previous descriptor.
2068                          */
2069                         i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2070                         sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2071
2072                         rxdesc = (sca_descriptor *)sc->rxdesc;
2073                         rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2074                         rxdesc = &rxdesc[rxndx];
2075
2076                         SRC_PUT16(hc->sca_base,
2077                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2078                                   (u_short)((u_int)(rxdesc + hc->mem_pstart)
2079                                              & 0xffff));
2080
2081                 } else {
2082                         int got_st3, got_cda, got_eda;
2083                         int tries = 5;
2084
2085                         while ((rxstat == 0xff) && --tries)
2086                                 sr_packet_avail(sc, &len, &rxstat);
2087
2088                         /*
2089                          * It look like we get an interrupt early
2090                          * sometimes and then the status is not
2091                          * filled in yet.
2092                          */
2093                         if (tries && (tries != 5))
2094                                 continue;
2095
2096                         /*
2097                          * This chunk of code handles the error packets.
2098                          * We'll log them for posterity...
2099                          */
2100                         sr_eat_packet(sc, 1);
2101
2102 #ifndef NETGRAPH
2103                         IFNET_STAT_INC(ifp, ierrors, 1);
2104 #else
2105                         sc->ierrors[0]++;
2106 #endif /* NETGRAPH */
2107
2108                         got_st3 = SRC_GET8(hc->sca_base,
2109                                   hc->sca->msci[sc->scachan].st3);
2110                         got_cda = SRC_GET16(hc->sca_base,
2111                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2112                         got_eda = SRC_GET16(hc->sca_base,
2113                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2114
2115 #if BUGGY > 0
2116                         kprintf("sr%d: Receive error chan %d, "
2117                                "stat %02x, msci st3 %02x,"
2118                                "rxhind %d, cda %04x, eda %04x.\n",
2119                                sc->unit, sc->scachan, rxstat,
2120                                got_st3, sc->rxhind, got_cda, got_eda);
2121 #endif
2122                 }
2123         }
2124
2125 #if BUGGY > 0
2126         kprintf("sr%d: sr_get_packets() found %d packet(s)\n",
2127                sc->unit, pkts);
2128 #endif
2129 }
2130
2131 /*
2132  * All DMA interrupts come here.
2133  *
2134  * Each channel has two interrupts.
2135  * Interrupt A for errors and Interrupt B for normal stuff like end
2136  * of transmit or receive dmas.
2137  */
2138 static void
2139 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2140 {
2141         u_char dsr;             /* contents of DMA Stat Reg */
2142         u_char dotxstart;       /* enables for tranmit part */
2143         int mch;                /* channel being processed */
2144         struct sr_softc *sc;    /* channel's softc structure */
2145         sca_regs *sca = hc->sca;
2146         dmac_channel *dmac;     /* dma structure of chip */
2147
2148 #if BUGGY > 0
2149         kprintf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2150 #endif
2151
2152         mch = 0;                /* assume chan0 on card */
2153         dotxstart = isr1;       /* copy for xmitter starts */
2154
2155         /*
2156          * Shortcut if there is no interrupts for dma channel 0 or 1.
2157          * Skip processing for channel 0 if no incoming hit
2158          */
2159         if ((isr1 & 0x0F) == 0) {
2160                 mch = 1;
2161                 isr1 >>= 4;
2162         }
2163         do {
2164                 sc = &hc->sc[mch];
2165
2166                 /*
2167                  * Transmit channel - DMA Status Register Evaluation
2168                  */
2169                 if (isr1 & 0x0C) {
2170                         u_long opkts;
2171
2172                         dmac = &sca->dmac[DMAC_TXCH(mch)];
2173
2174                         /*
2175                          * get the DMA Status Register contents and write
2176                          * back to reset interrupt...
2177                          */
2178                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2179                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2180
2181                         /*
2182                          * Check for (& process) a Counter overflow
2183                          */
2184                         if (dsr & SCA_DSR_COF) {
2185 #ifndef NETGRAPH
2186                                 IFNET_STAT_GET(&sc->ifsppp.pp_if, opackets,
2187                                     opkts);
2188                                 IFNET_STAT_INC(&sc->ifsppp.pp_if, oerrors, 1);
2189 #else
2190                                 opkts = sc->opackets;
2191                                 sc->oerrors++;
2192 #endif /* NETGRAPH */
2193                                 kprintf("sr%d: TX DMA Counter overflow, "
2194                                        "txpacket no %lu.\n",
2195                                        sc->unit, opkts);
2196                         }
2197                         /*
2198                          * Check for (& process) a Buffer overflow
2199                          */
2200                         if (dsr & SCA_DSR_BOF) {
2201 #ifndef NETGRAPH
2202                                 IFNET_STAT_GET(&sc->ifsppp.pp_if, opackets,
2203                                     opkts);
2204                                 IFNET_STAT_INC(&sc->ifsppp.pp_if, oerrors, 1);
2205 #else
2206                                 opkts = sc->opackets;
2207                                 sc->oerrors++;
2208 #endif /* NETGRAPH */
2209                                 kprintf("sr%d: TX DMA Buffer overflow, "
2210                                        "txpacket no %lu, dsr %02x, "
2211                                        "cda %04x, eda %04x.\n",
2212                                        sc->unit, opkts,
2213                                        dsr,
2214                                        SRC_GET16(hc->sca_base, dmac->cda),
2215                                        SRC_GET16(hc->sca_base, dmac->eda));
2216                         }
2217                         /*
2218                          * Check for (& process) an End of Transfer (OK)
2219                          */
2220                         if (dsr & SCA_DSR_EOT) {
2221                                 /*
2222                                  * This should be the most common case.
2223                                  *
2224                                  * Clear the OACTIVE flag.
2225                                  *
2226                                  * Call srstart to start a new transmit if
2227                                  * there is data to transmit.
2228                                  */
2229 #if BUGGY > 0
2230                                 kprintf("sr%d: TX Completed OK\n", sc->unit);
2231 #endif
2232                                 sc->xmit_busy = 0;
2233 #ifndef NETGRAPH
2234                                 ifq_clr_oactive(&sc->ifsppp.pp_if.if_snd);
2235                                 sc->ifsppp.pp_if.if_timer = 0;
2236 #else
2237                                 /* XXX may need to mark tx inactive? */
2238                                 sc->out_deficit++;
2239                                 sc->out_dog = DOG_HOLDOFF;
2240 #endif /* NETGRAPH */
2241
2242                                 if (sc->txb_inuse && --sc->txb_inuse)
2243                                         sr_xmit(sc);
2244                         }
2245                 }
2246                 /*
2247                  * Receive channel processing of DMA Status Register
2248                  */
2249                 if (isr1 & 0x03) {
2250                         u_long ipkts;
2251
2252                         dmac = &sca->dmac[DMAC_RXCH(mch)];
2253
2254                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2255                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2256
2257                         /*
2258                          * End of frame processing (MSG OK?)
2259                          */
2260                         if (dsr & SCA_DSR_EOM) {
2261 #if BUGGY > 0
2262                                 u_long tt, ntt;
2263                                 int ind;
2264
2265 #ifndef NETGRAPH
2266                                 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets, tt);
2267 #else   /* NETGRAPH */
2268                                 tt = sc->ipackets;
2269 #endif /* NETGRAPH */
2270                                 ind = sc->rxhind;
2271 #endif
2272
2273                                 sr_get_packets(sc);
2274 #if BUGGY > 0
2275 #ifndef NETGRAPH
2276                                 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2277                                     ntt);
2278 #else   /* NETGRAPH */
2279                                 ntt = sc->ipackets;
2280 #endif /* NETGRAPH */
2281                                 if (tt == ntt) {
2282                                         sca_descriptor *rxdesc;
2283                                         int i;
2284
2285                                         kprintf("SR: RXINTR isr1 %x, dsr %x, "
2286                                                "no data %d pkts, orxind %d.\n",
2287                                                dotxstart, dsr, tt, ind);
2288                                         kprintf("SR: rxdesc %x, rxstart %x, "
2289                                                "rxend %x, rxhind %d, "
2290                                                "rxmax %d.\n",
2291                                                sc->rxdesc, sc->rxstart,
2292                                                sc->rxend, sc->rxhind,
2293                                                sc->rxmax);
2294                                         kprintf("SR: cda %x, eda %x.\n",
2295                                             SRC_GET16(hc->sca_base, dmac->cda),
2296                                             SRC_GET16(hc->sca_base, dmac->eda));
2297
2298                                         rxdesc = (sca_descriptor *)
2299                                                  (hc->mem_start +
2300                                                   (sc->rxdesc & hc->winmsk));
2301                                         rxdesc = &rxdesc[sc->rxhind];
2302
2303                                         for (i = 0; i < 3; i++, rxdesc++)
2304                                                 kprintf("SR: rxdesc->stat %x, "
2305                                                        "len %d.\n",
2306                                                        rxdesc->stat,
2307                                                        rxdesc->len);
2308                                 }
2309 #endif /* BUGGY */
2310                         }
2311                         /*
2312                          * Check for Counter overflow
2313                          */
2314                         if (dsr & SCA_DSR_COF) {
2315 #ifndef NETGRAPH
2316                                 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2317                                     ipkts);
2318                                 IFNET_STAT_INC(&sc->ifsppp.pp_if, ierrors, 1);
2319 #else   /* NETGRAPH */
2320                                 ipkts = sc->ipackets;
2321                                 sc->ierrors[1]++;
2322 #endif /* NETGRAPH */
2323                                 kprintf("sr%d: RX DMA Counter overflow, "
2324                                        "rxpkts %lu.\n",
2325                                        sc->unit, ipkts);
2326                         }
2327                         /*
2328                          * Check for Buffer overflow
2329                          */
2330                         if (dsr & SCA_DSR_BOF) {
2331 #ifndef NETGRAPH
2332                                 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2333                                     ipkts);
2334 #else   /* NETGRAPH */
2335                                 ipkts = sc->ipackets;
2336 #endif /* NETGRAPH */
2337                                 kprintf("sr%d: RX DMA Buffer overflow, "
2338                                        "rxpkts %lu, rxind %d, "
2339                                        "cda %x, eda %x, dsr %x.\n",
2340                                        sc->unit, ipkts,
2341                                        sc->rxhind,
2342                                        SRC_GET16(hc->sca_base, dmac->cda),
2343                                        SRC_GET16(hc->sca_base, dmac->eda),
2344                                        dsr);
2345
2346                                 /*
2347                                  * Make sure we eat as many as possible.
2348                                  * Then get the system running again.
2349                                  */
2350
2351                                 sr_eat_packet(sc, 0);
2352 #ifndef NETGRAPH
2353                                 IFNET_STAT_INC(&sc->ifsppp.pp_if, ierrors, 1);
2354 #else   /* NETGRAPH */
2355                                 sc->ierrors[2]++;
2356 #endif /* NETGRAPH */
2357
2358                                 SRC_PUT8(hc->sca_base,
2359                                          sca->msci[mch].cmd,
2360                                          SCA_CMD_RXMSGREJ);
2361
2362                                 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2363
2364 #if BUGGY > 0
2365 #ifndef NETGRAPH
2366                                 ipkts = sc->ipackets;
2367 #else   /* NETGRAPH */
2368                                 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2369                                     ipkts);
2370 #endif /* NETGRAPH */
2371                                 kprintf("sr%d: RX DMA Buffer overflow, "
2372                                        "rxpkts %lu, rxind %d, "
2373                                        "cda %x, eda %x, dsr %x. After\n",
2374                                        sc->unit, ipkts,
2375                                        sc->rxhind,
2376                                        SRC_GET16(hc->sca_base, dmac->cda),
2377                                        SRC_GET16(hc->sca_base, dmac->eda),
2378                                        SRC_GET8(hc->sca_base, dmac->dsr));
2379 #endif
2380                         }
2381                         /*
2382                          * End of Transfer
2383                          */
2384                         if (dsr & SCA_DSR_EOT) {
2385                                 u_long ipkts;
2386
2387 #ifndef NETGRAPH
2388                                 IFNET_STAT_GET(&sc->ifsppp.pp_if, ipackets,
2389                                     ipkts);
2390                                 IFNET_STAT_INC(&sc->ifsppp.pp_if, ierrors, 1);
2391 #else
2392                                 ipkts = sc->ipackets;
2393                                 sc->ierrors[3]++;
2394 #endif /* NETGRAPH */
2395                                 /*
2396                                  * If this happen, it means that we are
2397                                  * receiving faster than what the processor
2398                                  * can handle.
2399                                  *
2400                                  * XXX We should enable the dma again.
2401                                  */
2402                                 kprintf("sr%d: RX End of xfer, rxpkts %lu.\n",
2403                                        sc->unit, ipkts);
2404                         }
2405                 }
2406                 isr1 >>= 4;     /* process next half of ISR */
2407                 mch++;          /* and move to next channel */
2408         } while ((mch < NCHAN) && isr1);        /* loop for each chn */
2409
2410         /*
2411          * Now that we have done all the urgent things, see if we can fill
2412          * the transmit buffers.
2413          */
2414         for (mch = 0; mch < NCHAN; mch++) {
2415                 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2416                         sc = &hc->sc[mch];
2417 #ifndef NETGRAPH
2418                         srstart(&sc->ifsppp.pp_if,
2419                             ifq_get_subq_default(&sc->ifsppp.pp_if.if_snd));
2420 #else
2421                         srstart(sc);
2422 #endif /* NETGRAPH */
2423                 }
2424                 dotxstart >>= 4;/* shift for next channel */
2425         }
2426 }
2427 #ifndef NETGRAPH
2428 #ifdef USE_MODEMCK
2429 /*
2430  * Perform timeout on an FR channel
2431  *
2432  * Establish a periodic check of open N2 ports;  If
2433  * a port is open/active, its DCD state is checked
2434  * and a loss of DCD is recognized (and eventually
2435  * processed).
2436  */
2437 static void
2438 sr_modemck(void *arg)
2439 {
2440         int card;               /* card index in table */
2441         int cards;              /* card list index */
2442         int mch;                /* channel on card */
2443         u_char dcd_v;           /* Data Carrier Detect */
2444         u_char got_st0;         /* contents of ST0 */
2445         u_char got_st1;         /* contents of ST1 */
2446         u_char got_st2;         /* contents of ST2 */
2447         u_char got_st3;         /* contents of ST3 */
2448         struct sr_hardc *hc;    /* card's configuration */
2449         struct sr_hardc *Card[16];/* up to 16 cards in system */
2450         struct sr_softc *sc;    /* channel's softc structure */
2451         struct ifnet *ifp;      /* interface control table */
2452         msci_channel *msci;     /* regs specific to channel */
2453
2454         crit_enter();
2455
2456 #if     0
2457         if (sr_opens == 0) {    /* count of "up" channels */
2458                 sr_watcher = 0; /* indicate no watcher */
2459
2460                 crit_exit();
2461
2462                 return;
2463         }
2464 #endif
2465
2466         sr_watcher = 1;         /* mark that we're online */
2467
2468         /*
2469          * Now we'll need a list of cards to process.  Since we can handle
2470          * both ISA and PCI cards (and I didn't think of making this logic
2471          * global YET) we'll generate a single table of card table
2472          * addresses.
2473          */
2474         cards = 0;
2475
2476         for (card = 0; card < NSR; card++) {
2477                 hc = &sr_hardc[card];
2478
2479                 if (hc->sc == NULL)
2480                         continue;
2481
2482                 Card[cards++] = hc;
2483         }
2484
2485         hc = sr_hardc_pci;
2486
2487         while (hc) {
2488                 Card[cards++] = hc;
2489                 hc = hc->next;
2490         }
2491
2492         /*
2493          * OK, we've got work we can do.  Let's do it... (Please note that
2494          * this code _only_ deals w/ ISA cards)
2495          */
2496         for (card = 0; card < cards; card++) {
2497                 hc = Card[card];/* get card table */
2498
2499                 for (mch = 0; mch < hc->numports; mch++) {
2500                         sc = &hc->sc[mch];
2501
2502                         ifp = &sc->ifsppp.pp_if;
2503
2504                         /*
2505                          * if this channel isn't "up", skip it
2506                          */
2507                         if ((ifp->if_flags & IFF_UP) == 0)
2508                                 continue;
2509
2510                         /*
2511                          * OK, now we can go looking at this channel's
2512                          * actual register contents...
2513                          */
2514                         msci = &hc->sca->msci[sc->scachan];
2515
2516                         /*
2517                          * OK, now we'll look into the actual status of this
2518                          * channel...
2519                          *
2520                          * I suck in more registers than strictly needed
2521                          */
2522                         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2523                         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2524                         got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2525                         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2526
2527                         /*
2528                          * We want to see if the DCD signal is up (DCD is
2529                          * true if zero)
2530                          */
2531                         dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2532
2533                         if (dcd_v == 0)
2534                                 kprintf("sr%d: DCD lost\n", sc->unit);
2535                 }
2536         }
2537
2538         /*
2539          * OK, now set up for the next modem signal checking pass...
2540          */
2541         timeout(sr_modemck, NULL, hz);
2542
2543         crit_exit();
2544 }
2545 #endif
2546 #else   /* NETGRAPH */
2547 /*
2548  * If a port is open/active, it's DCD state is checked
2549  * and a loss of DCD is recognized (and eventually processed?).
2550  */
2551 static void
2552 sr_modemck(struct sr_softc *sc )
2553 {
2554         u_char got_st3;                 /* contents of ST3 */
2555         struct sr_hardc *hc = sc->hc;   /* card's configuration */
2556         msci_channel *msci;             /* regs specific to channel */
2557
2558         crit_enter();
2559
2560         if (sc->running == 0) {
2561                 crit_exit();
2562                 return;
2563         }
2564
2565         /*
2566          * OK, now we can go looking at this channel's register contents...
2567          */
2568         msci = &hc->sca->msci[sc->scachan];
2569         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2570
2571         /*
2572          * We want to see if the DCD signal is up (DCD is true if zero)
2573          */
2574         sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2575
2576         crit_exit();
2577 }
2578
2579 #endif  /* NETGRAPH */
2580 static void
2581 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2582 {
2583         kprintf("src%d: SRINTR: MSCI\n", hc->cunit);
2584 }
2585
2586 static void
2587 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2588 {
2589         kprintf("src%d: SRINTR: TIMER\n", hc->cunit);
2590 }
2591
2592 #ifdef  NETGRAPH
2593 /*****************************************
2594  * Device timeout/watchdog routine.
2595  * called once per second.
2596  * checks to see that if activity was expected, that it hapenned.
2597  * At present we only look to see if expected output was completed.
2598  */
2599 static void
2600 ngsr_watchdog_frame(void * arg)
2601 {
2602         struct sr_softc * sc = arg;
2603         int     speed;
2604
2605         crit_enter();
2606
2607         if (sc->running == 0) {
2608                 crit_exit();
2609                 return; /* if we are not running let timeouts die */
2610         }
2611         /*
2612          * calculate the apparent throughputs
2613          *  XXX a real hack
2614          */
2615
2616         speed = sc->inbytes - sc->lastinbytes;
2617         sc->lastinbytes = sc->inbytes;
2618         if ( sc->inrate < speed )
2619                 sc->inrate = speed;
2620         speed = sc->outbytes - sc->lastoutbytes;
2621         sc->lastoutbytes = sc->outbytes;
2622         if ( sc->outrate < speed )
2623                 sc->outrate = speed;
2624         sc->inlast++;
2625
2626         crit_exit();
2627
2628         if ((sc->inlast > QUITE_A_WHILE)
2629         && (sc->out_deficit > LOTS_OF_PACKETS)) {
2630                 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2631
2632                 crit_enter();
2633
2634                 sr_down(sc);
2635                 sr_up(sc);
2636                 sc->inlast = sc->out_deficit = 0;
2637
2638                 crit_exit();
2639         } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2640                 if (sc->out_dog == 0) {
2641                         log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2642                                         sc->unit);
2643
2644                         crit_enter();
2645
2646                         srwatchdog(sc);
2647 #if 0
2648                         sr_down(sc);
2649                         sr_up(sc);
2650 #endif
2651
2652                         crit_exit();
2653
2654                         sc->inlast = sc->out_deficit = 0;
2655                 } else {
2656                         sc->out_dog--;
2657                 }
2658         }
2659         sr_modemck(sc);         /* update the DCD status */
2660         callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
2661 }
2662
2663 /***********************************************************************
2664  * This section contains the methods for the Netgraph interface
2665  ***********************************************************************/
2666 /*
2667  * It is not possible or allowable to create a node of this type.
2668  * If the hardware exists, it will already have created it.
2669  */
2670 static  int
2671 ngsr_constructor(node_p *nodep)
2672 {
2673         return (EINVAL);
2674 }
2675
2676 /*
2677  * give our ok for a hook to be added...
2678  * If we are not running this should kick the device into life.
2679  * The hook's private info points to our stash of info about that
2680  * channel.
2681  */
2682 static int
2683 ngsr_newhook(node_p node, hook_p hook, const char *name)
2684 {
2685         struct sr_softc *       sc = node->private;
2686
2687         /*
2688          * check if it's our friend the debug hook
2689          */
2690         if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2691                 hook->private = NULL; /* paranoid */
2692                 sc->debug_hook = hook;
2693                 return (0);
2694         }
2695
2696         /*
2697          * Check for raw mode hook.
2698          */
2699         if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2700                 return (EINVAL);
2701         }
2702         hook->private = sc;
2703         sc->hook = hook;
2704         sc->datahooks++;
2705         sr_up(sc);
2706         return (0);
2707 }
2708
2709 /*
2710  * incoming messages.
2711  * Just respond to the generic TEXT_STATUS message
2712  */
2713 static  int
2714 ngsr_rcvmsg(node_p node,
2715         struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2716 {
2717         struct sr_softc *       sc;
2718         int error = 0;
2719
2720         sc = node->private;
2721         switch (msg->header.typecookie) {
2722             case        NG_SR_COOKIE:
2723                 error = EINVAL;
2724                 break;
2725             case        NGM_GENERIC_COOKIE:
2726                 switch(msg->header.cmd) {
2727                     case NGM_TEXT_STATUS: {
2728                             char        *arg;
2729                             int pos = 0;
2730                             int resplen = sizeof(struct ng_mesg) + 512;
2731                             *resp = kmalloc(resplen, M_NETGRAPH,
2732                                             M_INTWAIT | M_ZERO);
2733                             if (*resp == NULL) {
2734                                 error = ENOMEM;
2735                                 break;
2736                             }
2737                             arg = (*resp)->data;
2738
2739                             /*
2740                              * Put in the throughput information.
2741                              */
2742                             pos = ksprintf(arg, "%ld bytes in, %ld bytes out\n"
2743                             "highest rate seen: %ld B/S in, %ld B/S out\n",
2744                             sc->inbytes, sc->outbytes,
2745                             sc->inrate, sc->outrate);
2746                             pos += ksprintf(arg + pos,
2747                                 "%ld output errors\n",
2748                                 sc->oerrors);
2749                             pos += ksprintf(arg + pos,
2750                                 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2751                                 sc->ierrors[0],
2752                                 sc->ierrors[1],
2753                                 sc->ierrors[2],
2754                                 sc->ierrors[3],
2755                                 sc->ierrors[4],
2756                                 sc->ierrors[5]);
2757
2758                             (*resp)->header.version = NG_VERSION;
2759                             (*resp)->header.arglen = strlen(arg) + 1;
2760                             (*resp)->header.token = msg->header.token;
2761                             (*resp)->header.typecookie = NG_SR_COOKIE;
2762                             (*resp)->header.cmd = msg->header.cmd;
2763                             strlcpy((*resp)->header.cmdstr, "status",
2764                                         NG_CMDSTRSIZ);
2765                         }
2766                         break;
2767                     default:
2768                         error = EINVAL;
2769                         break;
2770                     }
2771                 break;
2772             default:
2773                 error = EINVAL;
2774                 break;
2775         }
2776         kfree(msg, M_NETGRAPH);
2777         return (error);
2778 }
2779
2780 /*
2781  * get data from another node and transmit it to the correct channel
2782  */
2783 static  int
2784 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2785 {
2786         int error = 0;
2787         struct sr_softc * sc = hook->node->private;
2788         struct ifqueue  *xmitq_p;
2789
2790         /*
2791          * data doesn't come in from just anywhere (e.g control hook)
2792          */
2793         if ( hook->private == NULL) {
2794                 error = ENETDOWN;
2795                 goto bad;
2796         }
2797
2798         /*
2799          * Now queue the data for when it can be sent
2800          */
2801         if (meta && meta->priority > 0) {
2802                 xmitq_p = (&sc->xmitq_hipri);
2803         } else {
2804                 xmitq_p = (&sc->xmitq);
2805         }
2806
2807         crit_enter();
2808
2809         if (IF_QFULL(xmitq_p)) {
2810                 IF_DROP(xmitq_p);
2811
2812                 crit_exit();
2813
2814                 error = ENOBUFS;
2815                 goto bad;
2816         }
2817         IF_ENQUEUE(xmitq_p, m);
2818         srstart(sc);
2819
2820         crit_exit();
2821
2822         return (0);
2823
2824 bad:
2825         /*
2826          * It was an error case.
2827          * check if we need to free the mbuf, and then return the error
2828          */
2829         NG_FREE_DATA(m, meta);
2830         return (error);
2831 }
2832
2833 /*
2834  * do local shutdown processing..
2835  * this node will refuse to go away, unless the hardware says to..
2836  * don't unref the node, or remove our name. just clear our links up.
2837  */
2838 static  int
2839 ngsr_rmnode(node_p node)
2840 {
2841         struct sr_softc * sc = node->private;
2842
2843         sr_down(sc);
2844         ng_cutlinks(node);
2845         node->flags &= ~NG_INVALID; /* bounce back to life */
2846         return (0);
2847 }
2848
2849 /* already linked */
2850 static  int
2851 ngsr_connect(hook_p hook)
2852 {
2853         /* be really amiable and just say "YUP that's OK by me! " */
2854         return (0);
2855 }
2856
2857 /*
2858  * notify on hook disconnection (destruction)
2859  *
2860  * Invalidate the private data associated with this dlci.
2861  * For this type, removal of the last link resets tries to destroy the node.
2862  * As the device still exists, the shutdown method will not actually
2863  * destroy the node, but reset the device and leave it 'fresh' :)
2864  *
2865  * The node removal code will remove all references except that owned by the
2866  * driver.
2867  */
2868 static  int
2869 ngsr_disconnect(hook_p hook)
2870 {
2871         struct sr_softc * sc = hook->node->private;
2872         /*
2873          * If it's the data hook, then free resources etc.
2874          */
2875         if (hook->private) {
2876                 crit_enter();
2877
2878                 sc->datahooks--;
2879                 if (sc->datahooks == 0)
2880                         sr_down(sc);
2881
2882                 crit_exit();
2883         } else {
2884                 sc->debug_hook = NULL;
2885         }
2886         return (0);
2887 }
2888
2889 /*
2890  * called during bootup
2891  * or LKM loading to put this type into the list of known modules
2892  */
2893 static void
2894 ngsr_init(void *ignored)
2895 {
2896         if (ng_newtype(&typestruct))
2897                 kprintf("ngsr install failed\n");
2898         ngsr_done_init = 1;
2899 }
2900 #endif /* NETGRAPH */
2901
2902 /*
2903  ********************************* END ************************************
2904  */