2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/md_var.h>
36 #include <machine/pmap.h>
37 #include <machine_base/apic/lapic.h>
38 #include <machine_base/apic/ioapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
40 #include <machine_base/icu/icu_var.h>
41 #include <machine/segments.h>
42 #include <sys/thread2.h>
44 #include <machine/cputypes.h>
45 #include <machine/intr_machdep.h>
51 volatile lapic_t *lapic;
53 static void lapic_timer_calibrate(void);
54 static void lapic_timer_set_divisor(int);
55 static void lapic_timer_fixup_handler(void *);
56 static void lapic_timer_restart_handler(void *);
58 void lapic_timer_process(void);
59 void lapic_timer_process_frame(struct intrframe *);
60 void lapic_timer_always(struct intrframe *);
62 static int lapic_timer_enable = 1;
63 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
65 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
66 static void lapic_timer_intr_enable(struct cputimer_intr *);
67 static void lapic_timer_intr_restart(struct cputimer_intr *);
68 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
70 static struct cputimer_intr lapic_cputimer_intr = {
72 .reload = lapic_timer_intr_reload,
73 .enable = lapic_timer_intr_enable,
74 .config = cputimer_intr_default_config,
75 .restart = lapic_timer_intr_restart,
76 .pmfixup = lapic_timer_intr_pmfixup,
77 .initclock = cputimer_intr_default_initclock,
78 .next = SLIST_ENTRY_INITIALIZER,
80 .type = CPUTIMER_INTR_LAPIC,
81 .prio = CPUTIMER_INTR_PRIO_LAPIC,
82 .caps = CPUTIMER_INTR_CAP_NONE
85 static int lapic_timer_divisor_idx = -1;
86 static const uint32_t lapic_timer_divisors[] = {
87 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
88 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
90 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
93 * APIC ID <-> CPU ID mapping structures.
95 int cpu_id_to_apic_id[NAPICID];
96 int apic_id_to_cpu_id[NAPICID];
107 * Enable LAPIC, configure interrupts.
110 lapic_init(boolean_t bsp)
118 * Since IDT is shared between BSP and APs, these vectors
119 * only need to be installed once; we do it on BSP.
122 /* Install a 'Spurious INTerrupt' vector */
123 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
124 SDT_SYSIGT, SEL_KPL, 0);
126 /* Install a timer vector */
127 setidt(XTIMER_OFFSET, Xtimer,
128 SDT_SYSIGT, SEL_KPL, 0);
131 /* Install an inter-CPU IPI for TLB invalidation */
132 setidt(XINVLTLB_OFFSET, Xinvltlb,
133 SDT_SYSIGT, SEL_KPL, 0);
135 /* Install an inter-CPU IPI for IPIQ messaging */
136 setidt(XIPIQ_OFFSET, Xipiq,
137 SDT_SYSIGT, SEL_KPL, 0);
139 /* Install an inter-CPU IPI for CPU stop/restart */
140 setidt(XCPUSTOP_OFFSET, Xcpustop,
141 SDT_SYSIGT, SEL_KPL, 0);
146 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
147 * aggregate interrupt input from the 8259. The INTA cycle
148 * will be routed to the external controller (the 8259) which
149 * is expected to supply the vector.
151 * Must be setup edge triggered, active high.
153 * Disable LINT0 on BSP, if I/O APIC is enabled.
155 * Disable LINT0 on the APs. It doesn't matter what delivery
156 * mode we use because we leave it masked.
158 temp = lapic->lvt_lint0;
159 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
160 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
162 temp |= APIC_LVT_DM_EXTINT;
164 temp |= APIC_LVT_MASKED;
166 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
168 lapic->lvt_lint0 = temp;
171 * Setup LINT1 as NMI.
173 * Must be setup edge trigger, active high.
175 * Enable LINT1 on BSP, if I/O APIC is enabled.
177 * Disable LINT1 on the APs.
179 temp = lapic->lvt_lint1;
180 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
181 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
182 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
183 if (bsp && ioapic_enable)
184 temp &= ~APIC_LVT_MASKED;
185 lapic->lvt_lint1 = temp;
188 * Mask the LAPIC error interrupt, LAPIC performance counter
191 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
192 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
195 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
197 timer = lapic->lvt_timer;
198 timer &= ~APIC_LVTT_VECTOR;
199 timer |= XTIMER_OFFSET;
200 timer |= APIC_LVTT_MASKED;
201 lapic->lvt_timer = timer;
204 * Set the Task Priority Register as needed. At the moment allow
205 * interrupts on all cpus (the APs will remain CLId until they are
209 temp &= ~APIC_TPR_PRIO; /* clear priority field */
216 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
217 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
220 * Set the spurious interrupt vector. The low 4 bits of the vector
223 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
224 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
225 temp &= ~APIC_SVR_VECTOR;
226 temp |= XSPURIOUSINT_OFFSET;
231 * Pump out a few EOIs to clean out interrupts that got through
232 * before we were able to set the TPR.
239 lapic_timer_calibrate();
240 if (lapic_timer_enable) {
241 cputimer_intr_register(&lapic_cputimer_intr);
242 cputimer_intr_select(&lapic_cputimer_intr, 0);
245 lapic_timer_set_divisor(lapic_timer_divisor_idx);
249 apic_dump("apic_initialize()");
253 lapic_timer_set_divisor(int divisor_idx)
255 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
256 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
260 lapic_timer_oneshot(u_int count)
264 value = lapic->lvt_timer;
265 value &= ~APIC_LVTT_PERIODIC;
266 lapic->lvt_timer = value;
267 lapic->icr_timer = count;
271 lapic_timer_oneshot_quick(u_int count)
273 lapic->icr_timer = count;
277 lapic_timer_calibrate(void)
281 /* Try to calibrate the local APIC timer. */
282 for (lapic_timer_divisor_idx = 0;
283 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
284 lapic_timer_divisor_idx++) {
285 lapic_timer_set_divisor(lapic_timer_divisor_idx);
286 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
288 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
289 if (value != APIC_TIMER_MAX_COUNT)
292 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
293 panic("lapic: no proper timer divisor?!\n");
294 lapic_cputimer_intr.freq = value / 2;
296 kprintf("lapic: divisor index %d, frequency %u Hz\n",
297 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
301 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
305 gd->gd_timer_running = 0;
307 count = sys_cputimer->count();
308 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
309 systimer_intr(&count, 0, frame);
313 lapic_timer_process(void)
315 lapic_timer_process_oncpu(mycpu, NULL);
319 lapic_timer_process_frame(struct intrframe *frame)
321 lapic_timer_process_oncpu(mycpu, frame);
325 * This manual debugging code is called unconditionally from Xtimer
326 * (the lapic timer interrupt) whether the current thread is in a
327 * critical section or not) and can be useful in tracking down lockups.
329 * NOTE: MANUAL DEBUG CODE
332 static int saveticks[SMP_MAXCPU];
333 static int savecounts[SMP_MAXCPU];
337 lapic_timer_always(struct intrframe *frame)
340 globaldata_t gd = mycpu;
341 int cpu = gd->gd_cpuid;
347 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
348 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
351 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
352 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
354 for (i = 0; buf[i]; ++i) {
355 gptr[i] = 0x0700 | (unsigned char)buf[i];
359 if (saveticks[gd->gd_cpuid] != ticks) {
360 saveticks[gd->gd_cpuid] = ticks;
361 savecounts[gd->gd_cpuid] = 0;
363 ++savecounts[gd->gd_cpuid];
364 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
365 panic("cpud %d panicing on ticks failure",
368 for (i = 0; i < ncpus; ++i) {
370 if (saveticks[i] && panicstr == NULL) {
371 delta = saveticks[i] - ticks;
372 if (delta < -10 || delta > 10) {
373 panic("cpu %d panicing on cpu %d watchdog",
383 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
385 struct globaldata *gd = mycpu;
387 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
391 if (gd->gd_timer_running) {
392 if (reload < lapic->ccr_timer)
393 lapic_timer_oneshot_quick(reload);
395 gd->gd_timer_running = 1;
396 lapic_timer_oneshot_quick(reload);
401 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
405 timer = lapic->lvt_timer;
406 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
407 lapic->lvt_timer = timer;
409 lapic_timer_fixup_handler(NULL);
413 lapic_timer_fixup_handler(void *arg)
420 if (cpu_vendor_id == CPU_VENDOR_AMD) {
422 * Detect the presence of C1E capability mostly on latest
423 * dual-cores (or future) k8 family. This feature renders
424 * the local APIC timer dead, so we disable it by reading
425 * the Interrupt Pending Message register and clearing both
426 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
429 * "BIOS and Kernel Developer's Guide for AMD NPT
430 * Family 0Fh Processors"
431 * #32559 revision 3.00
433 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
434 (cpu_id & 0x0fff0000) >= 0x00040000) {
437 msr = rdmsr(0xc0010055);
438 if (msr & 0x18000000) {
439 struct globaldata *gd = mycpu;
441 kprintf("cpu%d: AMD C1E detected\n",
443 wrmsr(0xc0010055, msr & ~0x18000000ULL);
446 * We are kinda stalled;
449 gd->gd_timer_running = 1;
450 lapic_timer_oneshot_quick(2);
460 lapic_timer_restart_handler(void *dummy __unused)
464 lapic_timer_fixup_handler(&started);
466 struct globaldata *gd = mycpu;
468 gd->gd_timer_running = 1;
469 lapic_timer_oneshot_quick(2);
474 * This function is called only by ACPI-CA code currently:
475 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
476 * module controls PM. So once ACPI-CA is attached, we try
477 * to apply the fixup to prevent LAPIC timer from hanging.
480 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
483 lwkt_send_ipiq_mask(smp_active_mask,
484 lapic_timer_fixup_handler, NULL);
486 lapic_timer_fixup_handler(NULL);
491 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
494 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
496 lapic_timer_restart_handler(NULL);
502 * dump contents of local APIC registers
507 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
508 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
509 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
515 * Inter Processor Interrupt functions.
519 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
521 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
522 * vector is any valid SYSTEM INT vector
523 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
525 * A backlog of requests can create a deadlock between cpus. To avoid this
526 * we have to be able to accept IPIs at the same time we are trying to send
527 * them. The critical section prevents us from attempting to send additional
528 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
529 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
530 * to occur but fortunately it does not happen too often.
533 apic_ipi(int dest_type, int vector, int delivery_mode)
538 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
539 unsigned long rflags = read_rflags();
541 DEBUG_PUSH_INFO("apic_ipi");
542 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
546 write_rflags(rflags);
549 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
550 delivery_mode | vector;
551 lapic->icr_lo = icr_lo;
557 single_apic_ipi(int cpu, int vector, int delivery_mode)
563 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
564 unsigned long rflags = read_rflags();
566 DEBUG_PUSH_INFO("single_apic_ipi");
567 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
571 write_rflags(rflags);
573 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
574 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
575 lapic->icr_hi = icr_hi;
578 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
579 | APIC_DEST_DESTFLD | delivery_mode | vector;
582 lapic->icr_lo = icr_lo;
589 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
591 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
592 * to the target, and the scheduler does not 'poll' for IPI messages.
595 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
601 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
605 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
606 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
607 lapic->icr_hi = icr_hi;
610 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
611 | APIC_DEST_DESTFLD | delivery_mode | vector;
614 lapic->icr_lo = icr_lo;
622 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
624 * target is a bitmask of destination cpus. Vector is any
625 * valid system INT vector. Delivery mode may be either
626 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
629 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
633 int n = BSFCPUMASK(target);
634 target &= ~CPUMASK(n);
635 single_apic_ipi(n, vector, delivery_mode);
643 * Timer code, in development...
644 * - suggested by rgrimes@gndrsh.aac.dev.com
647 get_apic_timer_frequency(void)
649 return(lapic_cputimer_intr.freq);
653 * Load a 'downcount time' in uSeconds.
656 set_apic_timer(int us)
661 * When we reach here, lapic timer's frequency
662 * must have been calculated as well as the
663 * divisor (lapic->dcr_timer is setup during the
664 * divisor calculation).
666 KKASSERT(lapic_cputimer_intr.freq != 0 &&
667 lapic_timer_divisor_idx >= 0);
669 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
670 lapic_timer_oneshot(count);
675 * Read remaining time in timer.
678 read_apic_timer(void)
681 /** XXX FIXME: we need to return the actual remaining time,
682 * for now we just return the remaining count.
685 return lapic->ccr_timer;
691 * Spin-style delay, set delay time in uS, spin till it drains.
696 set_apic_timer(count);
697 while (read_apic_timer())
702 lapic_unused_apic_id(int start)
706 for (i = start; i < NAPICID; ++i) {
707 if (APICID_TO_CPUID(i) == -1)
714 lapic_map(vm_offset_t lapic_addr)
716 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
718 kprintf("lapic: at 0x%08lx\n", lapic_addr);
721 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
722 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
727 struct lapic_enumerator *e;
728 int error, i, ap_max;
730 KKASSERT(lapic_enable);
732 for (i = 0; i < NAPICID; ++i)
733 APICID_TO_CPUID(i) = -1;
735 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
736 error = e->lapic_probe(e);
741 kprintf("LAPIC: Can't find LAPIC\n");
745 e->lapic_enumerate(e);
748 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
749 if (ap_max > MAXCPU - 1)
753 kprintf("LAPIC: Warning use only %d out of %d "
763 lapic_enumerator_register(struct lapic_enumerator *ne)
765 struct lapic_enumerator *e;
767 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
768 if (e->lapic_prio < ne->lapic_prio) {
769 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
773 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
777 lapic_set_cpuid(int cpu_id, int apic_id)
779 CPUID_TO_APICID(cpu_id) = apic_id;
780 APICID_TO_CPUID(apic_id) = cpu_id;
784 lapic_fixup_noioapic(void)
788 /* Only allowed on BSP */
789 KKASSERT(mycpuid == 0);
790 KKASSERT(!ioapic_enable);
792 temp = lapic->lvt_lint0;
793 temp &= ~APIC_LVT_MASKED;
794 lapic->lvt_lint0 = temp;
796 temp = lapic->lvt_lint1;
797 temp |= APIC_LVT_MASKED;
798 lapic->lvt_lint1 = temp;
802 lapic_sysinit(void *dummy __unused)
807 error = lapic_config();
813 /* Initialize BSP's local APIC */
815 } else if (ioapic_enable) {
817 icu_reinit_noioapic();
820 SYSINIT(lapic, SI_BOOT2_LAPIC, SI_ORDER_FIRST, lapic_sysinit, NULL)