1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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32 ******************************************************************************/
35 #ifndef _IGB_H_DEFINED_
36 #define _IGB_H_DEFINED_
41 * IGB_TXD: Maximum number of Transmit Descriptors
43 * This value is the number of transmit descriptors allocated by the driver.
44 * Increasing this value allows the driver to queue more transmits. Each
45 * descriptor is 16 bytes.
46 * Since TDLEN should be multiple of 128bytes, the number of transmit
47 * desscriptors should meet the following condition.
48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
50 #define IGB_MIN_TXD 80
51 #define IGB_DEFAULT_TXD 256
52 #define IGB_MAX_TXD 4096
55 * IGB_RXD: Maximum number of Transmit Descriptors
57 * This value is the number of receive descriptors allocated by the driver.
58 * Increasing this value allows the driver to buffer more incoming packets.
59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
60 * descriptor. The maximum MTU size is 16110.
61 * Since TDLEN should be multiple of 128bytes, the number of transmit
62 * desscriptors should meet the following condition.
63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
65 #define IGB_MIN_RXD 80
66 #define IGB_DEFAULT_RXD 256
67 #define IGB_MAX_RXD 4096
70 * IGB_TIDV - Transmit Interrupt Delay Value
71 * Valid Range: 0-65535 (0=off)
73 * This value delays the generation of transmit interrupts in units of
74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
75 * efficiency if properly tuned for specific network traffic. If the
76 * system is reporting dropped transmits, this value may be set too high
77 * causing the driver to run out of available transmit descriptors.
82 * IGB_TADV - Transmit Absolute Interrupt Delay Value
83 * Valid Range: 0-65535 (0=off)
85 * This value, in units of 1.024 microseconds, limits the delay in which a
86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero,
87 * this value ensures that an interrupt is generated after the initial
88 * packet is sent on the wire within the set amount of time. Proper tuning,
89 * along with IGB_TIDV, may improve traffic throughput in specific
95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer)
96 * Valid Range: 0-65535 (0=off)
98 * This value delays the generation of receive interrupts in units of 1.024
99 * microseconds. Receive interrupt reduction can improve CPU efficiency if
100 * properly tuned for specific network traffic. Increasing this value adds
101 * extra latency to frame reception and can end up decreasing the throughput
102 * of TCP traffic. If the system is reporting dropped receives, this value
103 * may be set too high, causing the driver to run out of available receive
106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters
107 * may hang (stop transmitting) under certain network conditions.
108 * If this occurs a WATCHDOG message is logged in the system
109 * event log. In addition, the controller is automatically reset,
110 * restoring the network connection. To eliminate the potential
111 * for the hang ensure that IGB_RDTR is set to 0.
116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
117 * Valid Range: 0-65535 (0=off)
119 * This value, in units of 1.024 microseconds, limits the delay in which a
120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero,
121 * this value ensures that an interrupt is generated after the initial
122 * packet is received within the set amount of time. Proper tuning,
123 * along with IGB_RDTR, may improve traffic throughput in specific network
129 * This parameter controls the duration of transmit watchdog timer.
131 #define IGB_WATCHDOG (10 * hz)
134 * This parameter controls when the driver calls the routine to reclaim
135 * transmit descriptors.
137 #define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
138 #define IGB_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
141 * This parameter controls whether or not autonegotation is enabled.
142 * 0 - Disable autonegotiation
143 * 1 - Enable autonegotiation
145 #define DO_AUTO_NEG 1
148 * This parameter control whether or not the driver will wait for
149 * autonegotiation to complete.
150 * 1 - Wait for autonegotiation to complete
151 * 0 - Don't wait for autonegotiation to complete
153 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
155 /* Tunables -- End */
157 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
158 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
161 #define AUTO_ALL_MODES 0
163 /* PHY master/slave setting */
164 #define IGB_MASTER_SLAVE e1000_ms_hw_default
167 * Micellaneous constants
169 #define IGB_VENDOR_ID 0x8086
171 #define IGB_JUMBO_PBA 0x00000028
172 #define IGB_DEFAULT_PBA 0x00000030
173 #define IGB_SMARTSPEED_DOWNSHIFT 3
174 #define IGB_SMARTSPEED_MAX 15
175 #define IGB_MAX_LOOP 10
177 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
178 #define IGB_RX_HTHRESH 8
179 #define IGB_RX_WTHRESH 1
181 #define IGB_TX_PTHRESH 8
182 #define IGB_TX_HTHRESH 1
183 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
184 adapter->msix_mem) ? 1 : 16)
186 #define MAX_NUM_MULTICAST_ADDRESSES 128
187 #define PCI_ANY_ID (~0U)
188 #define ETHER_ALIGN 2
189 #define IGB_TX_BUFFER_SIZE ((uint32_t) 1514)
190 #define IGB_FC_PAUSE_TIME 0x0680
191 #define IGB_EEPROM_APME 0x400;
194 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
195 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
196 * also optimize cache line size effect. H/W supports up to cache line size 128.
198 #define IGB_DBA_ALIGN 128
200 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
202 /* PCI Config defines */
203 #define IGB_MSIX_BAR 3
206 ** This is the total number of MSIX vectors you wish
207 ** to use, it also controls the size of resources.
208 ** The 82575 has a total of 10, 82576 has 25. Set this
209 ** to the real amount you need to streamline data storage.
211 #define IGB_MSIX_VEC 6 /* MSIX vectors configured */
213 /* Defines for printing debug information */
215 #define DEBUG_IOCTL 0
218 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) kprintf(S "\n")
219 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) kprintf(S "\n", A)
220 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) kprintf(S "\n", A, B)
221 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) kprintf(S "\n")
222 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) kprintf(S "\n", A)
223 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) kprintf(S "\n", A, B)
224 #define HW_DEBUGOUT(S) if (DEBUG_HW) kprintf(S "\n")
225 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) kprintf(S "\n", A)
226 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) kprintf(S "\n", A, B)
228 #define IGB_MAX_SCATTER 64
229 #define IGB_VFTA_SIZE 128
230 #define IGB_BR_SIZE 4096 /* ring buf size */
231 #define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
232 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
233 #define IGB_HDR_BUF 128
234 #define IGB_PKTTYPE_MASK 0x0000FFF0
236 #define ETH_ADDR_LEN 6
238 /* Offload bits in mbuf flag */
239 #if __FreeBSD_version >= 800000
240 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
242 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
245 /* Define the starting Interrupt rate per Queue */
246 #define IGB_INTS_PER_SEC 8000
247 #define IGB_DEFAULT_ITR 1000000000/(IGB_INTS_PER_SEC * 256)
250 /* Header split codes for get_buf */
251 #define IGB_CLEAN_HEADER 0x01
252 #define IGB_CLEAN_PAYLOAD 0x02
253 #define IGB_CLEAN_BOTH (IGB_CLEAN_HEADER | IGB_CLEAN_PAYLOAD)
255 #define IGB_LINK_ITR 2000
257 /* Precision Time Sync (IEEE 1588) defines */
258 #define ETHERTYPE_IEEE1588 0x88F7
259 #define PICOSECS_PER_TICK 20833
260 #define TSYNC_PORT 319 /* UDP port for the protocol */
263 * Bus dma allocation structure used by
264 * e1000_dma_malloc and e1000_dma_free.
266 struct igb_dma_alloc {
267 bus_addr_t dma_paddr;
269 bus_dma_tag_t dma_tag;
270 bus_dmamap_t dma_map;
271 bus_dma_segment_t dma_seg;
277 ** Driver queue struct: this is the interrupt container
278 ** for the associated tx and rx ring.
281 struct adapter *adapter;
282 u32 msix; /* This queue's MSIX vector */
283 u32 eims; /* This queue's EIMS bit */
285 struct resource *res;
289 struct task que_task;
290 struct taskqueue *tq;
295 * Transmit ring: one per queue
298 struct adapter *adapter;
300 struct spinlock tx_spin;
302 struct igb_dma_alloc txdma;
303 struct e1000_tx_desc *tx_base;
306 volatile u16 tx_avail;
307 struct igb_tx_buffer *tx_buffers;
308 #if __FreeBSD_version >= 800000
323 * Receive ring: one per queue
326 struct adapter *adapter;
328 struct igb_dma_alloc rxdma;
329 union e1000_adv_rx_desc *rx_base;
336 struct spinlock rx_spin;
340 struct igb_rx_buf *rx_buffers;
341 bus_dma_tag_t rx_htag; /* dma tag for rx head */
342 bus_dmamap_t rx_hspare_map;
343 bus_dma_tag_t rx_ptag; /* dma tag for rx packet */
344 bus_dmamap_t rx_pspare_map;
346 * First/last mbuf pointers, for
347 * collecting multisegment RX packets.
356 u64 rx_split_packets;
363 struct arpcom arpcom;
367 struct e1000_osdep osdep;
370 struct resource *pci_mem;
371 struct resource *msix_mem;
372 struct resource *res;
378 struct task link_task;
381 struct ifmedia media;
382 struct callout timer;
383 int msix; /* total vectors allocated */
387 struct spinlock core_spin;
388 int igb_insert_vlan_header;
389 struct task rxtx_task;
390 struct taskqueue *tq; /* adapter task queue */
393 eventhandler_tag vlan_attach;
394 eventhandler_tag vlan_detach;
397 /* Management and WOL features */
401 /* Info about the board itself */
407 /* Interface queues */
408 struct igb_queue *queues;
413 struct tx_ring *tx_rings;
419 struct rx_ring *rx_rings;
422 int rx_process_limit;
426 /* Misc stats maintained by the driver */
427 unsigned long dropped_pkts;
428 unsigned long mbuf_defrag_failed;
429 unsigned long mbuf_header_failed;
430 unsigned long mbuf_packet_failed;
431 unsigned long no_tx_map_avail;
432 unsigned long no_tx_dma_setup;
433 unsigned long watchdog_events;
434 unsigned long rx_overruns;
439 /* IEEE 1588 precision time support */
440 struct cyclecounter cycles;
441 struct nettimer clock;
442 struct nettime_compare compare;
443 struct hwtstamp_ctrl hwtstamp;
446 /* sysctl tree glue */
447 struct sysctl_ctx_list sysctl_ctx;
448 struct sysctl_oid *sysctl_tree;
450 struct e1000_hw_stats stats;
453 /* ******************************************************************************
456 * This array contains the list of Subvendor/Subdevice IDs on which the driver
459 * ******************************************************************************/
460 typedef struct _igb_vendor_info_t {
461 unsigned int vendor_id;
462 unsigned int device_id;
463 unsigned int subvendor_id;
464 unsigned int subdevice_id;
469 struct igb_tx_buffer {
470 int next_eop; /* Index of the desc to watch */
472 bus_dmamap_t map; /* bus_dma map for packet */
478 bus_dmamap_t head_map; /* bus_dma map for packet */
479 bus_dmamap_t pack_map; /* bus_dma map for packet */
482 #define IGB_CORE_LOCK_INIT(_sc, _name) spin_init(&(_sc)->core_spin)
483 #define IGB_CORE_LOCK_DESTROY(_sc) spin_uninit(&(_sc)->core_spin)
484 #define IGB_CORE_LOCK(_sc) spin_lock(&(_sc)->core_spin)
485 #define IGB_CORE_UNLOCK(_sc) spin_unlock(&(_sc)->core_spin)
486 #define IGB_CORE_LOCK_ASSERT(_sc)
488 #define IGB_TX_LOCK_DESTROY(_sc) spin_uninit(&(_sc)->tx_spin)
489 #define IGB_TX_LOCK(_sc) spin_lock(&(_sc)->tx_spin)
490 #define IGB_TX_UNLOCK(_sc) spin_unlock(&(_sc)->tx_spin)
491 #define IGB_TX_TRYLOCK(_sc) spin_trylock(&(_sc)->tx_spin)
492 #define IGB_TX_LOCK_ASSERT(_sc)
494 #define IGB_RX_LOCK_DESTROY(_sc) spin_uninit(&(_sc)->rx_spin)
495 #define IGB_RX_LOCK(_sc) spin_lock(&(_sc)->rx_spin)
496 #define IGB_RX_UNLOCK(_sc) spin_unlock(&(_sc)->rx_spin)
497 #define IGB_TX_LOCK_ASSERT(_sc)
499 #endif /* _IGB_H_DEFINED_ */