sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.45 2005/08/19 14:43:30 joerg Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include <sys/param.h>
  76 #include <sys/systm.h>
  77 #include <sys/sockio.h>
  78 #include <sys/mbuf.h>
  79 #include <sys/malloc.h>
  80 #include <sys/kernel.h>
  81 #include <sys/socket.h>
  82 #include <sys/queue.h>
  83 #include <sys/thread2.h>
  84
  85 #include <net/if.h>
  86 #include <net/ifq_var.h>
  87 #include <net/if_arp.h>
  88 #include <net/ethernet.h>
  89 #include <net/if_dl.h>
  90 #include <net/if_media.h>
  91
  92 #include <net/bpf.h>
  93
  94 #include <net/if_types.h>
  95 #include <net/vlan/if_vlan_var.h>
  96
  97 #include <netinet/in_systm.h>
  98 #include <netinet/in.h>
  99 #include <netinet/ip.h>
 100
 101 #include <vm/vm.h>              /* for vtophys */
 102 #include <vm/pmap.h>            /* for vtophys */
 103 #include <machine/resource.h>
 104 #include <sys/bus.h>
 105 #include <sys/rman.h>
 106
 107 #include <dev/netif/mii_layer/mii.h>
 108 #include <dev/netif/mii_layer/miivar.h>
 109 #include <dev/netif/mii_layer/miidevs.h>
 110 #include <dev/netif/mii_layer/brgphyreg.h>
 111
 112 #include <bus/pci/pcidevs.h>
 113 #include <bus/pci/pcireg.h>
 114 #include <bus/pci/pcivar.h>
 115
 116 #include "if_bgereg.h"
 117
 118 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 119
 120 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 121 #include "miibus_if.h"
 122
 123 /*
 124  * Various supported device vendors/types and their names. Note: the
 125  * spec seems to indicate that the hardware still has Alteon's vendor
 126  * ID burned into it, though it will always be overriden by the vendor
 127  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 128  */
 129 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 130
 131 static struct bge_type bge_devs[] = {
 132         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 133                 "Alteon BCM5700 Gigabit Ethernet" },
 134         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 135                 "Alteon BCM5701 Gigabit Ethernet" },
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 141                 "Broadcom BCM5702X Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 143                 "Broadcom BCM5702 Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 145                 "Broadcom BCM5703X Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 149                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 151                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 153                 "Broadcom BCM5705 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 155                 "Broadcom BCM5705K Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 157                 "Broadcom BCM5705M Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 159                 "Broadcom BCM5705M Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5714C,
 161                 "Broadcom BCM5714C Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 163                 "Broadcom BCM5721 Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 165                 "Broadcom BCM5750 Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 167                 "Broadcom BCM5750M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 169                 "Broadcom BCM5751 Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 171                 "Broadcom BCM5751M Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 173                 "Broadcom BCM5782 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 175                 "Broadcom BCM5788 Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 177                 "Broadcom BCM5789 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 179                 "Broadcom BCM5901 Fast Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 181                 "Broadcom BCM5901A2 Fast Ethernet" },
 182         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 183                 "SysKonnect Gigabit Ethernet" },
 184         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 185                 "Altima AC1000 Gigabit Ethernet" },
 186         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 187                 "Altima AC1002 Gigabit Ethernet" },
 188         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 189                 "Altima AC9100 Gigabit Ethernet" },
 190         { 0, 0, NULL }
 191 };
 192
 193 static int      bge_probe(device_t);
 194 static int      bge_attach(device_t);
 195 static int      bge_detach(device_t);
 196 static void     bge_release_resources(struct bge_softc *);
 197 static void     bge_txeof(struct bge_softc *);
 198 static void     bge_rxeof(struct bge_softc *);
 199
 200 static void     bge_tick(void *);
 201 static void     bge_stats_update(struct bge_softc *);
 202 static void     bge_stats_update_regs(struct bge_softc *);
 203 static int      bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
 204
 205 static void     bge_intr(void *);
 206 static void     bge_start(struct ifnet *);
 207 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 208 static void     bge_init(void *);
 209 static void     bge_stop(struct bge_softc *);
 210 static void     bge_watchdog(struct ifnet *);
 211 static void     bge_shutdown(device_t);
 212 static int      bge_ifmedia_upd(struct ifnet *);
 213 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 214
 215 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 216 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 217
 218 static void     bge_setmulti(struct bge_softc *);
 219
 220 static void     bge_handle_events(struct bge_softc *);
 221 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 222 static void     bge_free_jumbo_mem(struct bge_softc *);
 223 static struct bge_jslot
 224                 *bge_jalloc(struct bge_softc *);
 225 static void     bge_jfree(void *);
 226 static void     bge_jref(void *);
 227 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 228 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 229 static int      bge_init_rx_ring_std(struct bge_softc *);
 230 static void     bge_free_rx_ring_std(struct bge_softc *);
 231 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 232 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 233 static void     bge_free_tx_ring(struct bge_softc *);
 234 static int      bge_init_tx_ring(struct bge_softc *);
 235
 236 static int      bge_chipinit(struct bge_softc *);
 237 static int      bge_blockinit(struct bge_softc *);
 238
 239 #ifdef notdef
 240 static uint8_t  bge_vpd_readbyte(struct bge_softc *, uint32_t);
 241 static void     bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
 242 static void     bge_vpd_read(struct bge_softc *);
 243 #endif
 244
 245 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 246 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 247 #ifdef notdef
 248 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 249 #endif
 250 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 251
 252 static int      bge_miibus_readreg(device_t, int, int);
 253 static int      bge_miibus_writereg(device_t, int, int, int);
 254 static void     bge_miibus_statchg(device_t);
 255
 256 static void     bge_reset(struct bge_softc *);
 257
 258 static device_method_t bge_methods[] = {
 259         /* Device interface */
 260         DEVMETHOD(device_probe,         bge_probe),
 261         DEVMETHOD(device_attach,        bge_attach),
 262         DEVMETHOD(device_detach,        bge_detach),
 263         DEVMETHOD(device_shutdown,      bge_shutdown),
 264
 265         /* bus interface */
 266         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 267         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 268
 269         /* MII interface */
 270         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 271         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 272         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 273
 274         { 0, 0 }
 275 };
 276
 277 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 278 static devclass_t bge_devclass;
 279
 280 DECLARE_DUMMY_MODULE(if_bge);
 281 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 282 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 283
 284 static uint32_t
 285 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 286 {
 287         device_t dev = sc->bge_dev;
 288
 289         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 290         return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
 291 }
 292
 293 static void
 294 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 295 {
 296         device_t dev = sc->bge_dev;
 297
 298         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 299         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 300 }
 301
 302 #ifdef notdef
 303 static uint32_t
 304 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 305 {
 306         device_t dev = sc->bge_dev;
 307
 308         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 309         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 310 }
 311 #endif
 312
 313 static void
 314 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 315 {
 316         device_t dev = sc->bge_dev;
 317
 318         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 319         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 320 }
 321
 322 #ifdef notdef
 323 static uint8_t
 324 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
 325 {
 326         device_t dev = sc->bge_dev;
 327         uint32_t val;
 328         int i;
 329
 330         pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
 331         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 332                 DELAY(10);
 333                 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
 334                         break;
 335         }
 336
 337         if (i == BGE_TIMEOUT) {
 338                 device_printf(sc->bge_dev, "VPD read timed out\n");
 339                 return(0);
 340         }
 341
 342         val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
 343
 344         return((val >> ((addr % 4) * 8)) & 0xFF);
 345 }
 346
 347 static void
 348 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
 349 {
 350         size_t i;
 351         uint8_t *ptr;
 352
 353         ptr = (uint8_t *)res;
 354         for (i = 0; i < sizeof(struct vpd_res); i++)
 355                 ptr[i] = bge_vpd_readbyte(sc, i + addr);
 356
 357         return;
 358 }
 359
 360 static void
 361 bge_vpd_read(struct bge_softc *sc)
 362 {
 363         int pos = 0, i;
 364         struct vpd_res res;
 365
 366         if (sc->bge_vpd_prodname != NULL)
 367                 free(sc->bge_vpd_prodname, M_DEVBUF);
 368         if (sc->bge_vpd_readonly != NULL)
 369                 free(sc->bge_vpd_readonly, M_DEVBUF);
 370         sc->bge_vpd_prodname = NULL;
 371         sc->bge_vpd_readonly = NULL;
 372
 373         bge_vpd_read_res(sc, &res, pos);
 374
 375         if (res.vr_id != VPD_RES_ID) {
 376                 device_printf(sc->bge_dev,
 377                               "bad VPD resource id: expected %x got %x\n",
 378                               VPD_RES_ID, res.vr_id);
 379                 return;
 380         }
 381
 382         pos += sizeof(res);
 383         sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
 384         for (i = 0; i < res.vr_len; i++)
 385                 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
 386         sc->bge_vpd_prodname[i] = '\0';
 387         pos += i;
 388
 389         bge_vpd_read_res(sc, &res, pos);
 390
 391         if (res.vr_id != VPD_RES_READ) {
 392                 device_printf(sc->bge_dev,
 393                               "bad VPD resource id: expected %x got %x\n",
 394                               VPD_RES_READ, res.vr_id);
 395                 return;
 396         }
 397
 398         pos += sizeof(res);
 399         sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
 400         for (i = 0; i < res.vr_len + 1; i++)
 401                 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
 402 }
 403 #endif
 404
 405 /*
 406  * Read a byte of data stored in the EEPROM at address 'addr.' The
 407  * BCM570x supports both the traditional bitbang interface and an
 408  * auto access interface for reading the EEPROM. We use the auto
 409  * access method.
 410  */
 411 static uint8_t
 412 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 413 {
 414         int i;
 415         uint32_t byte = 0;
 416
 417         /*
 418          * Enable use of auto EEPROM access so we can avoid
 419          * having to use the bitbang method.
 420          */
 421         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 422
 423         /* Reset the EEPROM, load the clock period. */
 424         CSR_WRITE_4(sc, BGE_EE_ADDR,
 425             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 426         DELAY(20);
 427
 428         /* Issue the read EEPROM command. */
 429         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 430
 431         /* Wait for completion */
 432         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 433                 DELAY(10);
 434                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 435                         break;
 436         }
 437
 438         if (i == BGE_TIMEOUT) {
 439                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 440                 return(0);
 441         }
 442
 443         /* Get result. */
 444         byte = CSR_READ_4(sc, BGE_EE_DATA);
 445
 446         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 447
 448         return(0);
 449 }
 450
 451 /*
 452  * Read a sequence of bytes from the EEPROM.
 453  */
 454 static int
 455 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 456 {
 457         size_t i;
 458         int err;
 459         uint8_t byte;
 460
 461         for (byte = 0, err = 0, i = 0; i < len; i++) {
 462                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 463                 if (err)
 464                         break;
 465                 *(dest + i) = byte;
 466         }
 467
 468         return(err ? 1 : 0);
 469 }
 470
 471 static int
 472 bge_miibus_readreg(device_t dev, int phy, int reg)
 473 {
 474         struct bge_softc *sc;
 475         struct ifnet *ifp;
 476         uint32_t val, autopoll;
 477         int i;
 478
 479         sc = device_get_softc(dev);
 480         ifp = &sc->arpcom.ac_if;
 481
 482         /*
 483          * Broadcom's own driver always assumes the internal
 484          * PHY is at GMII address 1. On some chips, the PHY responds
 485          * to accesses at all addresses, which could cause us to
 486          * bogusly attach the PHY 32 times at probe type. Always
 487          * restricting the lookup to address 1 is simpler than
 488          * trying to figure out which chips revisions should be
 489          * special-cased.
 490          */
 491         if (phy != 1)
 492                 return(0);
 493
 494         /* Reading with autopolling on may trigger PCI errors */
 495         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 496         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 497                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 498                 DELAY(40);
 499         }
 500
 501         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 502             BGE_MIPHY(phy)|BGE_MIREG(reg));
 503
 504         for (i = 0; i < BGE_TIMEOUT; i++) {
 505                 val = CSR_READ_4(sc, BGE_MI_COMM);
 506                 if (!(val & BGE_MICOMM_BUSY))
 507                         break;
 508         }
 509
 510         if (i == BGE_TIMEOUT) {
 511                 if_printf(ifp, "PHY read timed out\n");
 512                 val = 0;
 513                 goto done;
 514         }
 515
 516         val = CSR_READ_4(sc, BGE_MI_COMM);
 517
 518 done:
 519         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 520                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 521                 DELAY(40);
 522         }
 523
 524         if (val & BGE_MICOMM_READFAIL)
 525                 return(0);
 526
 527         return(val & 0xFFFF);
 528 }
 529
 530 static int
 531 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 532 {
 533         struct bge_softc *sc;
 534         uint32_t autopoll;
 535         int i;
 536
 537         sc = device_get_softc(dev);
 538
 539         /* Reading with autopolling on may trigger PCI errors */
 540         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 541         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 542                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 543                 DELAY(40);
 544         }
 545
 546         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 547             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 548
 549         for (i = 0; i < BGE_TIMEOUT; i++) {
 550                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 551                         break;
 552         }
 553
 554         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 555                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 556                 DELAY(40);
 557         }
 558
 559         if (i == BGE_TIMEOUT) {
 560                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 561                 return(0);
 562         }
 563
 564         return(0);
 565 }
 566
 567 static void
 568 bge_miibus_statchg(device_t dev)
 569 {
 570         struct bge_softc *sc;
 571         struct mii_data *mii;
 572
 573         sc = device_get_softc(dev);
 574         mii = device_get_softc(sc->bge_miibus);
 575
 576         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 577         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 578                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 579         } else {
 580                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 581         }
 582
 583         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 584                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 585         } else {
 586                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 587         }
 588 }
 589
 590 /*
 591  * Handle events that have triggered interrupts.
 592  */
 593 static void
 594 bge_handle_events(struct bge_softc *sc)
 595 {
 596 }
 597
 598 /*
 599  * Memory management for jumbo frames.
 600  */
 601 static int
 602 bge_alloc_jumbo_mem(struct bge_softc *sc)
 603 {
 604         struct bge_jslot *entry;
 605         caddr_t ptr;
 606         int i;
 607
 608         /* Grab a big chunk o' storage. */
 609         sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
 610                 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
 611
 612         if (sc->bge_cdata.bge_jumbo_buf == NULL) {
 613                 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
 614                 return(ENOBUFS);
 615         }
 616
 617         SLIST_INIT(&sc->bge_jfree_listhead);
 618
 619         /*
 620          * Now divide it up into 9K pieces and save the addresses
 621          * in an array. Note that we play an evil trick here by using
 622          * the first few bytes in the buffer to hold the the address
 623          * of the softc structure for this interface. This is because
 624          * bge_jfree() needs it, but it is called by the mbuf management
 625          * code which will not pass it to us explicitly.
 626          */
 627         ptr = sc->bge_cdata.bge_jumbo_buf;
 628         for (i = 0; i < BGE_JSLOTS; i++) {
 629                 entry = &sc->bge_cdata.bge_jslots[i];
 630                 entry->bge_sc = sc;
 631                 entry->bge_buf = ptr;
 632                 entry->bge_inuse = 0;
 633                 entry->bge_slot = i;
 634                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 635                 ptr += BGE_JLEN;
 636         }
 637
 638         return(0);
 639 }
 640
 641 static void
 642 bge_free_jumbo_mem(struct bge_softc *sc)
 643 {
 644         if (sc->bge_cdata.bge_jumbo_buf)
 645                 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
 646 }
 647
 648 /*
 649  * Allocate a jumbo buffer.
 650  */
 651 static struct bge_jslot *
 652 bge_jalloc(struct bge_softc *sc)
 653 {
 654         struct bge_jslot *entry;
 655
 656         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 657
 658         if (entry == NULL) {
 659                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 660                 return(NULL);
 661         }
 662
 663         SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 664         entry->bge_inuse = 1;
 665         return(entry);
 666 }
 667
 668 /*
 669  * Adjust usage count on a jumbo buffer.
 670  */
 671 static void
 672 bge_jref(void *arg)
 673 {
 674         struct bge_jslot *entry = (struct bge_jslot *)arg;
 675         struct bge_softc *sc = entry->bge_sc;
 676
 677         if (sc == NULL)
 678                 panic("bge_jref: can't find softc pointer!");
 679
 680         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
 681                 panic("bge_jref: asked to reference buffer "
 682                     "that we don't manage!");
 683         else if (entry->bge_inuse == 0)
 684                 panic("bge_jref: buffer already free!");
 685         else
 686                 entry->bge_inuse++;
 687 }
 688
 689 /*
 690  * Release a jumbo buffer.
 691  */
 692 static void
 693 bge_jfree(void *arg)
 694 {
 695         struct bge_jslot *entry = (struct bge_jslot *)arg;
 696         struct bge_softc *sc = entry->bge_sc;
 697
 698         if (sc == NULL)
 699                 panic("bge_jfree: can't find softc pointer!");
 700
 701         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
 702                 panic("bge_jfree: asked to free buffer that we don't manage!");
 703         else if (entry->bge_inuse == 0)
 704                 panic("bge_jfree: buffer already free!");
 705         else if (--entry->bge_inuse == 0)
 706                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 707 }
 708
 709
 710 /*
 711  * Intialize a standard receive ring descriptor.
 712  */
 713 static int
 714 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 715 {
 716         struct mbuf *m_new = NULL;
 717         struct bge_rx_bd *r;
 718
 719         if (m == NULL) {
 720                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 721                 if (m_new == NULL)
 722                         return (ENOBUFS);
 723                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 724         } else {
 725                 m_new = m;
 726                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 727                 m_new->m_data = m_new->m_ext.ext_buf;
 728         }
 729
 730         if (!sc->bge_rx_alignment_bug)
 731                 m_adj(m_new, ETHER_ALIGN);
 732         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 733         r = &sc->bge_rdata->bge_rx_std_ring[i];
 734         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 735         r->bge_flags = BGE_RXBDFLAG_END;
 736         r->bge_len = m_new->m_len;
 737         r->bge_idx = i;
 738
 739         return(0);
 740 }
 741
 742 /*
 743  * Initialize a jumbo receive ring descriptor. This allocates
 744  * a jumbo buffer from the pool managed internally by the driver.
 745  */
 746 static int
 747 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 748 {
 749         struct mbuf *m_new = NULL;
 750         struct bge_rx_bd *r;
 751
 752         if (m == NULL) {
 753                 struct bge_jslot *buf;
 754
 755                 /* Allocate the mbuf. */
 756                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 757                 if (m_new == NULL)
 758                         return(ENOBUFS);
 759
 760                 /* Allocate the jumbo buffer */
 761                 buf = bge_jalloc(sc);
 762                 if (buf == NULL) {
 763                         m_freem(m_new);
 764                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 765                             "-- packet dropped!\n");
 766                         return(ENOBUFS);
 767                 }
 768
 769                 /* Attach the buffer to the mbuf. */
 770                 m_new->m_ext.ext_arg = buf;
 771                 m_new->m_ext.ext_buf = buf->bge_buf;
 772                 m_new->m_ext.ext_free = bge_jfree;
 773                 m_new->m_ext.ext_ref = bge_jref;
 774                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 775
 776                 m_new->m_data = m_new->m_ext.ext_buf;
 777                 m_new->m_flags |= M_EXT;
 778                 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 779         } else {
 780                 m_new = m;
 781                 m_new->m_data = m_new->m_ext.ext_buf;
 782                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 783         }
 784
 785         if (!sc->bge_rx_alignment_bug)
 786                 m_adj(m_new, ETHER_ALIGN);
 787         /* Set up the descriptor. */
 788         r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
 789         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 790         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 791         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 792         r->bge_len = m_new->m_len;
 793         r->bge_idx = i;
 794
 795         return(0);
 796 }
 797
 798 /*
 799  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 800  * that's 1MB or memory, which is a lot. For now, we fill only the first
 801  * 256 ring entries and hope that our CPU is fast enough to keep up with
 802  * the NIC.
 803  */
 804 static int
 805 bge_init_rx_ring_std(struct bge_softc *sc)
 806 {
 807         int i;
 808
 809         for (i = 0; i < BGE_SSLOTS; i++) {
 810                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 811                         return(ENOBUFS);
 812         };
 813
 814         sc->bge_std = i - 1;
 815         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 816
 817         return(0);
 818 }
 819
 820 static void
 821 bge_free_rx_ring_std(struct bge_softc *sc)
 822 {
 823         int i;
 824
 825         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 826                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 827                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 828                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 829                 }
 830                 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
 831                     sizeof(struct bge_rx_bd));
 832         }
 833 }
 834
 835 static int
 836 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 837 {
 838         int i;
 839         struct bge_rcb *rcb;
 840
 841         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 842                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 843                         return(ENOBUFS);
 844         };
 845
 846         sc->bge_jumbo = i - 1;
 847
 848         rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 849         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 850         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 851
 852         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 853
 854         return(0);
 855 }
 856
 857 static void
 858 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 859 {
 860         int i;
 861
 862         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 863                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 864                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 865                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 866                 }
 867                 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
 868                     sizeof(struct bge_rx_bd));
 869         }
 870 }
 871
 872 static void
 873 bge_free_tx_ring(struct bge_softc *sc)
 874 {
 875         int i;
 876
 877         if (sc->bge_rdata->bge_tx_ring == NULL)
 878                 return;
 879
 880         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 881                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 882                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 883                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 884                 }
 885                 bzero(&sc->bge_rdata->bge_tx_ring[i],
 886                     sizeof(struct bge_tx_bd));
 887         }
 888 }
 889
 890 static int
 891 bge_init_tx_ring(struct bge_softc *sc)
 892 {
 893         sc->bge_txcnt = 0;
 894         sc->bge_tx_saved_considx = 0;
 895
 896         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 897         /* 5700 b2 errata */
 898         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 899                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 900
 901         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 902         /* 5700 b2 errata */
 903         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 904                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 905
 906         return(0);
 907 }
 908
 909 static void
 910 bge_setmulti(struct bge_softc *sc)
 911 {
 912         struct ifnet *ifp;
 913         struct ifmultiaddr *ifma;
 914         uint32_t hashes[4] = { 0, 0, 0, 0 };
 915         int h, i;
 916
 917         ifp = &sc->arpcom.ac_if;
 918
 919         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 920                 for (i = 0; i < 4; i++)
 921                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 922                 return;
 923         }
 924
 925         /* First, zot all the existing filters. */
 926         for (i = 0; i < 4; i++)
 927                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 928
 929         /* Now program new ones. */
 930         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 931                 if (ifma->ifma_addr->sa_family != AF_LINK)
 932                         continue;
 933                 h = ether_crc32_le(
 934                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 935                     ETHER_ADDR_LEN) & 0x7f;
 936                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 937         }
 938
 939         for (i = 0; i < 4; i++)
 940                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 941 }
 942
 943 /*
 944  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 945  * self-test results.
 946  */
 947 static int
 948 bge_chipinit(struct bge_softc *sc)
 949 {
 950         int i;
 951         uint32_t dma_rw_ctl;
 952
 953         /* Set endianness before we access any non-PCI registers. */
 954 #if BYTE_ORDER == BIG_ENDIAN
 955         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 956             BGE_BIGENDIAN_INIT, 4);
 957 #else
 958         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 959             BGE_LITTLEENDIAN_INIT, 4);
 960 #endif
 961
 962         /*
 963          * Check the 'ROM failed' bit on the RX CPU to see if
 964          * self-tests passed.
 965          */
 966         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
 967                 if_printf(&sc->arpcom.ac_if,
 968                           "RX CPU self-diagnostics failed!\n");
 969                 return(ENODEV);
 970         }
 971
 972         /* Clear the MAC control register */
 973         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 974
 975         /*
 976          * Clear the MAC statistics block in the NIC's
 977          * internal memory.
 978          */
 979         for (i = BGE_STATS_BLOCK;
 980             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 981                 BGE_MEMWIN_WRITE(sc, i, 0);
 982
 983         for (i = BGE_STATUS_BLOCK;
 984             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
 985                 BGE_MEMWIN_WRITE(sc, i, 0);
 986
 987         /* Set up the PCI DMA control register. */
 988         if (sc->bge_pcie) {
 989                 /* PCI Express */
 990                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 991                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 992                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 993         } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
 994                    BGE_PCISTATE_PCI_BUSMODE) {
 995                 /* Conventional PCI bus */
 996                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 997                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 998                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 999                     (0x0F);
1000         } else {
1001                 /* PCI-X bus */
1002                 /*
1003                  * The 5704 uses a different encoding of read/write
1004                  * watermarks.
1005                  */
1006                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1007                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1008                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1009                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1010                 else
1011                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1012                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1013                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1014                             (0x0F);
1015
1016                 /*
1017                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1018                  * for hardware bugs.
1019                  */
1020                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1021                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1022                         uint32_t tmp;
1023
1024                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1025                         if (tmp == 0x6 || tmp == 0x7)
1026                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1027                 }
1028         }
1029
1030         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1031             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1032             sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1033             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1034                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1035         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1036
1037         /*
1038          * Set up general mode register.
1039          */
1040         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1041             BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1042             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1043             BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1044
1045         /*
1046          * Disable memory write invalidate.  Apparently it is not supported
1047          * properly by these devices.
1048          */
1049         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1050
1051         /* Set the timer prescaler (always 66Mhz) */
1052         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1053
1054         return(0);
1055 }
1056
1057 static int
1058 bge_blockinit(struct bge_softc *sc)
1059 {
1060         struct bge_rcb *rcb;
1061         volatile struct bge_rcb *vrcb;
1062         int i;
1063
1064         /*
1065          * Initialize the memory window pointer register so that
1066          * we can access the first 32K of internal NIC RAM. This will
1067          * allow us to set up the TX send ring RCBs and the RX return
1068          * ring RCBs, plus other things which live in NIC memory.
1069          */
1070         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1071
1072         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1073
1074         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1075             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1076                 /* Configure mbuf memory pool */
1077                 if (sc->bge_extram) {
1078                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1079                             BGE_EXT_SSRAM);
1080                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1081                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1082                         else
1083                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1084                 } else {
1085                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1086                             BGE_BUFFPOOL_1);
1087                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1088                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1089                         else
1090                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1091                 }
1092
1093                 /* Configure DMA resource pool */
1094                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1095                     BGE_DMA_DESCRIPTORS);
1096                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1097         }
1098
1099         /* Configure mbuf pool watermarks */
1100         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1101             sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1102                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1103                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1104         } else {
1105                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1106                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1107         }
1108         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1109
1110         /* Configure DMA resource watermarks */
1111         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1112         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1113
1114         /* Enable buffer manager */
1115         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1116             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1117                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1118                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1119
1120                 /* Poll for buffer manager start indication */
1121                 for (i = 0; i < BGE_TIMEOUT; i++) {
1122                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1123                                 break;
1124                         DELAY(10);
1125                 }
1126
1127                 if (i == BGE_TIMEOUT) {
1128                         if_printf(&sc->arpcom.ac_if,
1129                                   "buffer manager failed to start\n");
1130                         return(ENXIO);
1131                 }
1132         }
1133
1134         /* Enable flow-through queues */
1135         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1136         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1137
1138         /* Wait until queue initialization is complete */
1139         for (i = 0; i < BGE_TIMEOUT; i++) {
1140                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1141                         break;
1142                 DELAY(10);
1143         }
1144
1145         if (i == BGE_TIMEOUT) {
1146                 if_printf(&sc->arpcom.ac_if,
1147                           "flow-through queue init failed\n");
1148                 return(ENXIO);
1149         }
1150
1151         /* Initialize the standard RX ring control block */
1152         rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1153         BGE_HOSTADDR(rcb->bge_hostaddr,
1154             vtophys(&sc->bge_rdata->bge_rx_std_ring));
1155         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1156             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1157                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1158         else
1159                 rcb->bge_maxlen_flags =
1160                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1161         if (sc->bge_extram)
1162                 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1163         else
1164                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1165         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1166         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1167         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1168         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1169
1170         /*
1171          * Initialize the jumbo RX ring control block
1172          * We set the 'ring disabled' bit in the flags
1173          * field until we're actually ready to start
1174          * using this ring (i.e. once we set the MTU
1175          * high enough to require it).
1176          */
1177         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1178             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1179                 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1180                 BGE_HOSTADDR(rcb->bge_hostaddr,
1181                     vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1182                 rcb->bge_maxlen_flags =
1183                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1184                     BGE_RCB_FLAG_RING_DISABLED);
1185                 if (sc->bge_extram)
1186                         rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1187                 else
1188                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1189                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1190                     rcb->bge_hostaddr.bge_addr_hi);
1191                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1192                     rcb->bge_hostaddr.bge_addr_lo);
1193                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1194                     rcb->bge_maxlen_flags);
1195                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1196
1197                 /* Set up dummy disabled mini ring RCB */
1198                 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1199                 rcb->bge_maxlen_flags =
1200                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1201                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1202                     rcb->bge_maxlen_flags);
1203         }
1204
1205         /*
1206          * Set the BD ring replentish thresholds. The recommended
1207          * values are 1/8th the number of descriptors allocated to
1208          * each ring.
1209          */
1210         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1211         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1212
1213         /*
1214          * Disable all unused send rings by setting the 'ring disabled'
1215          * bit in the flags field of all the TX send ring control blocks.
1216          * These are located in NIC memory.
1217          */
1218         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1219             BGE_SEND_RING_RCB);
1220         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1221                 vrcb->bge_maxlen_flags =
1222                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1223                 vrcb->bge_nicaddr = 0;
1224                 vrcb++;
1225         }
1226
1227         /* Configure TX RCB 0 (we use only the first ring) */
1228         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1229             BGE_SEND_RING_RCB);
1230         vrcb->bge_hostaddr.bge_addr_hi = 0;
1231         BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1232         vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1233         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1234             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1235                 vrcb->bge_maxlen_flags =
1236                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1237
1238         /* Disable all unused RX return rings */
1239         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1240             BGE_RX_RETURN_RING_RCB);
1241         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1242                 vrcb->bge_hostaddr.bge_addr_hi = 0;
1243                 vrcb->bge_hostaddr.bge_addr_lo = 0;
1244                 vrcb->bge_maxlen_flags =
1245                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1246                     BGE_RCB_FLAG_RING_DISABLED);
1247                 vrcb->bge_nicaddr = 0;
1248                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1249                     (i * (sizeof(uint64_t))), 0);
1250                 vrcb++;
1251         }
1252
1253         /* Initialize RX ring indexes */
1254         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1255         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1256         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1257
1258         /*
1259          * Set up RX return ring 0
1260          * Note that the NIC address for RX return rings is 0x00000000.
1261          * The return rings live entirely within the host, so the
1262          * nicaddr field in the RCB isn't used.
1263          */
1264         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1265             BGE_RX_RETURN_RING_RCB);
1266         vrcb->bge_hostaddr.bge_addr_hi = 0;
1267         BGE_HOSTADDR(vrcb->bge_hostaddr,
1268             vtophys(&sc->bge_rdata->bge_rx_return_ring));
1269         vrcb->bge_nicaddr = 0x00000000;
1270         vrcb->bge_maxlen_flags =
1271             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1272
1273         /* Set random backoff seed for TX */
1274         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1275             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1276             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1277             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1278             BGE_TX_BACKOFF_SEED_MASK);
1279
1280         /* Set inter-packet gap */
1281         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1282
1283         /*
1284          * Specify which ring to use for packets that don't match
1285          * any RX rules.
1286          */
1287         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1288
1289         /*
1290          * Configure number of RX lists. One interrupt distribution
1291          * list, sixteen active lists, one bad frames class.
1292          */
1293         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1294
1295         /* Inialize RX list placement stats mask. */
1296         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1297         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1298
1299         /* Disable host coalescing until we get it set up */
1300         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1301
1302         /* Poll to make sure it's shut down. */
1303         for (i = 0; i < BGE_TIMEOUT; i++) {
1304                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1305                         break;
1306                 DELAY(10);
1307         }
1308
1309         if (i == BGE_TIMEOUT) {
1310                 if_printf(&sc->arpcom.ac_if,
1311                           "host coalescing engine failed to idle\n");
1312                 return(ENXIO);
1313         }
1314
1315         /* Set up host coalescing defaults */
1316         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1317         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1318         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1319         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1320         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1321             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1322                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1323                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1324         }
1325         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1326         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1327
1328         /* Set up address of statistics block */
1329         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1330             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1331                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1332                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1333                     vtophys(&sc->bge_rdata->bge_info.bge_stats));
1334
1335                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1336                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1337                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1338         }
1339
1340         /* Set up address of status block */
1341         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1342         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1343             vtophys(&sc->bge_rdata->bge_status_block));
1344
1345         sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1346         sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1347
1348         /* Turn on host coalescing state machine */
1349         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1350
1351         /* Turn on RX BD completion state machine and enable attentions */
1352         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1353             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1354
1355         /* Turn on RX list placement state machine */
1356         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1357
1358         /* Turn on RX list selector state machine. */
1359         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1360             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1361                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1362
1363         /* Turn on DMA, clear stats */
1364         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1365             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1366             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1367             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1368             (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1369
1370         /* Set misc. local control, enable interrupts on attentions */
1371         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1372
1373 #ifdef notdef
1374         /* Assert GPIO pins for PHY reset */
1375         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1376             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1377         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1378             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1379 #endif
1380
1381         /* Turn on DMA completion state machine */
1382         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1383             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1384                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1385
1386         /* Turn on write DMA state machine */
1387         CSR_WRITE_4(sc, BGE_WDMA_MODE,
1388             BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1389
1390         /* Turn on read DMA state machine */
1391         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1392             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1393
1394         /* Turn on RX data completion state machine */
1395         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1396
1397         /* Turn on RX BD initiator state machine */
1398         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1399
1400         /* Turn on RX data and RX BD initiator state machine */
1401         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1402
1403         /* Turn on Mbuf cluster free state machine */
1404         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1405             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1406                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1407
1408         /* Turn on send BD completion state machine */
1409         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1410
1411         /* Turn on send data completion state machine */
1412         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1413
1414         /* Turn on send data initiator state machine */
1415         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1416
1417         /* Turn on send BD initiator state machine */
1418         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1419
1420         /* Turn on send BD selector state machine */
1421         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1422
1423         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1424         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1425             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1426
1427         /* ack/clear link change events */
1428         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1429             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1430             BGE_MACSTAT_LINK_CHANGED);
1431
1432         /* Enable PHY auto polling (for MII/GMII only) */
1433         if (sc->bge_tbi) {
1434                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1435         } else {
1436                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1437                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1438                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1439                             BGE_EVTENB_MI_INTERRUPT);
1440         }
1441
1442         /* Enable link state change attentions. */
1443         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1444
1445         return(0);
1446 }
1447
1448 /*
1449  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1450  * against our list and return its name if we find a match. Note
1451  * that since the Broadcom controller contains VPD support, we
1452  * can get the device name string from the controller itself instead
1453  * of the compiled-in string. This is a little slow, but it guarantees
1454  * we'll always announce the right product name.
1455  */
1456 static int
1457 bge_probe(device_t dev)
1458 {
1459         struct bge_softc *sc;
1460         struct bge_type *t;
1461         char *descbuf;
1462         uint16_t product, vendor;
1463
1464         product = pci_get_device(dev);
1465         vendor = pci_get_vendor(dev);
1466
1467         for (t = bge_devs; t->bge_name != NULL; t++) {
1468                 if (vendor == t->bge_vid && product == t->bge_did)
1469                         break;
1470         }
1471
1472         if (t->bge_name == NULL)
1473                 return(ENXIO);
1474
1475         sc = device_get_softc(dev);
1476 #ifdef notdef
1477         sc->bge_dev = dev;
1478
1479         bge_vpd_read(sc);
1480         device_set_desc(dev, sc->bge_vpd_prodname);
1481 #endif
1482         descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1483         snprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1484             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1485         device_set_desc_copy(dev, descbuf);
1486         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1487                 sc->bge_no_3_led = 1;
1488         free(descbuf, M_TEMP);
1489         return(0);
1490 }
1491
1492 static int
1493 bge_attach(device_t dev)
1494 {
1495         struct ifnet *ifp;
1496         struct bge_softc *sc;
1497         uint32_t hwcfg = 0;
1498         uint32_t mac_addr = 0;
1499         int error = 0, rid;
1500         uint8_t ether_addr[ETHER_ADDR_LEN];
1501
1502         sc = device_get_softc(dev);
1503         sc->bge_dev = dev;
1504         callout_init(&sc->bge_stat_timer);
1505
1506         /*
1507          * Map control/status registers.
1508          */
1509         pci_enable_busmaster(dev);
1510
1511         rid = BGE_PCI_BAR0;
1512         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1513             RF_ACTIVE);
1514
1515         if (sc->bge_res == NULL) {
1516                 device_printf(dev, "couldn't map memory\n");
1517                 error = ENXIO;
1518                 return(error);
1519         }
1520
1521         sc->bge_btag = rman_get_bustag(sc->bge_res);
1522         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1523         sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1524
1525         /* Allocate interrupt */
1526         rid = 0;
1527
1528         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1529             RF_SHAREABLE | RF_ACTIVE);
1530
1531         if (sc->bge_irq == NULL) {
1532                 device_printf(dev, "couldn't map interrupt\n");
1533                 error = ENXIO;
1534                 goto fail;
1535         }
1536
1537         /* Save ASIC rev. */
1538         sc->bge_chipid =
1539             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1540             BGE_PCIMISCCTL_ASICREV;
1541         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1542         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1543
1544         /*
1545          * Treat the 5714 like the 5750 until we have more info
1546          * on this chip.
1547          */
1548         if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
1549                 sc->bge_asicrev = BGE_ASICREV_BCM5750;
1550
1551         /*
1552          * XXX: Broadcom Linux driver.  Not in specs or eratta.
1553          * PCI-Express?
1554          */
1555         if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1556                 uint32_t v;
1557
1558                 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
1559                 if (((v >> 8) & 0xff) == BGE_PCIE_MSI_CAPID) {
1560                         v = pci_read_config(dev, BGE_PCIE_MSI_CAPID, 4);
1561                         if ((v & 0xff) == BGE_PCIE_MSI_CAPID_VAL)
1562                                 sc->bge_pcie = 1;
1563                 }
1564         }
1565
1566         ifp = &sc->arpcom.ac_if;
1567         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1568
1569         /* Try to reset the chip. */
1570         bge_reset(sc);
1571
1572         if (bge_chipinit(sc)) {
1573                 device_printf(dev, "chip initialization failed\n");
1574                 error = ENXIO;
1575                 goto fail;
1576         }
1577
1578         /*
1579          * Get station address from the EEPROM.
1580          */
1581         mac_addr = bge_readmem_ind(sc, 0x0c14);
1582         if ((mac_addr >> 16) == 0x484b) {
1583                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1584                 ether_addr[1] = (uint8_t)mac_addr;
1585                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1586                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1587                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1588                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1589                 ether_addr[5] = (uint8_t)mac_addr;
1590         } else if (bge_read_eeprom(sc, ether_addr,
1591             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1592                 device_printf(dev, "failed to read station address\n");
1593                 error = ENXIO;
1594                 goto fail;
1595         }
1596
1597         /* Allocate the general information block and ring buffers. */
1598         sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1599             M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1600
1601         if (sc->bge_rdata == NULL) {
1602                 error = ENXIO;
1603                 device_printf(dev, "no memory for list buffers!\n");
1604                 goto fail;
1605         }
1606
1607         bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1608
1609         /*
1610          * Try to allocate memory for jumbo buffers.
1611          * The 5705/5750 does not appear to support jumbo frames.
1612          */
1613         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1614             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1615                 if (bge_alloc_jumbo_mem(sc)) {
1616                         device_printf(dev, "jumbo buffer allocation failed\n");
1617                         error = ENXIO;
1618                         goto fail;
1619                 }
1620         }
1621
1622         /* Set default tuneable values. */
1623         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1624         sc->bge_rx_coal_ticks = 150;
1625         sc->bge_tx_coal_ticks = 150;
1626         sc->bge_rx_max_coal_bds = 64;
1627         sc->bge_tx_max_coal_bds = 128;
1628
1629         /* 5705/5750 limits RX return ring to 512 entries. */
1630         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1631             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1632                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1633         else
1634                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1635
1636         /* Set up ifnet structure */
1637         ifp->if_softc = sc;
1638         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1639         ifp->if_ioctl = bge_ioctl;
1640         ifp->if_start = bge_start;
1641         ifp->if_watchdog = bge_watchdog;
1642         ifp->if_init = bge_init;
1643         ifp->if_mtu = ETHERMTU;
1644         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1645         ifq_set_ready(&ifp->if_snd);
1646         ifp->if_hwassist = BGE_CSUM_FEATURES;
1647         ifp->if_capabilities = IFCAP_HWCSUM;
1648         ifp->if_capenable = ifp->if_capabilities;
1649
1650         /*
1651          * Figure out what sort of media we have by checking the
1652          * hardware config word in the first 32k of NIC internal memory,
1653          * or fall back to examining the EEPROM if necessary.
1654          * Note: on some BCM5700 cards, this value appears to be unset.
1655          * If that's the case, we have to rely on identifying the NIC
1656          * by its PCI subsystem ID, as we do below for the SysKonnect
1657          * SK-9D41.
1658          */
1659         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1660                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1661         else {
1662                 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1663                                 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1664                 hwcfg = ntohl(hwcfg);
1665         }
1666
1667         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1668                 sc->bge_tbi = 1;
1669
1670         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1671         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1672                 sc->bge_tbi = 1;
1673
1674         if (sc->bge_tbi) {
1675                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1676                     bge_ifmedia_upd, bge_ifmedia_sts);
1677                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1678                 ifmedia_add(&sc->bge_ifmedia,
1679                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1680                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1681                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1682         } else {
1683                 /*
1684                  * Do transceiver setup.
1685                  */
1686                 if (mii_phy_probe(dev, &sc->bge_miibus,
1687                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1688                         device_printf(dev, "MII without any PHY!\n");
1689                         error = ENXIO;
1690                         goto fail;
1691                 }
1692         }
1693
1694         /*
1695          * When using the BCM5701 in PCI-X mode, data corruption has
1696          * been observed in the first few bytes of some received packets.
1697          * Aligning the packet buffer in memory eliminates the corruption.
1698          * Unfortunately, this misaligns the packet payloads.  On platforms
1699          * which do not support unaligned accesses, we will realign the
1700          * payloads by copying the received packets.
1701          */
1702         switch (sc->bge_chipid) {
1703         case BGE_CHIPID_BCM5701_A0:
1704         case BGE_CHIPID_BCM5701_B0:
1705         case BGE_CHIPID_BCM5701_B2:
1706         case BGE_CHIPID_BCM5701_B5:
1707                 /* If in PCI-X mode, work around the alignment bug. */
1708                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1709                     (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1710                     BGE_PCISTATE_PCI_BUSSPEED)
1711                         sc->bge_rx_alignment_bug = 1;
1712                 break;
1713         }
1714
1715         /*
1716          * Call MI attach routine.
1717          */
1718         ether_ifattach(ifp, ether_addr);
1719
1720         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1721                                bge_intr, sc, &sc->bge_intrhand, NULL);
1722         if (error) {
1723                 ether_ifdetach(ifp);
1724                 device_printf(dev, "couldn't set up irq\n");
1725                 goto fail;
1726         }
1727
1728         return(0);
1729
1730 fail:
1731         bge_detach(dev);
1732
1733         return(error);
1734 }
1735
1736 static int
1737 bge_detach(device_t dev)
1738 {
1739         struct bge_softc *sc = device_get_softc(dev);
1740         struct ifnet *ifp = &sc->arpcom.ac_if;
1741
1742         crit_enter();
1743
1744         if (device_is_attached(dev)) {
1745                 ether_ifdetach(ifp);
1746                 bge_stop(sc);
1747                 bge_reset(sc);
1748         }
1749
1750         if (sc->bge_tbi)
1751                 ifmedia_removeall(&sc->bge_ifmedia);
1752         if (sc->bge_miibus);
1753                 device_delete_child(dev, sc->bge_miibus);
1754         bus_generic_detach(dev);
1755
1756         bge_release_resources(sc);
1757
1758         crit_exit();
1759
1760         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1761             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1762                 bge_free_jumbo_mem(sc);
1763
1764         return(0);
1765 }
1766
1767 static void
1768 bge_release_resources(struct bge_softc *sc)
1769 {
1770         device_t dev;
1771
1772         dev = sc->bge_dev;
1773
1774         if (sc->bge_vpd_prodname != NULL)
1775                 free(sc->bge_vpd_prodname, M_DEVBUF);
1776
1777         if (sc->bge_vpd_readonly != NULL)
1778                 free(sc->bge_vpd_readonly, M_DEVBUF);
1779
1780         if (sc->bge_intrhand != NULL)
1781                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1782
1783         if (sc->bge_irq != NULL)
1784                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1785
1786         if (sc->bge_res != NULL)
1787                 bus_release_resource(dev, SYS_RES_MEMORY,
1788                     BGE_PCI_BAR0, sc->bge_res);
1789
1790         if (sc->bge_rdata != NULL)
1791                 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1792                            M_DEVBUF);
1793
1794         return;
1795 }
1796
1797 static void
1798 bge_reset(struct bge_softc *sc)
1799 {
1800         device_t dev;
1801         uint32_t cachesize, command, pcistate, reset;
1802         int i, val = 0;
1803
1804         dev = sc->bge_dev;
1805
1806         /* Save some important PCI state. */
1807         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1808         command = pci_read_config(dev, BGE_PCI_CMD, 4);
1809         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1810
1811         pci_write_config(dev, BGE_PCI_MISC_CTL,
1812             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1813             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1814
1815         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
1816
1817         /* XXX: Broadcom Linux driver. */
1818         if (sc->bge_pcie) {
1819                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
1820                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
1821                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1822                         /* Prevent PCIE link training during global reset */
1823                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
1824                         reset |= (1<<29);
1825                 }
1826         }
1827
1828         /* Issue global reset */
1829         bge_writereg_ind(sc, BGE_MISC_CFG, reset);
1830
1831         DELAY(1000);
1832
1833         /* XXX: Broadcom Linux driver. */
1834         if (sc->bge_pcie) {
1835                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
1836                         uint32_t v;
1837
1838                         DELAY(500000); /* wait for link training to complete */
1839                         v = pci_read_config(dev, 0xc4, 4);
1840                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
1841                 }
1842                 /* Set PCIE max payload size and clear error status. */
1843                 pci_write_config(dev, 0xd8, 0xf5000, 4);
1844         }
1845
1846         /* Reset some of the PCI state that got zapped by reset */
1847         pci_write_config(dev, BGE_PCI_MISC_CTL,
1848             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1849             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1850         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1851         pci_write_config(dev, BGE_PCI_CMD, command, 4);
1852         bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1853
1854         /* Enable memory arbiter. */
1855         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1856                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1857
1858         /*
1859          * Prevent PXE restart: write a magic number to the
1860          * general communications memory at 0xB50.
1861          */
1862         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1863         /*
1864          * Poll the value location we just wrote until
1865          * we see the 1's complement of the magic number.
1866          * This indicates that the firmware initialization
1867          * is complete.
1868          */
1869         for (i = 0; i < BGE_TIMEOUT; i++) {
1870                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1871                 if (val == ~BGE_MAGIC_NUMBER)
1872                         break;
1873                 DELAY(10);
1874         }
1875
1876         if (i == BGE_TIMEOUT) {
1877                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1878                 return;
1879         }
1880
1881         /*
1882          * XXX Wait for the value of the PCISTATE register to
1883          * return to its original pre-reset state. This is a
1884          * fairly good indicator of reset completion. If we don't
1885          * wait for the reset to fully complete, trying to read
1886          * from the device's non-PCI registers may yield garbage
1887          * results.
1888          */
1889         for (i = 0; i < BGE_TIMEOUT; i++) {
1890                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1891                         break;
1892                 DELAY(10);
1893         }
1894
1895         /* Fix up byte swapping */
1896         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1897             BGE_MODECTL_BYTESWAP_DATA);
1898
1899         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1900
1901         /* XXX: Broadcom Linux driver. */
1902         if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1903                 uint32_t v;
1904
1905                 v = CSR_READ_4(sc, 0x7c00);
1906                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
1907         }
1908
1909         DELAY(10000);
1910 }
1911
1912 /*
1913  * Frame reception handling. This is called if there's a frame
1914  * on the receive return list.
1915  *
1916  * Note: we have to be able to handle two possibilities here:
1917  * 1) the frame is from the jumbo recieve ring
1918  * 2) the frame is from the standard receive ring
1919  */
1920
1921 static void
1922 bge_rxeof(struct bge_softc *sc)
1923 {
1924         struct ifnet *ifp;
1925         int stdcnt = 0, jumbocnt = 0;
1926
1927         ifp = &sc->arpcom.ac_if;
1928
1929         while(sc->bge_rx_saved_considx !=
1930             sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1931                 struct bge_rx_bd        *cur_rx;
1932                 uint32_t                rxidx;
1933                 struct mbuf             *m = NULL;
1934                 uint16_t                vlan_tag = 0;
1935                 int                     have_tag = 0;
1936
1937                 cur_rx =
1938             &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1939
1940                 rxidx = cur_rx->bge_idx;
1941                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1942
1943                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1944                         have_tag = 1;
1945                         vlan_tag = cur_rx->bge_vlan_tag;
1946                 }
1947
1948                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1949                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1950                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1951                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1952                         jumbocnt++;
1953                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1954                                 ifp->if_ierrors++;
1955                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1956                                 continue;
1957                         }
1958                         if (bge_newbuf_jumbo(sc,
1959                             sc->bge_jumbo, NULL) == ENOBUFS) {
1960                                 ifp->if_ierrors++;
1961                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1962                                 continue;
1963                         }
1964                 } else {
1965                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1966                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1967                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
1968                         stdcnt++;
1969                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1970                                 ifp->if_ierrors++;
1971                                 bge_newbuf_std(sc, sc->bge_std, m);
1972                                 continue;
1973                         }
1974                         if (bge_newbuf_std(sc, sc->bge_std,
1975                             NULL) == ENOBUFS) {
1976                                 ifp->if_ierrors++;
1977                                 bge_newbuf_std(sc, sc->bge_std, m);
1978                                 continue;
1979                         }
1980                 }
1981
1982                 ifp->if_ipackets++;
1983 #ifndef __i386__
1984                 /*
1985                  * The i386 allows unaligned accesses, but for other
1986                  * platforms we must make sure the payload is aligned.
1987                  */
1988                 if (sc->bge_rx_alignment_bug) {
1989                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
1990                             cur_rx->bge_len);
1991                         m->m_data += ETHER_ALIGN;
1992                 }
1993 #endif
1994                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
1995                 m->m_pkthdr.rcvif = ifp;
1996
1997 #if 0 /* currently broken for some packets, possibly related to TCP options */
1998                 if (ifp->if_hwassist) {
1999                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2000                         if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2001                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2002                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2003                                 m->m_pkthdr.csum_data =
2004                                     cur_rx->bge_tcp_udp_csum;
2005                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2006                         }
2007                 }
2008 #endif
2009
2010                 /*
2011                  * If we received a packet with a vlan tag, pass it
2012                  * to vlan_input() instead of ether_input().
2013                  */
2014                 if (have_tag) {
2015                         VLAN_INPUT_TAG(m, vlan_tag);
2016                         have_tag = vlan_tag = 0;
2017                         continue;
2018                 }
2019
2020                 (*ifp->if_input)(ifp, m);
2021         }
2022
2023         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2024         if (stdcnt)
2025                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2026         if (jumbocnt)
2027                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2028 }
2029
2030 static void
2031 bge_txeof(struct bge_softc *sc)
2032 {
2033         struct bge_tx_bd *cur_tx = NULL;
2034         struct ifnet *ifp;
2035
2036         ifp = &sc->arpcom.ac_if;
2037
2038         /*
2039          * Go through our tx ring and free mbufs for those
2040          * frames that have been sent.
2041          */
2042         while (sc->bge_tx_saved_considx !=
2043             sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2044                 uint32_t                idx = 0;
2045
2046                 idx = sc->bge_tx_saved_considx;
2047                 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2048                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2049                         ifp->if_opackets++;
2050                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2051                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2052                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2053                 }
2054                 sc->bge_txcnt--;
2055                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2056                 ifp->if_timer = 0;
2057         }
2058
2059         if (cur_tx != NULL)
2060                 ifp->if_flags &= ~IFF_OACTIVE;
2061 }
2062
2063 static void
2064 bge_intr(void *xsc)
2065 {
2066         struct bge_softc *sc = xsc;
2067         struct ifnet *ifp = &sc->arpcom.ac_if;
2068         uint32_t status, statusword, mimode;
2069
2070         /* XXX */
2071         statusword = loadandclear(&sc->bge_rdata->bge_status_block.bge_status);
2072
2073 #ifdef notdef
2074         /* Avoid this for now -- checking this register is expensive. */
2075         /* Make sure this is really our interrupt. */
2076         if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2077                 return;
2078 #endif
2079         /* Ack interrupt and stop others from occuring. */
2080         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2081
2082         /*
2083          * Process link state changes.
2084          * Grrr. The link status word in the status block does
2085          * not work correctly on the BCM5700 rev AX and BX chips,
2086          * according to all available information. Hence, we have
2087          * to enable MII interrupts in order to properly obtain
2088          * async link changes. Unfortunately, this also means that
2089          * we have to read the MAC status register to detect link
2090          * changes, thereby adding an additional register access to
2091          * the interrupt handler.
2092          */
2093
2094         if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2095                 status = CSR_READ_4(sc, BGE_MAC_STS);
2096                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2097                         sc->bge_link = 0;
2098                         callout_stop(&sc->bge_stat_timer);
2099                         bge_tick(sc);
2100                         /* Clear the interrupt */
2101                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2102                             BGE_EVTENB_MI_INTERRUPT);
2103                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2104                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2105                             BRGPHY_INTRS);
2106                 }
2107         } else {
2108                 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
2109                         /*
2110                          * Sometimes PCS encoding errors are detected in
2111                          * TBI mode (on fiber NICs), and for some reason
2112                          * the chip will signal them as link changes.
2113                          * If we get a link change event, but the 'PCS
2114                          * encoding error' bit in the MAC status register
2115                          * is set, don't bother doing a link check.
2116                          * This avoids spurious "gigabit link up" messages
2117                          * that sometimes appear on fiber NICs during
2118                          * periods of heavy traffic. (There should be no
2119                          * effect on copper NICs.)
2120                          *
2121                          * If we do have a copper NIC (bge_tbi == 0) then
2122                          * check that the AUTOPOLL bit is set before
2123                          * processing the event as a real link change.
2124                          * Turning AUTOPOLL on and off in the MII read/write
2125                          * functions will often trigger a link status
2126                          * interrupt for no reason.
2127                          */
2128                         status = CSR_READ_4(sc, BGE_MAC_STS);
2129                         mimode = CSR_READ_4(sc, BGE_MI_MODE);
2130                         if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR |
2131                                         BGE_MACSTAT_MI_COMPLETE)) &&
2132                             (!sc->bge_tbi && (mimode & BGE_MIMODE_AUTOPOLL))) {
2133                                 sc->bge_link = 0;
2134                                 callout_stop(&sc->bge_stat_timer);
2135                                 bge_tick(sc);
2136                         }
2137                         sc->bge_link = 0;
2138                         callout_stop(&sc->bge_stat_timer);
2139                         bge_tick(sc);
2140                         /* Clear the interrupt */
2141                         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2142                             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2143                             BGE_MACSTAT_LINK_CHANGED);
2144
2145                         /* Force flush the status block cached by PCI bridge */
2146                         CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2147                 }
2148         }
2149
2150         if (ifp->if_flags & IFF_RUNNING) {
2151                 /* Check RX return ring producer/consumer */
2152                 bge_rxeof(sc);
2153
2154                 /* Check TX ring producer/consumer */
2155                 bge_txeof(sc);
2156         }
2157
2158         bge_handle_events(sc);
2159
2160         /* Re-enable interrupts. */
2161         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2162
2163         if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2164                 (*ifp->if_start)(ifp);
2165 }
2166
2167 static void
2168 bge_tick(void *xsc)
2169 {
2170         struct bge_softc *sc = xsc;
2171         struct ifnet *ifp = &sc->arpcom.ac_if;
2172         struct mii_data *mii = NULL;
2173         struct ifmedia *ifm = NULL;
2174
2175         crit_enter();
2176
2177         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2178             sc->bge_asicrev == BGE_ASICREV_BCM5750)
2179                 bge_stats_update_regs(sc);
2180         else
2181                 bge_stats_update(sc);
2182
2183         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2184
2185         if (sc->bge_link) {
2186                 crit_exit();
2187                 return;
2188         }
2189
2190         if (sc->bge_tbi) {
2191                 ifm = &sc->bge_ifmedia;
2192                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2193                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2194                         sc->bge_link++;
2195                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2196                         if_printf(ifp, "gigabit link up\n");
2197                         if (!ifq_is_empty(&ifp->if_snd))
2198                                 (*ifp->if_start)(ifp);
2199                 }
2200                 crit_exit();
2201                 return;
2202         }
2203
2204         mii = device_get_softc(sc->bge_miibus);
2205         mii_tick(mii);
2206
2207         if (!sc->bge_link) {
2208                 mii_pollstat(mii);
2209                 if (mii->mii_media_status & IFM_ACTIVE &&
2210                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2211                         sc->bge_link++;
2212                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2213                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2214                                 if_printf(ifp, "gigabit link up\n");
2215                         if (!ifq_is_empty(&ifp->if_snd))
2216                                 (*ifp->if_start)(ifp);
2217                 }
2218         }
2219
2220         crit_exit();
2221 }
2222
2223 static void
2224 bge_stats_update_regs(struct bge_softc *sc)
2225 {
2226         struct ifnet *ifp = &sc->arpcom.ac_if;
2227         struct bge_mac_stats_regs stats;
2228         uint32_t *s;
2229         int i;
2230
2231         s = (uint32_t *)&stats;
2232         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2233                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2234                 s++;
2235         }
2236
2237         ifp->if_collisions +=
2238            (stats.dot3StatsSingleCollisionFrames +
2239            stats.dot3StatsMultipleCollisionFrames +
2240            stats.dot3StatsExcessiveCollisions +
2241            stats.dot3StatsLateCollisions) -
2242            ifp->if_collisions;
2243 }
2244
2245 static void
2246 bge_stats_update(struct bge_softc *sc)
2247 {
2248         struct ifnet *ifp = &sc->arpcom.ac_if;
2249         struct bge_stats *stats;
2250
2251         stats = (struct bge_stats *)(sc->bge_vhandle +
2252             BGE_MEMWIN_START + BGE_STATS_BLOCK);
2253
2254         ifp->if_collisions +=
2255            (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2256            stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2257            stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2258            stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2259            ifp->if_collisions;
2260
2261 #ifdef notdef
2262         ifp->if_collisions +=
2263            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2264            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2265            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2266            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2267            ifp->if_collisions;
2268 #endif
2269 }
2270
2271 /*
2272  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2273  * pointers to descriptors.
2274  */
2275 static int
2276 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2277 {
2278         struct bge_tx_bd *f = NULL;
2279         struct mbuf *m;
2280         uint32_t frag, cur, cnt = 0;
2281         uint16_t csum_flags = 0;
2282         struct ifvlan *ifv = NULL;
2283
2284         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2285             m_head->m_pkthdr.rcvif != NULL &&
2286             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2287                 ifv = m_head->m_pkthdr.rcvif->if_softc;
2288
2289         m = m_head;
2290         cur = frag = *txidx;
2291
2292         if (m_head->m_pkthdr.csum_flags) {
2293                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2294                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2295                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2296                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2297                 if (m_head->m_flags & M_LASTFRAG)
2298                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2299                 else if (m_head->m_flags & M_FRAG)
2300                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2301         }
2302         /*
2303          * Start packing the mbufs in this chain into
2304          * the fragment pointers. Stop when we run out
2305          * of fragments or hit the end of the mbuf chain.
2306          */
2307         for (m = m_head; m != NULL; m = m->m_next) {
2308                 if (m->m_len != 0) {
2309                         f = &sc->bge_rdata->bge_tx_ring[frag];
2310                         if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2311                                 break;
2312                         BGE_HOSTADDR(f->bge_addr,
2313                             vtophys(mtod(m, vm_offset_t)));
2314                         f->bge_len = m->m_len;
2315                         f->bge_flags = csum_flags;
2316                         if (ifv != NULL) {
2317                                 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2318                                 f->bge_vlan_tag = ifv->ifv_tag;
2319                         } else {
2320                                 f->bge_vlan_tag = 0;
2321                         }
2322                         /*
2323                          * Sanity check: avoid coming within 16 descriptors
2324                          * of the end of the ring.
2325                          */
2326                         if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2327                                 return(ENOBUFS);
2328                         cur = frag;
2329                         BGE_INC(frag, BGE_TX_RING_CNT);
2330                         cnt++;
2331                 }
2332         }
2333
2334         if (m != NULL)
2335                 return(ENOBUFS);
2336
2337         if (frag == sc->bge_tx_saved_considx)
2338                 return(ENOBUFS);
2339
2340         sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2341         sc->bge_cdata.bge_tx_chain[cur] = m_head;
2342         sc->bge_txcnt += cnt;
2343
2344         *txidx = frag;
2345
2346         return(0);
2347 }
2348
2349 /*
2350  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2351  * to the mbuf data regions directly in the transmit descriptors.
2352  */
2353 static void
2354 bge_start(struct ifnet *ifp)
2355 {
2356         struct bge_softc *sc;
2357         struct mbuf *m_head = NULL;
2358         uint32_t prodidx = 0;
2359
2360         sc = ifp->if_softc;
2361
2362         if (!sc->bge_link)
2363                 return;
2364
2365         prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2366
2367         while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2368                 m_head = ifq_poll(&ifp->if_snd);
2369                 if (m_head == NULL)
2370                         break;
2371
2372                 /*
2373                  * XXX
2374                  * safety overkill.  If this is a fragmented packet chain
2375                  * with delayed TCP/UDP checksums, then only encapsulate
2376                  * it if we have enough descriptors to handle the entire
2377                  * chain at once.
2378                  * (paranoia -- may not actually be needed)
2379                  */
2380                 if (m_head->m_flags & M_FIRSTFRAG &&
2381                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2382                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2383                             m_head->m_pkthdr.csum_data + 16) {
2384                                 ifp->if_flags |= IFF_OACTIVE;
2385                                 break;
2386                         }
2387                 }
2388
2389                 /*
2390                  * Pack the data into the transmit ring. If we
2391                  * don't have room, set the OACTIVE flag and wait
2392                  * for the NIC to drain the ring.
2393                  */
2394                 if (bge_encap(sc, m_head, &prodidx)) {
2395                         ifp->if_flags |= IFF_OACTIVE;
2396                         break;
2397                 }
2398                 m_head = ifq_dequeue(&ifp->if_snd);
2399
2400                 BPF_MTAP(ifp, m_head);
2401         }
2402
2403         /* Transmit */
2404         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2405         /* 5700 b2 errata */
2406         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2407                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2408
2409         /*
2410          * Set a timeout in case the chip goes out to lunch.
2411          */
2412         ifp->if_timer = 5;
2413 }
2414
2415 static void
2416 bge_init(void *xsc)
2417 {
2418         struct bge_softc *sc = xsc;
2419         struct ifnet *ifp = &sc->arpcom.ac_if;
2420         uint16_t *m;
2421
2422         crit_enter();
2423
2424         if (ifp->if_flags & IFF_RUNNING) {
2425                 crit_exit();
2426                 return;
2427         }
2428
2429         /* Cancel pending I/O and flush buffers. */
2430         bge_stop(sc);
2431         bge_reset(sc);
2432         bge_chipinit(sc);
2433
2434         /*
2435          * Init the various state machines, ring
2436          * control blocks and firmware.
2437          */
2438         if (bge_blockinit(sc)) {
2439                 if_printf(ifp, "initialization failure\n");
2440                 crit_exit();
2441                 return;
2442         }
2443
2444         /* Specify MTU. */
2445         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2446             ETHER_HDR_LEN + ETHER_CRC_LEN);
2447
2448         /* Load our MAC address. */
2449         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2450         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2451         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2452
2453         /* Enable or disable promiscuous mode as needed. */
2454         if (ifp->if_flags & IFF_PROMISC) {
2455                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2456         } else {
2457                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2458         }
2459
2460         /* Program multicast filter. */
2461         bge_setmulti(sc);
2462
2463         /* Init RX ring. */
2464         bge_init_rx_ring_std(sc);
2465
2466         /*
2467          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2468          * memory to insure that the chip has in fact read the first
2469          * entry of the ring.
2470          */
2471         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2472                 uint32_t                v, i;
2473                 for (i = 0; i < 10; i++) {
2474                         DELAY(20);
2475                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2476                         if (v == (MCLBYTES - ETHER_ALIGN))
2477                                 break;
2478                 }
2479                 if (i == 10)
2480                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2481         }
2482
2483         /* Init jumbo RX ring. */
2484         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2485                 bge_init_rx_ring_jumbo(sc);
2486
2487         /* Init our RX return ring index */
2488         sc->bge_rx_saved_considx = 0;
2489
2490         /* Init TX ring. */
2491         bge_init_tx_ring(sc);
2492
2493         /* Turn on transmitter */
2494         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2495
2496         /* Turn on receiver */
2497         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2498
2499         /* Tell firmware we're alive. */
2500         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2501
2502         /* Enable host interrupts. */
2503         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2504         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2505         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2506
2507         bge_ifmedia_upd(ifp);
2508
2509         ifp->if_flags |= IFF_RUNNING;
2510         ifp->if_flags &= ~IFF_OACTIVE;
2511
2512         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2513
2514         crit_exit();
2515 }
2516
2517 /*
2518  * Set media options.
2519  */
2520 static int
2521 bge_ifmedia_upd(struct ifnet *ifp)
2522 {
2523         struct bge_softc *sc = ifp->if_softc;
2524         struct ifmedia *ifm = &sc->bge_ifmedia;
2525         struct mii_data *mii;
2526
2527         /* If this is a 1000baseX NIC, enable the TBI port. */
2528         if (sc->bge_tbi) {
2529                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2530                         return(EINVAL);
2531                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2532                 case IFM_AUTO:
2533                         break;
2534                 case IFM_1000_SX:
2535                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2536                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2537                                     BGE_MACMODE_HALF_DUPLEX);
2538                         } else {
2539                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2540                                     BGE_MACMODE_HALF_DUPLEX);
2541                         }
2542                         break;
2543                 default:
2544                         return(EINVAL);
2545                 }
2546                 return(0);
2547         }
2548
2549         mii = device_get_softc(sc->bge_miibus);
2550         sc->bge_link = 0;
2551         if (mii->mii_instance) {
2552                 struct mii_softc *miisc;
2553                 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2554                     miisc = LIST_NEXT(miisc, mii_list))
2555                         mii_phy_reset(miisc);
2556         }
2557         mii_mediachg(mii);
2558
2559         return(0);
2560 }
2561
2562 /*
2563  * Report current media status.
2564  */
2565 static void
2566 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2567 {
2568         struct bge_softc *sc = ifp->if_softc;
2569         struct mii_data *mii;
2570
2571         if (sc->bge_tbi) {
2572                 ifmr->ifm_status = IFM_AVALID;
2573                 ifmr->ifm_active = IFM_ETHER;
2574                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2575                     BGE_MACSTAT_TBI_PCS_SYNCHED)
2576                         ifmr->ifm_status |= IFM_ACTIVE;
2577                 ifmr->ifm_active |= IFM_1000_SX;
2578                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2579                         ifmr->ifm_active |= IFM_HDX;
2580                 else
2581                         ifmr->ifm_active |= IFM_FDX;
2582                 return;
2583         }
2584
2585         mii = device_get_softc(sc->bge_miibus);
2586         mii_pollstat(mii);
2587         ifmr->ifm_active = mii->mii_media_active;
2588         ifmr->ifm_status = mii->mii_media_status;
2589 }
2590
2591 static int
2592 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2593 {
2594         struct bge_softc *sc = ifp->if_softc;
2595         struct ifreq *ifr = (struct ifreq *) data;
2596         int mask, error = 0;
2597         struct mii_data *mii;
2598
2599         crit_enter();
2600
2601         switch(command) {
2602         case SIOCSIFMTU:
2603                 /* Disallow jumbo frames on 5705/5750. */
2604                 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2605                       sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
2606                      ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2607                         error = EINVAL;
2608                 else {
2609                         ifp->if_mtu = ifr->ifr_mtu;
2610                         ifp->if_flags &= ~IFF_RUNNING;
2611                         bge_init(sc);
2612                 }
2613                 break;
2614         case SIOCSIFFLAGS:
2615                 if (ifp->if_flags & IFF_UP) {
2616                         /*
2617                          * If only the state of the PROMISC flag changed,
2618                          * then just use the 'set promisc mode' command
2619                          * instead of reinitializing the entire NIC. Doing
2620                          * a full re-init means reloading the firmware and
2621                          * waiting for it to start up, which may take a
2622                          * second or two.
2623                          */
2624                         if (ifp->if_flags & IFF_RUNNING &&
2625                             ifp->if_flags & IFF_PROMISC &&
2626                             !(sc->bge_if_flags & IFF_PROMISC)) {
2627                                 BGE_SETBIT(sc, BGE_RX_MODE,
2628                                     BGE_RXMODE_RX_PROMISC);
2629                         } else if (ifp->if_flags & IFF_RUNNING &&
2630                             !(ifp->if_flags & IFF_PROMISC) &&
2631                             sc->bge_if_flags & IFF_PROMISC) {
2632                                 BGE_CLRBIT(sc, BGE_RX_MODE,
2633                                     BGE_RXMODE_RX_PROMISC);
2634                         } else
2635                                 bge_init(sc);
2636                 } else {
2637                         if (ifp->if_flags & IFF_RUNNING) {
2638                                 bge_stop(sc);
2639                         }
2640                 }
2641                 sc->bge_if_flags = ifp->if_flags;
2642                 error = 0;
2643                 break;
2644         case SIOCADDMULTI:
2645         case SIOCDELMULTI:
2646                 if (ifp->if_flags & IFF_RUNNING) {
2647                         bge_setmulti(sc);
2648                         error = 0;
2649                 }
2650                 break;
2651         case SIOCSIFMEDIA:
2652         case SIOCGIFMEDIA:
2653                 if (sc->bge_tbi) {
2654                         error = ifmedia_ioctl(ifp, ifr,
2655                             &sc->bge_ifmedia, command);
2656                 } else {
2657                         mii = device_get_softc(sc->bge_miibus);
2658                         error = ifmedia_ioctl(ifp, ifr,
2659                             &mii->mii_media, command);
2660                 }
2661                 break;
2662         case SIOCSIFCAP:
2663                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2664                 if (mask & IFCAP_HWCSUM) {
2665                         if (IFCAP_HWCSUM & ifp->if_capenable)
2666                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2667                         else
2668                                 ifp->if_capenable |= IFCAP_HWCSUM;
2669                 }
2670                 error = 0;
2671                 break;
2672         default:
2673                 error = ether_ioctl(ifp, command, data);
2674                 break;
2675         }
2676
2677         crit_exit();
2678
2679         return(error);
2680 }
2681
2682 static void
2683 bge_watchdog(struct ifnet *ifp)
2684 {
2685         struct bge_softc *sc = ifp->if_softc;
2686
2687         if_printf(ifp, "watchdog timeout -- resetting\n");
2688
2689         ifp->if_flags &= ~IFF_RUNNING;
2690         bge_init(sc);
2691
2692         ifp->if_oerrors++;
2693 }
2694
2695 /*
2696  * Stop the adapter and free any mbufs allocated to the
2697  * RX and TX lists.
2698  */
2699 static void
2700 bge_stop(struct bge_softc *sc)
2701 {
2702         struct ifnet *ifp = &sc->arpcom.ac_if;
2703         struct ifmedia_entry *ifm;
2704         struct mii_data *mii = NULL;
2705         int mtmp, itmp;
2706
2707         if (!sc->bge_tbi)
2708                 mii = device_get_softc(sc->bge_miibus);
2709
2710         callout_stop(&sc->bge_stat_timer);
2711
2712         /*
2713          * Disable all of the receiver blocks
2714          */
2715         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2716         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2717         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2718         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2719             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2720                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2721         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2722         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2723         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2724
2725         /*
2726          * Disable all of the transmit blocks
2727          */
2728         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2729         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2730         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2731         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2732         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2733         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2734             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2735                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2736         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2737
2738         /*
2739          * Shut down all of the memory managers and related
2740          * state machines.
2741          */
2742         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2743         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2744         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2745             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2746                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2747         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2748         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2749         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2750             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2751                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2752                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2753         }
2754
2755         /* Disable host interrupts. */
2756         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2757         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2758
2759         /*
2760          * Tell firmware we're shutting down.
2761          */
2762         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2763
2764         /* Free the RX lists. */
2765         bge_free_rx_ring_std(sc);
2766
2767         /* Free jumbo RX list. */
2768         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2769             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2770                 bge_free_rx_ring_jumbo(sc);
2771
2772         /* Free TX buffers. */
2773         bge_free_tx_ring(sc);
2774
2775         /*
2776          * Isolate/power down the PHY, but leave the media selection
2777          * unchanged so that things will be put back to normal when
2778          * we bring the interface back up.
2779          */
2780         if (!sc->bge_tbi) {
2781                 itmp = ifp->if_flags;
2782                 ifp->if_flags |= IFF_UP;
2783                 ifm = mii->mii_media.ifm_cur;
2784                 mtmp = ifm->ifm_media;
2785                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2786                 mii_mediachg(mii);
2787                 ifm->ifm_media = mtmp;
2788                 ifp->if_flags = itmp;
2789         }
2790
2791         sc->bge_link = 0;
2792
2793         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2794
2795         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2796 }
2797
2798 /*
2799  * Stop all chip I/O so that the kernel's probe routines don't
2800  * get confused by errant DMAs when rebooting.
2801  */
2802 static void
2803 bge_shutdown(device_t dev)
2804 {
2805         struct bge_softc *sc = device_get_softc(dev);
2806
2807         bge_stop(sc);
2808         bge_reset(sc);
2809 }