2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/module.h>
28 #include "radeon_asic.h"
29 #include "radeon_audio.h"
30 #include <drm/radeon_drm.h>
33 #include "si_blit_shaders.h"
34 #include "clearstate_si.h"
35 #include "radeon_ucode.h"
38 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
39 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
40 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
41 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
42 MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
46 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
47 MODULE_FIRMWARE("radeon/tahiti_me.bin");
48 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
49 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
50 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
51 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
53 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
54 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
55 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
56 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
57 MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
58 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
59 MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
61 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
62 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
63 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
64 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
65 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
66 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
68 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
69 MODULE_FIRMWARE("radeon/VERDE_me.bin");
70 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
71 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
72 MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
73 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
74 MODULE_FIRMWARE("radeon/VERDE_smc.bin");
76 MODULE_FIRMWARE("radeon/verde_pfp.bin");
77 MODULE_FIRMWARE("radeon/verde_me.bin");
78 MODULE_FIRMWARE("radeon/verde_ce.bin");
79 MODULE_FIRMWARE("radeon/verde_mc.bin");
80 MODULE_FIRMWARE("radeon/verde_rlc.bin");
81 MODULE_FIRMWARE("radeon/verde_smc.bin");
83 MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
84 MODULE_FIRMWARE("radeon/OLAND_me.bin");
85 MODULE_FIRMWARE("radeon/OLAND_ce.bin");
86 MODULE_FIRMWARE("radeon/OLAND_mc.bin");
87 MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
88 MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
89 MODULE_FIRMWARE("radeon/OLAND_smc.bin");
91 MODULE_FIRMWARE("radeon/oland_pfp.bin");
92 MODULE_FIRMWARE("radeon/oland_me.bin");
93 MODULE_FIRMWARE("radeon/oland_ce.bin");
94 MODULE_FIRMWARE("radeon/oland_mc.bin");
95 MODULE_FIRMWARE("radeon/oland_rlc.bin");
96 MODULE_FIRMWARE("radeon/oland_smc.bin");
98 MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
99 MODULE_FIRMWARE("radeon/HAINAN_me.bin");
100 MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
101 MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
102 MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
103 MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
104 MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
106 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
107 MODULE_FIRMWARE("radeon/hainan_me.bin");
108 MODULE_FIRMWARE("radeon/hainan_ce.bin");
109 MODULE_FIRMWARE("radeon/hainan_mc.bin");
110 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
111 MODULE_FIRMWARE("radeon/hainan_smc.bin");
113 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
114 static void si_pcie_gen3_enable(struct radeon_device *rdev);
115 static void si_program_aspm(struct radeon_device *rdev);
116 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
118 static void si_init_pg(struct radeon_device *rdev);
119 static void si_init_cg(struct radeon_device *rdev);
120 static void si_fini_pg(struct radeon_device *rdev);
121 static void si_fini_cg(struct radeon_device *rdev);
122 static void si_rlc_stop(struct radeon_device *rdev);
124 static const u32 verde_rlc_save_restore_register_list[] =
126 (0x8000 << 16) | (0x98f4 >> 2),
128 (0x8040 << 16) | (0x98f4 >> 2),
130 (0x8000 << 16) | (0xe80 >> 2),
132 (0x8040 << 16) | (0xe80 >> 2),
134 (0x8000 << 16) | (0x89bc >> 2),
136 (0x8040 << 16) | (0x89bc >> 2),
138 (0x8000 << 16) | (0x8c1c >> 2),
140 (0x8040 << 16) | (0x8c1c >> 2),
142 (0x9c00 << 16) | (0x98f0 >> 2),
144 (0x9c00 << 16) | (0xe7c >> 2),
146 (0x8000 << 16) | (0x9148 >> 2),
148 (0x8040 << 16) | (0x9148 >> 2),
150 (0x9c00 << 16) | (0x9150 >> 2),
152 (0x9c00 << 16) | (0x897c >> 2),
154 (0x9c00 << 16) | (0x8d8c >> 2),
156 (0x9c00 << 16) | (0xac54 >> 2),
159 (0x9c00 << 16) | (0x98f8 >> 2),
161 (0x9c00 << 16) | (0x9910 >> 2),
163 (0x9c00 << 16) | (0x9914 >> 2),
165 (0x9c00 << 16) | (0x9918 >> 2),
167 (0x9c00 << 16) | (0x991c >> 2),
169 (0x9c00 << 16) | (0x9920 >> 2),
171 (0x9c00 << 16) | (0x9924 >> 2),
173 (0x9c00 << 16) | (0x9928 >> 2),
175 (0x9c00 << 16) | (0x992c >> 2),
177 (0x9c00 << 16) | (0x9930 >> 2),
179 (0x9c00 << 16) | (0x9934 >> 2),
181 (0x9c00 << 16) | (0x9938 >> 2),
183 (0x9c00 << 16) | (0x993c >> 2),
185 (0x9c00 << 16) | (0x9940 >> 2),
187 (0x9c00 << 16) | (0x9944 >> 2),
189 (0x9c00 << 16) | (0x9948 >> 2),
191 (0x9c00 << 16) | (0x994c >> 2),
193 (0x9c00 << 16) | (0x9950 >> 2),
195 (0x9c00 << 16) | (0x9954 >> 2),
197 (0x9c00 << 16) | (0x9958 >> 2),
199 (0x9c00 << 16) | (0x995c >> 2),
201 (0x9c00 << 16) | (0x9960 >> 2),
203 (0x9c00 << 16) | (0x9964 >> 2),
205 (0x9c00 << 16) | (0x9968 >> 2),
207 (0x9c00 << 16) | (0x996c >> 2),
209 (0x9c00 << 16) | (0x9970 >> 2),
211 (0x9c00 << 16) | (0x9974 >> 2),
213 (0x9c00 << 16) | (0x9978 >> 2),
215 (0x9c00 << 16) | (0x997c >> 2),
217 (0x9c00 << 16) | (0x9980 >> 2),
219 (0x9c00 << 16) | (0x9984 >> 2),
221 (0x9c00 << 16) | (0x9988 >> 2),
223 (0x9c00 << 16) | (0x998c >> 2),
225 (0x9c00 << 16) | (0x8c00 >> 2),
227 (0x9c00 << 16) | (0x8c14 >> 2),
229 (0x9c00 << 16) | (0x8c04 >> 2),
231 (0x9c00 << 16) | (0x8c08 >> 2),
233 (0x8000 << 16) | (0x9b7c >> 2),
235 (0x8040 << 16) | (0x9b7c >> 2),
237 (0x8000 << 16) | (0xe84 >> 2),
239 (0x8040 << 16) | (0xe84 >> 2),
241 (0x8000 << 16) | (0x89c0 >> 2),
243 (0x8040 << 16) | (0x89c0 >> 2),
245 (0x8000 << 16) | (0x914c >> 2),
247 (0x8040 << 16) | (0x914c >> 2),
249 (0x8000 << 16) | (0x8c20 >> 2),
251 (0x8040 << 16) | (0x8c20 >> 2),
253 (0x8000 << 16) | (0x9354 >> 2),
255 (0x8040 << 16) | (0x9354 >> 2),
257 (0x9c00 << 16) | (0x9060 >> 2),
259 (0x9c00 << 16) | (0x9364 >> 2),
261 (0x9c00 << 16) | (0x9100 >> 2),
263 (0x9c00 << 16) | (0x913c >> 2),
265 (0x8000 << 16) | (0x90e0 >> 2),
267 (0x8000 << 16) | (0x90e4 >> 2),
269 (0x8000 << 16) | (0x90e8 >> 2),
271 (0x8040 << 16) | (0x90e0 >> 2),
273 (0x8040 << 16) | (0x90e4 >> 2),
275 (0x8040 << 16) | (0x90e8 >> 2),
277 (0x9c00 << 16) | (0x8bcc >> 2),
279 (0x9c00 << 16) | (0x8b24 >> 2),
281 (0x9c00 << 16) | (0x88c4 >> 2),
283 (0x9c00 << 16) | (0x8e50 >> 2),
285 (0x9c00 << 16) | (0x8c0c >> 2),
287 (0x9c00 << 16) | (0x8e58 >> 2),
289 (0x9c00 << 16) | (0x8e5c >> 2),
291 (0x9c00 << 16) | (0x9508 >> 2),
293 (0x9c00 << 16) | (0x950c >> 2),
295 (0x9c00 << 16) | (0x9494 >> 2),
297 (0x9c00 << 16) | (0xac0c >> 2),
299 (0x9c00 << 16) | (0xac10 >> 2),
301 (0x9c00 << 16) | (0xac14 >> 2),
303 (0x9c00 << 16) | (0xae00 >> 2),
305 (0x9c00 << 16) | (0xac08 >> 2),
307 (0x9c00 << 16) | (0x88d4 >> 2),
309 (0x9c00 << 16) | (0x88c8 >> 2),
311 (0x9c00 << 16) | (0x88cc >> 2),
313 (0x9c00 << 16) | (0x89b0 >> 2),
315 (0x9c00 << 16) | (0x8b10 >> 2),
317 (0x9c00 << 16) | (0x8a14 >> 2),
319 (0x9c00 << 16) | (0x9830 >> 2),
321 (0x9c00 << 16) | (0x9834 >> 2),
323 (0x9c00 << 16) | (0x9838 >> 2),
325 (0x9c00 << 16) | (0x9a10 >> 2),
327 (0x8000 << 16) | (0x9870 >> 2),
329 (0x8000 << 16) | (0x9874 >> 2),
331 (0x8001 << 16) | (0x9870 >> 2),
333 (0x8001 << 16) | (0x9874 >> 2),
335 (0x8040 << 16) | (0x9870 >> 2),
337 (0x8040 << 16) | (0x9874 >> 2),
339 (0x8041 << 16) | (0x9870 >> 2),
341 (0x8041 << 16) | (0x9874 >> 2),
346 static const u32 tahiti_golden_rlc_registers[] =
348 0xc424, 0xffffffff, 0x00601005,
349 0xc47c, 0xffffffff, 0x10104040,
350 0xc488, 0xffffffff, 0x0100000a,
351 0xc314, 0xffffffff, 0x00000800,
352 0xc30c, 0xffffffff, 0x800000f4,
353 0xf4a8, 0xffffffff, 0x00000000
356 static const u32 tahiti_golden_registers[] =
358 0x9a10, 0x00010000, 0x00018208,
359 0x9830, 0xffffffff, 0x00000000,
360 0x9834, 0xf00fffff, 0x00000400,
361 0x9838, 0x0002021c, 0x00020200,
362 0xc78, 0x00000080, 0x00000000,
363 0xd030, 0x000300c0, 0x00800040,
364 0xd830, 0x000300c0, 0x00800040,
365 0x5bb0, 0x000000f0, 0x00000070,
366 0x5bc0, 0x00200000, 0x50100000,
367 0x7030, 0x31000311, 0x00000011,
368 0x277c, 0x00000003, 0x000007ff,
369 0x240c, 0x000007ff, 0x00000000,
370 0x8a14, 0xf000001f, 0x00000007,
371 0x8b24, 0xffffffff, 0x00ffffff,
372 0x8b10, 0x0000ff0f, 0x00000000,
373 0x28a4c, 0x07ffffff, 0x4e000000,
374 0x28350, 0x3f3f3fff, 0x2a00126a,
375 0x30, 0x000000ff, 0x0040,
376 0x34, 0x00000040, 0x00004040,
377 0x9100, 0x07ffffff, 0x03000000,
378 0x8e88, 0x01ff1f3f, 0x00000000,
379 0x8e84, 0x01ff1f3f, 0x00000000,
380 0x9060, 0x0000007f, 0x00000020,
381 0x9508, 0x00010000, 0x00010000,
382 0xac14, 0x00000200, 0x000002fb,
383 0xac10, 0xffffffff, 0x0000543b,
384 0xac0c, 0xffffffff, 0xa9210876,
385 0x88d0, 0xffffffff, 0x000fff40,
386 0x88d4, 0x0000001f, 0x00000010,
387 0x1410, 0x20000000, 0x20fffed8,
388 0x15c0, 0x000c0fc0, 0x000c0400
391 static const u32 tahiti_golden_registers2[] =
393 0xc64, 0x00000001, 0x00000001
396 static const u32 pitcairn_golden_rlc_registers[] =
398 0xc424, 0xffffffff, 0x00601004,
399 0xc47c, 0xffffffff, 0x10102020,
400 0xc488, 0xffffffff, 0x01000020,
401 0xc314, 0xffffffff, 0x00000800,
402 0xc30c, 0xffffffff, 0x800000a4
405 static const u32 pitcairn_golden_registers[] =
407 0x9a10, 0x00010000, 0x00018208,
408 0x9830, 0xffffffff, 0x00000000,
409 0x9834, 0xf00fffff, 0x00000400,
410 0x9838, 0x0002021c, 0x00020200,
411 0xc78, 0x00000080, 0x00000000,
412 0xd030, 0x000300c0, 0x00800040,
413 0xd830, 0x000300c0, 0x00800040,
414 0x5bb0, 0x000000f0, 0x00000070,
415 0x5bc0, 0x00200000, 0x50100000,
416 0x7030, 0x31000311, 0x00000011,
417 0x2ae4, 0x00073ffe, 0x000022a2,
418 0x240c, 0x000007ff, 0x00000000,
419 0x8a14, 0xf000001f, 0x00000007,
420 0x8b24, 0xffffffff, 0x00ffffff,
421 0x8b10, 0x0000ff0f, 0x00000000,
422 0x28a4c, 0x07ffffff, 0x4e000000,
423 0x28350, 0x3f3f3fff, 0x2a00126a,
424 0x30, 0x000000ff, 0x0040,
425 0x34, 0x00000040, 0x00004040,
426 0x9100, 0x07ffffff, 0x03000000,
427 0x9060, 0x0000007f, 0x00000020,
428 0x9508, 0x00010000, 0x00010000,
429 0xac14, 0x000003ff, 0x000000f7,
430 0xac10, 0xffffffff, 0x00000000,
431 0xac0c, 0xffffffff, 0x32761054,
432 0x88d4, 0x0000001f, 0x00000010,
433 0x15c0, 0x000c0fc0, 0x000c0400
436 static const u32 verde_golden_rlc_registers[] =
438 0xc424, 0xffffffff, 0x033f1005,
439 0xc47c, 0xffffffff, 0x10808020,
440 0xc488, 0xffffffff, 0x00800008,
441 0xc314, 0xffffffff, 0x00001000,
442 0xc30c, 0xffffffff, 0x80010014
445 static const u32 verde_golden_registers[] =
447 0x9a10, 0x00010000, 0x00018208,
448 0x9830, 0xffffffff, 0x00000000,
449 0x9834, 0xf00fffff, 0x00000400,
450 0x9838, 0x0002021c, 0x00020200,
451 0xc78, 0x00000080, 0x00000000,
452 0xd030, 0x000300c0, 0x00800040,
453 0xd030, 0x000300c0, 0x00800040,
454 0xd830, 0x000300c0, 0x00800040,
455 0xd830, 0x000300c0, 0x00800040,
456 0x5bb0, 0x000000f0, 0x00000070,
457 0x5bc0, 0x00200000, 0x50100000,
458 0x7030, 0x31000311, 0x00000011,
459 0x2ae4, 0x00073ffe, 0x000022a2,
460 0x2ae4, 0x00073ffe, 0x000022a2,
461 0x2ae4, 0x00073ffe, 0x000022a2,
462 0x240c, 0x000007ff, 0x00000000,
463 0x240c, 0x000007ff, 0x00000000,
464 0x240c, 0x000007ff, 0x00000000,
465 0x8a14, 0xf000001f, 0x00000007,
466 0x8a14, 0xf000001f, 0x00000007,
467 0x8a14, 0xf000001f, 0x00000007,
468 0x8b24, 0xffffffff, 0x00ffffff,
469 0x8b10, 0x0000ff0f, 0x00000000,
470 0x28a4c, 0x07ffffff, 0x4e000000,
471 0x28350, 0x3f3f3fff, 0x0000124a,
472 0x28350, 0x3f3f3fff, 0x0000124a,
473 0x28350, 0x3f3f3fff, 0x0000124a,
474 0x30, 0x000000ff, 0x0040,
475 0x34, 0x00000040, 0x00004040,
476 0x9100, 0x07ffffff, 0x03000000,
477 0x9100, 0x07ffffff, 0x03000000,
478 0x8e88, 0x01ff1f3f, 0x00000000,
479 0x8e88, 0x01ff1f3f, 0x00000000,
480 0x8e88, 0x01ff1f3f, 0x00000000,
481 0x8e84, 0x01ff1f3f, 0x00000000,
482 0x8e84, 0x01ff1f3f, 0x00000000,
483 0x8e84, 0x01ff1f3f, 0x00000000,
484 0x9060, 0x0000007f, 0x00000020,
485 0x9508, 0x00010000, 0x00010000,
486 0xac14, 0x000003ff, 0x00000003,
487 0xac14, 0x000003ff, 0x00000003,
488 0xac14, 0x000003ff, 0x00000003,
489 0xac10, 0xffffffff, 0x00000000,
490 0xac10, 0xffffffff, 0x00000000,
491 0xac10, 0xffffffff, 0x00000000,
492 0xac0c, 0xffffffff, 0x00001032,
493 0xac0c, 0xffffffff, 0x00001032,
494 0xac0c, 0xffffffff, 0x00001032,
495 0x88d4, 0x0000001f, 0x00000010,
496 0x88d4, 0x0000001f, 0x00000010,
497 0x88d4, 0x0000001f, 0x00000010,
498 0x15c0, 0x000c0fc0, 0x000c0400
501 static const u32 oland_golden_rlc_registers[] =
503 0xc424, 0xffffffff, 0x00601005,
504 0xc47c, 0xffffffff, 0x10104040,
505 0xc488, 0xffffffff, 0x0100000a,
506 0xc314, 0xffffffff, 0x00000800,
507 0xc30c, 0xffffffff, 0x800000f4
510 static const u32 oland_golden_registers[] =
512 0x9a10, 0x00010000, 0x00018208,
513 0x9830, 0xffffffff, 0x00000000,
514 0x9834, 0xf00fffff, 0x00000400,
515 0x9838, 0x0002021c, 0x00020200,
516 0xc78, 0x00000080, 0x00000000,
517 0xd030, 0x000300c0, 0x00800040,
518 0xd830, 0x000300c0, 0x00800040,
519 0x5bb0, 0x000000f0, 0x00000070,
520 0x5bc0, 0x00200000, 0x50100000,
521 0x7030, 0x31000311, 0x00000011,
522 0x2ae4, 0x00073ffe, 0x000022a2,
523 0x240c, 0x000007ff, 0x00000000,
524 0x8a14, 0xf000001f, 0x00000007,
525 0x8b24, 0xffffffff, 0x00ffffff,
526 0x8b10, 0x0000ff0f, 0x00000000,
527 0x28a4c, 0x07ffffff, 0x4e000000,
528 0x28350, 0x3f3f3fff, 0x00000082,
529 0x30, 0x000000ff, 0x0040,
530 0x34, 0x00000040, 0x00004040,
531 0x9100, 0x07ffffff, 0x03000000,
532 0x9060, 0x0000007f, 0x00000020,
533 0x9508, 0x00010000, 0x00010000,
534 0xac14, 0x000003ff, 0x000000f3,
535 0xac10, 0xffffffff, 0x00000000,
536 0xac0c, 0xffffffff, 0x00003210,
537 0x88d4, 0x0000001f, 0x00000010,
538 0x15c0, 0x000c0fc0, 0x000c0400
541 static const u32 hainan_golden_registers[] =
543 0x9a10, 0x00010000, 0x00018208,
544 0x9830, 0xffffffff, 0x00000000,
545 0x9834, 0xf00fffff, 0x00000400,
546 0x9838, 0x0002021c, 0x00020200,
547 0xd0c0, 0xff000fff, 0x00000100,
548 0xd030, 0x000300c0, 0x00800040,
549 0xd8c0, 0xff000fff, 0x00000100,
550 0xd830, 0x000300c0, 0x00800040,
551 0x2ae4, 0x00073ffe, 0x000022a2,
552 0x240c, 0x000007ff, 0x00000000,
553 0x8a14, 0xf000001f, 0x00000007,
554 0x8b24, 0xffffffff, 0x00ffffff,
555 0x8b10, 0x0000ff0f, 0x00000000,
556 0x28a4c, 0x07ffffff, 0x4e000000,
557 0x28350, 0x3f3f3fff, 0x00000000,
558 0x30, 0x000000ff, 0x0040,
559 0x34, 0x00000040, 0x00004040,
560 0x9100, 0x03e00000, 0x03600000,
561 0x9060, 0x0000007f, 0x00000020,
562 0x9508, 0x00010000, 0x00010000,
563 0xac14, 0x000003ff, 0x000000f1,
564 0xac10, 0xffffffff, 0x00000000,
565 0xac0c, 0xffffffff, 0x00003210,
566 0x88d4, 0x0000001f, 0x00000010,
567 0x15c0, 0x000c0fc0, 0x000c0400
570 static const u32 hainan_golden_registers2[] =
572 0x98f8, 0xffffffff, 0x02010001
575 static const u32 tahiti_mgcg_cgcg_init[] =
577 0xc400, 0xffffffff, 0xfffffffc,
578 0x802c, 0xffffffff, 0xe0000000,
579 0x9a60, 0xffffffff, 0x00000100,
580 0x92a4, 0xffffffff, 0x00000100,
581 0xc164, 0xffffffff, 0x00000100,
582 0x9774, 0xffffffff, 0x00000100,
583 0x8984, 0xffffffff, 0x06000100,
584 0x8a18, 0xffffffff, 0x00000100,
585 0x92a0, 0xffffffff, 0x00000100,
586 0xc380, 0xffffffff, 0x00000100,
587 0x8b28, 0xffffffff, 0x00000100,
588 0x9144, 0xffffffff, 0x00000100,
589 0x8d88, 0xffffffff, 0x00000100,
590 0x8d8c, 0xffffffff, 0x00000100,
591 0x9030, 0xffffffff, 0x00000100,
592 0x9034, 0xffffffff, 0x00000100,
593 0x9038, 0xffffffff, 0x00000100,
594 0x903c, 0xffffffff, 0x00000100,
595 0xad80, 0xffffffff, 0x00000100,
596 0xac54, 0xffffffff, 0x00000100,
597 0x897c, 0xffffffff, 0x06000100,
598 0x9868, 0xffffffff, 0x00000100,
599 0x9510, 0xffffffff, 0x00000100,
600 0xaf04, 0xffffffff, 0x00000100,
601 0xae04, 0xffffffff, 0x00000100,
602 0x949c, 0xffffffff, 0x00000100,
603 0x802c, 0xffffffff, 0xe0000000,
604 0x9160, 0xffffffff, 0x00010000,
605 0x9164, 0xffffffff, 0x00030002,
606 0x9168, 0xffffffff, 0x00040007,
607 0x916c, 0xffffffff, 0x00060005,
608 0x9170, 0xffffffff, 0x00090008,
609 0x9174, 0xffffffff, 0x00020001,
610 0x9178, 0xffffffff, 0x00040003,
611 0x917c, 0xffffffff, 0x00000007,
612 0x9180, 0xffffffff, 0x00060005,
613 0x9184, 0xffffffff, 0x00090008,
614 0x9188, 0xffffffff, 0x00030002,
615 0x918c, 0xffffffff, 0x00050004,
616 0x9190, 0xffffffff, 0x00000008,
617 0x9194, 0xffffffff, 0x00070006,
618 0x9198, 0xffffffff, 0x000a0009,
619 0x919c, 0xffffffff, 0x00040003,
620 0x91a0, 0xffffffff, 0x00060005,
621 0x91a4, 0xffffffff, 0x00000009,
622 0x91a8, 0xffffffff, 0x00080007,
623 0x91ac, 0xffffffff, 0x000b000a,
624 0x91b0, 0xffffffff, 0x00050004,
625 0x91b4, 0xffffffff, 0x00070006,
626 0x91b8, 0xffffffff, 0x0008000b,
627 0x91bc, 0xffffffff, 0x000a0009,
628 0x91c0, 0xffffffff, 0x000d000c,
629 0x91c4, 0xffffffff, 0x00060005,
630 0x91c8, 0xffffffff, 0x00080007,
631 0x91cc, 0xffffffff, 0x0000000b,
632 0x91d0, 0xffffffff, 0x000a0009,
633 0x91d4, 0xffffffff, 0x000d000c,
634 0x91d8, 0xffffffff, 0x00070006,
635 0x91dc, 0xffffffff, 0x00090008,
636 0x91e0, 0xffffffff, 0x0000000c,
637 0x91e4, 0xffffffff, 0x000b000a,
638 0x91e8, 0xffffffff, 0x000e000d,
639 0x91ec, 0xffffffff, 0x00080007,
640 0x91f0, 0xffffffff, 0x000a0009,
641 0x91f4, 0xffffffff, 0x0000000d,
642 0x91f8, 0xffffffff, 0x000c000b,
643 0x91fc, 0xffffffff, 0x000f000e,
644 0x9200, 0xffffffff, 0x00090008,
645 0x9204, 0xffffffff, 0x000b000a,
646 0x9208, 0xffffffff, 0x000c000f,
647 0x920c, 0xffffffff, 0x000e000d,
648 0x9210, 0xffffffff, 0x00110010,
649 0x9214, 0xffffffff, 0x000a0009,
650 0x9218, 0xffffffff, 0x000c000b,
651 0x921c, 0xffffffff, 0x0000000f,
652 0x9220, 0xffffffff, 0x000e000d,
653 0x9224, 0xffffffff, 0x00110010,
654 0x9228, 0xffffffff, 0x000b000a,
655 0x922c, 0xffffffff, 0x000d000c,
656 0x9230, 0xffffffff, 0x00000010,
657 0x9234, 0xffffffff, 0x000f000e,
658 0x9238, 0xffffffff, 0x00120011,
659 0x923c, 0xffffffff, 0x000c000b,
660 0x9240, 0xffffffff, 0x000e000d,
661 0x9244, 0xffffffff, 0x00000011,
662 0x9248, 0xffffffff, 0x0010000f,
663 0x924c, 0xffffffff, 0x00130012,
664 0x9250, 0xffffffff, 0x000d000c,
665 0x9254, 0xffffffff, 0x000f000e,
666 0x9258, 0xffffffff, 0x00100013,
667 0x925c, 0xffffffff, 0x00120011,
668 0x9260, 0xffffffff, 0x00150014,
669 0x9264, 0xffffffff, 0x000e000d,
670 0x9268, 0xffffffff, 0x0010000f,
671 0x926c, 0xffffffff, 0x00000013,
672 0x9270, 0xffffffff, 0x00120011,
673 0x9274, 0xffffffff, 0x00150014,
674 0x9278, 0xffffffff, 0x000f000e,
675 0x927c, 0xffffffff, 0x00110010,
676 0x9280, 0xffffffff, 0x00000014,
677 0x9284, 0xffffffff, 0x00130012,
678 0x9288, 0xffffffff, 0x00160015,
679 0x928c, 0xffffffff, 0x0010000f,
680 0x9290, 0xffffffff, 0x00120011,
681 0x9294, 0xffffffff, 0x00000015,
682 0x9298, 0xffffffff, 0x00140013,
683 0x929c, 0xffffffff, 0x00170016,
684 0x9150, 0xffffffff, 0x96940200,
685 0x8708, 0xffffffff, 0x00900100,
686 0xc478, 0xffffffff, 0x00000080,
687 0xc404, 0xffffffff, 0x0020003f,
688 0x30, 0xffffffff, 0x0000001c,
689 0x34, 0x000f0000, 0x000f0000,
690 0x160c, 0xffffffff, 0x00000100,
691 0x1024, 0xffffffff, 0x00000100,
692 0x102c, 0x00000101, 0x00000000,
693 0x20a8, 0xffffffff, 0x00000104,
694 0x264c, 0x000c0000, 0x000c0000,
695 0x2648, 0x000c0000, 0x000c0000,
696 0x55e4, 0xff000fff, 0x00000100,
697 0x55e8, 0x00000001, 0x00000001,
698 0x2f50, 0x00000001, 0x00000001,
699 0x30cc, 0xc0000fff, 0x00000104,
700 0xc1e4, 0x00000001, 0x00000001,
701 0xd0c0, 0xfffffff0, 0x00000100,
702 0xd8c0, 0xfffffff0, 0x00000100
705 static const u32 pitcairn_mgcg_cgcg_init[] =
707 0xc400, 0xffffffff, 0xfffffffc,
708 0x802c, 0xffffffff, 0xe0000000,
709 0x9a60, 0xffffffff, 0x00000100,
710 0x92a4, 0xffffffff, 0x00000100,
711 0xc164, 0xffffffff, 0x00000100,
712 0x9774, 0xffffffff, 0x00000100,
713 0x8984, 0xffffffff, 0x06000100,
714 0x8a18, 0xffffffff, 0x00000100,
715 0x92a0, 0xffffffff, 0x00000100,
716 0xc380, 0xffffffff, 0x00000100,
717 0x8b28, 0xffffffff, 0x00000100,
718 0x9144, 0xffffffff, 0x00000100,
719 0x8d88, 0xffffffff, 0x00000100,
720 0x8d8c, 0xffffffff, 0x00000100,
721 0x9030, 0xffffffff, 0x00000100,
722 0x9034, 0xffffffff, 0x00000100,
723 0x9038, 0xffffffff, 0x00000100,
724 0x903c, 0xffffffff, 0x00000100,
725 0xad80, 0xffffffff, 0x00000100,
726 0xac54, 0xffffffff, 0x00000100,
727 0x897c, 0xffffffff, 0x06000100,
728 0x9868, 0xffffffff, 0x00000100,
729 0x9510, 0xffffffff, 0x00000100,
730 0xaf04, 0xffffffff, 0x00000100,
731 0xae04, 0xffffffff, 0x00000100,
732 0x949c, 0xffffffff, 0x00000100,
733 0x802c, 0xffffffff, 0xe0000000,
734 0x9160, 0xffffffff, 0x00010000,
735 0x9164, 0xffffffff, 0x00030002,
736 0x9168, 0xffffffff, 0x00040007,
737 0x916c, 0xffffffff, 0x00060005,
738 0x9170, 0xffffffff, 0x00090008,
739 0x9174, 0xffffffff, 0x00020001,
740 0x9178, 0xffffffff, 0x00040003,
741 0x917c, 0xffffffff, 0x00000007,
742 0x9180, 0xffffffff, 0x00060005,
743 0x9184, 0xffffffff, 0x00090008,
744 0x9188, 0xffffffff, 0x00030002,
745 0x918c, 0xffffffff, 0x00050004,
746 0x9190, 0xffffffff, 0x00000008,
747 0x9194, 0xffffffff, 0x00070006,
748 0x9198, 0xffffffff, 0x000a0009,
749 0x919c, 0xffffffff, 0x00040003,
750 0x91a0, 0xffffffff, 0x00060005,
751 0x91a4, 0xffffffff, 0x00000009,
752 0x91a8, 0xffffffff, 0x00080007,
753 0x91ac, 0xffffffff, 0x000b000a,
754 0x91b0, 0xffffffff, 0x00050004,
755 0x91b4, 0xffffffff, 0x00070006,
756 0x91b8, 0xffffffff, 0x0008000b,
757 0x91bc, 0xffffffff, 0x000a0009,
758 0x91c0, 0xffffffff, 0x000d000c,
759 0x9200, 0xffffffff, 0x00090008,
760 0x9204, 0xffffffff, 0x000b000a,
761 0x9208, 0xffffffff, 0x000c000f,
762 0x920c, 0xffffffff, 0x000e000d,
763 0x9210, 0xffffffff, 0x00110010,
764 0x9214, 0xffffffff, 0x000a0009,
765 0x9218, 0xffffffff, 0x000c000b,
766 0x921c, 0xffffffff, 0x0000000f,
767 0x9220, 0xffffffff, 0x000e000d,
768 0x9224, 0xffffffff, 0x00110010,
769 0x9228, 0xffffffff, 0x000b000a,
770 0x922c, 0xffffffff, 0x000d000c,
771 0x9230, 0xffffffff, 0x00000010,
772 0x9234, 0xffffffff, 0x000f000e,
773 0x9238, 0xffffffff, 0x00120011,
774 0x923c, 0xffffffff, 0x000c000b,
775 0x9240, 0xffffffff, 0x000e000d,
776 0x9244, 0xffffffff, 0x00000011,
777 0x9248, 0xffffffff, 0x0010000f,
778 0x924c, 0xffffffff, 0x00130012,
779 0x9250, 0xffffffff, 0x000d000c,
780 0x9254, 0xffffffff, 0x000f000e,
781 0x9258, 0xffffffff, 0x00100013,
782 0x925c, 0xffffffff, 0x00120011,
783 0x9260, 0xffffffff, 0x00150014,
784 0x9150, 0xffffffff, 0x96940200,
785 0x8708, 0xffffffff, 0x00900100,
786 0xc478, 0xffffffff, 0x00000080,
787 0xc404, 0xffffffff, 0x0020003f,
788 0x30, 0xffffffff, 0x0000001c,
789 0x34, 0x000f0000, 0x000f0000,
790 0x160c, 0xffffffff, 0x00000100,
791 0x1024, 0xffffffff, 0x00000100,
792 0x102c, 0x00000101, 0x00000000,
793 0x20a8, 0xffffffff, 0x00000104,
794 0x55e4, 0xff000fff, 0x00000100,
795 0x55e8, 0x00000001, 0x00000001,
796 0x2f50, 0x00000001, 0x00000001,
797 0x30cc, 0xc0000fff, 0x00000104,
798 0xc1e4, 0x00000001, 0x00000001,
799 0xd0c0, 0xfffffff0, 0x00000100,
800 0xd8c0, 0xfffffff0, 0x00000100
803 static const u32 verde_mgcg_cgcg_init[] =
805 0xc400, 0xffffffff, 0xfffffffc,
806 0x802c, 0xffffffff, 0xe0000000,
807 0x9a60, 0xffffffff, 0x00000100,
808 0x92a4, 0xffffffff, 0x00000100,
809 0xc164, 0xffffffff, 0x00000100,
810 0x9774, 0xffffffff, 0x00000100,
811 0x8984, 0xffffffff, 0x06000100,
812 0x8a18, 0xffffffff, 0x00000100,
813 0x92a0, 0xffffffff, 0x00000100,
814 0xc380, 0xffffffff, 0x00000100,
815 0x8b28, 0xffffffff, 0x00000100,
816 0x9144, 0xffffffff, 0x00000100,
817 0x8d88, 0xffffffff, 0x00000100,
818 0x8d8c, 0xffffffff, 0x00000100,
819 0x9030, 0xffffffff, 0x00000100,
820 0x9034, 0xffffffff, 0x00000100,
821 0x9038, 0xffffffff, 0x00000100,
822 0x903c, 0xffffffff, 0x00000100,
823 0xad80, 0xffffffff, 0x00000100,
824 0xac54, 0xffffffff, 0x00000100,
825 0x897c, 0xffffffff, 0x06000100,
826 0x9868, 0xffffffff, 0x00000100,
827 0x9510, 0xffffffff, 0x00000100,
828 0xaf04, 0xffffffff, 0x00000100,
829 0xae04, 0xffffffff, 0x00000100,
830 0x949c, 0xffffffff, 0x00000100,
831 0x802c, 0xffffffff, 0xe0000000,
832 0x9160, 0xffffffff, 0x00010000,
833 0x9164, 0xffffffff, 0x00030002,
834 0x9168, 0xffffffff, 0x00040007,
835 0x916c, 0xffffffff, 0x00060005,
836 0x9170, 0xffffffff, 0x00090008,
837 0x9174, 0xffffffff, 0x00020001,
838 0x9178, 0xffffffff, 0x00040003,
839 0x917c, 0xffffffff, 0x00000007,
840 0x9180, 0xffffffff, 0x00060005,
841 0x9184, 0xffffffff, 0x00090008,
842 0x9188, 0xffffffff, 0x00030002,
843 0x918c, 0xffffffff, 0x00050004,
844 0x9190, 0xffffffff, 0x00000008,
845 0x9194, 0xffffffff, 0x00070006,
846 0x9198, 0xffffffff, 0x000a0009,
847 0x919c, 0xffffffff, 0x00040003,
848 0x91a0, 0xffffffff, 0x00060005,
849 0x91a4, 0xffffffff, 0x00000009,
850 0x91a8, 0xffffffff, 0x00080007,
851 0x91ac, 0xffffffff, 0x000b000a,
852 0x91b0, 0xffffffff, 0x00050004,
853 0x91b4, 0xffffffff, 0x00070006,
854 0x91b8, 0xffffffff, 0x0008000b,
855 0x91bc, 0xffffffff, 0x000a0009,
856 0x91c0, 0xffffffff, 0x000d000c,
857 0x9200, 0xffffffff, 0x00090008,
858 0x9204, 0xffffffff, 0x000b000a,
859 0x9208, 0xffffffff, 0x000c000f,
860 0x920c, 0xffffffff, 0x000e000d,
861 0x9210, 0xffffffff, 0x00110010,
862 0x9214, 0xffffffff, 0x000a0009,
863 0x9218, 0xffffffff, 0x000c000b,
864 0x921c, 0xffffffff, 0x0000000f,
865 0x9220, 0xffffffff, 0x000e000d,
866 0x9224, 0xffffffff, 0x00110010,
867 0x9228, 0xffffffff, 0x000b000a,
868 0x922c, 0xffffffff, 0x000d000c,
869 0x9230, 0xffffffff, 0x00000010,
870 0x9234, 0xffffffff, 0x000f000e,
871 0x9238, 0xffffffff, 0x00120011,
872 0x923c, 0xffffffff, 0x000c000b,
873 0x9240, 0xffffffff, 0x000e000d,
874 0x9244, 0xffffffff, 0x00000011,
875 0x9248, 0xffffffff, 0x0010000f,
876 0x924c, 0xffffffff, 0x00130012,
877 0x9250, 0xffffffff, 0x000d000c,
878 0x9254, 0xffffffff, 0x000f000e,
879 0x9258, 0xffffffff, 0x00100013,
880 0x925c, 0xffffffff, 0x00120011,
881 0x9260, 0xffffffff, 0x00150014,
882 0x9150, 0xffffffff, 0x96940200,
883 0x8708, 0xffffffff, 0x00900100,
884 0xc478, 0xffffffff, 0x00000080,
885 0xc404, 0xffffffff, 0x0020003f,
886 0x30, 0xffffffff, 0x0000001c,
887 0x34, 0x000f0000, 0x000f0000,
888 0x160c, 0xffffffff, 0x00000100,
889 0x1024, 0xffffffff, 0x00000100,
890 0x102c, 0x00000101, 0x00000000,
891 0x20a8, 0xffffffff, 0x00000104,
892 0x264c, 0x000c0000, 0x000c0000,
893 0x2648, 0x000c0000, 0x000c0000,
894 0x55e4, 0xff000fff, 0x00000100,
895 0x55e8, 0x00000001, 0x00000001,
896 0x2f50, 0x00000001, 0x00000001,
897 0x30cc, 0xc0000fff, 0x00000104,
898 0xc1e4, 0x00000001, 0x00000001,
899 0xd0c0, 0xfffffff0, 0x00000100,
900 0xd8c0, 0xfffffff0, 0x00000100
903 static const u32 oland_mgcg_cgcg_init[] =
905 0xc400, 0xffffffff, 0xfffffffc,
906 0x802c, 0xffffffff, 0xe0000000,
907 0x9a60, 0xffffffff, 0x00000100,
908 0x92a4, 0xffffffff, 0x00000100,
909 0xc164, 0xffffffff, 0x00000100,
910 0x9774, 0xffffffff, 0x00000100,
911 0x8984, 0xffffffff, 0x06000100,
912 0x8a18, 0xffffffff, 0x00000100,
913 0x92a0, 0xffffffff, 0x00000100,
914 0xc380, 0xffffffff, 0x00000100,
915 0x8b28, 0xffffffff, 0x00000100,
916 0x9144, 0xffffffff, 0x00000100,
917 0x8d88, 0xffffffff, 0x00000100,
918 0x8d8c, 0xffffffff, 0x00000100,
919 0x9030, 0xffffffff, 0x00000100,
920 0x9034, 0xffffffff, 0x00000100,
921 0x9038, 0xffffffff, 0x00000100,
922 0x903c, 0xffffffff, 0x00000100,
923 0xad80, 0xffffffff, 0x00000100,
924 0xac54, 0xffffffff, 0x00000100,
925 0x897c, 0xffffffff, 0x06000100,
926 0x9868, 0xffffffff, 0x00000100,
927 0x9510, 0xffffffff, 0x00000100,
928 0xaf04, 0xffffffff, 0x00000100,
929 0xae04, 0xffffffff, 0x00000100,
930 0x949c, 0xffffffff, 0x00000100,
931 0x802c, 0xffffffff, 0xe0000000,
932 0x9160, 0xffffffff, 0x00010000,
933 0x9164, 0xffffffff, 0x00030002,
934 0x9168, 0xffffffff, 0x00040007,
935 0x916c, 0xffffffff, 0x00060005,
936 0x9170, 0xffffffff, 0x00090008,
937 0x9174, 0xffffffff, 0x00020001,
938 0x9178, 0xffffffff, 0x00040003,
939 0x917c, 0xffffffff, 0x00000007,
940 0x9180, 0xffffffff, 0x00060005,
941 0x9184, 0xffffffff, 0x00090008,
942 0x9188, 0xffffffff, 0x00030002,
943 0x918c, 0xffffffff, 0x00050004,
944 0x9190, 0xffffffff, 0x00000008,
945 0x9194, 0xffffffff, 0x00070006,
946 0x9198, 0xffffffff, 0x000a0009,
947 0x919c, 0xffffffff, 0x00040003,
948 0x91a0, 0xffffffff, 0x00060005,
949 0x91a4, 0xffffffff, 0x00000009,
950 0x91a8, 0xffffffff, 0x00080007,
951 0x91ac, 0xffffffff, 0x000b000a,
952 0x91b0, 0xffffffff, 0x00050004,
953 0x91b4, 0xffffffff, 0x00070006,
954 0x91b8, 0xffffffff, 0x0008000b,
955 0x91bc, 0xffffffff, 0x000a0009,
956 0x91c0, 0xffffffff, 0x000d000c,
957 0x91c4, 0xffffffff, 0x00060005,
958 0x91c8, 0xffffffff, 0x00080007,
959 0x91cc, 0xffffffff, 0x0000000b,
960 0x91d0, 0xffffffff, 0x000a0009,
961 0x91d4, 0xffffffff, 0x000d000c,
962 0x9150, 0xffffffff, 0x96940200,
963 0x8708, 0xffffffff, 0x00900100,
964 0xc478, 0xffffffff, 0x00000080,
965 0xc404, 0xffffffff, 0x0020003f,
966 0x30, 0xffffffff, 0x0000001c,
967 0x34, 0x000f0000, 0x000f0000,
968 0x160c, 0xffffffff, 0x00000100,
969 0x1024, 0xffffffff, 0x00000100,
970 0x102c, 0x00000101, 0x00000000,
971 0x20a8, 0xffffffff, 0x00000104,
972 0x264c, 0x000c0000, 0x000c0000,
973 0x2648, 0x000c0000, 0x000c0000,
974 0x55e4, 0xff000fff, 0x00000100,
975 0x55e8, 0x00000001, 0x00000001,
976 0x2f50, 0x00000001, 0x00000001,
977 0x30cc, 0xc0000fff, 0x00000104,
978 0xc1e4, 0x00000001, 0x00000001,
979 0xd0c0, 0xfffffff0, 0x00000100,
980 0xd8c0, 0xfffffff0, 0x00000100
983 static const u32 hainan_mgcg_cgcg_init[] =
985 0xc400, 0xffffffff, 0xfffffffc,
986 0x802c, 0xffffffff, 0xe0000000,
987 0x9a60, 0xffffffff, 0x00000100,
988 0x92a4, 0xffffffff, 0x00000100,
989 0xc164, 0xffffffff, 0x00000100,
990 0x9774, 0xffffffff, 0x00000100,
991 0x8984, 0xffffffff, 0x06000100,
992 0x8a18, 0xffffffff, 0x00000100,
993 0x92a0, 0xffffffff, 0x00000100,
994 0xc380, 0xffffffff, 0x00000100,
995 0x8b28, 0xffffffff, 0x00000100,
996 0x9144, 0xffffffff, 0x00000100,
997 0x8d88, 0xffffffff, 0x00000100,
998 0x8d8c, 0xffffffff, 0x00000100,
999 0x9030, 0xffffffff, 0x00000100,
1000 0x9034, 0xffffffff, 0x00000100,
1001 0x9038, 0xffffffff, 0x00000100,
1002 0x903c, 0xffffffff, 0x00000100,
1003 0xad80, 0xffffffff, 0x00000100,
1004 0xac54, 0xffffffff, 0x00000100,
1005 0x897c, 0xffffffff, 0x06000100,
1006 0x9868, 0xffffffff, 0x00000100,
1007 0x9510, 0xffffffff, 0x00000100,
1008 0xaf04, 0xffffffff, 0x00000100,
1009 0xae04, 0xffffffff, 0x00000100,
1010 0x949c, 0xffffffff, 0x00000100,
1011 0x802c, 0xffffffff, 0xe0000000,
1012 0x9160, 0xffffffff, 0x00010000,
1013 0x9164, 0xffffffff, 0x00030002,
1014 0x9168, 0xffffffff, 0x00040007,
1015 0x916c, 0xffffffff, 0x00060005,
1016 0x9170, 0xffffffff, 0x00090008,
1017 0x9174, 0xffffffff, 0x00020001,
1018 0x9178, 0xffffffff, 0x00040003,
1019 0x917c, 0xffffffff, 0x00000007,
1020 0x9180, 0xffffffff, 0x00060005,
1021 0x9184, 0xffffffff, 0x00090008,
1022 0x9188, 0xffffffff, 0x00030002,
1023 0x918c, 0xffffffff, 0x00050004,
1024 0x9190, 0xffffffff, 0x00000008,
1025 0x9194, 0xffffffff, 0x00070006,
1026 0x9198, 0xffffffff, 0x000a0009,
1027 0x919c, 0xffffffff, 0x00040003,
1028 0x91a0, 0xffffffff, 0x00060005,
1029 0x91a4, 0xffffffff, 0x00000009,
1030 0x91a8, 0xffffffff, 0x00080007,
1031 0x91ac, 0xffffffff, 0x000b000a,
1032 0x91b0, 0xffffffff, 0x00050004,
1033 0x91b4, 0xffffffff, 0x00070006,
1034 0x91b8, 0xffffffff, 0x0008000b,
1035 0x91bc, 0xffffffff, 0x000a0009,
1036 0x91c0, 0xffffffff, 0x000d000c,
1037 0x91c4, 0xffffffff, 0x00060005,
1038 0x91c8, 0xffffffff, 0x00080007,
1039 0x91cc, 0xffffffff, 0x0000000b,
1040 0x91d0, 0xffffffff, 0x000a0009,
1041 0x91d4, 0xffffffff, 0x000d000c,
1042 0x9150, 0xffffffff, 0x96940200,
1043 0x8708, 0xffffffff, 0x00900100,
1044 0xc478, 0xffffffff, 0x00000080,
1045 0xc404, 0xffffffff, 0x0020003f,
1046 0x30, 0xffffffff, 0x0000001c,
1047 0x34, 0x000f0000, 0x000f0000,
1048 0x160c, 0xffffffff, 0x00000100,
1049 0x1024, 0xffffffff, 0x00000100,
1050 0x20a8, 0xffffffff, 0x00000104,
1051 0x264c, 0x000c0000, 0x000c0000,
1052 0x2648, 0x000c0000, 0x000c0000,
1053 0x2f50, 0x00000001, 0x00000001,
1054 0x30cc, 0xc0000fff, 0x00000104,
1055 0xc1e4, 0x00000001, 0x00000001,
1056 0xd0c0, 0xfffffff0, 0x00000100,
1057 0xd8c0, 0xfffffff0, 0x00000100
1060 static u32 verde_pg_init[] =
1062 0x353c, 0xffffffff, 0x40000,
1063 0x3538, 0xffffffff, 0x200010ff,
1064 0x353c, 0xffffffff, 0x0,
1065 0x353c, 0xffffffff, 0x0,
1066 0x353c, 0xffffffff, 0x0,
1067 0x353c, 0xffffffff, 0x0,
1068 0x353c, 0xffffffff, 0x0,
1069 0x353c, 0xffffffff, 0x7007,
1070 0x3538, 0xffffffff, 0x300010ff,
1071 0x353c, 0xffffffff, 0x0,
1072 0x353c, 0xffffffff, 0x0,
1073 0x353c, 0xffffffff, 0x0,
1074 0x353c, 0xffffffff, 0x0,
1075 0x353c, 0xffffffff, 0x0,
1076 0x353c, 0xffffffff, 0x400000,
1077 0x3538, 0xffffffff, 0x100010ff,
1078 0x353c, 0xffffffff, 0x0,
1079 0x353c, 0xffffffff, 0x0,
1080 0x353c, 0xffffffff, 0x0,
1081 0x353c, 0xffffffff, 0x0,
1082 0x353c, 0xffffffff, 0x0,
1083 0x353c, 0xffffffff, 0x120200,
1084 0x3538, 0xffffffff, 0x500010ff,
1085 0x353c, 0xffffffff, 0x0,
1086 0x353c, 0xffffffff, 0x0,
1087 0x353c, 0xffffffff, 0x0,
1088 0x353c, 0xffffffff, 0x0,
1089 0x353c, 0xffffffff, 0x0,
1090 0x353c, 0xffffffff, 0x1e1e16,
1091 0x3538, 0xffffffff, 0x600010ff,
1092 0x353c, 0xffffffff, 0x0,
1093 0x353c, 0xffffffff, 0x0,
1094 0x353c, 0xffffffff, 0x0,
1095 0x353c, 0xffffffff, 0x0,
1096 0x353c, 0xffffffff, 0x0,
1097 0x353c, 0xffffffff, 0x171f1e,
1098 0x3538, 0xffffffff, 0x700010ff,
1099 0x353c, 0xffffffff, 0x0,
1100 0x353c, 0xffffffff, 0x0,
1101 0x353c, 0xffffffff, 0x0,
1102 0x353c, 0xffffffff, 0x0,
1103 0x353c, 0xffffffff, 0x0,
1104 0x353c, 0xffffffff, 0x0,
1105 0x3538, 0xffffffff, 0x9ff,
1106 0x3500, 0xffffffff, 0x0,
1107 0x3504, 0xffffffff, 0x10000800,
1108 0x3504, 0xffffffff, 0xf,
1109 0x3504, 0xffffffff, 0xf,
1110 0x3500, 0xffffffff, 0x4,
1111 0x3504, 0xffffffff, 0x1000051e,
1112 0x3504, 0xffffffff, 0xffff,
1113 0x3504, 0xffffffff, 0xffff,
1114 0x3500, 0xffffffff, 0x8,
1115 0x3504, 0xffffffff, 0x80500,
1116 0x3500, 0xffffffff, 0x12,
1117 0x3504, 0xffffffff, 0x9050c,
1118 0x3500, 0xffffffff, 0x1d,
1119 0x3504, 0xffffffff, 0xb052c,
1120 0x3500, 0xffffffff, 0x2a,
1121 0x3504, 0xffffffff, 0x1053e,
1122 0x3500, 0xffffffff, 0x2d,
1123 0x3504, 0xffffffff, 0x10546,
1124 0x3500, 0xffffffff, 0x30,
1125 0x3504, 0xffffffff, 0xa054e,
1126 0x3500, 0xffffffff, 0x3c,
1127 0x3504, 0xffffffff, 0x1055f,
1128 0x3500, 0xffffffff, 0x3f,
1129 0x3504, 0xffffffff, 0x10567,
1130 0x3500, 0xffffffff, 0x42,
1131 0x3504, 0xffffffff, 0x1056f,
1132 0x3500, 0xffffffff, 0x45,
1133 0x3504, 0xffffffff, 0x10572,
1134 0x3500, 0xffffffff, 0x48,
1135 0x3504, 0xffffffff, 0x20575,
1136 0x3500, 0xffffffff, 0x4c,
1137 0x3504, 0xffffffff, 0x190801,
1138 0x3500, 0xffffffff, 0x67,
1139 0x3504, 0xffffffff, 0x1082a,
1140 0x3500, 0xffffffff, 0x6a,
1141 0x3504, 0xffffffff, 0x1b082d,
1142 0x3500, 0xffffffff, 0x87,
1143 0x3504, 0xffffffff, 0x310851,
1144 0x3500, 0xffffffff, 0xba,
1145 0x3504, 0xffffffff, 0x891,
1146 0x3500, 0xffffffff, 0xbc,
1147 0x3504, 0xffffffff, 0x893,
1148 0x3500, 0xffffffff, 0xbe,
1149 0x3504, 0xffffffff, 0x20895,
1150 0x3500, 0xffffffff, 0xc2,
1151 0x3504, 0xffffffff, 0x20899,
1152 0x3500, 0xffffffff, 0xc6,
1153 0x3504, 0xffffffff, 0x2089d,
1154 0x3500, 0xffffffff, 0xca,
1155 0x3504, 0xffffffff, 0x8a1,
1156 0x3500, 0xffffffff, 0xcc,
1157 0x3504, 0xffffffff, 0x8a3,
1158 0x3500, 0xffffffff, 0xce,
1159 0x3504, 0xffffffff, 0x308a5,
1160 0x3500, 0xffffffff, 0xd3,
1161 0x3504, 0xffffffff, 0x6d08cd,
1162 0x3500, 0xffffffff, 0x142,
1163 0x3504, 0xffffffff, 0x2000095a,
1164 0x3504, 0xffffffff, 0x1,
1165 0x3500, 0xffffffff, 0x144,
1166 0x3504, 0xffffffff, 0x301f095b,
1167 0x3500, 0xffffffff, 0x165,
1168 0x3504, 0xffffffff, 0xc094d,
1169 0x3500, 0xffffffff, 0x173,
1170 0x3504, 0xffffffff, 0xf096d,
1171 0x3500, 0xffffffff, 0x184,
1172 0x3504, 0xffffffff, 0x15097f,
1173 0x3500, 0xffffffff, 0x19b,
1174 0x3504, 0xffffffff, 0xc0998,
1175 0x3500, 0xffffffff, 0x1a9,
1176 0x3504, 0xffffffff, 0x409a7,
1177 0x3500, 0xffffffff, 0x1af,
1178 0x3504, 0xffffffff, 0xcdc,
1179 0x3500, 0xffffffff, 0x1b1,
1180 0x3504, 0xffffffff, 0x800,
1181 0x3508, 0xffffffff, 0x6c9b2000,
1182 0x3510, 0xfc00, 0x2000,
1183 0x3544, 0xffffffff, 0xfc0,
1184 0x28d4, 0x00000100, 0x100
1187 static void si_init_golden_registers(struct radeon_device *rdev)
1189 switch (rdev->family) {
1191 radeon_program_register_sequence(rdev,
1192 tahiti_golden_registers,
1193 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1194 radeon_program_register_sequence(rdev,
1195 tahiti_golden_rlc_registers,
1196 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1197 radeon_program_register_sequence(rdev,
1198 tahiti_mgcg_cgcg_init,
1199 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1200 radeon_program_register_sequence(rdev,
1201 tahiti_golden_registers2,
1202 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1205 radeon_program_register_sequence(rdev,
1206 pitcairn_golden_registers,
1207 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1208 radeon_program_register_sequence(rdev,
1209 pitcairn_golden_rlc_registers,
1210 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1211 radeon_program_register_sequence(rdev,
1212 pitcairn_mgcg_cgcg_init,
1213 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1216 radeon_program_register_sequence(rdev,
1217 verde_golden_registers,
1218 (const u32)ARRAY_SIZE(verde_golden_registers));
1219 radeon_program_register_sequence(rdev,
1220 verde_golden_rlc_registers,
1221 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1222 radeon_program_register_sequence(rdev,
1223 verde_mgcg_cgcg_init,
1224 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1225 radeon_program_register_sequence(rdev,
1227 (const u32)ARRAY_SIZE(verde_pg_init));
1230 radeon_program_register_sequence(rdev,
1231 oland_golden_registers,
1232 (const u32)ARRAY_SIZE(oland_golden_registers));
1233 radeon_program_register_sequence(rdev,
1234 oland_golden_rlc_registers,
1235 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1236 radeon_program_register_sequence(rdev,
1237 oland_mgcg_cgcg_init,
1238 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1241 radeon_program_register_sequence(rdev,
1242 hainan_golden_registers,
1243 (const u32)ARRAY_SIZE(hainan_golden_registers));
1244 radeon_program_register_sequence(rdev,
1245 hainan_golden_registers2,
1246 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1247 radeon_program_register_sequence(rdev,
1248 hainan_mgcg_cgcg_init,
1249 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1257 * si_get_allowed_info_register - fetch the register for the info ioctl
1259 * @rdev: radeon_device pointer
1260 * @reg: register offset in bytes
1261 * @val: register value
1263 * Returns 0 for success or -EINVAL for an invalid register
1266 int si_get_allowed_info_register(struct radeon_device *rdev,
1272 case GRBM_STATUS_SE0:
1273 case GRBM_STATUS_SE1:
1276 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
1277 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
1286 #define PCIE_BUS_CLK 10000
1287 #define TCLK (PCIE_BUS_CLK / 10)
1290 * si_get_xclk - get the xclk
1292 * @rdev: radeon_device pointer
1294 * Returns the reference clock used by the gfx engine
1297 u32 si_get_xclk(struct radeon_device *rdev)
1299 u32 reference_clock = rdev->clock.spll.reference_freq;
1302 tmp = RREG32(CG_CLKPIN_CNTL_2);
1303 if (tmp & MUX_TCLK_TO_XCLK)
1306 tmp = RREG32(CG_CLKPIN_CNTL);
1307 if (tmp & XTALIN_DIVIDE)
1308 return reference_clock / 4;
1310 return reference_clock;
1313 /* get temperature in millidegrees */
1314 int si_get_temp(struct radeon_device *rdev)
1317 int actual_temp = 0;
1319 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
1325 actual_temp = temp & 0x1ff;
1327 actual_temp = (actual_temp * 1000);
1332 #define TAHITI_IO_MC_REGS_SIZE 36
1334 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1335 {0x0000006f, 0x03044000},
1336 {0x00000070, 0x0480c018},
1337 {0x00000071, 0x00000040},
1338 {0x00000072, 0x01000000},
1339 {0x00000074, 0x000000ff},
1340 {0x00000075, 0x00143400},
1341 {0x00000076, 0x08ec0800},
1342 {0x00000077, 0x040000cc},
1343 {0x00000079, 0x00000000},
1344 {0x0000007a, 0x21000409},
1345 {0x0000007c, 0x00000000},
1346 {0x0000007d, 0xe8000000},
1347 {0x0000007e, 0x044408a8},
1348 {0x0000007f, 0x00000003},
1349 {0x00000080, 0x00000000},
1350 {0x00000081, 0x01000000},
1351 {0x00000082, 0x02000000},
1352 {0x00000083, 0x00000000},
1353 {0x00000084, 0xe3f3e4f4},
1354 {0x00000085, 0x00052024},
1355 {0x00000087, 0x00000000},
1356 {0x00000088, 0x66036603},
1357 {0x00000089, 0x01000000},
1358 {0x0000008b, 0x1c0a0000},
1359 {0x0000008c, 0xff010000},
1360 {0x0000008e, 0xffffefff},
1361 {0x0000008f, 0xfff3efff},
1362 {0x00000090, 0xfff3efbf},
1363 {0x00000094, 0x00101101},
1364 {0x00000095, 0x00000fff},
1365 {0x00000096, 0x00116fff},
1366 {0x00000097, 0x60010000},
1367 {0x00000098, 0x10010000},
1368 {0x00000099, 0x00006000},
1369 {0x0000009a, 0x00001000},
1370 {0x0000009f, 0x00a77400}
1373 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1374 {0x0000006f, 0x03044000},
1375 {0x00000070, 0x0480c018},
1376 {0x00000071, 0x00000040},
1377 {0x00000072, 0x01000000},
1378 {0x00000074, 0x000000ff},
1379 {0x00000075, 0x00143400},
1380 {0x00000076, 0x08ec0800},
1381 {0x00000077, 0x040000cc},
1382 {0x00000079, 0x00000000},
1383 {0x0000007a, 0x21000409},
1384 {0x0000007c, 0x00000000},
1385 {0x0000007d, 0xe8000000},
1386 {0x0000007e, 0x044408a8},
1387 {0x0000007f, 0x00000003},
1388 {0x00000080, 0x00000000},
1389 {0x00000081, 0x01000000},
1390 {0x00000082, 0x02000000},
1391 {0x00000083, 0x00000000},
1392 {0x00000084, 0xe3f3e4f4},
1393 {0x00000085, 0x00052024},
1394 {0x00000087, 0x00000000},
1395 {0x00000088, 0x66036603},
1396 {0x00000089, 0x01000000},
1397 {0x0000008b, 0x1c0a0000},
1398 {0x0000008c, 0xff010000},
1399 {0x0000008e, 0xffffefff},
1400 {0x0000008f, 0xfff3efff},
1401 {0x00000090, 0xfff3efbf},
1402 {0x00000094, 0x00101101},
1403 {0x00000095, 0x00000fff},
1404 {0x00000096, 0x00116fff},
1405 {0x00000097, 0x60010000},
1406 {0x00000098, 0x10010000},
1407 {0x00000099, 0x00006000},
1408 {0x0000009a, 0x00001000},
1409 {0x0000009f, 0x00a47400}
1412 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1413 {0x0000006f, 0x03044000},
1414 {0x00000070, 0x0480c018},
1415 {0x00000071, 0x00000040},
1416 {0x00000072, 0x01000000},
1417 {0x00000074, 0x000000ff},
1418 {0x00000075, 0x00143400},
1419 {0x00000076, 0x08ec0800},
1420 {0x00000077, 0x040000cc},
1421 {0x00000079, 0x00000000},
1422 {0x0000007a, 0x21000409},
1423 {0x0000007c, 0x00000000},
1424 {0x0000007d, 0xe8000000},
1425 {0x0000007e, 0x044408a8},
1426 {0x0000007f, 0x00000003},
1427 {0x00000080, 0x00000000},
1428 {0x00000081, 0x01000000},
1429 {0x00000082, 0x02000000},
1430 {0x00000083, 0x00000000},
1431 {0x00000084, 0xe3f3e4f4},
1432 {0x00000085, 0x00052024},
1433 {0x00000087, 0x00000000},
1434 {0x00000088, 0x66036603},
1435 {0x00000089, 0x01000000},
1436 {0x0000008b, 0x1c0a0000},
1437 {0x0000008c, 0xff010000},
1438 {0x0000008e, 0xffffefff},
1439 {0x0000008f, 0xfff3efff},
1440 {0x00000090, 0xfff3efbf},
1441 {0x00000094, 0x00101101},
1442 {0x00000095, 0x00000fff},
1443 {0x00000096, 0x00116fff},
1444 {0x00000097, 0x60010000},
1445 {0x00000098, 0x10010000},
1446 {0x00000099, 0x00006000},
1447 {0x0000009a, 0x00001000},
1448 {0x0000009f, 0x00a37400}
1451 static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1452 {0x0000006f, 0x03044000},
1453 {0x00000070, 0x0480c018},
1454 {0x00000071, 0x00000040},
1455 {0x00000072, 0x01000000},
1456 {0x00000074, 0x000000ff},
1457 {0x00000075, 0x00143400},
1458 {0x00000076, 0x08ec0800},
1459 {0x00000077, 0x040000cc},
1460 {0x00000079, 0x00000000},
1461 {0x0000007a, 0x21000409},
1462 {0x0000007c, 0x00000000},
1463 {0x0000007d, 0xe8000000},
1464 {0x0000007e, 0x044408a8},
1465 {0x0000007f, 0x00000003},
1466 {0x00000080, 0x00000000},
1467 {0x00000081, 0x01000000},
1468 {0x00000082, 0x02000000},
1469 {0x00000083, 0x00000000},
1470 {0x00000084, 0xe3f3e4f4},
1471 {0x00000085, 0x00052024},
1472 {0x00000087, 0x00000000},
1473 {0x00000088, 0x66036603},
1474 {0x00000089, 0x01000000},
1475 {0x0000008b, 0x1c0a0000},
1476 {0x0000008c, 0xff010000},
1477 {0x0000008e, 0xffffefff},
1478 {0x0000008f, 0xfff3efff},
1479 {0x00000090, 0xfff3efbf},
1480 {0x00000094, 0x00101101},
1481 {0x00000095, 0x00000fff},
1482 {0x00000096, 0x00116fff},
1483 {0x00000097, 0x60010000},
1484 {0x00000098, 0x10010000},
1485 {0x00000099, 0x00006000},
1486 {0x0000009a, 0x00001000},
1487 {0x0000009f, 0x00a17730}
1490 static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1491 {0x0000006f, 0x03044000},
1492 {0x00000070, 0x0480c018},
1493 {0x00000071, 0x00000040},
1494 {0x00000072, 0x01000000},
1495 {0x00000074, 0x000000ff},
1496 {0x00000075, 0x00143400},
1497 {0x00000076, 0x08ec0800},
1498 {0x00000077, 0x040000cc},
1499 {0x00000079, 0x00000000},
1500 {0x0000007a, 0x21000409},
1501 {0x0000007c, 0x00000000},
1502 {0x0000007d, 0xe8000000},
1503 {0x0000007e, 0x044408a8},
1504 {0x0000007f, 0x00000003},
1505 {0x00000080, 0x00000000},
1506 {0x00000081, 0x01000000},
1507 {0x00000082, 0x02000000},
1508 {0x00000083, 0x00000000},
1509 {0x00000084, 0xe3f3e4f4},
1510 {0x00000085, 0x00052024},
1511 {0x00000087, 0x00000000},
1512 {0x00000088, 0x66036603},
1513 {0x00000089, 0x01000000},
1514 {0x0000008b, 0x1c0a0000},
1515 {0x0000008c, 0xff010000},
1516 {0x0000008e, 0xffffefff},
1517 {0x0000008f, 0xfff3efff},
1518 {0x00000090, 0xfff3efbf},
1519 {0x00000094, 0x00101101},
1520 {0x00000095, 0x00000fff},
1521 {0x00000096, 0x00116fff},
1522 {0x00000097, 0x60010000},
1523 {0x00000098, 0x10010000},
1524 {0x00000099, 0x00006000},
1525 {0x0000009a, 0x00001000},
1526 {0x0000009f, 0x00a07730}
1530 int si_mc_load_microcode(struct radeon_device *rdev)
1532 const __be32 *fw_data = NULL;
1533 const __le32 *new_fw_data = NULL;
1534 u32 running, blackout = 0;
1535 u32 *io_mc_regs = NULL;
1536 const __le32 *new_io_mc_regs = NULL;
1537 int i, regs_size, ucode_size;
1543 const struct mc_firmware_header_v1_0 *hdr =
1544 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1546 radeon_ucode_print_mc_hdr(&hdr->header);
1547 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1548 new_io_mc_regs = (const __le32 *)
1549 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1550 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1551 new_fw_data = (const __le32 *)
1552 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1554 ucode_size = rdev->mc_fw->datasize / 4;
1556 switch (rdev->family) {
1558 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1559 regs_size = TAHITI_IO_MC_REGS_SIZE;
1562 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1563 regs_size = TAHITI_IO_MC_REGS_SIZE;
1567 io_mc_regs = (u32 *)&verde_io_mc_regs;
1568 regs_size = TAHITI_IO_MC_REGS_SIZE;
1571 io_mc_regs = (u32 *)&oland_io_mc_regs;
1572 regs_size = TAHITI_IO_MC_REGS_SIZE;
1575 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1576 regs_size = TAHITI_IO_MC_REGS_SIZE;
1579 fw_data = (const __be32 *)rdev->mc_fw->data;
1582 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1586 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1587 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1590 /* reset the engine and set to writable */
1591 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1592 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1594 /* load mc io regs */
1595 for (i = 0; i < regs_size; i++) {
1597 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1598 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1600 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1601 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1604 /* load the MC ucode */
1605 for (i = 0; i < ucode_size; i++) {
1607 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1609 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1612 /* put the engine back into the active state */
1613 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1614 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1615 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1617 /* wait for training to complete */
1618 for (i = 0; i < rdev->usec_timeout; i++) {
1619 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1623 for (i = 0; i < rdev->usec_timeout; i++) {
1624 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1630 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
1636 static int si_init_microcode(struct radeon_device *rdev)
1638 const char *chip_name;
1639 const char *new_chip_name;
1640 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1641 size_t smc_req_size, mc2_req_size;
1648 switch (rdev->family) {
1650 chip_name = "TAHITI";
1651 new_chip_name = "tahiti";
1652 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1653 me_req_size = SI_PM4_UCODE_SIZE * 4;
1654 ce_req_size = SI_CE_UCODE_SIZE * 4;
1655 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1656 mc_req_size = SI_MC_UCODE_SIZE * 4;
1657 mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
1658 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1661 chip_name = "PITCAIRN";
1662 new_chip_name = "pitcairn";
1663 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1664 me_req_size = SI_PM4_UCODE_SIZE * 4;
1665 ce_req_size = SI_CE_UCODE_SIZE * 4;
1666 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1667 mc_req_size = SI_MC_UCODE_SIZE * 4;
1668 mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
1669 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1672 chip_name = "VERDE";
1673 new_chip_name = "verde";
1674 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1675 me_req_size = SI_PM4_UCODE_SIZE * 4;
1676 ce_req_size = SI_CE_UCODE_SIZE * 4;
1677 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1678 mc_req_size = SI_MC_UCODE_SIZE * 4;
1679 mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
1680 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1683 chip_name = "OLAND";
1684 new_chip_name = "oland";
1685 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1686 me_req_size = SI_PM4_UCODE_SIZE * 4;
1687 ce_req_size = SI_CE_UCODE_SIZE * 4;
1688 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1689 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1690 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1693 chip_name = "HAINAN";
1694 new_chip_name = "hainan";
1695 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1696 me_req_size = SI_PM4_UCODE_SIZE * 4;
1697 ce_req_size = SI_CE_UCODE_SIZE * 4;
1698 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1699 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1700 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1705 DRM_INFO("Loading %s Microcode\n", new_chip_name);
1707 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", new_chip_name);
1708 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1710 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
1711 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1714 if (rdev->pfp_fw->datasize != pfp_req_size) {
1716 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1717 rdev->pfp_fw->datasize, fw_name);
1722 err = radeon_ucode_validate(rdev->pfp_fw);
1725 "si_cp: validation failed for firmware \"%s\"\n",
1733 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", new_chip_name);
1734 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1736 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
1737 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1740 if (rdev->me_fw->datasize != me_req_size) {
1742 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1743 rdev->me_fw->datasize, fw_name);
1747 err = radeon_ucode_validate(rdev->me_fw);
1750 "si_cp: validation failed for firmware \"%s\"\n",
1758 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_ce", new_chip_name);
1759 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1761 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_ce", chip_name);
1762 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1765 if (rdev->ce_fw->datasize != ce_req_size) {
1767 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1768 rdev->ce_fw->datasize, fw_name);
1772 err = radeon_ucode_validate(rdev->ce_fw);
1775 "si_cp: validation failed for firmware \"%s\"\n",
1783 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", new_chip_name);
1784 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1786 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_rlc", chip_name);
1787 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1790 if (rdev->rlc_fw->datasize != rlc_req_size) {
1792 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
1793 rdev->rlc_fw->datasize, fw_name);
1797 err = radeon_ucode_validate(rdev->rlc_fw);
1800 "si_cp: validation failed for firmware \"%s\"\n",
1808 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", new_chip_name);
1809 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1811 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc2", chip_name);
1812 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1814 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_mc", chip_name);
1815 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1819 if ((rdev->mc_fw->datasize != mc_req_size) &&
1820 (rdev->mc_fw->datasize != mc2_req_size)) {
1822 "si_mc: Bogus length %zu in firmware \"%s\"\n",
1823 rdev->mc_fw->datasize, fw_name);
1826 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->datasize);
1828 err = radeon_ucode_validate(rdev->mc_fw);
1831 "si_cp: validation failed for firmware \"%s\"\n",
1839 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", new_chip_name);
1840 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1842 ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_smc", chip_name);
1843 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1846 "smc: error loading firmware \"%s\"\n",
1848 release_firmware(rdev->smc_fw);
1849 rdev->smc_fw = NULL;
1851 } else if (rdev->smc_fw->datasize != smc_req_size) {
1853 "si_smc: Bogus length %zu in firmware \"%s\"\n",
1854 rdev->smc_fw->datasize, fw_name);
1858 err = radeon_ucode_validate(rdev->smc_fw);
1861 "si_cp: validation failed for firmware \"%s\"\n",
1870 rdev->new_fw = false;
1871 } else if (new_fw < 6) {
1872 printk(KERN_ERR "si_fw: mixing new and old firmware!\n");
1875 rdev->new_fw = true;
1881 "si_cp: Failed to load firmware \"%s\"\n",
1883 release_firmware(rdev->pfp_fw);
1884 rdev->pfp_fw = NULL;
1885 release_firmware(rdev->me_fw);
1887 release_firmware(rdev->ce_fw);
1889 release_firmware(rdev->rlc_fw);
1890 rdev->rlc_fw = NULL;
1891 release_firmware(rdev->mc_fw);
1893 release_firmware(rdev->smc_fw);
1894 rdev->smc_fw = NULL;
1900 * si_fini_microcode - drop the firmwares image references
1902 * @rdev: radeon_device pointer
1904 * Drop the pfp, me, rlc, mc and ce firmware image references.
1905 * Called at driver shutdown.
1907 static void si_fini_microcode(struct radeon_device *rdev)
1909 release_firmware(rdev->pfp_fw);
1910 rdev->pfp_fw = NULL;
1911 release_firmware(rdev->me_fw);
1913 release_firmware(rdev->rlc_fw);
1914 rdev->rlc_fw = NULL;
1915 release_firmware(rdev->mc_fw);
1917 release_firmware(rdev->smc_fw);
1918 rdev->smc_fw = NULL;
1919 release_firmware(rdev->ce_fw);
1923 /* watermark setup */
1924 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
1925 struct radeon_crtc *radeon_crtc,
1926 struct drm_display_mode *mode,
1927 struct drm_display_mode *other_mode)
1929 u32 tmp, buffer_alloc, i;
1930 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
1933 * There are 3 line buffers, each one shared by 2 display controllers.
1934 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1935 * the display controllers. The paritioning is done via one of four
1936 * preset allocations specified in bits 21:20:
1938 * 2 - whole lb, other crtc must be disabled
1940 /* this can get tricky if we have two large displays on a paired group
1941 * of crtcs. Ideally for multiple large displays we'd assign them to
1942 * non-linked crtcs for maximum line buffer allocation.
1944 if (radeon_crtc->base.enabled && mode) {
1949 tmp = 2; /* whole */
1957 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
1958 DC_LB_MEMORY_CONFIG(tmp));
1960 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1961 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
1962 for (i = 0; i < rdev->usec_timeout; i++) {
1963 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1964 DMIF_BUFFERS_ALLOCATED_COMPLETED)
1969 if (radeon_crtc->base.enabled && mode) {
1979 /* controller not enabled, so no lb used */
1983 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
1985 u32 tmp = RREG32(MC_SHARED_CHMAP);
1987 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2010 struct dce6_wm_params {
2011 u32 dram_channels; /* number of dram channels */
2012 u32 yclk; /* bandwidth per dram data pin in kHz */
2013 u32 sclk; /* engine clock in kHz */
2014 u32 disp_clk; /* display clock in kHz */
2015 u32 src_width; /* viewport width */
2016 u32 active_time; /* active display time in ns */
2017 u32 blank_time; /* blank time in ns */
2018 bool interlaced; /* mode is interlaced */
2019 fixed20_12 vsc; /* vertical scale ratio */
2020 u32 num_heads; /* number of active crtcs */
2021 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
2022 u32 lb_size; /* line buffer allocated to pipe */
2023 u32 vtaps; /* vertical scaler taps */
2026 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
2028 /* Calculate raw DRAM Bandwidth */
2029 fixed20_12 dram_efficiency; /* 0.7 */
2030 fixed20_12 yclk, dram_channels, bandwidth;
2033 a.full = dfixed_const(1000);
2034 yclk.full = dfixed_const(wm->yclk);
2035 yclk.full = dfixed_div(yclk, a);
2036 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2037 a.full = dfixed_const(10);
2038 dram_efficiency.full = dfixed_const(7);
2039 dram_efficiency.full = dfixed_div(dram_efficiency, a);
2040 bandwidth.full = dfixed_mul(dram_channels, yclk);
2041 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
2043 return dfixed_trunc(bandwidth);
2046 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2048 /* Calculate DRAM Bandwidth and the part allocated to display. */
2049 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
2050 fixed20_12 yclk, dram_channels, bandwidth;
2053 a.full = dfixed_const(1000);
2054 yclk.full = dfixed_const(wm->yclk);
2055 yclk.full = dfixed_div(yclk, a);
2056 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2057 a.full = dfixed_const(10);
2058 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
2059 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
2060 bandwidth.full = dfixed_mul(dram_channels, yclk);
2061 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
2063 return dfixed_trunc(bandwidth);
2066 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
2068 /* Calculate the display Data return Bandwidth */
2069 fixed20_12 return_efficiency; /* 0.8 */
2070 fixed20_12 sclk, bandwidth;
2073 a.full = dfixed_const(1000);
2074 sclk.full = dfixed_const(wm->sclk);
2075 sclk.full = dfixed_div(sclk, a);
2076 a.full = dfixed_const(10);
2077 return_efficiency.full = dfixed_const(8);
2078 return_efficiency.full = dfixed_div(return_efficiency, a);
2079 a.full = dfixed_const(32);
2080 bandwidth.full = dfixed_mul(a, sclk);
2081 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
2083 return dfixed_trunc(bandwidth);
2086 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
2091 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
2093 /* Calculate the DMIF Request Bandwidth */
2094 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
2095 fixed20_12 disp_clk, sclk, bandwidth;
2096 fixed20_12 a, b1, b2;
2099 a.full = dfixed_const(1000);
2100 disp_clk.full = dfixed_const(wm->disp_clk);
2101 disp_clk.full = dfixed_div(disp_clk, a);
2102 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
2103 b1.full = dfixed_mul(a, disp_clk);
2105 a.full = dfixed_const(1000);
2106 sclk.full = dfixed_const(wm->sclk);
2107 sclk.full = dfixed_div(sclk, a);
2108 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
2109 b2.full = dfixed_mul(a, sclk);
2111 a.full = dfixed_const(10);
2112 disp_clk_request_efficiency.full = dfixed_const(8);
2113 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
2115 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
2117 a.full = dfixed_const(min_bandwidth);
2118 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
2120 return dfixed_trunc(bandwidth);
2123 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
2125 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
2126 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
2127 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
2128 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
2130 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
2133 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
2135 /* Calculate the display mode Average Bandwidth
2136 * DisplayMode should contain the source and destination dimensions,
2140 fixed20_12 line_time;
2141 fixed20_12 src_width;
2142 fixed20_12 bandwidth;
2145 a.full = dfixed_const(1000);
2146 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
2147 line_time.full = dfixed_div(line_time, a);
2148 bpp.full = dfixed_const(wm->bytes_per_pixel);
2149 src_width.full = dfixed_const(wm->src_width);
2150 bandwidth.full = dfixed_mul(src_width, bpp);
2151 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
2152 bandwidth.full = dfixed_div(bandwidth, line_time);
2154 return dfixed_trunc(bandwidth);
2157 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
2159 /* First calcualte the latency in ns */
2160 u32 mc_latency = 2000; /* 2000 ns. */
2161 u32 available_bandwidth = dce6_available_bandwidth(wm);
2162 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
2163 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
2164 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2165 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2166 (wm->num_heads * cursor_line_pair_return_time);
2167 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
2168 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
2169 u32 tmp, dmif_size = 12288;
2172 if (wm->num_heads == 0)
2175 a.full = dfixed_const(2);
2176 b.full = dfixed_const(1);
2177 if ((wm->vsc.full > a.full) ||
2178 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2180 ((wm->vsc.full >= a.full) && wm->interlaced))
2181 max_src_lines_per_dst_line = 4;
2183 max_src_lines_per_dst_line = 2;
2185 a.full = dfixed_const(available_bandwidth);
2186 b.full = dfixed_const(wm->num_heads);
2187 a.full = dfixed_div(a, b);
2189 b.full = dfixed_const(mc_latency + 512);
2190 c.full = dfixed_const(wm->disp_clk);
2191 b.full = dfixed_div(b, c);
2193 c.full = dfixed_const(dmif_size);
2194 b.full = dfixed_div(c, b);
2196 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
2198 b.full = dfixed_const(1000);
2199 c.full = dfixed_const(wm->disp_clk);
2200 b.full = dfixed_div(c, b);
2201 c.full = dfixed_const(wm->bytes_per_pixel);
2202 b.full = dfixed_mul(b, c);
2204 lb_fill_bw = min(tmp, dfixed_trunc(b));
2206 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
2207 b.full = dfixed_const(1000);
2208 c.full = dfixed_const(lb_fill_bw);
2209 b.full = dfixed_div(c, b);
2210 a.full = dfixed_div(a, b);
2211 line_fill_time = dfixed_trunc(a);
2213 if (line_fill_time < wm->active_time)
2216 return latency + (line_fill_time - wm->active_time);
2220 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2222 if (dce6_average_bandwidth(wm) <=
2223 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2229 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
2231 if (dce6_average_bandwidth(wm) <=
2232 (dce6_available_bandwidth(wm) / wm->num_heads))
2238 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
2240 u32 lb_partitions = wm->lb_size / wm->src_width;
2241 u32 line_time = wm->active_time + wm->blank_time;
2242 u32 latency_tolerant_lines;
2246 a.full = dfixed_const(1);
2247 if (wm->vsc.full > a.full)
2248 latency_tolerant_lines = 1;
2250 if (lb_partitions <= (wm->vtaps + 1))
2251 latency_tolerant_lines = 1;
2253 latency_tolerant_lines = 2;
2256 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
2258 if (dce6_latency_watermark(wm) <= latency_hiding)
2264 static void dce6_program_watermarks(struct radeon_device *rdev,
2265 struct radeon_crtc *radeon_crtc,
2266 u32 lb_size, u32 num_heads)
2268 struct drm_display_mode *mode = &radeon_crtc->base.mode;
2269 struct dce6_wm_params wm_low, wm_high;
2273 u32 latency_watermark_a = 0, latency_watermark_b = 0;
2274 u32 priority_a_mark = 0, priority_b_mark = 0;
2275 u32 priority_a_cnt = PRIORITY_OFF;
2276 u32 priority_b_cnt = PRIORITY_OFF;
2277 u32 tmp, arb_control3;
2280 if (radeon_crtc->base.enabled && num_heads && mode) {
2281 pixel_period = 1000000 / (u32)mode->clock;
2282 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
2286 if (rdev->family == CHIP_ARUBA)
2287 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2289 dram_channels = si_get_number_of_dram_channels(rdev);
2291 /* watermark for high clocks */
2292 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2294 radeon_dpm_get_mclk(rdev, false) * 10;
2296 radeon_dpm_get_sclk(rdev, false) * 10;
2298 wm_high.yclk = rdev->pm.current_mclk * 10;
2299 wm_high.sclk = rdev->pm.current_sclk * 10;
2302 wm_high.disp_clk = mode->clock;
2303 wm_high.src_width = mode->crtc_hdisplay;
2304 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
2305 wm_high.blank_time = line_time - wm_high.active_time;
2306 wm_high.interlaced = false;
2307 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2308 wm_high.interlaced = true;
2309 wm_high.vsc = radeon_crtc->vsc;
2311 if (radeon_crtc->rmx_type != RMX_OFF)
2313 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
2314 wm_high.lb_size = lb_size;
2315 wm_high.dram_channels = dram_channels;
2316 wm_high.num_heads = num_heads;
2318 /* watermark for low clocks */
2319 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2321 radeon_dpm_get_mclk(rdev, true) * 10;
2323 radeon_dpm_get_sclk(rdev, true) * 10;
2325 wm_low.yclk = rdev->pm.current_mclk * 10;
2326 wm_low.sclk = rdev->pm.current_sclk * 10;
2329 wm_low.disp_clk = mode->clock;
2330 wm_low.src_width = mode->crtc_hdisplay;
2331 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
2332 wm_low.blank_time = line_time - wm_low.active_time;
2333 wm_low.interlaced = false;
2334 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2335 wm_low.interlaced = true;
2336 wm_low.vsc = radeon_crtc->vsc;
2338 if (radeon_crtc->rmx_type != RMX_OFF)
2340 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
2341 wm_low.lb_size = lb_size;
2342 wm_low.dram_channels = dram_channels;
2343 wm_low.num_heads = num_heads;
2345 /* set for high clocks */
2346 latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);
2347 /* set for low clocks */
2348 latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);
2350 /* possibly force display priority to high */
2351 /* should really do this at mode validation time... */
2352 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
2353 !dce6_average_bandwidth_vs_available_bandwidth(&wm_high) ||
2354 !dce6_check_latency_hiding(&wm_high) ||
2355 (rdev->disp_priority == 2)) {
2356 DRM_DEBUG_KMS("force priority to high\n");
2357 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2358 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2360 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
2361 !dce6_average_bandwidth_vs_available_bandwidth(&wm_low) ||
2362 !dce6_check_latency_hiding(&wm_low) ||
2363 (rdev->disp_priority == 2)) {
2364 DRM_DEBUG_KMS("force priority to high\n");
2365 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2366 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2369 a.full = dfixed_const(1000);
2370 b.full = dfixed_const(mode->clock);
2371 b.full = dfixed_div(b, a);
2372 c.full = dfixed_const(latency_watermark_a);
2373 c.full = dfixed_mul(c, b);
2374 c.full = dfixed_mul(c, radeon_crtc->hsc);
2375 c.full = dfixed_div(c, a);
2376 a.full = dfixed_const(16);
2377 c.full = dfixed_div(c, a);
2378 priority_a_mark = dfixed_trunc(c);
2379 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
2381 a.full = dfixed_const(1000);
2382 b.full = dfixed_const(mode->clock);
2383 b.full = dfixed_div(b, a);
2384 c.full = dfixed_const(latency_watermark_b);
2385 c.full = dfixed_mul(c, b);
2386 c.full = dfixed_mul(c, radeon_crtc->hsc);
2387 c.full = dfixed_div(c, a);
2388 a.full = dfixed_const(16);
2389 c.full = dfixed_div(c, a);
2390 priority_b_mark = dfixed_trunc(c);
2391 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
2393 /* Save number of lines the linebuffer leads before the scanout */
2394 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
2398 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2400 tmp &= ~LATENCY_WATERMARK_MASK(3);
2401 tmp |= LATENCY_WATERMARK_MASK(1);
2402 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2403 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2404 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
2405 LATENCY_HIGH_WATERMARK(line_time)));
2407 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2408 tmp &= ~LATENCY_WATERMARK_MASK(3);
2409 tmp |= LATENCY_WATERMARK_MASK(2);
2410 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2411 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2412 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
2413 LATENCY_HIGH_WATERMARK(line_time)));
2414 /* restore original selection */
2415 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
2417 /* write the priority marks */
2418 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2419 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2421 /* save values for DPM */
2422 radeon_crtc->line_time = line_time;
2423 radeon_crtc->wm_high = latency_watermark_a;
2424 radeon_crtc->wm_low = latency_watermark_b;
2427 void dce6_bandwidth_update(struct radeon_device *rdev)
2429 struct drm_display_mode *mode0 = NULL;
2430 struct drm_display_mode *mode1 = NULL;
2431 u32 num_heads = 0, lb_size;
2434 if (!rdev->mode_info.mode_config_initialized)
2437 radeon_update_display_priority(rdev);
2439 for (i = 0; i < rdev->num_crtc; i++) {
2440 if (rdev->mode_info.crtcs[i]->base.enabled)
2443 for (i = 0; i < rdev->num_crtc; i += 2) {
2444 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2445 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2446 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2447 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2448 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2449 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2456 static void si_tiling_mode_table_init(struct radeon_device *rdev)
2458 u32 *tile = rdev->config.si.tile_mode_array;
2459 const u32 num_tile_mode_states =
2460 ARRAY_SIZE(rdev->config.si.tile_mode_array);
2461 u32 reg_offset, split_equal_to_row_size;
2463 switch (rdev->config.si.mem_row_size_in_kb) {
2465 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2469 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2472 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2476 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2477 tile[reg_offset] = 0;
2479 switch(rdev->family) {
2482 /* non-AA compressed depth or any compressed stencil */
2483 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2484 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2485 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2486 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2487 NUM_BANKS(ADDR_SURF_16_BANK) |
2488 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2489 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2490 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2491 /* 2xAA/4xAA compressed depth only */
2492 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2493 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2494 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2495 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2496 NUM_BANKS(ADDR_SURF_16_BANK) |
2497 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2500 /* 8xAA compressed depth only */
2501 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2502 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2503 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2504 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2505 NUM_BANKS(ADDR_SURF_16_BANK) |
2506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2509 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2510 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2511 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2514 NUM_BANKS(ADDR_SURF_16_BANK) |
2515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2518 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2519 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2520 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2521 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2522 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2523 NUM_BANKS(ADDR_SURF_16_BANK) |
2524 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2525 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2526 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2527 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2528 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2529 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2530 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2531 TILE_SPLIT(split_equal_to_row_size) |
2532 NUM_BANKS(ADDR_SURF_16_BANK) |
2533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2536 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2537 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2538 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2539 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2540 TILE_SPLIT(split_equal_to_row_size) |
2541 NUM_BANKS(ADDR_SURF_16_BANK) |
2542 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2543 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2544 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2545 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2546 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2547 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2548 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2549 TILE_SPLIT(split_equal_to_row_size) |
2550 NUM_BANKS(ADDR_SURF_16_BANK) |
2551 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2553 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2554 /* 1D and 1D Array Surfaces */
2555 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2556 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2557 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2558 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2559 NUM_BANKS(ADDR_SURF_16_BANK) |
2560 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2563 /* Displayable maps. */
2564 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2565 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2567 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2568 NUM_BANKS(ADDR_SURF_16_BANK) |
2569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2573 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2574 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2575 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2577 NUM_BANKS(ADDR_SURF_16_BANK) |
2578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2581 /* Display 16bpp. */
2582 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2583 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2584 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2586 NUM_BANKS(ADDR_SURF_16_BANK) |
2587 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2588 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2589 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2590 /* Display 32bpp. */
2591 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2592 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2593 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2594 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2595 NUM_BANKS(ADDR_SURF_16_BANK) |
2596 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2597 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2598 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2600 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2601 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2602 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2603 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2604 NUM_BANKS(ADDR_SURF_16_BANK) |
2605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2609 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2610 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2611 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2612 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2613 NUM_BANKS(ADDR_SURF_16_BANK) |
2614 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2615 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2616 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2618 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2619 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2620 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2621 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2622 NUM_BANKS(ADDR_SURF_16_BANK) |
2623 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2627 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2628 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2629 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2630 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2631 NUM_BANKS(ADDR_SURF_16_BANK) |
2632 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2633 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2634 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2636 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2637 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2638 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2639 TILE_SPLIT(split_equal_to_row_size) |
2640 NUM_BANKS(ADDR_SURF_16_BANK) |
2641 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2642 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2643 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2645 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2646 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2647 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2648 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2649 NUM_BANKS(ADDR_SURF_16_BANK) |
2650 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2654 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2655 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2656 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2657 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2658 NUM_BANKS(ADDR_SURF_16_BANK) |
2659 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2660 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2661 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2663 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2664 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2665 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2666 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2667 NUM_BANKS(ADDR_SURF_16_BANK) |
2668 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2669 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2670 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2672 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2673 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2674 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2675 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2676 NUM_BANKS(ADDR_SURF_16_BANK) |
2677 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2678 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2679 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2681 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2682 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2683 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2684 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2685 NUM_BANKS(ADDR_SURF_8_BANK) |
2686 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2690 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2691 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2697 /* non-AA compressed depth or any compressed stencil */
2698 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2699 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2700 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2701 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2702 NUM_BANKS(ADDR_SURF_16_BANK) |
2703 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2704 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2705 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2706 /* 2xAA/4xAA compressed depth only */
2707 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2708 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2709 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2710 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2711 NUM_BANKS(ADDR_SURF_16_BANK) |
2712 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2713 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2714 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2715 /* 8xAA compressed depth only */
2716 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2717 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2718 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2719 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2720 NUM_BANKS(ADDR_SURF_16_BANK) |
2721 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2722 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2723 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2724 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2725 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2726 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2727 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2728 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2729 NUM_BANKS(ADDR_SURF_16_BANK) |
2730 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2731 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2732 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2733 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2734 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2735 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2736 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2737 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2738 NUM_BANKS(ADDR_SURF_16_BANK) |
2739 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2740 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2741 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2742 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2743 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2744 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2745 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2746 TILE_SPLIT(split_equal_to_row_size) |
2747 NUM_BANKS(ADDR_SURF_16_BANK) |
2748 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2749 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2750 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2751 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2752 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2753 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2754 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2755 TILE_SPLIT(split_equal_to_row_size) |
2756 NUM_BANKS(ADDR_SURF_16_BANK) |
2757 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2758 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2759 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2760 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2761 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2762 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2763 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2764 TILE_SPLIT(split_equal_to_row_size) |
2765 NUM_BANKS(ADDR_SURF_16_BANK) |
2766 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2769 /* 1D and 1D Array Surfaces */
2770 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2771 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2772 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2773 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2774 NUM_BANKS(ADDR_SURF_16_BANK) |
2775 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2776 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2777 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2778 /* Displayable maps. */
2779 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2780 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2781 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2782 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2783 NUM_BANKS(ADDR_SURF_16_BANK) |
2784 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2785 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2786 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2788 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2789 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2790 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2791 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2792 NUM_BANKS(ADDR_SURF_16_BANK) |
2793 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2795 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2796 /* Display 16bpp. */
2797 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2798 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2799 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2800 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2801 NUM_BANKS(ADDR_SURF_16_BANK) |
2802 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2803 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2804 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2805 /* Display 32bpp. */
2806 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2807 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2808 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2809 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2810 NUM_BANKS(ADDR_SURF_16_BANK) |
2811 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2812 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2813 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2815 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2816 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2817 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2818 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2819 NUM_BANKS(ADDR_SURF_16_BANK) |
2820 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2821 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2822 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2824 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2825 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2826 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2827 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2828 NUM_BANKS(ADDR_SURF_16_BANK) |
2829 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2830 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2831 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2833 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2834 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2835 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2836 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2837 NUM_BANKS(ADDR_SURF_16_BANK) |
2838 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2839 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2840 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2842 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2843 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2844 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2845 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2846 NUM_BANKS(ADDR_SURF_16_BANK) |
2847 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2851 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2852 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2853 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2854 TILE_SPLIT(split_equal_to_row_size) |
2855 NUM_BANKS(ADDR_SURF_16_BANK) |
2856 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2857 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2858 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2860 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2861 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2862 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2863 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2864 NUM_BANKS(ADDR_SURF_16_BANK) |
2865 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2869 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2870 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2871 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2872 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2873 NUM_BANKS(ADDR_SURF_16_BANK) |
2874 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2878 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2879 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2880 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2881 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2882 NUM_BANKS(ADDR_SURF_16_BANK) |
2883 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2884 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2885 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2887 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2888 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2889 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2890 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2891 NUM_BANKS(ADDR_SURF_16_BANK) |
2892 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2893 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2894 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2896 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2897 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2898 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2899 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2900 NUM_BANKS(ADDR_SURF_8_BANK) |
2901 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2902 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2903 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2905 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2906 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2910 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
2914 static void si_select_se_sh(struct radeon_device *rdev,
2915 u32 se_num, u32 sh_num)
2917 u32 data = INSTANCE_BROADCAST_WRITES;
2919 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
2920 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2921 else if (se_num == 0xffffffff)
2922 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
2923 else if (sh_num == 0xffffffff)
2924 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
2926 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
2927 WREG32(GRBM_GFX_INDEX, data);
2930 static u32 si_create_bitmask(u32 bit_width)
2934 for (i = 0; i < bit_width; i++) {
2941 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
2945 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2947 data &= INACTIVE_CUS_MASK;
2950 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2952 data >>= INACTIVE_CUS_SHIFT;
2954 mask = si_create_bitmask(cu_per_sh);
2956 return ~data & mask;
2959 static void si_setup_spi(struct radeon_device *rdev,
2960 u32 se_num, u32 sh_per_se,
2964 u32 data, mask, active_cu;
2966 for (i = 0; i < se_num; i++) {
2967 for (j = 0; j < sh_per_se; j++) {
2968 si_select_se_sh(rdev, i, j);
2969 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
2970 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
2973 for (k = 0; k < 16; k++) {
2975 if (active_cu & mask) {
2977 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
2983 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2986 static u32 si_get_rb_disabled(struct radeon_device *rdev,
2987 u32 max_rb_num_per_se,
2992 data = RREG32(CC_RB_BACKEND_DISABLE);
2994 data &= BACKEND_DISABLE_MASK;
2997 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
2999 data >>= BACKEND_DISABLE_SHIFT;
3001 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
3006 static void si_setup_rb(struct radeon_device *rdev,
3007 u32 se_num, u32 sh_per_se,
3008 u32 max_rb_num_per_se)
3012 u32 disabled_rbs = 0;
3013 u32 enabled_rbs = 0;
3015 for (i = 0; i < se_num; i++) {
3016 for (j = 0; j < sh_per_se; j++) {
3017 si_select_se_sh(rdev, i, j);
3018 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3019 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
3022 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3025 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3026 if (!(disabled_rbs & mask))
3027 enabled_rbs |= mask;
3031 rdev->config.si.backend_enable_mask = enabled_rbs;
3033 for (i = 0; i < se_num; i++) {
3034 si_select_se_sh(rdev, i, 0xffffffff);
3036 for (j = 0; j < sh_per_se; j++) {
3037 switch (enabled_rbs & 3) {
3039 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3042 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3046 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3051 WREG32(PA_SC_RASTER_CONFIG, data);
3053 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3056 static void si_gpu_init(struct radeon_device *rdev)
3058 u32 gb_addr_config = 0;
3059 u32 mc_shared_chmap, mc_arb_ramcfg;
3061 u32 hdp_host_path_cntl;
3065 switch (rdev->family) {
3067 rdev->config.si.max_shader_engines = 2;
3068 rdev->config.si.max_tile_pipes = 12;
3069 rdev->config.si.max_cu_per_sh = 8;
3070 rdev->config.si.max_sh_per_se = 2;
3071 rdev->config.si.max_backends_per_se = 4;
3072 rdev->config.si.max_texture_channel_caches = 12;
3073 rdev->config.si.max_gprs = 256;
3074 rdev->config.si.max_gs_threads = 32;
3075 rdev->config.si.max_hw_contexts = 8;
3077 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3078 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3079 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3080 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3081 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3084 rdev->config.si.max_shader_engines = 2;
3085 rdev->config.si.max_tile_pipes = 8;
3086 rdev->config.si.max_cu_per_sh = 5;
3087 rdev->config.si.max_sh_per_se = 2;
3088 rdev->config.si.max_backends_per_se = 4;
3089 rdev->config.si.max_texture_channel_caches = 8;
3090 rdev->config.si.max_gprs = 256;
3091 rdev->config.si.max_gs_threads = 32;
3092 rdev->config.si.max_hw_contexts = 8;
3094 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3095 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3096 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3097 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3098 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3102 rdev->config.si.max_shader_engines = 1;
3103 rdev->config.si.max_tile_pipes = 4;
3104 rdev->config.si.max_cu_per_sh = 5;
3105 rdev->config.si.max_sh_per_se = 2;
3106 rdev->config.si.max_backends_per_se = 4;
3107 rdev->config.si.max_texture_channel_caches = 4;
3108 rdev->config.si.max_gprs = 256;
3109 rdev->config.si.max_gs_threads = 32;
3110 rdev->config.si.max_hw_contexts = 8;
3112 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3113 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3114 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3115 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3116 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3119 rdev->config.si.max_shader_engines = 1;
3120 rdev->config.si.max_tile_pipes = 4;
3121 rdev->config.si.max_cu_per_sh = 6;
3122 rdev->config.si.max_sh_per_se = 1;
3123 rdev->config.si.max_backends_per_se = 2;
3124 rdev->config.si.max_texture_channel_caches = 4;
3125 rdev->config.si.max_gprs = 256;
3126 rdev->config.si.max_gs_threads = 16;
3127 rdev->config.si.max_hw_contexts = 8;
3129 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3130 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3131 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3132 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3133 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3136 rdev->config.si.max_shader_engines = 1;
3137 rdev->config.si.max_tile_pipes = 4;
3138 rdev->config.si.max_cu_per_sh = 5;
3139 rdev->config.si.max_sh_per_se = 1;
3140 rdev->config.si.max_backends_per_se = 1;
3141 rdev->config.si.max_texture_channel_caches = 2;
3142 rdev->config.si.max_gprs = 256;
3143 rdev->config.si.max_gs_threads = 16;
3144 rdev->config.si.max_hw_contexts = 8;
3146 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3147 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3148 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3149 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3150 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
3154 /* Initialize HDP */
3155 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3156 WREG32((0x2c14 + j), 0x00000000);
3157 WREG32((0x2c18 + j), 0x00000000);
3158 WREG32((0x2c1c + j), 0x00000000);
3159 WREG32((0x2c20 + j), 0x00000000);
3160 WREG32((0x2c24 + j), 0x00000000);
3163 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3164 WREG32(SRBM_INT_CNTL, 1);
3165 WREG32(SRBM_INT_ACK, 1);
3167 evergreen_fix_pci_max_read_req_size(rdev);
3169 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3171 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3172 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3174 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
3175 rdev->config.si.mem_max_burst_length_bytes = 256;
3176 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3177 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3178 if (rdev->config.si.mem_row_size_in_kb > 4)
3179 rdev->config.si.mem_row_size_in_kb = 4;
3180 /* XXX use MC settings? */
3181 rdev->config.si.shader_engine_tile_size = 32;
3182 rdev->config.si.num_gpus = 1;
3183 rdev->config.si.multi_gpu_tile_size = 64;
3185 /* fix up row size */
3186 gb_addr_config &= ~ROW_SIZE_MASK;
3187 switch (rdev->config.si.mem_row_size_in_kb) {
3190 gb_addr_config |= ROW_SIZE(0);
3193 gb_addr_config |= ROW_SIZE(1);
3196 gb_addr_config |= ROW_SIZE(2);
3200 /* setup tiling info dword. gb_addr_config is not adequate since it does
3201 * not have bank info, so create a custom tiling dword.
3202 * bits 3:0 num_pipes
3203 * bits 7:4 num_banks
3204 * bits 11:8 group_size
3205 * bits 15:12 row_size
3207 rdev->config.si.tile_config = 0;
3208 switch (rdev->config.si.num_tile_pipes) {
3210 rdev->config.si.tile_config |= (0 << 0);
3213 rdev->config.si.tile_config |= (1 << 0);
3216 rdev->config.si.tile_config |= (2 << 0);
3220 /* XXX what about 12? */
3221 rdev->config.si.tile_config |= (3 << 0);
3224 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3225 case 0: /* four banks */
3226 rdev->config.si.tile_config |= 0 << 4;
3228 case 1: /* eight banks */
3229 rdev->config.si.tile_config |= 1 << 4;
3231 case 2: /* sixteen banks */
3233 rdev->config.si.tile_config |= 2 << 4;
3236 rdev->config.si.tile_config |=
3237 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3238 rdev->config.si.tile_config |=
3239 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3241 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3242 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3243 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3244 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3245 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3246 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
3247 if (rdev->has_uvd) {
3248 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3249 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3250 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3253 si_tiling_mode_table_init(rdev);
3255 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
3256 rdev->config.si.max_sh_per_se,
3257 rdev->config.si.max_backends_per_se);
3259 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
3260 rdev->config.si.max_sh_per_se,
3261 rdev->config.si.max_cu_per_sh);
3263 rdev->config.si.active_cus = 0;
3264 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
3265 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
3266 rdev->config.si.active_cus +=
3267 hweight32(si_get_cu_active_bitmap(rdev, i, j));
3271 /* set HW defaults for 3D engine */
3272 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3273 ROQ_IB2_START(0x2b)));
3274 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3276 sx_debug_1 = RREG32(SX_DEBUG_1);
3277 WREG32(SX_DEBUG_1, sx_debug_1);
3279 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3281 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
3282 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
3283 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
3284 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
3286 WREG32(VGT_NUM_INSTANCES, 1);
3288 WREG32(CP_PERFMON_CNTL, 0);
3290 WREG32(SQ_CONFIG, 0);
3292 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3293 FORCE_EOV_MAX_REZ_CNT(255)));
3295 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3296 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3298 WREG32(VGT_GS_VERTEX_REUSE, 16);
3299 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3301 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
3302 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
3303 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
3304 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
3305 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
3306 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
3307 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
3308 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
3310 tmp = RREG32(HDP_MISC_CNTL);
3311 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3312 WREG32(HDP_MISC_CNTL, tmp);
3314 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3315 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3317 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3323 * GPU scratch registers helpers function.
3325 static void si_scratch_init(struct radeon_device *rdev)
3329 rdev->scratch.num_reg = 7;
3330 rdev->scratch.reg_base = SCRATCH_REG0;
3331 for (i = 0; i < rdev->scratch.num_reg; i++) {
3332 rdev->scratch.free[i] = true;
3333 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3337 void si_fence_ring_emit(struct radeon_device *rdev,
3338 struct radeon_fence *fence)
3340 struct radeon_ring *ring = &rdev->ring[fence->ring];
3341 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3343 /* flush read cache over gart */
3344 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3345 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3346 radeon_ring_write(ring, 0);
3347 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3348 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3349 PACKET3_TC_ACTION_ENA |
3350 PACKET3_SH_KCACHE_ACTION_ENA |
3351 PACKET3_SH_ICACHE_ACTION_ENA);
3352 radeon_ring_write(ring, 0xFFFFFFFF);
3353 radeon_ring_write(ring, 0);
3354 radeon_ring_write(ring, 10); /* poll interval */
3355 /* EVENT_WRITE_EOP - flush caches, send int */
3356 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3357 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
3358 radeon_ring_write(ring, lower_32_bits(addr));
3359 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3360 radeon_ring_write(ring, fence->seq);
3361 radeon_ring_write(ring, 0);
3367 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3369 struct radeon_ring *ring = &rdev->ring[ib->ring];
3370 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3373 if (ib->is_const_ib) {
3374 /* set switch buffer packet before const IB */
3375 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3376 radeon_ring_write(ring, 0);
3378 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3381 if (ring->rptr_save_reg) {
3382 next_rptr = ring->wptr + 3 + 4 + 8;
3383 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3384 radeon_ring_write(ring, ((ring->rptr_save_reg -
3385 PACKET3_SET_CONFIG_REG_START) >> 2));
3386 radeon_ring_write(ring, next_rptr);
3387 } else if (rdev->wb.enabled) {
3388 next_rptr = ring->wptr + 5 + 4 + 8;
3389 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3390 radeon_ring_write(ring, (1 << 8));
3391 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3392 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3393 radeon_ring_write(ring, next_rptr);
3396 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3399 radeon_ring_write(ring, header);
3400 radeon_ring_write(ring,
3404 (ib->gpu_addr & 0xFFFFFFFC));
3405 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3406 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
3408 if (!ib->is_const_ib) {
3409 /* flush read cache over gart for this vmid */
3410 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3411 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3412 radeon_ring_write(ring, vm_id);
3413 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3414 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3415 PACKET3_TC_ACTION_ENA |
3416 PACKET3_SH_KCACHE_ACTION_ENA |
3417 PACKET3_SH_ICACHE_ACTION_ENA);
3418 radeon_ring_write(ring, 0xFFFFFFFF);
3419 radeon_ring_write(ring, 0);
3420 radeon_ring_write(ring, 10); /* poll interval */
3427 static void si_cp_enable(struct radeon_device *rdev, bool enable)
3430 WREG32(CP_ME_CNTL, 0);
3432 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3433 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3434 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3435 WREG32(SCRATCH_UMSK, 0);
3436 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3437 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3438 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3443 static int si_cp_load_microcode(struct radeon_device *rdev)
3447 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3450 si_cp_enable(rdev, false);
3453 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3454 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3455 const struct gfx_firmware_header_v1_0 *ce_hdr =
3456 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3457 const struct gfx_firmware_header_v1_0 *me_hdr =
3458 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3459 const __le32 *fw_data;
3462 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3463 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3464 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3467 fw_data = (const __le32 *)
3468 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3469 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3470 WREG32(CP_PFP_UCODE_ADDR, 0);
3471 for (i = 0; i < fw_size; i++)
3472 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3473 WREG32(CP_PFP_UCODE_ADDR, 0);
3476 fw_data = (const __le32 *)
3477 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3478 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3479 WREG32(CP_CE_UCODE_ADDR, 0);
3480 for (i = 0; i < fw_size; i++)
3481 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3482 WREG32(CP_CE_UCODE_ADDR, 0);
3485 fw_data = (const __be32 *)
3486 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3487 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3488 WREG32(CP_ME_RAM_WADDR, 0);
3489 for (i = 0; i < fw_size; i++)
3490 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3491 WREG32(CP_ME_RAM_WADDR, 0);
3493 const __be32 *fw_data;
3496 fw_data = (const __be32 *)rdev->pfp_fw->data;
3497 WREG32(CP_PFP_UCODE_ADDR, 0);
3498 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
3499 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3500 WREG32(CP_PFP_UCODE_ADDR, 0);
3503 fw_data = (const __be32 *)rdev->ce_fw->data;
3504 WREG32(CP_CE_UCODE_ADDR, 0);
3505 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
3506 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3507 WREG32(CP_CE_UCODE_ADDR, 0);
3510 fw_data = (const __be32 *)rdev->me_fw->data;
3511 WREG32(CP_ME_RAM_WADDR, 0);
3512 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
3513 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3514 WREG32(CP_ME_RAM_WADDR, 0);
3517 WREG32(CP_PFP_UCODE_ADDR, 0);
3518 WREG32(CP_CE_UCODE_ADDR, 0);
3519 WREG32(CP_ME_RAM_WADDR, 0);
3520 WREG32(CP_ME_RAM_RADDR, 0);
3524 static int si_cp_start(struct radeon_device *rdev)
3526 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3529 r = radeon_ring_lock(rdev, ring, 7 + 4);
3531 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3535 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3536 radeon_ring_write(ring, 0x1);
3537 radeon_ring_write(ring, 0x0);
3538 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
3539 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
3540 radeon_ring_write(ring, 0);
3541 radeon_ring_write(ring, 0);
3543 /* init the CE partitions */
3544 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3545 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3546 radeon_ring_write(ring, 0xc000);
3547 radeon_ring_write(ring, 0xe000);
3548 radeon_ring_unlock_commit(rdev, ring, false);
3550 si_cp_enable(rdev, true);
3552 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
3554 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3558 /* setup clear context state */
3559 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3560 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3562 for (i = 0; i < si_default_size; i++)
3563 radeon_ring_write(ring, si_default_state[i]);
3565 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3566 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3568 /* set clear context state */
3569 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3570 radeon_ring_write(ring, 0);
3572 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3573 radeon_ring_write(ring, 0x00000316);
3574 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3575 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3577 radeon_ring_unlock_commit(rdev, ring, false);
3579 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
3580 ring = &rdev->ring[i];
3581 r = radeon_ring_lock(rdev, ring, 2);
3583 /* clear the compute context state */
3584 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
3585 radeon_ring_write(ring, 0);
3587 radeon_ring_unlock_commit(rdev, ring, false);
3593 static void si_cp_fini(struct radeon_device *rdev)
3595 struct radeon_ring *ring;
3596 si_cp_enable(rdev, false);
3598 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3599 radeon_ring_fini(rdev, ring);
3600 radeon_scratch_free(rdev, ring->rptr_save_reg);
3602 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3603 radeon_ring_fini(rdev, ring);
3604 radeon_scratch_free(rdev, ring->rptr_save_reg);
3606 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3607 radeon_ring_fini(rdev, ring);
3608 radeon_scratch_free(rdev, ring->rptr_save_reg);
3611 static int si_cp_resume(struct radeon_device *rdev)
3613 struct radeon_ring *ring;
3618 si_enable_gui_idle_interrupt(rdev, false);
3620 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3621 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3623 /* Set the write pointer delay */
3624 WREG32(CP_RB_WPTR_DELAY, 0);
3626 WREG32(CP_DEBUG, 0);
3627 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3629 /* ring 0 - compute and gfx */
3630 /* Set ring buffer size */
3631 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3632 rb_bufsz = order_base_2(ring->ring_size / 8);
3633 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3635 tmp |= BUF_SWAP_32BIT;
3637 WREG32(CP_RB0_CNTL, tmp);
3639 /* Initialize the ring buffer's read and write pointers */
3640 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
3642 WREG32(CP_RB0_WPTR, ring->wptr);
3644 /* set the wb address whether it's enabled or not */
3645 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
3646 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3648 if (rdev->wb.enabled)
3649 WREG32(SCRATCH_UMSK, 0xff);
3651 tmp |= RB_NO_UPDATE;
3652 WREG32(SCRATCH_UMSK, 0);
3656 WREG32(CP_RB0_CNTL, tmp);
3658 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3660 /* ring1 - compute only */
3661 /* Set ring buffer size */
3662 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3663 rb_bufsz = order_base_2(ring->ring_size / 8);
3664 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3666 tmp |= BUF_SWAP_32BIT;
3668 WREG32(CP_RB1_CNTL, tmp);
3670 /* Initialize the ring buffer's read and write pointers */
3671 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
3673 WREG32(CP_RB1_WPTR, ring->wptr);
3675 /* set the wb address whether it's enabled or not */
3676 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
3677 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
3680 WREG32(CP_RB1_CNTL, tmp);
3682 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3684 /* ring2 - compute only */
3685 /* Set ring buffer size */
3686 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3687 rb_bufsz = order_base_2(ring->ring_size / 8);
3688 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3690 tmp |= BUF_SWAP_32BIT;
3692 WREG32(CP_RB2_CNTL, tmp);
3694 /* Initialize the ring buffer's read and write pointers */
3695 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
3697 WREG32(CP_RB2_WPTR, ring->wptr);
3699 /* set the wb address whether it's enabled or not */
3700 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
3701 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
3704 WREG32(CP_RB2_CNTL, tmp);
3706 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3708 /* start the rings */
3710 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3711 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3712 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3713 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3715 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3716 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3717 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3720 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3722 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3724 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3726 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3729 si_enable_gui_idle_interrupt(rdev, true);
3731 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3732 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3737 u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
3743 tmp = RREG32(GRBM_STATUS);
3744 if (tmp & (PA_BUSY | SC_BUSY |
3745 BCI_BUSY | SX_BUSY |
3746 TA_BUSY | VGT_BUSY |
3748 GDS_BUSY | SPI_BUSY |
3749 IA_BUSY | IA_BUSY_NO_DMA))
3750 reset_mask |= RADEON_RESET_GFX;
3752 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
3753 CP_BUSY | CP_COHERENCY_BUSY))
3754 reset_mask |= RADEON_RESET_CP;
3756 if (tmp & GRBM_EE_BUSY)
3757 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
3760 tmp = RREG32(GRBM_STATUS2);
3761 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
3762 reset_mask |= RADEON_RESET_RLC;
3764 /* DMA_STATUS_REG 0 */
3765 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3766 if (!(tmp & DMA_IDLE))
3767 reset_mask |= RADEON_RESET_DMA;
3769 /* DMA_STATUS_REG 1 */
3770 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
3771 if (!(tmp & DMA_IDLE))
3772 reset_mask |= RADEON_RESET_DMA1;
3775 tmp = RREG32(SRBM_STATUS2);
3777 reset_mask |= RADEON_RESET_DMA;
3779 if (tmp & DMA1_BUSY)
3780 reset_mask |= RADEON_RESET_DMA1;
3783 tmp = RREG32(SRBM_STATUS);
3786 reset_mask |= RADEON_RESET_IH;
3789 reset_mask |= RADEON_RESET_SEM;
3791 if (tmp & GRBM_RQ_PENDING)
3792 reset_mask |= RADEON_RESET_GRBM;
3795 reset_mask |= RADEON_RESET_VMC;
3797 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
3798 MCC_BUSY | MCD_BUSY))
3799 reset_mask |= RADEON_RESET_MC;
3801 if (evergreen_is_display_hung(rdev))
3802 reset_mask |= RADEON_RESET_DISPLAY;
3805 tmp = RREG32(VM_L2_STATUS);
3807 reset_mask |= RADEON_RESET_VMC;
3809 /* Skip MC reset as it's mostly likely not hung, just busy */
3810 if (reset_mask & RADEON_RESET_MC) {
3811 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
3812 reset_mask &= ~RADEON_RESET_MC;
3818 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3820 struct evergreen_mc_save save;
3821 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3824 if (reset_mask == 0)
3827 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3829 evergreen_print_gpu_status_regs(rdev);
3830 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3831 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3832 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3833 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3842 /* Disable CP parsing/prefetching */
3843 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3845 if (reset_mask & RADEON_RESET_DMA) {
3847 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3848 tmp &= ~DMA_RB_ENABLE;
3849 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3851 if (reset_mask & RADEON_RESET_DMA1) {
3853 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3854 tmp &= ~DMA_RB_ENABLE;
3855 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3860 evergreen_mc_stop(rdev, &save);
3861 if (evergreen_mc_wait_for_idle(rdev)) {
3862 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3865 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
3866 grbm_soft_reset = SOFT_RESET_CB |
3880 if (reset_mask & RADEON_RESET_CP) {
3881 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
3883 srbm_soft_reset |= SOFT_RESET_GRBM;
3886 if (reset_mask & RADEON_RESET_DMA)
3887 srbm_soft_reset |= SOFT_RESET_DMA;
3889 if (reset_mask & RADEON_RESET_DMA1)
3890 srbm_soft_reset |= SOFT_RESET_DMA1;
3892 if (reset_mask & RADEON_RESET_DISPLAY)
3893 srbm_soft_reset |= SOFT_RESET_DC;
3895 if (reset_mask & RADEON_RESET_RLC)
3896 grbm_soft_reset |= SOFT_RESET_RLC;
3898 if (reset_mask & RADEON_RESET_SEM)
3899 srbm_soft_reset |= SOFT_RESET_SEM;
3901 if (reset_mask & RADEON_RESET_IH)
3902 srbm_soft_reset |= SOFT_RESET_IH;
3904 if (reset_mask & RADEON_RESET_GRBM)
3905 srbm_soft_reset |= SOFT_RESET_GRBM;
3907 if (reset_mask & RADEON_RESET_VMC)
3908 srbm_soft_reset |= SOFT_RESET_VMC;
3910 if (reset_mask & RADEON_RESET_MC)
3911 srbm_soft_reset |= SOFT_RESET_MC;
3913 if (grbm_soft_reset) {
3914 tmp = RREG32(GRBM_SOFT_RESET);
3915 tmp |= grbm_soft_reset;
3916 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3917 WREG32(GRBM_SOFT_RESET, tmp);
3918 tmp = RREG32(GRBM_SOFT_RESET);
3922 tmp &= ~grbm_soft_reset;
3923 WREG32(GRBM_SOFT_RESET, tmp);
3924 tmp = RREG32(GRBM_SOFT_RESET);
3927 if (srbm_soft_reset) {
3928 tmp = RREG32(SRBM_SOFT_RESET);
3929 tmp |= srbm_soft_reset;
3930 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3931 WREG32(SRBM_SOFT_RESET, tmp);
3932 tmp = RREG32(SRBM_SOFT_RESET);
3936 tmp &= ~srbm_soft_reset;
3937 WREG32(SRBM_SOFT_RESET, tmp);
3938 tmp = RREG32(SRBM_SOFT_RESET);
3941 /* Wait a little for things to settle down */
3944 evergreen_mc_resume(rdev, &save);
3947 evergreen_print_gpu_status_regs(rdev);
3950 static void si_set_clk_bypass_mode(struct radeon_device *rdev)
3954 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3955 tmp |= SPLL_BYPASS_EN;
3956 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3958 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3959 tmp |= SPLL_CTLREQ_CHG;
3960 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3962 for (i = 0; i < rdev->usec_timeout; i++) {
3963 if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
3968 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3969 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
3970 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3972 tmp = RREG32(MPLL_CNTL_MODE);
3973 tmp &= ~MPLL_MCLK_SEL;
3974 WREG32(MPLL_CNTL_MODE, tmp);
3977 static void si_spll_powerdown(struct radeon_device *rdev)
3981 tmp = RREG32(SPLL_CNTL_MODE);
3982 tmp |= SPLL_SW_DIR_CONTROL;
3983 WREG32(SPLL_CNTL_MODE, tmp);
3985 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3987 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3989 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3991 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3993 tmp = RREG32(SPLL_CNTL_MODE);
3994 tmp &= ~SPLL_SW_DIR_CONTROL;
3995 WREG32(SPLL_CNTL_MODE, tmp);
3998 static void si_gpu_pci_config_reset(struct radeon_device *rdev)
4000 struct evergreen_mc_save save;
4003 dev_info(rdev->dev, "GPU pci config reset\n");
4011 /* Disable CP parsing/prefetching */
4012 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
4014 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
4015 tmp &= ~DMA_RB_ENABLE;
4016 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
4018 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
4019 tmp &= ~DMA_RB_ENABLE;
4020 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
4021 /* XXX other engines? */
4023 /* halt the rlc, disable cp internal ints */
4028 /* disable mem access */
4029 evergreen_mc_stop(rdev, &save);
4030 if (evergreen_mc_wait_for_idle(rdev)) {
4031 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
4034 /* set mclk/sclk to bypass */
4035 si_set_clk_bypass_mode(rdev);
4036 /* powerdown spll */
4037 si_spll_powerdown(rdev);
4039 pci_clear_master(rdev->pdev);
4041 radeon_pci_config_reset(rdev);
4042 /* wait for asic to come out of reset */
4043 for (i = 0; i < rdev->usec_timeout; i++) {
4044 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
4050 int si_asic_reset(struct radeon_device *rdev, bool hard)
4055 si_gpu_pci_config_reset(rdev);
4059 reset_mask = si_gpu_check_soft_reset(rdev);
4062 r600_set_bios_scratch_engine_hung(rdev, true);
4064 /* try soft reset */
4065 si_gpu_soft_reset(rdev, reset_mask);
4067 reset_mask = si_gpu_check_soft_reset(rdev);
4069 /* try pci config reset */
4070 if (reset_mask && radeon_hard_reset)
4071 si_gpu_pci_config_reset(rdev);
4073 reset_mask = si_gpu_check_soft_reset(rdev);
4076 r600_set_bios_scratch_engine_hung(rdev, false);
4082 * si_gfx_is_lockup - Check if the GFX engine is locked up
4084 * @rdev: radeon_device pointer
4085 * @ring: radeon_ring structure holding ring information
4087 * Check if the GFX engine is locked up.
4088 * Returns true if the engine appears to be locked up, false if not.
4090 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4092 u32 reset_mask = si_gpu_check_soft_reset(rdev);
4094 if (!(reset_mask & (RADEON_RESET_GFX |
4095 RADEON_RESET_COMPUTE |
4096 RADEON_RESET_CP))) {
4097 radeon_ring_lockup_update(rdev, ring);
4100 return radeon_ring_test_lockup(rdev, ring);
4104 static void si_mc_program(struct radeon_device *rdev)
4106 struct evergreen_mc_save save;
4110 /* Initialize HDP */
4111 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
4112 WREG32((0x2c14 + j), 0x00000000);
4113 WREG32((0x2c18 + j), 0x00000000);
4114 WREG32((0x2c1c + j), 0x00000000);
4115 WREG32((0x2c20 + j), 0x00000000);
4116 WREG32((0x2c24 + j), 0x00000000);
4118 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
4120 evergreen_mc_stop(rdev, &save);
4121 if (radeon_mc_wait_for_idle(rdev)) {
4122 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4124 if (!ASIC_IS_NODCE(rdev))
4125 /* Lockout access through VGA aperture*/
4126 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
4127 /* Update configuration */
4128 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
4129 rdev->mc.vram_start >> 12);
4130 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
4131 rdev->mc.vram_end >> 12);
4132 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
4133 rdev->vram_scratch.gpu_addr >> 12);
4134 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
4135 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
4136 WREG32(MC_VM_FB_LOCATION, tmp);
4137 /* XXX double check these! */
4138 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
4139 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
4140 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
4141 WREG32(MC_VM_AGP_BASE, 0);
4142 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
4143 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
4144 if (radeon_mc_wait_for_idle(rdev)) {
4145 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4147 evergreen_mc_resume(rdev, &save);
4148 if (!ASIC_IS_NODCE(rdev)) {
4149 /* we need to own VRAM, so turn off the VGA renderer here
4150 * to stop it overwriting our objects */
4151 rv515_vga_render_disable(rdev);
4155 void si_vram_gtt_location(struct radeon_device *rdev,
4156 struct radeon_mc *mc)
4158 if (mc->mc_vram_size > 0xFFC0000000ULL) {
4159 /* leave room for at least 1024M GTT */
4160 dev_warn(rdev->dev, "limiting VRAM\n");
4161 mc->real_vram_size = 0xFFC0000000ULL;
4162 mc->mc_vram_size = 0xFFC0000000ULL;
4164 radeon_vram_location(rdev, &rdev->mc, 0);
4165 rdev->mc.gtt_base_align = 0;
4166 radeon_gtt_location(rdev, mc);
4169 static int si_mc_init(struct radeon_device *rdev)
4172 int chansize, numchan;
4174 /* Get VRAM informations */
4175 rdev->mc.vram_is_ddr = true;
4176 tmp = RREG32(MC_ARB_RAMCFG);
4177 if (tmp & CHANSIZE_OVERRIDE) {
4179 } else if (tmp & CHANSIZE_MASK) {
4184 tmp = RREG32(MC_SHARED_CHMAP);
4185 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
4215 rdev->mc.vram_width = numchan * chansize;
4216 /* Could aper size report 0 ? */
4217 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
4218 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
4219 /* size in MB on si */
4220 tmp = RREG32(CONFIG_MEMSIZE);
4221 /* some boards may have garbage in the upper 16 bits */
4222 if (tmp & 0xffff0000) {
4223 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
4227 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
4228 rdev->mc.real_vram_size = rdev->mc.mc_vram_size;
4229 rdev->mc.visible_vram_size = rdev->mc.aper_size;
4230 si_vram_gtt_location(rdev, &rdev->mc);
4231 radeon_update_bandwidth_info(rdev);
4239 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
4241 /* flush hdp cache */
4242 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4244 /* bits 0-15 are the VM contexts0-15 */
4245 WREG32(VM_INVALIDATE_REQUEST, 1);
4248 static int si_pcie_gart_enable(struct radeon_device *rdev)
4252 if (rdev->gart.robj == NULL) {
4253 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
4256 r = radeon_gart_table_vram_pin(rdev);
4259 /* Setup TLB control */
4260 WREG32(MC_VM_MX_L1_TLB_CNTL,
4263 ENABLE_L1_FRAGMENT_PROCESSING |
4264 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4265 ENABLE_ADVANCED_DRIVER_MODEL |
4266 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4267 /* Setup L2 cache */
4268 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
4269 ENABLE_L2_FRAGMENT_PROCESSING |
4270 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4271 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4272 EFFECTIVE_L2_QUEUE_SIZE(7) |
4273 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4274 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
4275 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4277 L2_CACHE_BIGK_FRAGMENT_SIZE(4));
4278 /* setup context0 */
4279 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
4280 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
4281 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
4282 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
4283 (u32)(rdev->dummy_page.addr >> 12));
4284 WREG32(VM_CONTEXT0_CNTL2, 0);
4285 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
4286 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
4292 /* empty context1-15 */
4293 /* set vm size, must be a multiple of 4 */
4294 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
4295 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
4296 /* Assign the pt base to something valid for now; the pts used for
4297 * the VMs are determined by the application and setup and assigned
4298 * on the fly in the vm part of radeon_gart.c
4300 for (i = 1; i < 16; i++) {
4302 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
4303 rdev->vm_manager.saved_table_addr[i]);
4305 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
4306 rdev->vm_manager.saved_table_addr[i]);
4309 /* enable context1-15 */
4310 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
4311 (u32)(rdev->dummy_page.addr >> 12));
4312 WREG32(VM_CONTEXT1_CNTL2, 4);
4313 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
4314 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
4315 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4316 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4317 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4318 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4319 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
4320 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
4321 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
4322 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
4323 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
4324 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
4325 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4326 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
4328 si_pcie_gart_tlb_flush(rdev);
4329 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
4330 (unsigned)(rdev->mc.gtt_size >> 20),
4331 (unsigned long long)rdev->gart.table_addr);
4332 rdev->gart.ready = true;
4336 static void si_pcie_gart_disable(struct radeon_device *rdev)
4340 for (i = 1; i < 16; ++i) {
4343 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
4345 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
4346 rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
4349 /* Disable all tables */
4350 WREG32(VM_CONTEXT0_CNTL, 0);
4351 WREG32(VM_CONTEXT1_CNTL, 0);
4352 /* Setup TLB control */
4353 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4354 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4355 /* Setup L2 cache */
4356 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4357 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4358 EFFECTIVE_L2_QUEUE_SIZE(7) |
4359 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4360 WREG32(VM_L2_CNTL2, 0);
4361 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4362 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
4363 radeon_gart_table_vram_unpin(rdev);
4366 static void si_pcie_gart_fini(struct radeon_device *rdev)
4368 si_pcie_gart_disable(rdev);
4369 radeon_gart_table_vram_free(rdev);
4370 radeon_gart_fini(rdev);
4374 static bool si_vm_reg_valid(u32 reg)
4376 /* context regs are fine */
4380 /* shader regs are also fine */
4381 if (reg >= 0xB000 && reg < 0xC000)
4384 /* check config regs */
4386 case GRBM_GFX_INDEX:
4387 case CP_STRMOUT_CNTL:
4388 case VGT_VTX_VECT_EJECT_REG:
4389 case VGT_CACHE_INVALIDATION:
4390 case VGT_ESGS_RING_SIZE:
4391 case VGT_GSVS_RING_SIZE:
4392 case VGT_GS_VERTEX_REUSE:
4393 case VGT_PRIMITIVE_TYPE:
4394 case VGT_INDEX_TYPE:
4395 case VGT_NUM_INDICES:
4396 case VGT_NUM_INSTANCES:
4397 case VGT_TF_RING_SIZE:
4398 case VGT_HS_OFFCHIP_PARAM:
4399 case VGT_TF_MEMORY_BASE:
4401 case PA_SU_LINE_STIPPLE_VALUE:
4402 case PA_SC_LINE_STIPPLE_STATE:
4405 case SPI_STATIC_THREAD_MGMT_1:
4406 case SPI_STATIC_THREAD_MGMT_2:
4407 case SPI_STATIC_THREAD_MGMT_3:
4408 case SPI_PS_MAX_WAVE_ID:
4409 case SPI_CONFIG_CNTL:
4410 case SPI_CONFIG_CNTL_1:
4414 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
4419 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
4420 u32 *ib, struct radeon_cs_packet *pkt)
4422 switch (pkt->opcode) {
4424 case PACKET3_SET_BASE:
4425 case PACKET3_SET_CE_DE_COUNTERS:
4426 case PACKET3_LOAD_CONST_RAM:
4427 case PACKET3_WRITE_CONST_RAM:
4428 case PACKET3_WRITE_CONST_RAM_OFFSET:
4429 case PACKET3_DUMP_CONST_RAM:
4430 case PACKET3_INCREMENT_CE_COUNTER:
4431 case PACKET3_WAIT_ON_DE_COUNTER:
4432 case PACKET3_CE_WRITE:
4435 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
4441 static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
4443 u32 start_reg, reg, i;
4444 u32 command = ib[idx + 4];
4445 u32 info = ib[idx + 1];
4446 u32 idx_value = ib[idx];
4447 if (command & PACKET3_CP_DMA_CMD_SAS) {
4448 /* src address space is register */
4449 if (((info & 0x60000000) >> 29) == 0) {
4450 start_reg = idx_value << 2;
4451 if (command & PACKET3_CP_DMA_CMD_SAIC) {
4453 if (!si_vm_reg_valid(reg)) {
4454 DRM_ERROR("CP DMA Bad SRC register\n");
4458 for (i = 0; i < (command & 0x1fffff); i++) {
4459 reg = start_reg + (4 * i);
4460 if (!si_vm_reg_valid(reg)) {
4461 DRM_ERROR("CP DMA Bad SRC register\n");
4468 if (command & PACKET3_CP_DMA_CMD_DAS) {
4469 /* dst address space is register */
4470 if (((info & 0x00300000) >> 20) == 0) {
4471 start_reg = ib[idx + 2];
4472 if (command & PACKET3_CP_DMA_CMD_DAIC) {
4474 if (!si_vm_reg_valid(reg)) {
4475 DRM_ERROR("CP DMA Bad DST register\n");
4479 for (i = 0; i < (command & 0x1fffff); i++) {
4480 reg = start_reg + (4 * i);
4481 if (!si_vm_reg_valid(reg)) {
4482 DRM_ERROR("CP DMA Bad DST register\n");
4492 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
4493 u32 *ib, struct radeon_cs_packet *pkt)
4496 u32 idx = pkt->idx + 1;
4497 u32 idx_value = ib[idx];
4498 u32 start_reg, end_reg, reg, i;
4500 switch (pkt->opcode) {
4502 case PACKET3_SET_BASE:
4503 case PACKET3_CLEAR_STATE:
4504 case PACKET3_INDEX_BUFFER_SIZE:
4505 case PACKET3_DISPATCH_DIRECT:
4506 case PACKET3_DISPATCH_INDIRECT:
4507 case PACKET3_ALLOC_GDS:
4508 case PACKET3_WRITE_GDS_RAM:
4509 case PACKET3_ATOMIC_GDS:
4510 case PACKET3_ATOMIC:
4511 case PACKET3_OCCLUSION_QUERY:
4512 case PACKET3_SET_PREDICATION:
4513 case PACKET3_COND_EXEC:
4514 case PACKET3_PRED_EXEC:
4515 case PACKET3_DRAW_INDIRECT:
4516 case PACKET3_DRAW_INDEX_INDIRECT:
4517 case PACKET3_INDEX_BASE:
4518 case PACKET3_DRAW_INDEX_2:
4519 case PACKET3_CONTEXT_CONTROL:
4520 case PACKET3_INDEX_TYPE:
4521 case PACKET3_DRAW_INDIRECT_MULTI:
4522 case PACKET3_DRAW_INDEX_AUTO:
4523 case PACKET3_DRAW_INDEX_IMMD:
4524 case PACKET3_NUM_INSTANCES:
4525 case PACKET3_DRAW_INDEX_MULTI_AUTO:
4526 case PACKET3_STRMOUT_BUFFER_UPDATE:
4527 case PACKET3_DRAW_INDEX_OFFSET_2:
4528 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
4529 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
4530 case PACKET3_MPEG_INDEX:
4531 case PACKET3_WAIT_REG_MEM:
4532 case PACKET3_MEM_WRITE:
4533 case PACKET3_PFP_SYNC_ME:
4534 case PACKET3_SURFACE_SYNC:
4535 case PACKET3_EVENT_WRITE:
4536 case PACKET3_EVENT_WRITE_EOP:
4537 case PACKET3_EVENT_WRITE_EOS:
4538 case PACKET3_SET_CONTEXT_REG:
4539 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4540 case PACKET3_SET_SH_REG:
4541 case PACKET3_SET_SH_REG_OFFSET:
4542 case PACKET3_INCREMENT_DE_COUNTER:
4543 case PACKET3_WAIT_ON_CE_COUNTER:
4544 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4545 case PACKET3_ME_WRITE:
4547 case PACKET3_COPY_DATA:
4548 if ((idx_value & 0xf00) == 0) {
4549 reg = ib[idx + 3] * 4;
4550 if (!si_vm_reg_valid(reg))
4554 case PACKET3_WRITE_DATA:
4555 if ((idx_value & 0xf00) == 0) {
4556 start_reg = ib[idx + 1] * 4;
4557 if (idx_value & 0x10000) {
4558 if (!si_vm_reg_valid(start_reg))
4561 for (i = 0; i < (pkt->count - 2); i++) {
4562 reg = start_reg + (4 * i);
4563 if (!si_vm_reg_valid(reg))
4569 case PACKET3_COND_WRITE:
4570 if (idx_value & 0x100) {
4571 reg = ib[idx + 5] * 4;
4572 if (!si_vm_reg_valid(reg))
4576 case PACKET3_COPY_DW:
4577 if (idx_value & 0x2) {
4578 reg = ib[idx + 3] * 4;
4579 if (!si_vm_reg_valid(reg))
4583 case PACKET3_SET_CONFIG_REG:
4584 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
4585 end_reg = 4 * pkt->count + start_reg - 4;
4586 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
4587 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
4588 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
4589 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
4592 for (i = 0; i < pkt->count; i++) {
4593 reg = start_reg + (4 * i);
4594 if (!si_vm_reg_valid(reg))
4598 case PACKET3_CP_DMA:
4599 r = si_vm_packet3_cp_dma_check(ib, idx);
4604 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
4610 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
4611 u32 *ib, struct radeon_cs_packet *pkt)
4614 u32 idx = pkt->idx + 1;
4615 u32 idx_value = ib[idx];
4616 u32 start_reg, reg, i;
4618 switch (pkt->opcode) {
4620 case PACKET3_SET_BASE:
4621 case PACKET3_CLEAR_STATE:
4622 case PACKET3_DISPATCH_DIRECT:
4623 case PACKET3_DISPATCH_INDIRECT:
4624 case PACKET3_ALLOC_GDS:
4625 case PACKET3_WRITE_GDS_RAM:
4626 case PACKET3_ATOMIC_GDS:
4627 case PACKET3_ATOMIC:
4628 case PACKET3_OCCLUSION_QUERY:
4629 case PACKET3_SET_PREDICATION:
4630 case PACKET3_COND_EXEC:
4631 case PACKET3_PRED_EXEC:
4632 case PACKET3_CONTEXT_CONTROL:
4633 case PACKET3_STRMOUT_BUFFER_UPDATE:
4634 case PACKET3_WAIT_REG_MEM:
4635 case PACKET3_MEM_WRITE:
4636 case PACKET3_PFP_SYNC_ME:
4637 case PACKET3_SURFACE_SYNC:
4638 case PACKET3_EVENT_WRITE:
4639 case PACKET3_EVENT_WRITE_EOP:
4640 case PACKET3_EVENT_WRITE_EOS:
4641 case PACKET3_SET_CONTEXT_REG:
4642 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4643 case PACKET3_SET_SH_REG:
4644 case PACKET3_SET_SH_REG_OFFSET:
4645 case PACKET3_INCREMENT_DE_COUNTER:
4646 case PACKET3_WAIT_ON_CE_COUNTER:
4647 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4648 case PACKET3_ME_WRITE:
4650 case PACKET3_COPY_DATA:
4651 if ((idx_value & 0xf00) == 0) {
4652 reg = ib[idx + 3] * 4;
4653 if (!si_vm_reg_valid(reg))
4657 case PACKET3_WRITE_DATA:
4658 if ((idx_value & 0xf00) == 0) {
4659 start_reg = ib[idx + 1] * 4;
4660 if (idx_value & 0x10000) {
4661 if (!si_vm_reg_valid(start_reg))
4664 for (i = 0; i < (pkt->count - 2); i++) {
4665 reg = start_reg + (4 * i);
4666 if (!si_vm_reg_valid(reg))
4672 case PACKET3_COND_WRITE:
4673 if (idx_value & 0x100) {
4674 reg = ib[idx + 5] * 4;
4675 if (!si_vm_reg_valid(reg))
4679 case PACKET3_COPY_DW:
4680 if (idx_value & 0x2) {
4681 reg = ib[idx + 3] * 4;
4682 if (!si_vm_reg_valid(reg))
4686 case PACKET3_CP_DMA:
4687 r = si_vm_packet3_cp_dma_check(ib, idx);
4692 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
4698 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4702 struct radeon_cs_packet pkt;
4706 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
4707 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
4710 case RADEON_PACKET_TYPE0:
4711 dev_err(rdev->dev, "Packet0 not allowed!\n");
4714 case RADEON_PACKET_TYPE2:
4717 case RADEON_PACKET_TYPE3:
4718 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
4719 if (ib->is_const_ib)
4720 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
4723 case RADEON_RING_TYPE_GFX_INDEX:
4724 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
4726 case CAYMAN_RING_TYPE_CP1_INDEX:
4727 case CAYMAN_RING_TYPE_CP2_INDEX:
4728 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
4731 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
4736 idx += pkt.count + 2;
4739 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
4744 for (i = 0; i < ib->length_dw; i++) {
4746 printk("\t0x%08x <---\n", ib->ptr[i]);
4748 printk("\t0x%08x\n", ib->ptr[i]);
4752 } while (idx < ib->length_dw);
4760 int si_vm_init(struct radeon_device *rdev)
4763 rdev->vm_manager.nvm = 16;
4764 /* base offset of vram pages */
4765 rdev->vm_manager.vram_base_offset = 0;
4770 void si_vm_fini(struct radeon_device *rdev)
4775 * si_vm_decode_fault - print human readable fault info
4777 * @rdev: radeon_device pointer
4778 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
4779 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
4781 * Print human readable fault information (SI).
4783 static void si_vm_decode_fault(struct radeon_device *rdev,
4784 u32 status, u32 addr)
4786 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
4787 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4788 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4791 if (rdev->family == CHIP_TAHITI) {
5032 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
5033 protections, vmid, addr,
5034 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
5038 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
5039 unsigned vm_id, uint64_t pd_addr)
5041 /* write new base address */
5042 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5043 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5044 WRITE_DATA_DST_SEL(0)));
5047 radeon_ring_write(ring,
5048 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
5050 radeon_ring_write(ring,
5051 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
5053 radeon_ring_write(ring, 0);
5054 radeon_ring_write(ring, pd_addr >> 12);
5056 /* flush hdp cache */
5057 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5058 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5059 WRITE_DATA_DST_SEL(0)));
5060 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
5061 radeon_ring_write(ring, 0);
5062 radeon_ring_write(ring, 0x1);
5064 /* bits 0-15 are the VM contexts0-15 */
5065 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5066 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5067 WRITE_DATA_DST_SEL(0)));
5068 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5069 radeon_ring_write(ring, 0);
5070 radeon_ring_write(ring, 1 << vm_id);
5072 /* wait for the invalidate to complete */
5073 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5074 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
5075 WAIT_REG_MEM_ENGINE(0))); /* me */
5076 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5077 radeon_ring_write(ring, 0);
5078 radeon_ring_write(ring, 0); /* ref */
5079 radeon_ring_write(ring, 0); /* mask */
5080 radeon_ring_write(ring, 0x20); /* poll interval */
5082 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5083 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5084 radeon_ring_write(ring, 0x0);
5088 * Power and clock gating
5090 static void si_wait_for_rlc_serdes(struct radeon_device *rdev)
5094 for (i = 0; i < rdev->usec_timeout; i++) {
5095 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
5100 for (i = 0; i < rdev->usec_timeout; i++) {
5101 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
5107 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
5110 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5115 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5117 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5118 WREG32(CP_INT_CNTL_RING0, tmp);
5121 /* read a gfx register */
5122 tmp = RREG32(DB_DEPTH_INFO);
5124 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
5125 for (i = 0; i < rdev->usec_timeout; i++) {
5126 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
5133 static void si_set_uvd_dcm(struct radeon_device *rdev,
5138 tmp = RREG32(UVD_CGC_CTRL);
5139 tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
5140 tmp |= DCM | CG_DT(1) | CLK_OD(4);
5144 tmp2 = DYN_OR_EN | DYN_RR_EN | G_DIV_ID(7);
5150 WREG32(UVD_CGC_CTRL, tmp);
5151 WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2);
5154 void si_init_uvd_internal_cg(struct radeon_device *rdev)
5156 bool hw_mode = true;
5159 si_set_uvd_dcm(rdev, false);
5161 u32 tmp = RREG32(UVD_CGC_CTRL);
5163 WREG32(UVD_CGC_CTRL, tmp);
5167 static u32 si_halt_rlc(struct radeon_device *rdev)
5171 orig = data = RREG32(RLC_CNTL);
5173 if (data & RLC_ENABLE) {
5174 data &= ~RLC_ENABLE;
5175 WREG32(RLC_CNTL, data);
5177 si_wait_for_rlc_serdes(rdev);
5183 static void si_update_rlc(struct radeon_device *rdev, u32 rlc)
5187 tmp = RREG32(RLC_CNTL);
5189 WREG32(RLC_CNTL, rlc);
5192 static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
5196 orig = data = RREG32(DMA_PG);
5197 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))
5198 data |= PG_CNTL_ENABLE;
5200 data &= ~PG_CNTL_ENABLE;
5202 WREG32(DMA_PG, data);
5205 static void si_init_dma_pg(struct radeon_device *rdev)
5209 WREG32(DMA_PGFSM_WRITE, 0x00002000);
5210 WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
5212 for (tmp = 0; tmp < 5; tmp++)
5213 WREG32(DMA_PGFSM_WRITE, 0);
5216 static void si_enable_gfx_cgpg(struct radeon_device *rdev,
5221 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
5222 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
5223 WREG32(RLC_TTOP_D, tmp);
5225 tmp = RREG32(RLC_PG_CNTL);
5226 tmp |= GFX_PG_ENABLE;
5227 WREG32(RLC_PG_CNTL, tmp);
5229 tmp = RREG32(RLC_AUTO_PG_CTRL);
5231 WREG32(RLC_AUTO_PG_CTRL, tmp);
5233 tmp = RREG32(RLC_AUTO_PG_CTRL);
5235 WREG32(RLC_AUTO_PG_CTRL, tmp);
5237 tmp = RREG32(DB_RENDER_CONTROL);
5241 static void si_init_gfx_cgpg(struct radeon_device *rdev)
5245 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5247 tmp = RREG32(RLC_PG_CNTL);
5249 WREG32(RLC_PG_CNTL, tmp);
5251 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5253 tmp = RREG32(RLC_AUTO_PG_CTRL);
5255 tmp &= ~GRBM_REG_SGIT_MASK;
5256 tmp |= GRBM_REG_SGIT(0x700);
5257 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
5258 WREG32(RLC_AUTO_PG_CTRL, tmp);
5261 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
5263 u32 mask = 0, tmp, tmp1;
5266 si_select_se_sh(rdev, se, sh);
5267 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
5268 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
5269 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5276 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) {
5281 return (~tmp) & mask;
5284 static void si_init_ao_cu_mask(struct radeon_device *rdev)
5286 u32 i, j, k, active_cu_number = 0;
5287 u32 mask, counter, cu_bitmap;
5290 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
5291 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
5295 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
5296 if (si_get_cu_active_bitmap(rdev, i, j) & mask) {
5304 active_cu_number += counter;
5305 tmp |= (cu_bitmap << (i * 16 + j * 8));
5309 WREG32(RLC_PG_AO_CU_MASK, tmp);
5311 tmp = RREG32(RLC_MAX_PG_CU);
5312 tmp &= ~MAX_PU_CU_MASK;
5313 tmp |= MAX_PU_CU(active_cu_number);
5314 WREG32(RLC_MAX_PG_CU, tmp);
5317 static void si_enable_cgcg(struct radeon_device *rdev,
5320 u32 data, orig, tmp;
5322 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
5324 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
5325 si_enable_gui_idle_interrupt(rdev, true);
5327 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
5329 tmp = si_halt_rlc(rdev);
5331 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5332 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5333 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
5335 si_wait_for_rlc_serdes(rdev);
5337 si_update_rlc(rdev, tmp);
5339 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
5341 data |= CGCG_EN | CGLS_EN;
5343 si_enable_gui_idle_interrupt(rdev, false);
5345 RREG32(CB_CGTT_SCLK_CTRL);
5346 RREG32(CB_CGTT_SCLK_CTRL);
5347 RREG32(CB_CGTT_SCLK_CTRL);
5348 RREG32(CB_CGTT_SCLK_CTRL);
5350 data &= ~(CGCG_EN | CGLS_EN);
5354 WREG32(RLC_CGCG_CGLS_CTRL, data);
5357 static void si_enable_mgcg(struct radeon_device *rdev,
5360 u32 data, orig, tmp = 0;
5362 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
5363 orig = data = RREG32(CGTS_SM_CTRL_REG);
5366 WREG32(CGTS_SM_CTRL_REG, data);
5368 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
5369 orig = data = RREG32(CP_MEM_SLP_CNTL);
5370 data |= CP_MEM_LS_EN;
5372 WREG32(CP_MEM_SLP_CNTL, data);
5375 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5378 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5380 tmp = si_halt_rlc(rdev);
5382 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5383 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5384 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
5386 si_update_rlc(rdev, tmp);
5388 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5391 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5393 data = RREG32(CP_MEM_SLP_CNTL);
5394 if (data & CP_MEM_LS_EN) {
5395 data &= ~CP_MEM_LS_EN;
5396 WREG32(CP_MEM_SLP_CNTL, data);
5398 orig = data = RREG32(CGTS_SM_CTRL_REG);
5399 data |= LS_OVERRIDE | OVERRIDE;
5401 WREG32(CGTS_SM_CTRL_REG, data);
5403 tmp = si_halt_rlc(rdev);
5405 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5406 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5407 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
5409 si_update_rlc(rdev, tmp);
5413 static void si_enable_uvd_mgcg(struct radeon_device *rdev,
5416 u32 orig, data, tmp;
5418 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
5419 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5421 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5423 orig = data = RREG32(UVD_CGC_CTRL);
5426 WREG32(UVD_CGC_CTRL, data);
5428 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0);
5429 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0);
5431 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5433 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5435 orig = data = RREG32(UVD_CGC_CTRL);
5438 WREG32(UVD_CGC_CTRL, data);
5440 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff);
5441 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
5445 static const u32 mc_cg_registers[] =
5458 static void si_enable_mc_ls(struct radeon_device *rdev,
5464 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5465 orig = data = RREG32(mc_cg_registers[i]);
5466 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
5467 data |= MC_LS_ENABLE;
5469 data &= ~MC_LS_ENABLE;
5471 WREG32(mc_cg_registers[i], data);
5475 static void si_enable_mc_mgcg(struct radeon_device *rdev,
5481 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5482 orig = data = RREG32(mc_cg_registers[i]);
5483 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
5484 data |= MC_CG_ENABLE;
5486 data &= ~MC_CG_ENABLE;
5488 WREG32(mc_cg_registers[i], data);
5492 static void si_enable_dma_mgcg(struct radeon_device *rdev,
5495 u32 orig, data, offset;
5498 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
5499 for (i = 0; i < 2; i++) {
5501 offset = DMA0_REGISTER_OFFSET;
5503 offset = DMA1_REGISTER_OFFSET;
5504 orig = data = RREG32(DMA_POWER_CNTL + offset);
5505 data &= ~MEM_POWER_OVERRIDE;
5507 WREG32(DMA_POWER_CNTL + offset, data);
5508 WREG32(DMA_CLK_CTRL + offset, 0x00000100);
5511 for (i = 0; i < 2; i++) {
5513 offset = DMA0_REGISTER_OFFSET;
5515 offset = DMA1_REGISTER_OFFSET;
5516 orig = data = RREG32(DMA_POWER_CNTL + offset);
5517 data |= MEM_POWER_OVERRIDE;
5519 WREG32(DMA_POWER_CNTL + offset, data);
5521 orig = data = RREG32(DMA_CLK_CTRL + offset);
5524 WREG32(DMA_CLK_CTRL + offset, data);
5529 static void si_enable_bif_mgls(struct radeon_device *rdev,
5534 orig = data = RREG32_PCIE(PCIE_CNTL2);
5536 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
5537 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
5538 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
5540 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
5541 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
5544 WREG32_PCIE(PCIE_CNTL2, data);
5547 static void si_enable_hdp_mgcg(struct radeon_device *rdev,
5552 orig = data = RREG32(HDP_HOST_PATH_CNTL);
5554 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
5555 data &= ~CLOCK_GATING_DIS;
5557 data |= CLOCK_GATING_DIS;
5560 WREG32(HDP_HOST_PATH_CNTL, data);
5563 static void si_enable_hdp_ls(struct radeon_device *rdev,
5568 orig = data = RREG32(HDP_MEM_POWER_LS);
5570 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
5571 data |= HDP_LS_ENABLE;
5573 data &= ~HDP_LS_ENABLE;
5576 WREG32(HDP_MEM_POWER_LS, data);
5579 static void si_update_cg(struct radeon_device *rdev,
5580 u32 block, bool enable)
5582 if (block & RADEON_CG_BLOCK_GFX) {
5583 si_enable_gui_idle_interrupt(rdev, false);
5584 /* order matters! */
5586 si_enable_mgcg(rdev, true);
5587 si_enable_cgcg(rdev, true);
5589 si_enable_cgcg(rdev, false);
5590 si_enable_mgcg(rdev, false);
5592 si_enable_gui_idle_interrupt(rdev, true);
5595 if (block & RADEON_CG_BLOCK_MC) {
5596 si_enable_mc_mgcg(rdev, enable);
5597 si_enable_mc_ls(rdev, enable);
5600 if (block & RADEON_CG_BLOCK_SDMA) {
5601 si_enable_dma_mgcg(rdev, enable);
5604 if (block & RADEON_CG_BLOCK_BIF) {
5605 si_enable_bif_mgls(rdev, enable);
5608 if (block & RADEON_CG_BLOCK_UVD) {
5609 if (rdev->has_uvd) {
5610 si_enable_uvd_mgcg(rdev, enable);
5614 if (block & RADEON_CG_BLOCK_HDP) {
5615 si_enable_hdp_mgcg(rdev, enable);
5616 si_enable_hdp_ls(rdev, enable);
5620 static void si_init_cg(struct radeon_device *rdev)
5622 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5623 RADEON_CG_BLOCK_MC |
5624 RADEON_CG_BLOCK_SDMA |
5625 RADEON_CG_BLOCK_BIF |
5626 RADEON_CG_BLOCK_HDP), true);
5627 if (rdev->has_uvd) {
5628 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
5629 si_init_uvd_internal_cg(rdev);
5633 static void si_fini_cg(struct radeon_device *rdev)
5635 if (rdev->has_uvd) {
5636 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
5638 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5639 RADEON_CG_BLOCK_MC |
5640 RADEON_CG_BLOCK_SDMA |
5641 RADEON_CG_BLOCK_BIF |
5642 RADEON_CG_BLOCK_HDP), false);
5645 u32 si_get_csb_size(struct radeon_device *rdev)
5648 const struct cs_section_def *sect = NULL;
5649 const struct cs_extent_def *ext = NULL;
5651 if (rdev->rlc.cs_data == NULL)
5654 /* begin clear state */
5656 /* context control state */
5659 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5660 for (ext = sect->section; ext->extent != NULL; ++ext) {
5661 if (sect->id == SECT_CONTEXT)
5662 count += 2 + ext->reg_count;
5667 /* pa_sc_raster_config */
5669 /* end clear state */
5677 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
5680 const struct cs_section_def *sect = NULL;
5681 const struct cs_extent_def *ext = NULL;
5683 if (rdev->rlc.cs_data == NULL)
5688 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5689 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5691 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5692 buffer[count++] = cpu_to_le32(0x80000000);
5693 buffer[count++] = cpu_to_le32(0x80000000);
5695 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5696 for (ext = sect->section; ext->extent != NULL; ++ext) {
5697 if (sect->id == SECT_CONTEXT) {
5699 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
5700 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
5701 for (i = 0; i < ext->reg_count; i++)
5702 buffer[count++] = cpu_to_le32(ext->extent[i]);
5709 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5710 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
5711 switch (rdev->family) {
5714 buffer[count++] = cpu_to_le32(0x2a00126a);
5717 buffer[count++] = cpu_to_le32(0x0000124a);
5720 buffer[count++] = cpu_to_le32(0x00000082);
5723 buffer[count++] = cpu_to_le32(0x00000000);
5726 buffer[count++] = cpu_to_le32(0x00000000);
5730 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5731 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
5733 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
5734 buffer[count++] = cpu_to_le32(0);
5737 static void si_init_pg(struct radeon_device *rdev)
5739 if (rdev->pg_flags) {
5740 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {
5741 si_init_dma_pg(rdev);
5743 si_init_ao_cu_mask(rdev);
5744 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5745 si_init_gfx_cgpg(rdev);
5747 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5748 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5750 si_enable_dma_pg(rdev, true);
5751 si_enable_gfx_cgpg(rdev, true);
5753 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5754 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5758 static void si_fini_pg(struct radeon_device *rdev)
5760 if (rdev->pg_flags) {
5761 si_enable_dma_pg(rdev, false);
5762 si_enable_gfx_cgpg(rdev, false);
5769 void si_rlc_reset(struct radeon_device *rdev)
5771 u32 tmp = RREG32(GRBM_SOFT_RESET);
5773 tmp |= SOFT_RESET_RLC;
5774 WREG32(GRBM_SOFT_RESET, tmp);
5776 tmp &= ~SOFT_RESET_RLC;
5777 WREG32(GRBM_SOFT_RESET, tmp);
5781 static void si_rlc_stop(struct radeon_device *rdev)
5783 WREG32(RLC_CNTL, 0);
5785 si_enable_gui_idle_interrupt(rdev, false);
5787 si_wait_for_rlc_serdes(rdev);
5790 static void si_rlc_start(struct radeon_device *rdev)
5792 WREG32(RLC_CNTL, RLC_ENABLE);
5794 si_enable_gui_idle_interrupt(rdev, true);
5799 static bool si_lbpw_supported(struct radeon_device *rdev)
5803 /* Enable LBPW only for DDR3 */
5804 tmp = RREG32(MC_SEQ_MISC0);
5805 if ((tmp & 0xF0000000) == 0xB0000000)
5810 static void si_enable_lbpw(struct radeon_device *rdev, bool enable)
5814 tmp = RREG32(RLC_LB_CNTL);
5816 tmp |= LOAD_BALANCE_ENABLE;
5818 tmp &= ~LOAD_BALANCE_ENABLE;
5819 WREG32(RLC_LB_CNTL, tmp);
5822 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5823 WREG32(SPI_LB_CU_MASK, 0x00ff);
5827 static int si_rlc_resume(struct radeon_device *rdev)
5842 WREG32(RLC_RL_BASE, 0);
5843 WREG32(RLC_RL_SIZE, 0);
5844 WREG32(RLC_LB_CNTL, 0);
5845 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
5846 WREG32(RLC_LB_CNTR_INIT, 0);
5847 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5849 WREG32(RLC_MC_CNTL, 0);
5850 WREG32(RLC_UCODE_CNTL, 0);
5853 const struct rlc_firmware_header_v1_0 *hdr =
5854 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5855 u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5856 const __le32 *fw_data = (const __le32 *)
5857 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5859 radeon_ucode_print_rlc_hdr(&hdr->header);
5861 for (i = 0; i < fw_size; i++) {
5862 WREG32(RLC_UCODE_ADDR, i);
5863 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
5866 const __be32 *fw_data =
5867 (const __be32 *)rdev->rlc_fw->data;
5868 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
5869 WREG32(RLC_UCODE_ADDR, i);
5870 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
5873 WREG32(RLC_UCODE_ADDR, 0);
5875 si_enable_lbpw(rdev, si_lbpw_supported(rdev));
5882 static void si_enable_interrupts(struct radeon_device *rdev)
5884 u32 ih_cntl = RREG32(IH_CNTL);
5885 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5887 ih_cntl |= ENABLE_INTR;
5888 ih_rb_cntl |= IH_RB_ENABLE;
5889 WREG32(IH_CNTL, ih_cntl);
5890 WREG32(IH_RB_CNTL, ih_rb_cntl);
5891 rdev->ih.enabled = true;
5894 static void si_disable_interrupts(struct radeon_device *rdev)
5896 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5897 u32 ih_cntl = RREG32(IH_CNTL);
5899 ih_rb_cntl &= ~IH_RB_ENABLE;
5900 ih_cntl &= ~ENABLE_INTR;
5901 WREG32(IH_RB_CNTL, ih_rb_cntl);
5902 WREG32(IH_CNTL, ih_cntl);
5903 /* set rptr, wptr to 0 */
5904 WREG32(IH_RB_RPTR, 0);
5905 WREG32(IH_RB_WPTR, 0);
5906 rdev->ih.enabled = false;
5910 static void si_disable_interrupt_state(struct radeon_device *rdev)
5914 tmp = RREG32(CP_INT_CNTL_RING0) &
5915 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5916 WREG32(CP_INT_CNTL_RING0, tmp);
5917 WREG32(CP_INT_CNTL_RING1, 0);
5918 WREG32(CP_INT_CNTL_RING2, 0);
5919 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5920 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
5921 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5922 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
5923 WREG32(GRBM_INT_CNTL, 0);
5924 WREG32(SRBM_INT_CNTL, 0);
5925 if (rdev->num_crtc >= 2) {
5926 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5927 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
5929 if (rdev->num_crtc >= 4) {
5930 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
5931 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
5933 if (rdev->num_crtc >= 6) {
5934 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
5935 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
5938 if (rdev->num_crtc >= 2) {
5939 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5940 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
5942 if (rdev->num_crtc >= 4) {
5943 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
5944 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
5946 if (rdev->num_crtc >= 6) {
5947 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
5948 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
5951 if (!ASIC_IS_NODCE(rdev)) {
5952 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
5954 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5955 WREG32(DC_HPD1_INT_CONTROL, tmp);
5956 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5957 WREG32(DC_HPD2_INT_CONTROL, tmp);
5958 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5959 WREG32(DC_HPD3_INT_CONTROL, tmp);
5960 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5961 WREG32(DC_HPD4_INT_CONTROL, tmp);
5962 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5963 WREG32(DC_HPD5_INT_CONTROL, tmp);
5964 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5965 WREG32(DC_HPD6_INT_CONTROL, tmp);
5969 static int si_irq_init(struct radeon_device *rdev)
5973 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
5976 ret = r600_ih_ring_alloc(rdev);
5981 si_disable_interrupts(rdev);
5984 ret = si_rlc_resume(rdev);
5986 r600_ih_ring_fini(rdev);
5990 /* setup interrupt control */
5991 /* set dummy read address to ring address */
5992 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
5993 interrupt_cntl = RREG32(INTERRUPT_CNTL);
5994 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
5995 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
5997 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
5998 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
5999 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
6000 WREG32(INTERRUPT_CNTL, interrupt_cntl);
6002 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
6003 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
6005 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
6006 IH_WPTR_OVERFLOW_CLEAR |
6009 if (rdev->wb.enabled)
6010 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
6012 /* set the writeback address whether it's enabled or not */
6013 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
6014 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
6016 WREG32(IH_RB_CNTL, ih_rb_cntl);
6018 /* set rptr, wptr to 0 */
6019 WREG32(IH_RB_RPTR, 0);
6020 WREG32(IH_RB_WPTR, 0);
6022 /* Default settings for IH_CNTL (disabled at first) */
6023 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
6024 /* RPTR_REARM only works if msi's are enabled */
6025 if (rdev->msi_enabled)
6026 ih_cntl |= RPTR_REARM;
6027 WREG32(IH_CNTL, ih_cntl);
6029 /* force the active interrupt state to all disabled */
6030 si_disable_interrupt_state(rdev);
6032 pci_set_master(rdev->pdev);
6035 si_enable_interrupts(rdev);
6040 int si_irq_set(struct radeon_device *rdev)
6043 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
6044 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
6045 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
6046 u32 grbm_int_cntl = 0;
6047 u32 dma_cntl, dma_cntl1;
6048 u32 thermal_int = 0;
6050 if (!rdev->irq.installed) {
6051 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
6054 /* don't enable anything if the ih is disabled */
6055 if (!rdev->ih.enabled) {
6056 si_disable_interrupts(rdev);
6057 /* force the active interrupt state to all disabled */
6058 si_disable_interrupt_state(rdev);
6062 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6063 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6065 if (!ASIC_IS_NODCE(rdev)) {
6066 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6067 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6068 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6069 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6070 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6071 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6074 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6075 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6077 thermal_int = RREG32(CG_THERMAL_INT) &
6078 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6080 /* enable CP interrupts on all rings */
6081 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
6082 DRM_DEBUG("si_irq_set: sw int gfx\n");
6083 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
6085 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
6086 DRM_DEBUG("si_irq_set: sw int cp1\n");
6087 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
6089 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
6090 DRM_DEBUG("si_irq_set: sw int cp2\n");
6091 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
6093 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
6094 DRM_DEBUG("si_irq_set: sw int dma\n");
6095 dma_cntl |= TRAP_ENABLE;
6098 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
6099 DRM_DEBUG("si_irq_set: sw int dma1\n");
6100 dma_cntl1 |= TRAP_ENABLE;
6102 if (rdev->irq.crtc_vblank_int[0] ||
6103 atomic_read(&rdev->irq.pflip[0])) {
6104 DRM_DEBUG("si_irq_set: vblank 0\n");
6105 crtc1 |= VBLANK_INT_MASK;
6107 if (rdev->irq.crtc_vblank_int[1] ||
6108 atomic_read(&rdev->irq.pflip[1])) {
6109 DRM_DEBUG("si_irq_set: vblank 1\n");
6110 crtc2 |= VBLANK_INT_MASK;
6112 if (rdev->irq.crtc_vblank_int[2] ||
6113 atomic_read(&rdev->irq.pflip[2])) {
6114 DRM_DEBUG("si_irq_set: vblank 2\n");
6115 crtc3 |= VBLANK_INT_MASK;
6117 if (rdev->irq.crtc_vblank_int[3] ||
6118 atomic_read(&rdev->irq.pflip[3])) {
6119 DRM_DEBUG("si_irq_set: vblank 3\n");
6120 crtc4 |= VBLANK_INT_MASK;
6122 if (rdev->irq.crtc_vblank_int[4] ||
6123 atomic_read(&rdev->irq.pflip[4])) {
6124 DRM_DEBUG("si_irq_set: vblank 4\n");
6125 crtc5 |= VBLANK_INT_MASK;
6127 if (rdev->irq.crtc_vblank_int[5] ||
6128 atomic_read(&rdev->irq.pflip[5])) {
6129 DRM_DEBUG("si_irq_set: vblank 5\n");
6130 crtc6 |= VBLANK_INT_MASK;
6132 if (rdev->irq.hpd[0]) {
6133 DRM_DEBUG("si_irq_set: hpd 1\n");
6134 hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6136 if (rdev->irq.hpd[1]) {
6137 DRM_DEBUG("si_irq_set: hpd 2\n");
6138 hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6140 if (rdev->irq.hpd[2]) {
6141 DRM_DEBUG("si_irq_set: hpd 3\n");
6142 hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6144 if (rdev->irq.hpd[3]) {
6145 DRM_DEBUG("si_irq_set: hpd 4\n");
6146 hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6148 if (rdev->irq.hpd[4]) {
6149 DRM_DEBUG("si_irq_set: hpd 5\n");
6150 hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6152 if (rdev->irq.hpd[5]) {
6153 DRM_DEBUG("si_irq_set: hpd 6\n");
6154 hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6157 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
6158 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
6159 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
6161 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
6162 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
6164 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
6166 if (rdev->irq.dpm_thermal) {
6167 DRM_DEBUG("dpm thermal\n");
6168 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6171 if (rdev->num_crtc >= 2) {
6172 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
6173 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
6175 if (rdev->num_crtc >= 4) {
6176 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
6177 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
6179 if (rdev->num_crtc >= 6) {
6180 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
6181 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
6184 if (rdev->num_crtc >= 2) {
6185 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
6186 GRPH_PFLIP_INT_MASK);
6187 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
6188 GRPH_PFLIP_INT_MASK);
6190 if (rdev->num_crtc >= 4) {
6191 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
6192 GRPH_PFLIP_INT_MASK);
6193 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
6194 GRPH_PFLIP_INT_MASK);
6196 if (rdev->num_crtc >= 6) {
6197 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
6198 GRPH_PFLIP_INT_MASK);
6199 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
6200 GRPH_PFLIP_INT_MASK);
6203 if (!ASIC_IS_NODCE(rdev)) {
6204 WREG32(DC_HPD1_INT_CONTROL, hpd1);
6205 WREG32(DC_HPD2_INT_CONTROL, hpd2);
6206 WREG32(DC_HPD3_INT_CONTROL, hpd3);
6207 WREG32(DC_HPD4_INT_CONTROL, hpd4);
6208 WREG32(DC_HPD5_INT_CONTROL, hpd5);
6209 WREG32(DC_HPD6_INT_CONTROL, hpd6);
6212 WREG32(CG_THERMAL_INT, thermal_int);
6215 RREG32(SRBM_STATUS);
6220 static inline void si_irq_ack(struct radeon_device *rdev)
6224 if (ASIC_IS_NODCE(rdev))
6227 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
6228 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
6229 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
6230 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
6231 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
6232 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
6233 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
6234 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
6235 if (rdev->num_crtc >= 4) {
6236 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
6237 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
6239 if (rdev->num_crtc >= 6) {
6240 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
6241 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
6244 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
6245 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6246 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
6247 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6248 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
6249 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6250 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
6251 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6252 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
6253 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6254 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
6255 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
6257 if (rdev->num_crtc >= 4) {
6258 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
6259 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6260 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
6261 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6262 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
6263 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
6264 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
6265 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
6266 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
6267 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
6268 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
6269 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
6272 if (rdev->num_crtc >= 6) {
6273 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
6274 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6275 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
6276 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6277 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
6278 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
6279 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
6280 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
6281 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
6282 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
6283 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
6284 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
6287 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
6288 tmp = RREG32(DC_HPD1_INT_CONTROL);
6289 tmp |= DC_HPDx_INT_ACK;
6290 WREG32(DC_HPD1_INT_CONTROL, tmp);
6292 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
6293 tmp = RREG32(DC_HPD2_INT_CONTROL);
6294 tmp |= DC_HPDx_INT_ACK;
6295 WREG32(DC_HPD2_INT_CONTROL, tmp);
6297 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
6298 tmp = RREG32(DC_HPD3_INT_CONTROL);
6299 tmp |= DC_HPDx_INT_ACK;
6300 WREG32(DC_HPD3_INT_CONTROL, tmp);
6302 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
6303 tmp = RREG32(DC_HPD4_INT_CONTROL);
6304 tmp |= DC_HPDx_INT_ACK;
6305 WREG32(DC_HPD4_INT_CONTROL, tmp);
6307 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
6308 tmp = RREG32(DC_HPD5_INT_CONTROL);
6309 tmp |= DC_HPDx_INT_ACK;
6310 WREG32(DC_HPD5_INT_CONTROL, tmp);
6312 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
6313 tmp = RREG32(DC_HPD6_INT_CONTROL);
6314 tmp |= DC_HPDx_INT_ACK;
6315 WREG32(DC_HPD6_INT_CONTROL, tmp);
6318 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) {
6319 tmp = RREG32(DC_HPD1_INT_CONTROL);
6320 tmp |= DC_HPDx_RX_INT_ACK;
6321 WREG32(DC_HPD1_INT_CONTROL, tmp);
6323 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) {
6324 tmp = RREG32(DC_HPD2_INT_CONTROL);
6325 tmp |= DC_HPDx_RX_INT_ACK;
6326 WREG32(DC_HPD2_INT_CONTROL, tmp);
6328 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {
6329 tmp = RREG32(DC_HPD3_INT_CONTROL);
6330 tmp |= DC_HPDx_RX_INT_ACK;
6331 WREG32(DC_HPD3_INT_CONTROL, tmp);
6333 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {
6334 tmp = RREG32(DC_HPD4_INT_CONTROL);
6335 tmp |= DC_HPDx_RX_INT_ACK;
6336 WREG32(DC_HPD4_INT_CONTROL, tmp);
6338 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {
6339 tmp = RREG32(DC_HPD5_INT_CONTROL);
6340 tmp |= DC_HPDx_RX_INT_ACK;
6341 WREG32(DC_HPD5_INT_CONTROL, tmp);
6343 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
6344 tmp = RREG32(DC_HPD6_INT_CONTROL);
6345 tmp |= DC_HPDx_RX_INT_ACK;
6346 WREG32(DC_HPD6_INT_CONTROL, tmp);
6350 static void si_irq_disable(struct radeon_device *rdev)
6352 si_disable_interrupts(rdev);
6353 /* Wait and acknowledge irq */
6356 si_disable_interrupt_state(rdev);
6359 static void si_irq_suspend(struct radeon_device *rdev)
6361 si_irq_disable(rdev);
6365 static void si_irq_fini(struct radeon_device *rdev)
6367 si_irq_suspend(rdev);
6368 r600_ih_ring_fini(rdev);
6371 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
6375 if (rdev->wb.enabled)
6376 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
6378 wptr = RREG32(IH_RB_WPTR);
6380 if (wptr & RB_OVERFLOW) {
6381 wptr &= ~RB_OVERFLOW;
6382 /* When a ring buffer overflow happen start parsing interrupt
6383 * from the last not overwritten vector (wptr + 16). Hopefully
6384 * this should allow us to catchup.
6386 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
6387 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
6388 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
6389 tmp = RREG32(IH_RB_CNTL);
6390 tmp |= IH_WPTR_OVERFLOW_CLEAR;
6391 WREG32(IH_RB_CNTL, tmp);
6393 return (wptr & rdev->ih.ptr_mask);
6397 * Each IV ring entry is 128 bits:
6398 * [7:0] - interrupt source id
6400 * [59:32] - interrupt source data
6401 * [63:60] - reserved
6404 * [127:80] - reserved
6406 irqreturn_t si_irq_process(struct radeon_device *rdev)
6410 u32 src_id, src_data, ring_id;
6412 bool queue_hotplug = false;
6413 bool queue_dp = false;
6414 bool queue_thermal = false;
6417 if (!rdev->ih.enabled || rdev->shutdown)
6420 wptr = si_get_ih_wptr(rdev);
6423 /* is somebody else already processing irqs? */
6424 if (atomic_xchg(&rdev->ih.lock, 1))
6427 rptr = rdev->ih.rptr;
6428 DRM_DEBUG_VBLANK("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
6430 /* Order reading of wptr vs. reading of IH ring data */
6433 /* display interrupts */
6436 while (rptr != wptr) {
6437 /* wptr/rptr are in bytes! */
6438 ring_index = rptr / 4;
6439 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
6440 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
6441 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
6444 case 1: /* D1 vblank/vline */
6446 case 0: /* D1 vblank */
6447 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT))
6448 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6450 if (rdev->irq.crtc_vblank_int[0]) {
6451 drm_handle_vblank(rdev->ddev, 0);
6452 rdev->pm.vblank_sync = true;
6453 wake_up(&rdev->irq.vblank_queue);
6455 if (atomic_read(&rdev->irq.pflip[0]))
6456 radeon_crtc_handle_vblank(rdev, 0);
6457 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
6458 DRM_DEBUG_VBLANK("IH: D1 vblank\n");
6461 case 1: /* D1 vline */
6462 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT))
6463 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6465 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
6466 DRM_DEBUG_VBLANK("IH: D1 vline\n");
6470 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6474 case 2: /* D2 vblank/vline */
6476 case 0: /* D2 vblank */
6477 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
6478 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6480 if (rdev->irq.crtc_vblank_int[1]) {
6481 drm_handle_vblank(rdev->ddev, 1);
6482 rdev->pm.vblank_sync = true;
6483 wake_up(&rdev->irq.vblank_queue);
6485 if (atomic_read(&rdev->irq.pflip[1]))
6486 radeon_crtc_handle_vblank(rdev, 1);
6487 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
6488 DRM_DEBUG_VBLANK("IH: D2 vblank\n");
6491 case 1: /* D2 vline */
6492 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT))
6493 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6495 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
6496 DRM_DEBUG_VBLANK("IH: D2 vline\n");
6500 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6504 case 3: /* D3 vblank/vline */
6506 case 0: /* D3 vblank */
6507 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
6508 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6510 if (rdev->irq.crtc_vblank_int[2]) {
6511 drm_handle_vblank(rdev->ddev, 2);
6512 rdev->pm.vblank_sync = true;
6513 wake_up(&rdev->irq.vblank_queue);
6515 if (atomic_read(&rdev->irq.pflip[2]))
6516 radeon_crtc_handle_vblank(rdev, 2);
6517 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
6518 DRM_DEBUG_VBLANK("IH: D3 vblank\n");
6521 case 1: /* D3 vline */
6522 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
6523 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6525 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
6526 DRM_DEBUG_VBLANK("IH: D3 vline\n");
6530 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6534 case 4: /* D4 vblank/vline */
6536 case 0: /* D4 vblank */
6537 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
6538 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6540 if (rdev->irq.crtc_vblank_int[3]) {
6541 drm_handle_vblank(rdev->ddev, 3);
6542 rdev->pm.vblank_sync = true;
6543 wake_up(&rdev->irq.vblank_queue);
6545 if (atomic_read(&rdev->irq.pflip[3]))
6546 radeon_crtc_handle_vblank(rdev, 3);
6547 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
6548 DRM_DEBUG_VBLANK("IH: D4 vblank\n");
6551 case 1: /* D4 vline */
6552 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
6553 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6555 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
6556 DRM_DEBUG_VBLANK("IH: D4 vline\n");
6560 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6564 case 5: /* D5 vblank/vline */
6566 case 0: /* D5 vblank */
6567 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
6568 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6570 if (rdev->irq.crtc_vblank_int[4]) {
6571 drm_handle_vblank(rdev->ddev, 4);
6572 rdev->pm.vblank_sync = true;
6573 wake_up(&rdev->irq.vblank_queue);
6575 if (atomic_read(&rdev->irq.pflip[4]))
6576 radeon_crtc_handle_vblank(rdev, 4);
6577 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
6578 DRM_DEBUG_VBLANK("IH: D5 vblank\n");
6581 case 1: /* D5 vline */
6582 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
6583 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6585 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
6586 DRM_DEBUG_VBLANK("IH: D5 vline\n");
6590 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6594 case 6: /* D6 vblank/vline */
6596 case 0: /* D6 vblank */
6597 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
6598 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6600 if (rdev->irq.crtc_vblank_int[5]) {
6601 drm_handle_vblank(rdev->ddev, 5);
6602 rdev->pm.vblank_sync = true;
6603 wake_up(&rdev->irq.vblank_queue);
6605 if (atomic_read(&rdev->irq.pflip[5]))
6606 radeon_crtc_handle_vblank(rdev, 5);
6607 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
6608 DRM_DEBUG_VBLANK("IH: D6 vblank\n");
6611 case 1: /* D6 vline */
6612 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
6613 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6615 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
6616 DRM_DEBUG_VBLANK("IH: D6 vline\n");
6620 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6624 case 8: /* D1 page flip */
6625 case 10: /* D2 page flip */
6626 case 12: /* D3 page flip */
6627 case 14: /* D4 page flip */
6628 case 16: /* D5 page flip */
6629 case 18: /* D6 page flip */
6630 DRM_DEBUG_VBLANK("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
6631 if (radeon_use_pflipirq > 0)
6632 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
6634 case 42: /* HPD hotplug */
6637 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT))
6638 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6640 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
6641 queue_hotplug = true;
6642 DRM_DEBUG("IH: HPD1\n");
6646 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT))
6647 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6649 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
6650 queue_hotplug = true;
6651 DRM_DEBUG("IH: HPD2\n");
6655 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT))
6656 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6658 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
6659 queue_hotplug = true;
6660 DRM_DEBUG("IH: HPD3\n");
6664 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT))
6665 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6667 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
6668 queue_hotplug = true;
6669 DRM_DEBUG("IH: HPD4\n");
6673 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT))
6674 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6676 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
6677 queue_hotplug = true;
6678 DRM_DEBUG("IH: HPD5\n");
6682 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT))
6683 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6685 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
6686 queue_hotplug = true;
6687 DRM_DEBUG("IH: HPD6\n");
6691 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT))
6692 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6694 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT;
6696 DRM_DEBUG("IH: HPD_RX 1\n");
6700 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT))
6701 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6703 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
6705 DRM_DEBUG("IH: HPD_RX 2\n");
6709 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
6710 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6712 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
6714 DRM_DEBUG("IH: HPD_RX 3\n");
6718 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
6719 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6721 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
6723 DRM_DEBUG("IH: HPD_RX 4\n");
6727 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
6728 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6730 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
6732 DRM_DEBUG("IH: HPD_RX 5\n");
6736 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
6737 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6739 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
6741 DRM_DEBUG("IH: HPD_RX 6\n");
6745 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6750 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
6751 WREG32(SRBM_INT_ACK, 0x1);
6754 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
6755 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
6759 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
6760 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
6761 /* reset addr and status */
6762 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
6763 if (addr == 0x0 && status == 0x0)
6765 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
6766 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
6768 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
6770 si_vm_decode_fault(rdev, status, addr);
6772 case 176: /* RINGID0 CP_INT */
6773 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6775 case 177: /* RINGID1 CP_INT */
6776 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6778 case 178: /* RINGID2 CP_INT */
6779 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6781 case 181: /* CP EOP event */
6782 DRM_DEBUG("IH: CP EOP\n");
6785 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6788 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6791 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6795 case 224: /* DMA trap event */
6796 DRM_DEBUG("IH: DMA trap\n");
6797 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
6799 case 230: /* thermal low to high */
6800 DRM_DEBUG("IH: thermal low to high\n");
6801 rdev->pm.dpm.thermal.high_to_low = false;
6802 queue_thermal = true;
6804 case 231: /* thermal high to low */
6805 DRM_DEBUG("IH: thermal high to low\n");
6806 rdev->pm.dpm.thermal.high_to_low = true;
6807 queue_thermal = true;
6809 case 233: /* GUI IDLE */
6810 DRM_DEBUG("IH: GUI idle\n");
6812 case 244: /* DMA trap event */
6813 DRM_DEBUG("IH: DMA1 trap\n");
6814 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
6817 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6821 /* wptr/rptr are in bytes! */
6823 rptr &= rdev->ih.ptr_mask;
6824 WREG32(IH_RB_RPTR, rptr);
6827 schedule_work(&rdev->dp_work);
6829 schedule_delayed_work(&rdev->hotplug_work, 0);
6830 if (queue_thermal && rdev->pm.dpm_enabled)
6831 schedule_work(&rdev->pm.dpm.thermal.work);
6832 rdev->ih.rptr = rptr;
6833 atomic_set(&rdev->ih.lock, 0);
6835 /* make sure wptr hasn't changed while processing */
6836 wptr = si_get_ih_wptr(rdev);
6844 * startup/shutdown callbacks
6846 static void si_uvd_init(struct radeon_device *rdev)
6853 r = radeon_uvd_init(rdev);
6855 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
6857 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
6858 * to early fails uvd_v2_2_resume() and thus nothing happens
6859 * there. So it is pointless to try to go through that code
6860 * hence why we disable uvd here.
6865 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
6866 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
6869 static void si_uvd_start(struct radeon_device *rdev)
6876 r = uvd_v2_2_resume(rdev);
6878 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
6881 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
6883 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
6889 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
6892 static void si_uvd_resume(struct radeon_device *rdev)
6894 struct radeon_ring *ring;
6897 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
6900 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
6901 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, RADEON_CP_PACKET2);
6903 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
6906 r = uvd_v1_0_init(rdev);
6908 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
6913 static void si_vce_init(struct radeon_device *rdev)
6920 r = radeon_vce_init(rdev);
6922 dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
6924 * At this point rdev->vce.vcpu_bo is NULL which trickles down
6925 * to early fails si_vce_start() and thus nothing happens
6926 * there. So it is pointless to try to go through that code
6927 * hence why we disable vce here.
6932 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
6933 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
6934 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
6935 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
6938 static void si_vce_start(struct radeon_device *rdev)
6945 r = radeon_vce_resume(rdev);
6947 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
6950 r = vce_v1_0_resume(rdev);
6952 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
6955 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
6957 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
6960 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
6962 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
6968 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
6969 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
6972 static void si_vce_resume(struct radeon_device *rdev)
6974 struct radeon_ring *ring;
6977 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
6980 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
6981 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
6983 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
6986 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
6987 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
6989 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
6992 r = vce_v1_0_init(rdev);
6994 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
6999 static int si_startup(struct radeon_device *rdev)
7001 struct radeon_ring *ring;
7004 /* enable pcie gen2/3 link */
7005 si_pcie_gen3_enable(rdev);
7007 si_program_aspm(rdev);
7009 /* scratch needs to be initialized before MC */
7010 r = r600_vram_scratch_init(rdev);
7014 si_mc_program(rdev);
7016 if (!rdev->pm.dpm_enabled) {
7017 r = si_mc_load_microcode(rdev);
7019 DRM_ERROR("Failed to load MC firmware!\n");
7024 r = si_pcie_gart_enable(rdev);
7029 /* allocate rlc buffers */
7030 if (rdev->family == CHIP_VERDE) {
7031 rdev->rlc.reg_list = verde_rlc_save_restore_register_list;
7032 rdev->rlc.reg_list_size =
7033 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
7035 rdev->rlc.cs_data = si_cs_data;
7036 r = sumo_rlc_init(rdev);
7038 DRM_ERROR("Failed to init rlc BOs!\n");
7042 /* allocate wb buffer */
7043 r = radeon_wb_init(rdev);
7047 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
7049 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7053 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
7055 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7059 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
7061 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7065 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
7067 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
7071 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
7073 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
7081 if (!rdev->irq.installed) {
7082 r = radeon_irq_kms_init(rdev);
7087 r = si_irq_init(rdev);
7089 DRM_ERROR("radeon: IH init failed (%d).\n", r);
7090 radeon_irq_kms_fini(rdev);
7095 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7096 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
7101 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7102 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
7107 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7108 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
7113 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7114 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
7115 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
7119 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7120 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
7121 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
7125 r = si_cp_load_microcode(rdev);
7128 r = si_cp_resume(rdev);
7132 r = cayman_dma_resume(rdev);
7136 si_uvd_resume(rdev);
7137 si_vce_resume(rdev);
7139 r = radeon_ib_pool_init(rdev);
7141 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
7145 r = radeon_vm_manager_init(rdev);
7147 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
7151 r = radeon_audio_init(rdev);
7158 int si_resume(struct radeon_device *rdev)
7162 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
7163 * posting will perform necessary task to bring back GPU into good
7167 atom_asic_init(rdev->mode_info.atom_context);
7169 /* init golden registers */
7170 si_init_golden_registers(rdev);
7172 if (rdev->pm.pm_method == PM_METHOD_DPM)
7173 radeon_pm_resume(rdev);
7175 rdev->accel_working = true;
7176 r = si_startup(rdev);
7178 DRM_ERROR("si startup failed on resume\n");
7179 rdev->accel_working = false;
7187 int si_suspend(struct radeon_device *rdev)
7189 radeon_pm_suspend(rdev);
7190 radeon_audio_fini(rdev);
7191 radeon_vm_manager_fini(rdev);
7192 si_cp_enable(rdev, false);
7193 cayman_dma_stop(rdev);
7194 if (rdev->has_uvd) {
7195 uvd_v1_0_fini(rdev);
7196 radeon_uvd_suspend(rdev);
7199 radeon_vce_suspend(rdev);
7202 si_irq_suspend(rdev);
7203 radeon_wb_disable(rdev);
7204 si_pcie_gart_disable(rdev);
7208 /* Plan is to move initialization in that function and use
7209 * helper function so that radeon_device_init pretty much
7210 * do nothing more than calling asic specific function. This
7211 * should also allow to remove a bunch of callback function
7214 int si_init(struct radeon_device *rdev)
7216 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7220 if (!radeon_get_bios(rdev)) {
7221 if (ASIC_IS_AVIVO(rdev))
7224 /* Must be an ATOMBIOS */
7225 if (!rdev->is_atom_bios) {
7226 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
7229 r = radeon_atombios_init(rdev);
7233 /* Post card if necessary */
7234 if (!radeon_card_posted(rdev)) {
7236 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
7239 DRM_INFO("GPU not posted. posting now...\n");
7240 atom_asic_init(rdev->mode_info.atom_context);
7242 /* init golden registers */
7243 si_init_golden_registers(rdev);
7244 /* Initialize scratch registers */
7245 si_scratch_init(rdev);
7246 /* Initialize surface registers */
7247 radeon_surface_init(rdev);
7248 /* Initialize clocks */
7249 radeon_get_clock_info(rdev->ddev);
7252 r = radeon_fence_driver_init(rdev);
7256 /* initialize memory controller */
7257 r = si_mc_init(rdev);
7260 /* Memory manager */
7261 r = radeon_bo_init(rdev);
7265 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
7266 !rdev->rlc_fw || !rdev->mc_fw) {
7267 r = si_init_microcode(rdev);
7269 DRM_ERROR("Failed to load firmware!\n");
7274 /* Initialize power management */
7275 radeon_pm_init(rdev);
7277 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7278 ring->ring_obj = NULL;
7279 r600_ring_init(rdev, ring, 1024 * 1024);
7281 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7282 ring->ring_obj = NULL;
7283 r600_ring_init(rdev, ring, 1024 * 1024);
7285 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7286 ring->ring_obj = NULL;
7287 r600_ring_init(rdev, ring, 1024 * 1024);
7289 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7290 ring->ring_obj = NULL;
7291 r600_ring_init(rdev, ring, 64 * 1024);
7293 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7294 ring->ring_obj = NULL;
7295 r600_ring_init(rdev, ring, 64 * 1024);
7300 rdev->ih.ring_obj = NULL;
7301 r600_ih_ring_init(rdev, 64 * 1024);
7303 r = r600_pcie_gart_init(rdev);
7307 rdev->accel_working = true;
7308 r = si_startup(rdev);
7310 dev_err(rdev->dev, "disabling GPU acceleration\n");
7312 cayman_dma_fini(rdev);
7314 sumo_rlc_fini(rdev);
7315 radeon_wb_fini(rdev);
7316 radeon_ib_pool_fini(rdev);
7317 radeon_vm_manager_fini(rdev);
7318 radeon_irq_kms_fini(rdev);
7319 si_pcie_gart_fini(rdev);
7320 rdev->accel_working = false;
7323 /* Don't start up if the MC ucode is missing.
7324 * The default clocks and voltages before the MC ucode
7325 * is loaded are not suffient for advanced operations.
7328 DRM_ERROR("radeon: MC ucode required for NI+.\n");
7335 void si_fini(struct radeon_device *rdev)
7337 radeon_pm_fini(rdev);
7339 cayman_dma_fini(rdev);
7343 sumo_rlc_fini(rdev);
7344 radeon_wb_fini(rdev);
7345 radeon_vm_manager_fini(rdev);
7346 radeon_ib_pool_fini(rdev);
7347 radeon_irq_kms_fini(rdev);
7348 if (rdev->has_uvd) {
7349 uvd_v1_0_fini(rdev);
7350 radeon_uvd_fini(rdev);
7353 radeon_vce_fini(rdev);
7354 si_pcie_gart_fini(rdev);
7355 r600_vram_scratch_fini(rdev);
7356 radeon_gem_fini(rdev);
7357 radeon_fence_driver_fini(rdev);
7358 radeon_bo_fini(rdev);
7359 radeon_atombios_fini(rdev);
7360 si_fini_microcode(rdev);
7366 * si_get_gpu_clock_counter - return GPU clock counter snapshot
7368 * @rdev: radeon_device pointer
7370 * Fetches a GPU clock counter snapshot (SI).
7371 * Returns the 64 bit clock counter snapshot.
7373 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
7377 mutex_lock(&rdev->gpu_clock_mutex);
7378 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
7379 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
7380 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
7381 mutex_unlock(&rdev->gpu_clock_mutex);
7385 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
7387 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
7390 /* bypass vclk and dclk with bclk */
7391 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7392 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
7393 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7395 /* put PLL in bypass mode */
7396 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
7398 if (!vclk || !dclk) {
7399 /* keep the Bypass mode */
7403 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
7404 16384, 0x03FFFFFF, 0, 128, 5,
7405 &fb_div, &vclk_div, &dclk_div);
7409 /* set RESET_ANTI_MUX to 0 */
7410 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7412 /* set VCO_MODE to 1 */
7413 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
7415 /* disable sleep mode */
7416 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
7418 /* deassert UPLL_RESET */
7419 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7423 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7427 /* assert UPLL_RESET again */
7428 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
7430 /* disable spread spectrum. */
7431 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7433 /* set feedback divider */
7434 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
7436 /* set ref divider to 0 */
7437 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
7439 if (fb_div < 307200)
7440 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
7442 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
7444 /* set PDIV_A and PDIV_B */
7445 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7446 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
7447 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
7449 /* give the PLL some time to settle */
7452 /* deassert PLL_RESET */
7453 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7457 /* switch from bypass mode to normal mode */
7458 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
7460 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7464 /* switch VCLK and DCLK selection */
7465 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7466 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
7467 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7474 static void si_pcie_gen3_enable(struct radeon_device *rdev)
7476 struct pci_dev *root = rdev->pdev->bus->self;
7477 int bridge_pos, gpu_pos;
7478 u32 speed_cntl, mask, current_data_rate;
7483 if (pci_is_root_bus(rdev->pdev->bus))
7487 if (radeon_pcie_gen2 == 0)
7490 if (rdev->flags & RADEON_IS_IGP)
7493 if (!(rdev->flags & RADEON_IS_PCIE))
7496 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
7500 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
7503 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7504 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
7505 LC_CURRENT_DATA_RATE_SHIFT;
7506 if (mask & DRM_PCIE_SPEED_80) {
7507 if (current_data_rate == 2) {
7508 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
7511 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
7512 } else if (mask & DRM_PCIE_SPEED_50) {
7513 if (current_data_rate == 1) {
7514 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
7517 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
7520 bridge_pos = pci_pcie_cap(root);
7524 gpu_pos = pci_pcie_cap(rdev->pdev);
7528 if (mask & DRM_PCIE_SPEED_80) {
7529 /* re-try equalization if gen3 is not already enabled */
7530 if (current_data_rate != 2) {
7531 u16 bridge_cfg, gpu_cfg;
7532 u16 bridge_cfg2, gpu_cfg2;
7533 u32 max_lw, current_lw, tmp;
7535 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7536 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7538 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
7539 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7541 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
7542 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7544 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
7545 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
7546 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
7548 if (current_lw < max_lw) {
7549 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7550 if (tmp & LC_RENEGOTIATION_SUPPORT) {
7551 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
7552 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
7553 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
7554 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
7558 for (i = 0; i < 10; i++) {
7560 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
7561 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
7564 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7565 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7567 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
7568 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
7570 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7571 tmp |= LC_SET_QUIESCE;
7572 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7574 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7576 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7581 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
7582 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7583 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
7584 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7586 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
7587 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7588 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
7589 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7592 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
7593 tmp16 &= ~((1 << 4) | (7 << 9));
7594 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
7595 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
7597 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7598 tmp16 &= ~((1 << 4) | (7 << 9));
7599 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
7600 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7602 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7603 tmp &= ~LC_SET_QUIESCE;
7604 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7609 /* set the link speed */
7610 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
7611 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
7612 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7614 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7616 if (mask & DRM_PCIE_SPEED_80)
7617 tmp16 |= 3; /* gen3 */
7618 else if (mask & DRM_PCIE_SPEED_50)
7619 tmp16 |= 2; /* gen2 */
7621 tmp16 |= 1; /* gen1 */
7622 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7624 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7625 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
7626 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7628 for (i = 0; i < rdev->usec_timeout; i++) {
7629 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7630 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
7636 static void si_program_aspm(struct radeon_device *rdev)
7639 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
7641 bool disable_clkreq = false;
7644 if (radeon_aspm == 0)
7647 if (!(rdev->flags & RADEON_IS_PCIE))
7650 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7651 data &= ~LC_XMIT_N_FTS_MASK;
7652 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
7654 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
7656 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
7657 data |= LC_GO_TO_RECOVERY;
7659 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
7661 orig = data = RREG32_PCIE(PCIE_P_CNTL);
7662 data |= P_IGNORE_EDB_ERR;
7664 WREG32_PCIE(PCIE_P_CNTL, data);
7666 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7667 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
7668 data |= LC_PMI_TO_L1_DIS;
7670 data |= LC_L0S_INACTIVITY(7);
7673 data |= LC_L1_INACTIVITY(7);
7674 data &= ~LC_PMI_TO_L1_DIS;
7676 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7678 if (!disable_plloff_in_l1) {
7679 bool clk_req_support;
7681 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7682 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7683 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7685 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7687 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7688 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7689 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7691 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7693 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7694 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7695 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7697 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7699 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7700 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7701 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7703 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7705 if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) {
7706 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7707 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7709 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7711 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7712 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7714 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7716 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2);
7717 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7719 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2, data);
7721 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3);
7722 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7724 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3, data);
7726 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7727 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7729 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7731 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7732 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7734 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7736 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2);
7737 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7739 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2, data);
7741 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3);
7742 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7744 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3, data);
7746 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7747 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
7748 data |= LC_DYN_LANES_PWR_STATE(3);
7750 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
7752 orig = data = RREG32_PIF_PHY0(PB0_PIF_CNTL);
7753 data &= ~LS2_EXIT_TIME_MASK;
7754 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7755 data |= LS2_EXIT_TIME(5);
7757 WREG32_PIF_PHY0(PB0_PIF_CNTL, data);
7759 orig = data = RREG32_PIF_PHY1(PB1_PIF_CNTL);
7760 data &= ~LS2_EXIT_TIME_MASK;
7761 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7762 data |= LS2_EXIT_TIME(5);
7764 WREG32_PIF_PHY1(PB1_PIF_CNTL, data);
7767 if (!disable_clkreq &&
7768 !pci_is_root_bus(rdev->pdev->bus)) {
7769 struct pci_dev *root = rdev->pdev->bus->self;
7772 clk_req_support = false;
7773 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
7774 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
7775 clk_req_support = true;
7777 clk_req_support = false;
7780 clk_req_support = false;
7783 if (clk_req_support) {
7784 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
7785 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
7787 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
7789 orig = data = RREG32(THM_CLK_CNTL);
7790 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
7791 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
7793 WREG32(THM_CLK_CNTL, data);
7795 orig = data = RREG32(MISC_CLK_CNTL);
7796 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
7797 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
7799 WREG32(MISC_CLK_CNTL, data);
7801 orig = data = RREG32(CG_CLKPIN_CNTL);
7802 data &= ~BCLK_AS_XCLK;
7804 WREG32(CG_CLKPIN_CNTL, data);
7806 orig = data = RREG32(CG_CLKPIN_CNTL_2);
7807 data &= ~FORCE_BIF_REFCLK_EN;
7809 WREG32(CG_CLKPIN_CNTL_2, data);
7811 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
7812 data &= ~MPLL_CLKOUT_SEL_MASK;
7813 data |= MPLL_CLKOUT_SEL(4);
7815 WREG32(MPLL_BYPASSCLK_SEL, data);
7817 orig = data = RREG32(SPLL_CNTL_MODE);
7818 data &= ~SPLL_REFCLK_SEL_MASK;
7820 WREG32(SPLL_CNTL_MODE, data);
7825 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7828 orig = data = RREG32_PCIE(PCIE_CNTL2);
7829 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
7831 WREG32_PCIE(PCIE_CNTL2, data);
7834 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7835 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
7836 data = RREG32_PCIE(PCIE_LC_STATUS1);
7837 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
7838 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7839 data &= ~LC_L0S_INACTIVITY_MASK;
7841 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7847 static int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev)
7851 /* make sure VCEPLL_CTLREQ is deasserted */
7852 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7856 /* assert UPLL_CTLREQ */
7857 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
7859 /* wait for CTLACK and CTLACK2 to get asserted */
7860 for (i = 0; i < 100; ++i) {
7861 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
7862 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
7867 /* deassert UPLL_CTLREQ */
7868 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7871 DRM_ERROR("Timeout setting UVD clocks!\n");
7878 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
7880 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0;
7883 /* bypass evclk and ecclk with bclk */
7884 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7885 EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1),
7886 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
7888 /* put PLL in bypass mode */
7889 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,
7890 ~VCEPLL_BYPASS_EN_MASK);
7892 if (!evclk || !ecclk) {
7893 /* keep the Bypass mode, put PLL to sleep */
7894 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7895 ~VCEPLL_SLEEP_MASK);
7899 r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000,
7900 16384, 0x03FFFFFF, 0, 128, 5,
7901 &fb_div, &evclk_div, &ecclk_div);
7905 /* set RESET_ANTI_MUX to 0 */
7906 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7908 /* set VCO_MODE to 1 */
7909 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,
7910 ~VCEPLL_VCO_MODE_MASK);
7912 /* toggle VCEPLL_SLEEP to 1 then back to 0 */
7913 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7914 ~VCEPLL_SLEEP_MASK);
7915 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);
7917 /* deassert VCEPLL_RESET */
7918 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7922 r = si_vce_send_vcepll_ctlreq(rdev);
7926 /* assert VCEPLL_RESET again */
7927 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);
7929 /* disable spread spectrum. */
7930 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7932 /* set feedback divider */
7933 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);
7935 /* set ref divider to 0 */
7936 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);
7938 /* set PDIV_A and PDIV_B */
7939 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7940 VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div),
7941 ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK));
7943 /* give the PLL some time to settle */
7946 /* deassert PLL_RESET */
7947 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7951 /* switch from bypass mode to normal mode */
7952 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);
7954 r = si_vce_send_vcepll_ctlreq(rdev);
7958 /* switch VCLK and DCLK selection */
7959 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7960 EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16),
7961 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
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