2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
168 * this code MUST be enabled here and in mpboot.s.
169 * it follows the very early stages of AP boot by placing values in CMOS ram.
170 * it NORMALLY will never be needed and thus the primitive method for enabling.
173 #if defined(CHECK_POINTS)
174 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
175 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
177 #define CHECK_INIT(D); \
178 CHECK_WRITE(0x34, (D)); \
179 CHECK_WRITE(0x35, (D)); \
180 CHECK_WRITE(0x36, (D)); \
181 CHECK_WRITE(0x37, (D)); \
182 CHECK_WRITE(0x38, (D)); \
183 CHECK_WRITE(0x39, (D));
185 #define CHECK_PRINT(S); \
186 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
195 #else /* CHECK_POINTS */
197 #define CHECK_INIT(D)
198 #define CHECK_PRINT(S)
200 #endif /* CHECK_POINTS */
203 * Values to send to the POST hardware.
205 #define MP_BOOTADDRESS_POST 0x10
206 #define MP_PROBE_POST 0x11
207 #define MPTABLE_PASS1_POST 0x12
209 #define MP_START_POST 0x13
210 #define MP_ENABLE_POST 0x14
211 #define MPTABLE_PASS2_POST 0x15
213 #define START_ALL_APS_POST 0x16
214 #define INSTALL_AP_TRAMP_POST 0x17
215 #define START_AP_POST 0x18
217 #define MP_ANNOUNCE_POST 0x19
219 static int need_hyperthreading_fixup;
220 static u_int logical_cpus;
221 u_int logical_cpus_mask;
223 static int madt_probe_test;
224 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
226 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227 int current_postcode;
229 /** XXX FIXME: what system files declare these??? */
230 extern struct region_descriptor r_gdt, r_idt;
232 int bsp_apic_ready = 0; /* flags useability of BSP apic */
233 int mp_naps; /* # of Applications processors */
234 int mp_nbusses; /* # of busses */
236 int mp_napics; /* # of IO APICs */
238 vm_offset_t cpu_apic_address;
240 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
241 u_int32_t *io_apic_versions;
245 u_int32_t cpu_apic_versions[MAXCPU];
247 extern int64_t tsc_offsets[];
249 extern u_long ebda_addr;
252 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
256 * APIC ID logical/physical mapping structures.
257 * We oversize these to simplify boot-time config.
259 int cpu_num_to_apic_id[NAPICID];
261 int io_num_to_apic_id[NAPICID];
263 int apic_id_to_logical[NAPICID];
265 /* AP uses this during bootstrap. Do not staticize. */
269 /* Hotwire a 0->4MB V==P mapping */
270 extern pt_entry_t *KPTphys;
273 * SMP page table page. Setup by locore to point to a page table
274 * page from which we allocate per-cpu privatespace areas io_apics,
278 #define IO_MAPPING_START_INDEX \
279 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
281 extern pt_entry_t *SMPpt;
282 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
284 struct pcb stoppcbs[MAXCPU];
287 * Local data and functions.
290 static u_int boot_address;
291 static u_int base_memory;
292 static int mp_finish;
294 static void mp_enable(u_int boot_addr);
296 static int mptable_probe(void);
297 static int mptable_search_sig(u_int32_t target, int count);
298 static void mptable_hyperthread_fixup(u_int id_mask);
299 static void mptable_pass1(struct mptable_pos *);
300 static int mptable_pass2(struct mptable_pos *);
301 static void mptable_default(int type);
302 static void mptable_fix(void);
303 static void mptable_map(struct mptable_pos *, vm_paddr_t);
304 static void mptable_unmap(struct mptable_pos *);
307 static void setup_apic_irq_mapping(void);
308 static int apic_int_is_bus_type(int intr, int bus_type);
310 static int start_all_aps(u_int boot_addr);
311 static void install_ap_tramp(u_int boot_addr);
312 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
314 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
315 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
316 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
319 * Calculate usable address in base memory for AP trampoline code.
322 mp_bootaddress(u_int basemem)
324 POSTCODE(MP_BOOTADDRESS_POST);
326 base_memory = basemem;
328 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
329 if ((base_memory - boot_address) < bootMP_size)
330 boot_address -= 4096; /* not enough, lower by 4k */
337 * Look for an Intel MP spec table (ie, SMP capable hardware).
346 * Make sure our SMPpt[] page table is big enough to hold all the
349 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
351 POSTCODE(MP_PROBE_POST);
353 /* see if EBDA exists */
354 if (ebda_addr != 0) {
355 /* search first 1K of EBDA */
356 target = (u_int32_t)ebda_addr;
357 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
360 /* last 1K of base memory, effective 'top of base' passed in */
361 target = (u_int32_t)(base_memory - 0x400);
362 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
366 /* search the BIOS */
367 target = (u_int32_t)BIOS_BASE;
368 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
377 * Startup the SMP processors.
382 POSTCODE(MP_START_POST);
383 mp_enable(boot_address);
388 * Print various information about the SMP system hardware and setup.
395 POSTCODE(MP_ANNOUNCE_POST);
397 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
398 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
399 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
400 kprintf(", at 0x%08x\n", cpu_apic_address);
401 for (x = 1; x <= mp_naps; ++x) {
402 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
403 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
404 kprintf(", at 0x%08x\n", cpu_apic_address);
408 for (x = 0; x < mp_napics; ++x) {
409 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
410 kprintf(", version: 0x%08x", io_apic_versions[x]);
411 kprintf(", at 0x%08x\n", io_apic_address[x]);
414 kprintf(" Warning: APIC I/O disabled\n");
419 * AP cpu's call this to sync up protected mode.
421 * WARNING! We must ensure that the cpu is sufficiently initialized to
422 * be able to use to the FP for our optimized bzero/bcopy code before
423 * we enter more mainstream C code.
425 * WARNING! %fs is not set up on entry. This routine sets up %fs.
431 int x, myid = bootAP;
433 struct mdglobaldata *md;
434 struct privatespace *ps;
436 ps = &CPU_prvspace[myid];
438 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
439 gdt_segs[GPROC0_SEL].ssd_base =
440 (int) &ps->mdglobaldata.gd_common_tss;
441 ps->mdglobaldata.mi.gd_prvspace = ps;
443 for (x = 0; x < NGDT; x++) {
444 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
447 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
448 r_gdt.rd_base = (int) &gdt[myid * NGDT];
449 lgdt(&r_gdt); /* does magic intra-segment return */
454 mdcpu->gd_currentldt = _default_ldt;
456 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
457 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
459 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
461 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
462 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
463 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
464 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
465 md->gd_common_tssd = *md->gd_tss_gdt;
469 * Set to a known state:
470 * Set by mpboot.s: CR0_PG, CR0_PE
471 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
474 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
476 pmap_set_opt(); /* PSE/4MB pages, etc */
478 /* set up CPU registers and state */
481 /* set up FPU state on the AP */
482 npxinit(__INITIAL_NPXCW__);
484 /* set up SSE registers */
488 /*******************************************************************
489 * local functions and data
493 * start the SMP system
496 mp_enable(u_int boot_addr)
503 vm_paddr_t mpfps_paddr;
505 POSTCODE(MP_ENABLE_POST);
510 mpfps_paddr = mptable_probe();
513 struct mptable_pos mpt;
515 mptable_map(&mpt, mpfps_paddr);
518 * We can safely map physical memory into SMPpt after
519 * mptable_pass1() completes.
523 if (cpu_apic_address == 0)
524 panic("mp_enable: no local apic (mptable)!\n");
527 * Examine the MP table for needed info
529 x = mptable_pass2(&mpt);
533 /* Local apic is mapped on last page */
534 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
535 pmap_get_pgeflag() | (cpu_apic_address & PG_FRAME));
538 * Can't process default configs till the
539 * CPU APIC is pmapped
544 /* Post scan cleanup */
547 vm_paddr_t madt_paddr;
550 madt_paddr = madt_probe();
552 panic("mp_enable: madt_probe failed\n");
554 cpu_apic_address = madt_pass1(madt_paddr);
555 if (cpu_apic_address == 0)
556 panic("mp_enable: no local apic (madt)!\n");
558 /* Local apic is mapped on last page */
559 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
560 pmap_get_pgeflag() | (cpu_apic_address & PG_FRAME));
562 bsp_apic_id = (lapic.id & 0xff000000) >> 24;
563 if (madt_pass2(madt_paddr, bsp_apic_id))
564 panic("mp_enable: madt_pass2 failed\n");
569 setup_apic_irq_mapping();
571 /* fill the LOGICAL io_apic_versions table */
572 for (apic = 0; apic < mp_napics; ++apic) {
573 ux = io_apic_read(apic, IOAPIC_VER);
574 io_apic_versions[apic] = ux;
575 io_apic_set_id(apic, IO_TO_ID(apic));
578 /* program each IO APIC in the system */
579 for (apic = 0; apic < mp_napics; ++apic)
580 if (io_apic_setup(apic) < 0)
581 panic("IO APIC setup failure");
586 * These are required for SMP operation
589 /* install a 'Spurious INTerrupt' vector */
590 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
593 /* install an inter-CPU IPI for TLB invalidation */
594 setidt(XINVLTLB_OFFSET, Xinvltlb,
595 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
597 /* install an inter-CPU IPI for IPIQ messaging */
598 setidt(XIPIQ_OFFSET, Xipiq,
599 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
601 /* install a timer vector */
602 setidt(XTIMER_OFFSET, Xtimer,
603 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
605 /* install an inter-CPU IPI for CPU stop/restart */
606 setidt(XCPUSTOP_OFFSET, Xcpustop,
607 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
609 /* start each Application Processor */
610 start_all_aps(boot_addr);
615 * look for the MP spec signature
618 /* string defined by the Intel MP Spec as identifying the MP table */
619 #define MP_SIG 0x5f504d5f /* _MP_ */
620 #define NEXT(X) ((X) += 4)
622 mptable_search_sig(u_int32_t target, int count)
628 KKASSERT(target != 0);
630 map_size = count * sizeof(u_int32_t);
631 addr = pmap_mapdev((vm_paddr_t)target, map_size);
634 for (x = 0; x < count; NEXT(x)) {
635 if (addr[x] == MP_SIG) {
636 /* make array index a byte index */
637 ret = target + (x * sizeof(u_int32_t));
642 pmap_unmapdev((vm_offset_t)addr, map_size);
647 static basetable_entry basetable_entry_types[] =
649 {0, 20, "Processor"},
656 typedef struct BUSDATA {
658 enum busTypes bus_type;
661 typedef struct INTDATA {
671 typedef struct BUSTYPENAME {
676 static bus_type_name bus_type_table[] =
682 {UNKNOWN_BUSTYPE, "---"},
685 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
687 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
696 {UNKNOWN_BUSTYPE, "---"}
698 /* from MP spec v1.4, table 5-1 */
699 static int default_data[7][5] =
701 /* nbus, id0, type0, id1, type1 */
702 {1, 0, ISA, 255, 255},
703 {1, 0, EISA, 255, 255},
704 {1, 0, EISA, 255, 255},
705 {1, 0, MCA, 255, 255},
707 {2, 0, EISA, 1, PCI},
713 static bus_datum *bus_data;
716 /* the IO INT data, one entry per possible APIC INTerrupt */
717 static io_int *io_apic_ints;
721 static int processor_entry (proc_entry_ptr entry, int cpu);
722 static int bus_entry (bus_entry_ptr entry, int bus);
724 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
725 static int int_entry (int_entry_ptr entry, int intr);
727 static int lookup_bus_type (char *name);
731 * 1st pass on motherboard's Intel MP specification table.
734 * cpu_apic_address (common to all CPUs)
740 * need_hyperthreading_fixup
744 mptable_pass1(struct mptable_pos *mpt)
757 POSTCODE(MPTABLE_PASS1_POST);
760 KKASSERT(fps != NULL);
763 /* clear various tables */
764 for (x = 0; x < NAPICID; ++x) {
765 io_apic_address[x] = ~0; /* IO APIC address table */
769 /* init everything to empty */
778 /* check for use of 'default' configuration */
779 if (fps->mpfb1 != 0) {
780 /* use default addresses */
781 cpu_apic_address = DEFAULT_APIC_BASE;
783 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
786 /* fill in with defaults */
787 mp_naps = 2; /* includes BSP */
788 mp_nbusses = default_data[fps->mpfb1 - 1][0];
797 panic("MP Configuration Table Header MISSING!");
799 cpu_apic_address = (vm_offset_t) cth->apic_address;
801 /* walk the table, recording info of interest */
802 totalSize = cth->base_table_length - sizeof(struct MPCTH);
803 position = (u_char *) cth + sizeof(struct MPCTH);
804 count = cth->entry_count;
807 switch (type = *(u_char *) position) {
808 case 0: /* processor_entry */
809 if (((proc_entry_ptr)position)->cpu_flags
810 & PROCENTRY_FLAG_EN) {
813 ((proc_entry_ptr)position)->apic_id;
816 case 1: /* bus_entry */
819 case 2: /* io_apic_entry */
821 if (((io_apic_entry_ptr)position)->apic_flags
822 & IOAPICENTRY_FLAG_EN)
823 io_apic_address[mp_napics++] =
824 (vm_offset_t)((io_apic_entry_ptr)
825 position)->apic_address;
828 case 3: /* int_entry */
833 case 4: /* int_entry */
836 panic("mpfps Base Table HOSED!");
840 totalSize -= basetable_entry_types[type].length;
841 position = (uint8_t *)position +
842 basetable_entry_types[type].length;
846 /* qualify the numbers */
847 if (mp_naps > MAXCPU) {
848 kprintf("Warning: only using %d of %d available CPUs!\n",
853 /* See if we need to fixup HT logical CPUs. */
854 mptable_hyperthread_fixup(id_mask);
856 --mp_naps; /* subtract the BSP */
861 * 2nd pass on motherboard's Intel MP specification table.
865 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
866 * CPU_TO_ID(N), logical CPU to APIC ID table
867 * IO_TO_ID(N), logical IO to APIC ID table
872 mptable_pass2(struct mptable_pos *mpt)
874 struct PROCENTRY proc;
882 int apic, bus, cpu, intr;
885 POSTCODE(MPTABLE_PASS2_POST);
888 KKASSERT(fps != NULL);
890 /* Initialize fake proc entry for use with HT fixup. */
891 bzero(&proc, sizeof(proc));
893 proc.cpu_flags = PROCENTRY_FLAG_EN;
896 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
898 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
899 M_DEVBUF, M_WAITOK | M_ZERO);
900 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
903 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
907 for (i = 0; i < mp_napics; i++) {
908 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
912 /* clear various tables */
913 for (x = 0; x < NAPICID; ++x) {
914 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
916 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
917 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
921 /* clear bus data table */
922 for (x = 0; x < mp_nbusses; ++x)
923 bus_data[x].bus_id = 0xff;
926 /* clear IO APIC INT table */
927 for (x = 0; x < (nintrs + 1); ++x) {
928 io_apic_ints[x].int_type = 0xff;
929 io_apic_ints[x].int_vector = 0xff;
933 /* record whether PIC or virtual-wire mode */
934 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
936 /* check for use of 'default' configuration */
938 return fps->mpfb1; /* return default configuration type */
942 panic("MP Configuration Table Header MISSING!");
944 /* walk the table, recording info of interest */
945 totalSize = cth->base_table_length - sizeof(struct MPCTH);
946 position = (u_char *) cth + sizeof(struct MPCTH);
947 count = cth->entry_count;
948 apic = bus = intr = 0;
949 cpu = 1; /* pre-count the BSP */
952 switch (type = *(u_char *) position) {
954 if (processor_entry(position, cpu))
957 if (need_hyperthreading_fixup) {
959 * Create fake mptable processor entries
960 * and feed them to processor_entry() to
961 * enumerate the logical CPUs.
963 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
964 for (i = 1; i < logical_cpus; i++) {
966 processor_entry(&proc, cpu);
967 logical_cpus_mask |= (1 << cpu);
973 if (bus_entry(position, bus))
978 if (io_apic_entry(position, apic))
984 if (int_entry(position, intr))
989 /* int_entry(position); */
992 panic("mpfps Base Table HOSED!");
996 totalSize -= basetable_entry_types[type].length;
997 position = (uint8_t *)position + basetable_entry_types[type].length;
1000 if (CPU_TO_ID(0) < 0)
1001 panic("NO BSP found!");
1003 /* report fact that its NOT a default configuration */
1008 * Check if we should perform a hyperthreading "fix-up" to
1009 * enumerate any logical CPU's that aren't already listed
1012 * XXX: We assume that all of the physical CPUs in the
1013 * system have the same number of logical CPUs.
1015 * XXX: We assume that APIC ID's are allocated such that
1016 * the APIC ID's for a physical processor are aligned
1017 * with the number of logical CPU's in the processor.
1020 mptable_hyperthread_fixup(u_int id_mask)
1024 /* Nothing to do if there is no HTT support. */
1025 if ((cpu_feature & CPUID_HTT) == 0)
1027 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1028 if (logical_cpus <= 1)
1032 * For each APIC ID of a CPU that is set in the mask,
1033 * scan the other candidate APIC ID's for this
1034 * physical processor. If any of those ID's are
1035 * already in the table, then kill the fixup.
1037 for (id = 0; id <= MAXCPU; id++) {
1038 if ((id_mask & 1 << id) == 0)
1040 /* First, make sure we are on a logical_cpus boundary. */
1041 if (id % logical_cpus != 0)
1043 for (i = id + 1; i < id + logical_cpus; i++)
1044 if ((id_mask & 1 << i) != 0)
1049 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1050 * mp_naps right now.
1052 need_hyperthreading_fixup = 1;
1053 mp_naps *= logical_cpus;
1057 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1061 vm_size_t cth_mapsz = 0;
1063 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1064 if (fps->pap != 0) {
1066 * Map configuration table header to get
1067 * the base table size
1069 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1070 cth_mapsz = cth->base_table_length;
1071 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1074 * Map the base table
1076 cth = pmap_mapdev(fps->pap, cth_mapsz);
1081 mpt->mp_cth_mapsz = cth_mapsz;
1085 mptable_unmap(struct mptable_pos *mpt)
1087 if (mpt->mp_cth != NULL) {
1088 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1090 mpt->mp_cth_mapsz = 0;
1092 if (mpt->mp_fps != NULL) {
1093 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1101 assign_apic_irq(int apic, int intpin, int irq)
1105 if (int_to_apicintpin[irq].ioapic != -1)
1106 panic("assign_apic_irq: inconsistent table");
1108 int_to_apicintpin[irq].ioapic = apic;
1109 int_to_apicintpin[irq].int_pin = intpin;
1110 int_to_apicintpin[irq].apic_address = ioapic[apic];
1111 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1113 for (x = 0; x < nintrs; x++) {
1114 if ((io_apic_ints[x].int_type == 0 ||
1115 io_apic_ints[x].int_type == 3) &&
1116 io_apic_ints[x].int_vector == 0xff &&
1117 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1118 io_apic_ints[x].dst_apic_int == intpin)
1119 io_apic_ints[x].int_vector = irq;
1124 revoke_apic_irq(int irq)
1130 if (int_to_apicintpin[irq].ioapic == -1)
1131 panic("revoke_apic_irq: inconsistent table");
1133 oldapic = int_to_apicintpin[irq].ioapic;
1134 oldintpin = int_to_apicintpin[irq].int_pin;
1136 int_to_apicintpin[irq].ioapic = -1;
1137 int_to_apicintpin[irq].int_pin = 0;
1138 int_to_apicintpin[irq].apic_address = NULL;
1139 int_to_apicintpin[irq].redirindex = 0;
1141 for (x = 0; x < nintrs; x++) {
1142 if ((io_apic_ints[x].int_type == 0 ||
1143 io_apic_ints[x].int_type == 3) &&
1144 io_apic_ints[x].int_vector != 0xff &&
1145 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1146 io_apic_ints[x].dst_apic_int == oldintpin)
1147 io_apic_ints[x].int_vector = 0xff;
1155 allocate_apic_irq(int intr)
1161 if (io_apic_ints[intr].int_vector != 0xff)
1162 return; /* Interrupt handler already assigned */
1164 if (io_apic_ints[intr].int_type != 0 &&
1165 (io_apic_ints[intr].int_type != 3 ||
1166 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1167 io_apic_ints[intr].dst_apic_int == 0)))
1168 return; /* Not INT or ExtInt on != (0, 0) */
1171 while (irq < APIC_INTMAPSIZE &&
1172 int_to_apicintpin[irq].ioapic != -1)
1175 if (irq >= APIC_INTMAPSIZE)
1176 return; /* No free interrupt handlers */
1178 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1179 intpin = io_apic_ints[intr].dst_apic_int;
1181 assign_apic_irq(apic, intpin, irq);
1182 io_apic_setup_intpin(apic, intpin);
1187 swap_apic_id(int apic, int oldid, int newid)
1194 return; /* Nothing to do */
1196 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1197 apic, oldid, newid);
1199 /* Swap physical APIC IDs in interrupt entries */
1200 for (x = 0; x < nintrs; x++) {
1201 if (io_apic_ints[x].dst_apic_id == oldid)
1202 io_apic_ints[x].dst_apic_id = newid;
1203 else if (io_apic_ints[x].dst_apic_id == newid)
1204 io_apic_ints[x].dst_apic_id = oldid;
1207 /* Swap physical APIC IDs in IO_TO_ID mappings */
1208 for (oapic = 0; oapic < mp_napics; oapic++)
1209 if (IO_TO_ID(oapic) == newid)
1212 if (oapic < mp_napics) {
1213 kprintf("Changing APIC ID for IO APIC #%d from "
1214 "%d to %d in MP table\n",
1215 oapic, newid, oldid);
1216 IO_TO_ID(oapic) = oldid;
1218 IO_TO_ID(apic) = newid;
1223 fix_id_to_io_mapping(void)
1227 for (x = 0; x < NAPICID; x++)
1230 for (x = 0; x <= mp_naps; x++)
1231 if (CPU_TO_ID(x) < NAPICID)
1232 ID_TO_IO(CPU_TO_ID(x)) = x;
1234 for (x = 0; x < mp_napics; x++)
1235 if (IO_TO_ID(x) < NAPICID)
1236 ID_TO_IO(IO_TO_ID(x)) = x;
1241 first_free_apic_id(void)
1245 for (freeid = 0; freeid < NAPICID; freeid++) {
1246 for (x = 0; x <= mp_naps; x++)
1247 if (CPU_TO_ID(x) == freeid)
1251 for (x = 0; x < mp_napics; x++)
1252 if (IO_TO_ID(x) == freeid)
1263 io_apic_id_acceptable(int apic, int id)
1265 int cpu; /* Logical CPU number */
1266 int oapic; /* Logical IO APIC number for other IO APIC */
1269 return 0; /* Out of range */
1271 for (cpu = 0; cpu <= mp_naps; cpu++)
1272 if (CPU_TO_ID(cpu) == id)
1273 return 0; /* Conflict with CPU */
1275 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1276 if (IO_TO_ID(oapic) == id)
1277 return 0; /* Conflict with other APIC */
1279 return 1; /* ID is acceptable for IO APIC */
1284 io_apic_find_int_entry(int apic, int pin)
1288 /* search each of the possible INTerrupt sources */
1289 for (x = 0; x < nintrs; ++x) {
1290 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1291 (pin == io_apic_ints[x].dst_apic_int))
1292 return (&io_apic_ints[x]);
1300 * parse an Intel MP specification table
1308 int apic; /* IO APIC unit number */
1309 int freeid; /* Free physical APIC ID */
1310 int physid; /* Current physical IO APIC ID */
1313 int bus_0 = 0; /* Stop GCC warning */
1314 int bus_pci = 0; /* Stop GCC warning */
1318 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1319 * did it wrong. The MP spec says that when more than 1 PCI bus
1320 * exists the BIOS must begin with bus entries for the PCI bus and use
1321 * actual PCI bus numbering. This implies that when only 1 PCI bus
1322 * exists the BIOS can choose to ignore this ordering, and indeed many
1323 * MP motherboards do ignore it. This causes a problem when the PCI
1324 * sub-system makes requests of the MP sub-system based on PCI bus
1325 * numbers. So here we look for the situation and renumber the
1326 * busses and associated INTs in an effort to "make it right".
1329 /* find bus 0, PCI bus, count the number of PCI busses */
1330 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1331 if (bus_data[x].bus_id == 0) {
1334 if (bus_data[x].bus_type == PCI) {
1340 * bus_0 == slot of bus with ID of 0
1341 * bus_pci == slot of last PCI bus encountered
1344 /* check the 1 PCI bus case for sanity */
1345 /* if it is number 0 all is well */
1346 if (num_pci_bus == 1 &&
1347 bus_data[bus_pci].bus_id != 0) {
1349 /* mis-numbered, swap with whichever bus uses slot 0 */
1351 /* swap the bus entry types */
1352 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1353 bus_data[bus_0].bus_type = PCI;
1356 /* swap each relavant INTerrupt entry */
1357 id = bus_data[bus_pci].bus_id;
1358 for (x = 0; x < nintrs; ++x) {
1359 if (io_apic_ints[x].src_bus_id == id) {
1360 io_apic_ints[x].src_bus_id = 0;
1362 else if (io_apic_ints[x].src_bus_id == 0) {
1363 io_apic_ints[x].src_bus_id = id;
1370 /* Assign IO APIC IDs.
1372 * First try the existing ID. If a conflict is detected, try
1373 * the ID in the MP table. If a conflict is still detected, find
1376 * We cannot use the ID_TO_IO table before all conflicts has been
1377 * resolved and the table has been corrected.
1379 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1381 /* First try to use the value set by the BIOS */
1382 physid = io_apic_get_id(apic);
1383 if (io_apic_id_acceptable(apic, physid)) {
1384 if (IO_TO_ID(apic) != physid)
1385 swap_apic_id(apic, IO_TO_ID(apic), physid);
1389 /* Then check if the value in the MP table is acceptable */
1390 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1393 /* Last resort, find a free APIC ID and use it */
1394 freeid = first_free_apic_id();
1395 if (freeid >= NAPICID)
1396 panic("No free physical APIC IDs found");
1398 if (io_apic_id_acceptable(apic, freeid)) {
1399 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1402 panic("Free physical APIC ID not usable");
1404 fix_id_to_io_mapping();
1408 /* detect and fix broken Compaq MP table */
1409 if (apic_int_type(0, 0) == -1) {
1410 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1411 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1412 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1413 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1414 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1415 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1417 } else if (apic_int_type(0, 0) == 0) {
1418 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1419 for (x = 0; x < nintrs; ++x)
1420 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1421 (0 == io_apic_ints[x].dst_apic_int)) {
1422 io_apic_ints[x].int_type = 3;
1423 io_apic_ints[x].int_vector = 0xff;
1429 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1430 * controllers universally come in pairs. If IRQ 14 is specified
1431 * as an ISA interrupt, then IRQ 15 had better be too.
1433 * [ Shuttle XPC / AMD Athlon X2 ]
1434 * The MPTable is missing an entry for IRQ 15. Note that the
1435 * ACPI table has an entry for both 14 and 15.
1437 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1438 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1439 io14 = io_apic_find_int_entry(0, 14);
1440 io_apic_ints[nintrs] = *io14;
1441 io_apic_ints[nintrs].src_bus_irq = 15;
1442 io_apic_ints[nintrs].dst_apic_int = 15;
1450 /* Assign low level interrupt handlers */
1452 setup_apic_irq_mapping(void)
1458 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1459 int_to_apicintpin[x].ioapic = -1;
1460 int_to_apicintpin[x].int_pin = 0;
1461 int_to_apicintpin[x].apic_address = NULL;
1462 int_to_apicintpin[x].redirindex = 0;
1465 /* First assign ISA/EISA interrupts */
1466 for (x = 0; x < nintrs; x++) {
1467 int_vector = io_apic_ints[x].src_bus_irq;
1468 if (int_vector < APIC_INTMAPSIZE &&
1469 io_apic_ints[x].int_vector == 0xff &&
1470 int_to_apicintpin[int_vector].ioapic == -1 &&
1471 (apic_int_is_bus_type(x, ISA) ||
1472 apic_int_is_bus_type(x, EISA)) &&
1473 io_apic_ints[x].int_type == 0) {
1474 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1475 io_apic_ints[x].dst_apic_int,
1480 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1481 for (x = 0; x < nintrs; x++) {
1482 if (io_apic_ints[x].dst_apic_int == 0 &&
1483 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1484 io_apic_ints[x].int_vector == 0xff &&
1485 int_to_apicintpin[0].ioapic == -1 &&
1486 io_apic_ints[x].int_type == 3) {
1487 assign_apic_irq(0, 0, 0);
1491 /* PCI interrupt assignment is deferred */
1497 mp_set_cpuids(int cpu_id, int apic_id)
1499 CPU_TO_ID(cpu_id) = apic_id;
1500 ID_TO_CPU(apic_id) = cpu_id;
1504 processor_entry(proc_entry_ptr entry, int cpu)
1508 /* check for usability */
1509 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1512 if(entry->apic_id >= NAPICID)
1513 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1514 /* check for BSP flag */
1515 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1516 mp_set_cpuids(0, entry->apic_id);
1517 return 0; /* its already been counted */
1520 /* add another AP to list, if less than max number of CPUs */
1521 else if (cpu < MAXCPU) {
1522 mp_set_cpuids(cpu, entry->apic_id);
1531 bus_entry(bus_entry_ptr entry, int bus)
1536 /* encode the name into an index */
1537 for (x = 0; x < 6; ++x) {
1538 if ((c = entry->bus_type[x]) == ' ')
1544 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1545 panic("unknown bus type: '%s'", name);
1547 bus_data[bus].bus_id = entry->bus_id;
1548 bus_data[bus].bus_type = x;
1556 io_apic_entry(io_apic_entry_ptr entry, int apic)
1558 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1561 IO_TO_ID(apic) = entry->apic_id;
1562 if (entry->apic_id < NAPICID)
1563 ID_TO_IO(entry->apic_id) = apic;
1571 lookup_bus_type(char *name)
1575 for (x = 0; x < MAX_BUSTYPE; ++x)
1576 if (strcmp(bus_type_table[x].name, name) == 0)
1577 return bus_type_table[x].type;
1579 return UNKNOWN_BUSTYPE;
1585 int_entry(int_entry_ptr entry, int intr)
1589 io_apic_ints[intr].int_type = entry->int_type;
1590 io_apic_ints[intr].int_flags = entry->int_flags;
1591 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1592 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1593 if (entry->dst_apic_id == 255) {
1594 /* This signal goes to all IO APICS. Select an IO APIC
1595 with sufficient number of interrupt pins */
1596 for (apic = 0; apic < mp_napics; apic++)
1597 if (((io_apic_read(apic, IOAPIC_VER) &
1598 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1599 entry->dst_apic_int)
1601 if (apic < mp_napics)
1602 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1604 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1606 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1607 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1613 apic_int_is_bus_type(int intr, int bus_type)
1617 for (bus = 0; bus < mp_nbusses; ++bus)
1618 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1619 && ((int) bus_data[bus].bus_type == bus_type))
1626 * Given a traditional ISA INT mask, return an APIC mask.
1629 isa_apic_mask(u_int isa_mask)
1634 #if defined(SKIP_IRQ15_REDIRECT)
1635 if (isa_mask == (1 << 15)) {
1636 kprintf("skipping ISA IRQ15 redirect\n");
1639 #endif /* SKIP_IRQ15_REDIRECT */
1641 isa_irq = ffs(isa_mask); /* find its bit position */
1642 if (isa_irq == 0) /* doesn't exist */
1644 --isa_irq; /* make it zero based */
1646 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1650 return (1 << apic_pin); /* convert pin# to a mask */
1654 * Determine which APIC pin an ISA/EISA INT is attached to.
1656 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1657 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1658 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1659 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1661 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1663 isa_apic_irq(int isa_irq)
1667 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1668 if (INTTYPE(intr) == 0) { /* standard INT */
1669 if (SRCBUSIRQ(intr) == isa_irq) {
1670 if (apic_int_is_bus_type(intr, ISA) ||
1671 apic_int_is_bus_type(intr, EISA)) {
1672 if (INTIRQ(intr) == 0xff)
1673 return -1; /* unassigned */
1674 return INTIRQ(intr); /* found */
1679 return -1; /* NOT found */
1684 * Determine which APIC pin a PCI INT is attached to.
1686 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1687 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1688 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1690 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1694 --pciInt; /* zero based */
1696 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1697 if ((INTTYPE(intr) == 0) /* standard INT */
1698 && (SRCBUSID(intr) == pciBus)
1699 && (SRCBUSDEVICE(intr) == pciDevice)
1700 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1701 if (apic_int_is_bus_type(intr, PCI)) {
1702 if (INTIRQ(intr) == 0xff)
1703 allocate_apic_irq(intr);
1704 if (INTIRQ(intr) == 0xff)
1705 return -1; /* unassigned */
1706 return INTIRQ(intr); /* exact match */
1711 return -1; /* NOT found */
1715 next_apic_irq(int irq)
1722 for (intr = 0; intr < nintrs; intr++) {
1723 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1725 bus = SRCBUSID(intr);
1726 bustype = apic_bus_type(bus);
1727 if (bustype != ISA &&
1733 if (intr >= nintrs) {
1736 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1737 if (INTTYPE(ointr) != 0)
1739 if (bus != SRCBUSID(ointr))
1741 if (bustype == PCI) {
1742 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1744 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1747 if (bustype == ISA || bustype == EISA) {
1748 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1751 if (INTPIN(intr) == INTPIN(ointr))
1755 if (ointr >= nintrs) {
1758 return INTIRQ(ointr);
1773 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1776 * Exactly what this means is unclear at this point. It is a solution
1777 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1778 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1779 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1783 undirect_isa_irq(int rirq)
1787 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1788 /** FIXME: tickle the MB redirector chip */
1792 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1799 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1802 undirect_pci_irq(int rirq)
1806 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1808 /** FIXME: tickle the MB redirector chip */
1812 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1820 * given a bus ID, return:
1821 * the bus type if found
1825 apic_bus_type(int id)
1829 for (x = 0; x < mp_nbusses; ++x)
1830 if (bus_data[x].bus_id == id)
1831 return bus_data[x].bus_type;
1839 * given a LOGICAL APIC# and pin#, return:
1840 * the associated src bus ID if found
1844 apic_src_bus_id(int apic, int pin)
1848 /* search each of the possible INTerrupt sources */
1849 for (x = 0; x < nintrs; ++x)
1850 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1851 (pin == io_apic_ints[x].dst_apic_int))
1852 return (io_apic_ints[x].src_bus_id);
1854 return -1; /* NOT found */
1858 * given a LOGICAL APIC# and pin#, return:
1859 * the associated src bus IRQ if found
1863 apic_src_bus_irq(int apic, int pin)
1867 for (x = 0; x < nintrs; x++)
1868 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1869 (pin == io_apic_ints[x].dst_apic_int))
1870 return (io_apic_ints[x].src_bus_irq);
1872 return -1; /* NOT found */
1877 * given a LOGICAL APIC# and pin#, return:
1878 * the associated INTerrupt type if found
1882 apic_int_type(int apic, int pin)
1886 /* search each of the possible INTerrupt sources */
1887 for (x = 0; x < nintrs; ++x) {
1888 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1889 (pin == io_apic_ints[x].dst_apic_int))
1890 return (io_apic_ints[x].int_type);
1892 return -1; /* NOT found */
1896 * Return the IRQ associated with an APIC pin
1899 apic_irq(int apic, int pin)
1904 for (x = 0; x < nintrs; ++x) {
1905 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1906 (pin == io_apic_ints[x].dst_apic_int)) {
1907 res = io_apic_ints[x].int_vector;
1910 if (apic != int_to_apicintpin[res].ioapic)
1911 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1912 if (pin != int_to_apicintpin[res].int_pin)
1913 panic("apic_irq inconsistent table (2)");
1922 * given a LOGICAL APIC# and pin#, return:
1923 * the associated trigger mode if found
1927 apic_trigger(int apic, int pin)
1931 /* search each of the possible INTerrupt sources */
1932 for (x = 0; x < nintrs; ++x)
1933 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1934 (pin == io_apic_ints[x].dst_apic_int))
1935 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1937 return -1; /* NOT found */
1942 * given a LOGICAL APIC# and pin#, return:
1943 * the associated 'active' level if found
1947 apic_polarity(int apic, int pin)
1951 /* search each of the possible INTerrupt sources */
1952 for (x = 0; x < nintrs; ++x)
1953 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1954 (pin == io_apic_ints[x].dst_apic_int))
1955 return (io_apic_ints[x].int_flags & 0x03);
1957 return -1; /* NOT found */
1963 * set data according to MP defaults
1964 * FIXME: probably not complete yet...
1967 mptable_default(int type)
1969 int ap_cpu_id, boot_cpu_id;
1970 #if defined(APIC_IO)
1973 #endif /* APIC_IO */
1976 kprintf(" MP default config type: %d\n", type);
1979 kprintf(" bus: ISA, APIC: 82489DX\n");
1982 kprintf(" bus: EISA, APIC: 82489DX\n");
1985 kprintf(" bus: EISA, APIC: 82489DX\n");
1988 kprintf(" bus: MCA, APIC: 82489DX\n");
1991 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1994 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1997 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2000 kprintf(" future type\n");
2006 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
2007 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2010 CPU_TO_ID(0) = boot_cpu_id;
2011 ID_TO_CPU(boot_cpu_id) = 0;
2013 /* one and only AP */
2014 CPU_TO_ID(1) = ap_cpu_id;
2015 ID_TO_CPU(ap_cpu_id) = 1;
2017 #if defined(APIC_IO)
2018 /* one and only IO APIC */
2019 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2022 * sanity check, refer to MP spec section 3.6.6, last paragraph
2023 * necessary as some hardware isn't properly setting up the IO APIC
2025 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2026 if (io_apic_id != 2) {
2028 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2029 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2030 io_apic_set_id(0, 2);
2033 IO_TO_ID(0) = io_apic_id;
2034 ID_TO_IO(io_apic_id) = 0;
2035 #endif /* APIC_IO */
2037 /* fill out bus entries */
2046 bus_data[0].bus_id = default_data[type - 1][1];
2047 bus_data[0].bus_type = default_data[type - 1][2];
2048 bus_data[1].bus_id = default_data[type - 1][3];
2049 bus_data[1].bus_type = default_data[type - 1][4];
2052 /* case 4: case 7: MCA NOT supported */
2053 default: /* illegal/reserved */
2054 panic("BAD default MP config: %d", type);
2058 #if defined(APIC_IO)
2059 /* general cases from MP v1.4, table 5-2 */
2060 for (pin = 0; pin < 16; ++pin) {
2061 io_apic_ints[pin].int_type = 0;
2062 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2063 io_apic_ints[pin].src_bus_id = 0;
2064 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2065 io_apic_ints[pin].dst_apic_id = io_apic_id;
2066 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2069 /* special cases from MP v1.4, table 5-2 */
2071 io_apic_ints[2].int_type = 0xff; /* N/C */
2072 io_apic_ints[13].int_type = 0xff; /* N/C */
2073 #if !defined(APIC_MIXED_MODE)
2075 panic("sorry, can't support type 2 default yet");
2076 #endif /* APIC_MIXED_MODE */
2079 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2082 io_apic_ints[0].int_type = 0xff; /* N/C */
2084 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2085 #endif /* APIC_IO */
2089 * Map a physical memory address representing I/O into KVA. The I/O
2090 * block is assumed not to cross a page boundary.
2093 permanent_io_mapping(vm_paddr_t pa)
2099 KKASSERT(pa < 0x100000000LL);
2101 pgeflag = 0; /* not used for SMP yet */
2104 * If the requested physical address has already been incidently
2105 * mapped, just use the existing mapping. Otherwise create a new
2108 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2109 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2110 ((vm_offset_t)pa & PG_FRAME)) {
2114 if (i == SMPpt_alloc_index) {
2115 if (i == NPTEPG - 2) {
2116 panic("permanent_io_mapping: We ran out of space"
2119 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2120 ((vm_offset_t)pa & PG_FRAME));
2121 ++SMPpt_alloc_index;
2123 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2124 ((vm_offset_t)pa & PAGE_MASK);
2125 return ((void *)vaddr);
2129 * start each AP in our list
2132 start_all_aps(u_int boot_addr)
2136 u_char mpbiosreason;
2137 u_long mpbioswarmvec;
2138 struct mdglobaldata *gd;
2139 struct privatespace *ps;
2143 POSTCODE(START_ALL_APS_POST);
2145 /* Initialize BSP's local APIC */
2146 apic_initialize(TRUE);
2149 /* install the AP 1st level boot code */
2150 install_ap_tramp(boot_addr);
2153 /* save the current value of the warm-start vector */
2154 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2155 outb(CMOS_REG, BIOS_RESET);
2156 mpbiosreason = inb(CMOS_DATA);
2158 /* set up temporary P==V mapping for AP boot */
2159 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2160 kptbase = (uintptr_t)(void *)KPTphys;
2161 for (x = 0; x < NKPT; x++) {
2162 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2163 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2168 for (x = 1; x <= mp_naps; ++x) {
2170 /* This is a bit verbose, it will go away soon. */
2172 /* first page of AP's private space */
2173 pg = x * i386_btop(sizeof(struct privatespace));
2175 /* allocate new private data page(s) */
2176 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2177 MDGLOBALDATA_BASEALLOC_SIZE);
2178 /* wire it into the private page table page */
2179 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2180 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2181 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2183 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2185 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2186 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2187 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2188 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2190 /* allocate and set up an idle stack data page */
2191 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2192 for (i = 0; i < UPAGES; i++) {
2193 SMPpt[pg + 4 + i] = (pt_entry_t)
2194 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2197 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2198 bzero(gd, sizeof(*gd));
2199 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2201 /* prime data page for it to use */
2202 mi_gdinit(&gd->mi, x);
2204 gd->gd_CMAP1 = &SMPpt[pg + 0];
2205 gd->gd_CMAP2 = &SMPpt[pg + 1];
2206 gd->gd_CMAP3 = &SMPpt[pg + 2];
2207 gd->gd_PMAP1 = &SMPpt[pg + 3];
2208 gd->gd_CADDR1 = ps->CPAGE1;
2209 gd->gd_CADDR2 = ps->CPAGE2;
2210 gd->gd_CADDR3 = ps->CPAGE3;
2211 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2212 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2213 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2215 /* setup a vector to our boot code */
2216 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2217 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2218 outb(CMOS_REG, BIOS_RESET);
2219 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2222 * Setup the AP boot stack
2224 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2227 /* attempt to start the Application Processor */
2228 CHECK_INIT(99); /* setup checkpoints */
2229 if (!start_ap(gd, boot_addr)) {
2230 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2231 CHECK_PRINT("trace"); /* show checkpoints */
2232 /* better panic as the AP may be running loose */
2233 kprintf("panic y/n? [y] ");
2234 if (cngetc() != 'n')
2237 CHECK_PRINT("trace"); /* show checkpoints */
2239 /* record its version info */
2240 cpu_apic_versions[x] = cpu_apic_versions[0];
2243 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2246 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2247 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2250 ncpus2_shift = shift;
2251 ncpus2 = 1 << shift;
2252 ncpus2_mask = ncpus2 - 1;
2254 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2255 if ((1 << shift) < ncpus)
2257 ncpus_fit = 1 << shift;
2258 ncpus_fit_mask = ncpus_fit - 1;
2260 /* build our map of 'other' CPUs */
2261 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2262 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2263 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2265 /* fill in our (BSP) APIC version */
2266 cpu_apic_versions[0] = lapic.version;
2268 /* restore the warmstart vector */
2269 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2270 outb(CMOS_REG, BIOS_RESET);
2271 outb(CMOS_DATA, mpbiosreason);
2274 * NOTE! The idlestack for the BSP was setup by locore. Finish
2275 * up, clean out the P==V mapping we did earlier.
2277 for (x = 0; x < NKPT; x++)
2281 /* number of APs actually started */
2287 * load the 1st level AP boot code into base memory.
2290 /* targets for relocation */
2291 extern void bigJump(void);
2292 extern void bootCodeSeg(void);
2293 extern void bootDataSeg(void);
2294 extern void MPentry(void);
2295 extern u_int MP_GDT;
2296 extern u_int mp_gdtbase;
2299 install_ap_tramp(u_int boot_addr)
2302 int size = *(int *) ((u_long) & bootMP_size);
2303 u_char *src = (u_char *) ((u_long) bootMP);
2304 u_char *dst = (u_char *) boot_addr + KERNBASE;
2305 u_int boot_base = (u_int) bootMP;
2310 POSTCODE(INSTALL_AP_TRAMP_POST);
2312 for (x = 0; x < size; ++x)
2316 * modify addresses in code we just moved to basemem. unfortunately we
2317 * need fairly detailed info about mpboot.s for this to work. changes
2318 * to mpboot.s might require changes here.
2321 /* boot code is located in KERNEL space */
2322 dst = (u_char *) boot_addr + KERNBASE;
2324 /* modify the lgdt arg */
2325 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2326 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2328 /* modify the ljmp target for MPentry() */
2329 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2330 *dst32 = ((u_int) MPentry - KERNBASE);
2332 /* modify the target for boot code segment */
2333 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2334 dst8 = (u_int8_t *) (dst16 + 1);
2335 *dst16 = (u_int) boot_addr & 0xffff;
2336 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2338 /* modify the target for boot data segment */
2339 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2340 dst8 = (u_int8_t *) (dst16 + 1);
2341 *dst16 = (u_int) boot_addr & 0xffff;
2342 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2347 * this function starts the AP (application processor) identified
2348 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2349 * to accomplish this. This is necessary because of the nuances
2350 * of the different hardware we might encounter. It ain't pretty,
2351 * but it seems to work.
2353 * NOTE: eventually an AP gets to ap_init(), which is called just
2354 * before the AP goes into the LWKT scheduler's idle loop.
2357 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2361 u_long icr_lo, icr_hi;
2363 POSTCODE(START_AP_POST);
2365 /* get the PHYSICAL APIC ID# */
2366 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2368 /* calculate the vector */
2369 vector = (boot_addr >> 12) & 0xff;
2371 /* Make sure the target cpu sees everything */
2375 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2376 * and running the target CPU. OR this INIT IPI might be latched (P5
2377 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2381 /* setup the address for the target AP */
2382 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2383 icr_hi |= (physical_cpu << 24);
2384 lapic.icr_hi = icr_hi;
2386 /* do an INIT IPI: assert RESET */
2387 icr_lo = lapic.icr_lo & 0xfff00000;
2388 lapic.icr_lo = icr_lo | 0x0000c500;
2390 /* wait for pending status end */
2391 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2394 /* do an INIT IPI: deassert RESET */
2395 lapic.icr_lo = icr_lo | 0x00008500;
2397 /* wait for pending status end */
2398 u_sleep(10000); /* wait ~10mS */
2399 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2403 * next we do a STARTUP IPI: the previous INIT IPI might still be
2404 * latched, (P5 bug) this 1st STARTUP would then terminate
2405 * immediately, and the previously started INIT IPI would continue. OR
2406 * the previous INIT IPI has already run. and this STARTUP IPI will
2407 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2411 /* do a STARTUP IPI */
2412 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2413 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2415 u_sleep(200); /* wait ~200uS */
2418 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2419 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2420 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2421 * recognized after hardware RESET or INIT IPI.
2424 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2425 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2427 u_sleep(200); /* wait ~200uS */
2429 /* wait for it to start, see ap_init() */
2430 set_apic_timer(5000000);/* == 5 seconds */
2431 while (read_apic_timer()) {
2432 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2433 return 1; /* return SUCCESS */
2435 return 0; /* return FAILURE */
2440 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2442 * If for some reason we were unable to start all cpus we cannot safely
2443 * use broadcast IPIs.
2449 if (smp_startup_mask == smp_active_mask) {
2450 all_but_self_ipi(XINVLTLB_OFFSET);
2452 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2453 APIC_DELMODE_FIXED);
2459 * When called the executing CPU will send an IPI to all other CPUs
2460 * requesting that they halt execution.
2462 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2464 * - Signals all CPUs in map to stop.
2465 * - Waits for each to stop.
2472 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2473 * from executing at same time.
2476 stop_cpus(u_int map)
2478 map &= smp_active_mask;
2480 /* send the Xcpustop IPI to all CPUs in map */
2481 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2483 while ((stopped_cpus & map) != map)
2491 * Called by a CPU to restart stopped CPUs.
2493 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2495 * - Signals all CPUs in map to restart.
2496 * - Waits for each to restart.
2504 restart_cpus(u_int map)
2506 /* signal other cpus to restart */
2507 started_cpus = map & smp_active_mask;
2509 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2516 * This is called once the mpboot code has gotten us properly relocated
2517 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2518 * and when it returns the scheduler will call the real cpu_idle() main
2519 * loop for the idlethread. Interrupts are disabled on entry and should
2520 * remain disabled at return.
2528 * Adjust smp_startup_mask to signal the BSP that we have started
2529 * up successfully. Note that we do not yet hold the BGL. The BSP
2530 * is waiting for our signal.
2532 * We can't set our bit in smp_active_mask yet because we are holding
2533 * interrupts physically disabled and remote cpus could deadlock
2534 * trying to send us an IPI.
2536 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2540 * Interlock for finalization. Wait until mp_finish is non-zero,
2541 * then get the MP lock.
2543 * Note: We are in a critical section.
2545 * Note: We have to synchronize td_mpcount to our desired MP state
2546 * before calling cpu_try_mplock().
2548 * Note: we are the idle thread, we can only spin.
2550 * Note: The load fence is memory volatile and prevents the compiler
2551 * from improperly caching mp_finish, and the cpu from improperly
2554 while (mp_finish == 0)
2556 ++curthread->td_mpcount;
2557 while (cpu_try_mplock() == 0)
2560 if (cpu_feature & CPUID_TSC) {
2562 * The BSP is constantly updating tsc0_offset, figure out the
2563 * relative difference to synchronize ktrdump.
2565 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2568 /* BSP may have changed PTD while we're waiting for the lock */
2571 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2575 /* Build our map of 'other' CPUs. */
2576 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2578 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2580 /* A quick check from sanity claus */
2581 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2582 if (mycpu->gd_cpuid != apic_id) {
2583 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2584 kprintf("SMP: apic_id = %d\n", apic_id);
2585 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2586 panic("cpuid mismatch! boom!!");
2589 /* Initialize AP's local APIC for irq's */
2590 apic_initialize(FALSE);
2592 /* Set memory range attributes for this CPU to match the BSP */
2593 mem_range_AP_init();
2596 * Once we go active we must process any IPIQ messages that may
2597 * have been queued, because no actual IPI will occur until we
2598 * set our bit in the smp_active_mask. If we don't the IPI
2599 * message interlock could be left set which would also prevent
2602 * The idle loop doesn't expect the BGL to be held and while
2603 * lwkt_switch() normally cleans things up this is a special case
2604 * because we returning almost directly into the idle loop.
2606 * The idle thread is never placed on the runq, make sure
2607 * nothing we've done put it there.
2609 KKASSERT(curthread->td_mpcount == 1);
2610 smp_active_mask |= 1 << mycpu->gd_cpuid;
2613 * Enable interrupts here. idle_restore will also do it, but
2614 * doing it here lets us clean up any strays that got posted to
2615 * the CPU during the AP boot while we are still in a critical
2618 __asm __volatile("sti; pause; pause"::);
2619 mdcpu->gd_fpending = 0;
2620 mdcpu->gd_ipending = 0;
2622 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2623 lwkt_process_ipiq();
2626 * Releasing the mp lock lets the BSP finish up the SMP init
2629 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2633 * Get SMP fully working before we start initializing devices.
2641 kprintf("Finish MP startup\n");
2642 if (cpu_feature & CPUID_TSC)
2643 tsc0_offset = rdtsc();
2646 while (smp_active_mask != smp_startup_mask) {
2648 if (cpu_feature & CPUID_TSC)
2649 tsc0_offset = rdtsc();
2651 while (try_mplock() == 0)
2654 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2657 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2660 cpu_send_ipiq(int dcpu)
2662 if ((1 << dcpu) & smp_active_mask)
2663 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2666 #if 0 /* single_apic_ipi_passive() not working yet */
2668 * Returns 0 on failure, 1 on success
2671 cpu_send_ipiq_passive(int dcpu)
2674 if ((1 << dcpu) & smp_active_mask) {
2675 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2676 APIC_DELMODE_FIXED);