2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
10 * This code is derived from software contributed to Berkeley by
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
49 #include <sys/thread2.h>
51 #include <machine/smp.h>
52 #include <machine/segments.h>
53 #include <machine/md_var.h>
54 #include <machine/intr_machdep.h>
55 #include <machine/globaldata.h>
57 #include <machine_base/isa/isa_intr.h>
58 #include <machine_base/icu/icu.h>
59 #include <machine_base/icu/icu_var.h>
60 #include <machine_base/apic/ioapic.h>
61 #include <machine_base/apic/ioapic_abi.h>
62 #include <machine_base/apic/ioapic_ipl.h>
63 #include <machine_base/apic/apicreg.h>
65 #include <dev/acpica5/acpi_sci_var.h>
67 #define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
80 IDTVEC(ioapic_intr10),
81 IDTVEC(ioapic_intr11),
82 IDTVEC(ioapic_intr12),
83 IDTVEC(ioapic_intr13),
84 IDTVEC(ioapic_intr14),
85 IDTVEC(ioapic_intr15),
86 IDTVEC(ioapic_intr16),
87 IDTVEC(ioapic_intr17),
88 IDTVEC(ioapic_intr18),
89 IDTVEC(ioapic_intr19),
90 IDTVEC(ioapic_intr20),
91 IDTVEC(ioapic_intr21),
92 IDTVEC(ioapic_intr22),
93 IDTVEC(ioapic_intr23),
94 IDTVEC(ioapic_intr24),
95 IDTVEC(ioapic_intr25),
96 IDTVEC(ioapic_intr26),
97 IDTVEC(ioapic_intr27),
98 IDTVEC(ioapic_intr28),
99 IDTVEC(ioapic_intr29),
100 IDTVEC(ioapic_intr30),
101 IDTVEC(ioapic_intr31),
102 IDTVEC(ioapic_intr32),
103 IDTVEC(ioapic_intr33),
104 IDTVEC(ioapic_intr34),
105 IDTVEC(ioapic_intr35),
106 IDTVEC(ioapic_intr36),
107 IDTVEC(ioapic_intr37),
108 IDTVEC(ioapic_intr38),
109 IDTVEC(ioapic_intr39),
110 IDTVEC(ioapic_intr40),
111 IDTVEC(ioapic_intr41),
112 IDTVEC(ioapic_intr42),
113 IDTVEC(ioapic_intr43),
114 IDTVEC(ioapic_intr44),
115 IDTVEC(ioapic_intr45),
116 IDTVEC(ioapic_intr46),
117 IDTVEC(ioapic_intr47),
118 IDTVEC(ioapic_intr48),
119 IDTVEC(ioapic_intr49),
120 IDTVEC(ioapic_intr50),
121 IDTVEC(ioapic_intr51),
122 IDTVEC(ioapic_intr52),
123 IDTVEC(ioapic_intr53),
124 IDTVEC(ioapic_intr54),
125 IDTVEC(ioapic_intr55),
126 IDTVEC(ioapic_intr56),
127 IDTVEC(ioapic_intr57),
128 IDTVEC(ioapic_intr58),
129 IDTVEC(ioapic_intr59),
130 IDTVEC(ioapic_intr60),
131 IDTVEC(ioapic_intr61),
132 IDTVEC(ioapic_intr62),
133 IDTVEC(ioapic_intr63),
134 IDTVEC(ioapic_intr64),
135 IDTVEC(ioapic_intr65),
136 IDTVEC(ioapic_intr66),
137 IDTVEC(ioapic_intr67),
138 IDTVEC(ioapic_intr68),
139 IDTVEC(ioapic_intr69),
140 IDTVEC(ioapic_intr70),
141 IDTVEC(ioapic_intr71),
142 IDTVEC(ioapic_intr72),
143 IDTVEC(ioapic_intr73),
144 IDTVEC(ioapic_intr74),
145 IDTVEC(ioapic_intr75),
146 IDTVEC(ioapic_intr76),
147 IDTVEC(ioapic_intr77),
148 IDTVEC(ioapic_intr78),
149 IDTVEC(ioapic_intr79),
150 IDTVEC(ioapic_intr80),
151 IDTVEC(ioapic_intr81),
152 IDTVEC(ioapic_intr82),
153 IDTVEC(ioapic_intr83),
154 IDTVEC(ioapic_intr84),
155 IDTVEC(ioapic_intr85),
156 IDTVEC(ioapic_intr86),
157 IDTVEC(ioapic_intr87),
158 IDTVEC(ioapic_intr88),
159 IDTVEC(ioapic_intr89),
160 IDTVEC(ioapic_intr90),
161 IDTVEC(ioapic_intr91),
162 IDTVEC(ioapic_intr92),
163 IDTVEC(ioapic_intr93),
164 IDTVEC(ioapic_intr94),
165 IDTVEC(ioapic_intr95),
166 IDTVEC(ioapic_intr96),
167 IDTVEC(ioapic_intr97),
168 IDTVEC(ioapic_intr98),
169 IDTVEC(ioapic_intr99),
170 IDTVEC(ioapic_intr100),
171 IDTVEC(ioapic_intr101),
172 IDTVEC(ioapic_intr102),
173 IDTVEC(ioapic_intr103),
174 IDTVEC(ioapic_intr104),
175 IDTVEC(ioapic_intr105),
176 IDTVEC(ioapic_intr106),
177 IDTVEC(ioapic_intr107),
178 IDTVEC(ioapic_intr108),
179 IDTVEC(ioapic_intr109),
180 IDTVEC(ioapic_intr110),
181 IDTVEC(ioapic_intr111),
182 IDTVEC(ioapic_intr112),
183 IDTVEC(ioapic_intr113),
184 IDTVEC(ioapic_intr114),
185 IDTVEC(ioapic_intr115),
186 IDTVEC(ioapic_intr116),
187 IDTVEC(ioapic_intr117),
188 IDTVEC(ioapic_intr118),
189 IDTVEC(ioapic_intr119),
190 IDTVEC(ioapic_intr120),
191 IDTVEC(ioapic_intr121),
192 IDTVEC(ioapic_intr122),
193 IDTVEC(ioapic_intr123),
194 IDTVEC(ioapic_intr124),
195 IDTVEC(ioapic_intr125),
196 IDTVEC(ioapic_intr126),
197 IDTVEC(ioapic_intr127),
198 IDTVEC(ioapic_intr128),
199 IDTVEC(ioapic_intr129),
200 IDTVEC(ioapic_intr130),
201 IDTVEC(ioapic_intr131),
202 IDTVEC(ioapic_intr132),
203 IDTVEC(ioapic_intr133),
204 IDTVEC(ioapic_intr134),
205 IDTVEC(ioapic_intr135),
206 IDTVEC(ioapic_intr136),
207 IDTVEC(ioapic_intr137),
208 IDTVEC(ioapic_intr138),
209 IDTVEC(ioapic_intr139),
210 IDTVEC(ioapic_intr140),
211 IDTVEC(ioapic_intr141),
212 IDTVEC(ioapic_intr142),
213 IDTVEC(ioapic_intr143),
214 IDTVEC(ioapic_intr144),
215 IDTVEC(ioapic_intr145),
216 IDTVEC(ioapic_intr146),
217 IDTVEC(ioapic_intr147),
218 IDTVEC(ioapic_intr148),
219 IDTVEC(ioapic_intr149),
220 IDTVEC(ioapic_intr150),
221 IDTVEC(ioapic_intr151),
222 IDTVEC(ioapic_intr152),
223 IDTVEC(ioapic_intr153),
224 IDTVEC(ioapic_intr154),
225 IDTVEC(ioapic_intr155),
226 IDTVEC(ioapic_intr156),
227 IDTVEC(ioapic_intr157),
228 IDTVEC(ioapic_intr158),
229 IDTVEC(ioapic_intr159),
230 IDTVEC(ioapic_intr160),
231 IDTVEC(ioapic_intr161),
232 IDTVEC(ioapic_intr162),
233 IDTVEC(ioapic_intr163),
234 IDTVEC(ioapic_intr164),
235 IDTVEC(ioapic_intr165),
236 IDTVEC(ioapic_intr166),
237 IDTVEC(ioapic_intr167),
238 IDTVEC(ioapic_intr168),
239 IDTVEC(ioapic_intr169),
240 IDTVEC(ioapic_intr170),
241 IDTVEC(ioapic_intr171),
242 IDTVEC(ioapic_intr172),
243 IDTVEC(ioapic_intr173),
244 IDTVEC(ioapic_intr174),
245 IDTVEC(ioapic_intr175),
246 IDTVEC(ioapic_intr176),
247 IDTVEC(ioapic_intr177),
248 IDTVEC(ioapic_intr178),
249 IDTVEC(ioapic_intr179),
250 IDTVEC(ioapic_intr180),
251 IDTVEC(ioapic_intr181),
252 IDTVEC(ioapic_intr182),
253 IDTVEC(ioapic_intr183),
254 IDTVEC(ioapic_intr184),
255 IDTVEC(ioapic_intr185),
256 IDTVEC(ioapic_intr186),
257 IDTVEC(ioapic_intr187),
258 IDTVEC(ioapic_intr188),
259 IDTVEC(ioapic_intr189),
260 IDTVEC(ioapic_intr190),
261 IDTVEC(ioapic_intr191);
263 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
264 &IDTVEC(ioapic_intr0),
265 &IDTVEC(ioapic_intr1),
266 &IDTVEC(ioapic_intr2),
267 &IDTVEC(ioapic_intr3),
268 &IDTVEC(ioapic_intr4),
269 &IDTVEC(ioapic_intr5),
270 &IDTVEC(ioapic_intr6),
271 &IDTVEC(ioapic_intr7),
272 &IDTVEC(ioapic_intr8),
273 &IDTVEC(ioapic_intr9),
274 &IDTVEC(ioapic_intr10),
275 &IDTVEC(ioapic_intr11),
276 &IDTVEC(ioapic_intr12),
277 &IDTVEC(ioapic_intr13),
278 &IDTVEC(ioapic_intr14),
279 &IDTVEC(ioapic_intr15),
280 &IDTVEC(ioapic_intr16),
281 &IDTVEC(ioapic_intr17),
282 &IDTVEC(ioapic_intr18),
283 &IDTVEC(ioapic_intr19),
284 &IDTVEC(ioapic_intr20),
285 &IDTVEC(ioapic_intr21),
286 &IDTVEC(ioapic_intr22),
287 &IDTVEC(ioapic_intr23),
288 &IDTVEC(ioapic_intr24),
289 &IDTVEC(ioapic_intr25),
290 &IDTVEC(ioapic_intr26),
291 &IDTVEC(ioapic_intr27),
292 &IDTVEC(ioapic_intr28),
293 &IDTVEC(ioapic_intr29),
294 &IDTVEC(ioapic_intr30),
295 &IDTVEC(ioapic_intr31),
296 &IDTVEC(ioapic_intr32),
297 &IDTVEC(ioapic_intr33),
298 &IDTVEC(ioapic_intr34),
299 &IDTVEC(ioapic_intr35),
300 &IDTVEC(ioapic_intr36),
301 &IDTVEC(ioapic_intr37),
302 &IDTVEC(ioapic_intr38),
303 &IDTVEC(ioapic_intr39),
304 &IDTVEC(ioapic_intr40),
305 &IDTVEC(ioapic_intr41),
306 &IDTVEC(ioapic_intr42),
307 &IDTVEC(ioapic_intr43),
308 &IDTVEC(ioapic_intr44),
309 &IDTVEC(ioapic_intr45),
310 &IDTVEC(ioapic_intr46),
311 &IDTVEC(ioapic_intr47),
312 &IDTVEC(ioapic_intr48),
313 &IDTVEC(ioapic_intr49),
314 &IDTVEC(ioapic_intr50),
315 &IDTVEC(ioapic_intr51),
316 &IDTVEC(ioapic_intr52),
317 &IDTVEC(ioapic_intr53),
318 &IDTVEC(ioapic_intr54),
319 &IDTVEC(ioapic_intr55),
320 &IDTVEC(ioapic_intr56),
321 &IDTVEC(ioapic_intr57),
322 &IDTVEC(ioapic_intr58),
323 &IDTVEC(ioapic_intr59),
324 &IDTVEC(ioapic_intr60),
325 &IDTVEC(ioapic_intr61),
326 &IDTVEC(ioapic_intr62),
327 &IDTVEC(ioapic_intr63),
328 &IDTVEC(ioapic_intr64),
329 &IDTVEC(ioapic_intr65),
330 &IDTVEC(ioapic_intr66),
331 &IDTVEC(ioapic_intr67),
332 &IDTVEC(ioapic_intr68),
333 &IDTVEC(ioapic_intr69),
334 &IDTVEC(ioapic_intr70),
335 &IDTVEC(ioapic_intr71),
336 &IDTVEC(ioapic_intr72),
337 &IDTVEC(ioapic_intr73),
338 &IDTVEC(ioapic_intr74),
339 &IDTVEC(ioapic_intr75),
340 &IDTVEC(ioapic_intr76),
341 &IDTVEC(ioapic_intr77),
342 &IDTVEC(ioapic_intr78),
343 &IDTVEC(ioapic_intr79),
344 &IDTVEC(ioapic_intr80),
345 &IDTVEC(ioapic_intr81),
346 &IDTVEC(ioapic_intr82),
347 &IDTVEC(ioapic_intr83),
348 &IDTVEC(ioapic_intr84),
349 &IDTVEC(ioapic_intr85),
350 &IDTVEC(ioapic_intr86),
351 &IDTVEC(ioapic_intr87),
352 &IDTVEC(ioapic_intr88),
353 &IDTVEC(ioapic_intr89),
354 &IDTVEC(ioapic_intr90),
355 &IDTVEC(ioapic_intr91),
356 &IDTVEC(ioapic_intr92),
357 &IDTVEC(ioapic_intr93),
358 &IDTVEC(ioapic_intr94),
359 &IDTVEC(ioapic_intr95),
360 &IDTVEC(ioapic_intr96),
361 &IDTVEC(ioapic_intr97),
362 &IDTVEC(ioapic_intr98),
363 &IDTVEC(ioapic_intr99),
364 &IDTVEC(ioapic_intr100),
365 &IDTVEC(ioapic_intr101),
366 &IDTVEC(ioapic_intr102),
367 &IDTVEC(ioapic_intr103),
368 &IDTVEC(ioapic_intr104),
369 &IDTVEC(ioapic_intr105),
370 &IDTVEC(ioapic_intr106),
371 &IDTVEC(ioapic_intr107),
372 &IDTVEC(ioapic_intr108),
373 &IDTVEC(ioapic_intr109),
374 &IDTVEC(ioapic_intr110),
375 &IDTVEC(ioapic_intr111),
376 &IDTVEC(ioapic_intr112),
377 &IDTVEC(ioapic_intr113),
378 &IDTVEC(ioapic_intr114),
379 &IDTVEC(ioapic_intr115),
380 &IDTVEC(ioapic_intr116),
381 &IDTVEC(ioapic_intr117),
382 &IDTVEC(ioapic_intr118),
383 &IDTVEC(ioapic_intr119),
384 &IDTVEC(ioapic_intr120),
385 &IDTVEC(ioapic_intr121),
386 &IDTVEC(ioapic_intr122),
387 &IDTVEC(ioapic_intr123),
388 &IDTVEC(ioapic_intr124),
389 &IDTVEC(ioapic_intr125),
390 &IDTVEC(ioapic_intr126),
391 &IDTVEC(ioapic_intr127),
392 &IDTVEC(ioapic_intr128),
393 &IDTVEC(ioapic_intr129),
394 &IDTVEC(ioapic_intr130),
395 &IDTVEC(ioapic_intr131),
396 &IDTVEC(ioapic_intr132),
397 &IDTVEC(ioapic_intr133),
398 &IDTVEC(ioapic_intr134),
399 &IDTVEC(ioapic_intr135),
400 &IDTVEC(ioapic_intr136),
401 &IDTVEC(ioapic_intr137),
402 &IDTVEC(ioapic_intr138),
403 &IDTVEC(ioapic_intr139),
404 &IDTVEC(ioapic_intr140),
405 &IDTVEC(ioapic_intr141),
406 &IDTVEC(ioapic_intr142),
407 &IDTVEC(ioapic_intr143),
408 &IDTVEC(ioapic_intr144),
409 &IDTVEC(ioapic_intr145),
410 &IDTVEC(ioapic_intr146),
411 &IDTVEC(ioapic_intr147),
412 &IDTVEC(ioapic_intr148),
413 &IDTVEC(ioapic_intr149),
414 &IDTVEC(ioapic_intr150),
415 &IDTVEC(ioapic_intr151),
416 &IDTVEC(ioapic_intr152),
417 &IDTVEC(ioapic_intr153),
418 &IDTVEC(ioapic_intr154),
419 &IDTVEC(ioapic_intr155),
420 &IDTVEC(ioapic_intr156),
421 &IDTVEC(ioapic_intr157),
422 &IDTVEC(ioapic_intr158),
423 &IDTVEC(ioapic_intr159),
424 &IDTVEC(ioapic_intr160),
425 &IDTVEC(ioapic_intr161),
426 &IDTVEC(ioapic_intr162),
427 &IDTVEC(ioapic_intr163),
428 &IDTVEC(ioapic_intr164),
429 &IDTVEC(ioapic_intr165),
430 &IDTVEC(ioapic_intr166),
431 &IDTVEC(ioapic_intr167),
432 &IDTVEC(ioapic_intr168),
433 &IDTVEC(ioapic_intr169),
434 &IDTVEC(ioapic_intr170),
435 &IDTVEC(ioapic_intr171),
436 &IDTVEC(ioapic_intr172),
437 &IDTVEC(ioapic_intr173),
438 &IDTVEC(ioapic_intr174),
439 &IDTVEC(ioapic_intr175),
440 &IDTVEC(ioapic_intr176),
441 &IDTVEC(ioapic_intr177),
442 &IDTVEC(ioapic_intr178),
443 &IDTVEC(ioapic_intr179),
444 &IDTVEC(ioapic_intr180),
445 &IDTVEC(ioapic_intr181),
446 &IDTVEC(ioapic_intr182),
447 &IDTVEC(ioapic_intr183),
448 &IDTVEC(ioapic_intr184),
449 &IDTVEC(ioapic_intr185),
450 &IDTVEC(ioapic_intr186),
451 &IDTVEC(ioapic_intr187),
452 &IDTVEC(ioapic_intr188),
453 &IDTVEC(ioapic_intr189),
454 &IDTVEC(ioapic_intr190),
455 &IDTVEC(ioapic_intr191)
458 #define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
460 static struct ioapic_irqmap {
461 int im_type; /* IOAPIC_IMT_ */
462 enum intr_trigger im_trig;
463 enum intr_polarity im_pola;
465 uint32_t im_flags; /* IOAPIC_IMF_ */
466 } ioapic_irqmaps[IOAPIC_HWI_VECTORS];
468 #define IOAPIC_IMT_UNUSED 0
469 #define IOAPIC_IMT_RESERVED 1
470 #define IOAPIC_IMT_LINE 2
471 #define IOAPIC_IMT_SYSCALL 3
473 #define IOAPIC_IMF_CONF 0x1
475 extern void IOAPIC_INTREN(int);
476 extern void IOAPIC_INTRDIS(int);
478 extern int imcr_present;
480 static void ioapic_abi_intr_enable(int);
481 static void ioapic_abi_intr_disable(int);
482 static void ioapic_abi_intr_setup(int, int);
483 static void ioapic_abi_intr_teardown(int);
484 static void ioapic_abi_intr_config(int,
485 enum intr_trigger, enum intr_polarity);
486 static int ioapic_abi_intr_cpuid(int);
488 static void ioapic_abi_finalize(void);
489 static void ioapic_abi_cleanup(void);
490 static void ioapic_abi_setdefault(void);
491 static void ioapic_abi_stabilize(void);
492 static void ioapic_abi_initmap(void);
494 static int ioapic_abi_gsi_cpuid(int, int);
496 struct machintr_abi MachIntrABI_IOAPIC = {
498 .intr_disable = ioapic_abi_intr_disable,
499 .intr_enable = ioapic_abi_intr_enable,
500 .intr_setup = ioapic_abi_intr_setup,
501 .intr_teardown = ioapic_abi_intr_teardown,
502 .intr_config = ioapic_abi_intr_config,
503 .intr_cpuid = ioapic_abi_intr_cpuid,
505 .finalize = ioapic_abi_finalize,
506 .cleanup = ioapic_abi_cleanup,
507 .setdefault = ioapic_abi_setdefault,
508 .stabilize = ioapic_abi_stabilize,
509 .initmap = ioapic_abi_initmap
512 static int ioapic_abi_extint_irq = -1;
513 static int ioapic_abi_line_irq_max;
515 struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
518 ioapic_abi_intr_enable(int irq)
520 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
521 kprintf("ioapic_abi_intr_enable invalid irq %d\n", irq);
528 ioapic_abi_intr_disable(int irq)
530 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
531 kprintf("ioapic_abi_intr_disable invalid irq %d\n", irq);
538 ioapic_abi_finalize(void)
540 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
541 KKASSERT(ioapic_enable);
544 * If an IMCR is present, program bit 0 to disconnect the 8259
548 outb(0x22, 0x70); /* select IMCR */
549 outb(0x23, 0x01); /* disconnect 8259 */
554 * This routine is called after physical interrupts are enabled but before
555 * the critical section is released. We need to clean out any interrupts
556 * that had already been posted to the cpu.
559 ioapic_abi_cleanup(void)
561 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
564 /* Must never be called */
566 ioapic_abi_stabilize(void)
568 panic("ioapic_stabilize is called\n");
572 ioapic_abi_intr_setup(int intr, int flags)
578 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
579 intr != IOAPIC_HWI_SYSCALL);
580 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
585 vector = IDT_OFFSET + intr;
588 * Now reprogram the vector in the IO APIC. In order to avoid
589 * losing an EOI for a level interrupt, which is vector based,
590 * make sure that the IO APIC is programmed for edge-triggering
591 * first, then reprogrammed with the new vector. This should
596 select = ioapic_irqs[intr].io_idx;
597 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
598 value |= IOART_INTMSET;
600 ioapic_write(ioapic_irqs[intr].io_addr, select,
601 (value & ~APIC_TRIGMOD_MASK));
602 ioapic_write(ioapic_irqs[intr].io_addr, select,
603 (value & ~IOART_INTVEC) | vector);
607 machintr_intr_enable(intr);
613 ioapic_abi_intr_teardown(int intr)
619 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
620 intr != IOAPIC_HWI_SYSCALL);
621 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
627 * Teardown an interrupt vector. The vector should already be
628 * installed in the cpu's IDT, but make sure.
630 machintr_intr_disable(intr);
632 vector = IDT_OFFSET + intr;
635 * In order to avoid losing an EOI for a level interrupt, which
636 * is vector based, make sure that the IO APIC is programmed for
637 * edge-triggering first, then reprogrammed with the new vector.
638 * This should clear the IRR bit.
642 select = ioapic_irqs[intr].io_idx;
643 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
645 ioapic_write(ioapic_irqs[intr].io_addr, select,
646 (value & ~APIC_TRIGMOD_MASK));
647 ioapic_write(ioapic_irqs[intr].io_addr, select,
648 (value & ~IOART_INTVEC) | vector);
656 ioapic_abi_setdefault(void)
660 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
661 if (intr == IOAPIC_HWI_SYSCALL)
663 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
669 ioapic_abi_initmap(void)
673 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
674 ioapic_irqmaps[i].im_gsi = -1;
675 ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
679 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
680 enum intr_polarity pola)
682 struct ioapic_irqinfo *info;
683 struct ioapic_irqmap *map;
687 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
688 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
690 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
691 if (irq > ioapic_abi_line_irq_max)
692 ioapic_abi_line_irq_max = irq;
694 map = &ioapic_irqmaps[irq];
696 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
697 map->im_type = IOAPIC_IMT_LINE;
704 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
706 intr_str_trigger(map->im_trig),
707 intr_str_polarity(map->im_pola));
710 pin = ioapic_gsi_pin(map->im_gsi);
711 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
713 cpuid = ioapic_abi_gsi_cpuid(irq, map->im_gsi);
715 info = &ioapic_irqs[irq];
719 info->io_addr = ioaddr;
720 info->io_idx = IOAPIC_REDTBL + (2 * pin);
721 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
722 if (map->im_trig == INTR_TRIGGER_LEVEL)
723 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
725 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
726 map->im_trig, map->im_pola, cpuid);
732 ioapic_abi_fixup_irqmap(void)
736 for (i = 0; i < ISA_IRQ_CNT; ++i) {
737 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
739 if (map->im_type == IOAPIC_IMT_UNUSED) {
740 map->im_type = IOAPIC_IMT_RESERVED;
742 kprintf("IOAPIC: irq %d reserved\n", i);
745 ioapic_abi_line_irq_max += 1;
747 kprintf("IOAPIC: line irq max %d\n", ioapic_abi_line_irq_max);
751 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
755 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
756 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
758 for (irq = 0; irq < ioapic_abi_line_irq_max; ++irq) {
759 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
761 if (map->im_gsi == gsi) {
762 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
764 if (map->im_flags & IOAPIC_IMF_CONF) {
765 if (map->im_trig != trig ||
766 map->im_pola != pola)
776 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
778 const struct ioapic_irqmap *map;
780 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
781 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
783 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
785 map = &ioapic_irqmaps[irq];
787 if (map->im_type != IOAPIC_IMT_LINE)
790 if (map->im_flags & IOAPIC_IMF_CONF) {
791 if (map->im_trig != trig || map->im_pola != pola)
798 ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
800 struct ioapic_irqinfo *info;
801 struct ioapic_irqmap *map;
805 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
806 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
808 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
809 map = &ioapic_irqmaps[irq];
811 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
814 if (map->im_flags & IOAPIC_IMF_CONF) {
815 if (trig != map->im_trig) {
816 panic("ioapic_intr_config: trig %s -> %s\n",
817 intr_str_trigger(map->im_trig),
818 intr_str_trigger(trig));
820 if (pola != map->im_pola) {
821 panic("ioapic_intr_config: pola %s -> %s\n",
822 intr_str_polarity(map->im_pola),
823 intr_str_polarity(pola));
828 map->im_flags |= IOAPIC_IMF_CONF;
830 if (trig == map->im_trig && pola == map->im_pola)
834 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
836 intr_str_trigger(map->im_trig),
837 intr_str_polarity(map->im_pola),
838 intr_str_trigger(trig),
839 intr_str_polarity(pola));
844 pin = ioapic_gsi_pin(map->im_gsi);
845 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
847 cpuid = ioapic_abi_gsi_cpuid(irq, map->im_gsi);
849 info = &ioapic_irqs[irq];
853 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
854 if (map->im_trig == INTR_TRIGGER_LEVEL)
855 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
857 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
858 map->im_trig, map->im_pola, cpuid);
864 ioapic_abi_extint_irqmap(int irq)
866 struct ioapic_irqinfo *info;
867 struct ioapic_irqmap *map;
871 /* XXX only irq0 is allowed */
874 vec = IDT_OFFSET + irq;
876 if (ioapic_abi_extint_irq == irq)
878 else if (ioapic_abi_extint_irq >= 0)
881 error = icu_ioapic_extint(irq, vec);
885 map = &ioapic_irqmaps[irq];
887 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
888 map->im_type == IOAPIC_IMT_LINE);
889 if (map->im_type == IOAPIC_IMT_LINE) {
890 if (map->im_flags & IOAPIC_IMF_CONF)
893 ioapic_abi_extint_irq = irq;
895 map->im_type = IOAPIC_IMT_LINE;
896 map->im_trig = INTR_TRIGGER_EDGE;
897 map->im_pola = INTR_POLARITY_HIGH;
898 map->im_flags = IOAPIC_IMF_CONF;
900 map->im_gsi = ioapic_extpin_gsi();
901 KKASSERT(map->im_gsi >= 0);
904 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
906 intr_str_trigger(map->im_trig),
907 intr_str_polarity(map->im_pola));
910 pin = ioapic_gsi_pin(map->im_gsi);
911 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
913 info = &ioapic_irqs[irq];
917 info->io_addr = ioaddr;
918 info->io_idx = IOAPIC_REDTBL + (2 * pin);
919 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
921 ioapic_extpin_setup(ioaddr, pin, vec);
929 ioapic_abi_intr_cpuid(int irq)
931 const struct ioapic_irqmap *map;
933 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
934 map = &ioapic_irqmaps[irq];
936 if (map->im_type == IOAPIC_IMT_RESERVED) {
937 /* XXX some drivers tries to peek at IRQ 2 */
941 KASSERT(map->im_type == IOAPIC_IMT_LINE,
942 ("invalid irq %d, type %d\n", irq, map->im_type));
943 KKASSERT(map->im_gsi >= 0);
945 return ioapic_abi_gsi_cpuid(irq, map->im_gsi);
949 ioapic_abi_gsi_cpuid(int irq, int gsi)
956 if (irq == 0 || gsi == 0) {
958 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
964 if (irq == acpi_sci_irqno()) {
966 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
972 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
973 kgetenv_int(envpath, &cpuid);
978 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
981 } else if (cpuid >= ncpus) {
984 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
989 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",