2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
38 #include <sys/cpu_topology.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/lapic.h>
60 #include <machine_base/apic/ioapic.h>
61 #include <machine_base/acpica/acpi_md_cpu.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
68 #include <machine/clock.h>
70 #include <machine/md_var.h> /* setidt() */
71 #include <machine_base/icu/icu.h> /* IPIs */
72 #include <machine_base/icu/icu_var.h>
73 #include <machine_base/apic/ioapic_abi.h>
74 #include <machine/intr_machdep.h> /* IPIs */
76 #define WARMBOOT_TARGET 0
77 #define WARMBOOT_OFF (KERNBASE + 0x0467)
78 #define WARMBOOT_SEG (KERNBASE + 0x0469)
80 #define CMOS_REG (0x70)
81 #define CMOS_DATA (0x71)
82 #define BIOS_RESET (0x0f)
83 #define BIOS_WARM (0x0a)
86 * this code MUST be enabled here and in mpboot.s.
87 * it follows the very early stages of AP boot by placing values in CMOS ram.
88 * it NORMALLY will never be needed and thus the primitive method for enabling.
91 #if defined(CHECK_POINTS)
92 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
93 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
95 #define CHECK_INIT(D); \
96 CHECK_WRITE(0x34, (D)); \
97 CHECK_WRITE(0x35, (D)); \
98 CHECK_WRITE(0x36, (D)); \
99 CHECK_WRITE(0x37, (D)); \
100 CHECK_WRITE(0x38, (D)); \
101 CHECK_WRITE(0x39, (D));
103 #define CHECK_PRINT(S); \
104 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
113 #else /* CHECK_POINTS */
115 #define CHECK_INIT(D)
116 #define CHECK_PRINT(S)
118 #endif /* CHECK_POINTS */
121 * Values to send to the POST hardware.
123 #define MP_BOOTADDRESS_POST 0x10
124 #define MP_PROBE_POST 0x11
125 #define MPTABLE_PASS1_POST 0x12
127 #define MP_START_POST 0x13
128 #define MP_ENABLE_POST 0x14
129 #define MPTABLE_PASS2_POST 0x15
131 #define START_ALL_APS_POST 0x16
132 #define INSTALL_AP_TRAMP_POST 0x17
133 #define START_AP_POST 0x18
135 #define MP_ANNOUNCE_POST 0x19
137 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
138 int current_postcode;
140 /** XXX FIXME: what system files declare these??? */
141 extern struct region_descriptor r_gdt;
147 extern int64_t tsc_offsets[];
149 /* AP uses this during bootstrap. Do not staticize. */
153 struct pcb stoppcbs[MAXCPU];
155 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
158 * Local data and functions.
161 static u_int boot_address;
162 static int mp_finish;
163 static int mp_finish_lapic;
165 static int start_all_aps(u_int boot_addr);
167 static void install_ap_tramp(u_int boot_addr);
169 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
170 static int smitest(void);
171 static void mp_bsp_simple_setup(void);
173 /* which cpus have been started */
174 static cpumask_t smp_startup_mask = CPUMASK_INITIALIZER_ONLYONE;
175 /* which cpus have lapic been inited */
176 static cpumask_t smp_lapic_mask = CPUMASK_INITIALIZER_ONLYONE;
177 /* which cpus are ready for IPIs etc? */
178 cpumask_t smp_active_mask = CPUMASK_INITIALIZER_ONLYONE;
179 cpumask_t smp_finalize_mask = CPUMASK_INITIALIZER_ONLYONE;
181 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
182 static u_int bootMP_size;
183 static u_int report_invlpg_src;
184 SYSCTL_INT(_machdep, OID_AUTO, report_invlpg_src, CTLFLAG_RW,
185 &report_invlpg_src, 0, "");
186 static u_int report_invltlb_src;
187 SYSCTL_INT(_machdep, OID_AUTO, report_invltlb_src, CTLFLAG_RW,
188 &report_invltlb_src, 0, "");
189 static int optimized_invltlb;
190 SYSCTL_INT(_machdep, OID_AUTO, optimized_invltlb, CTLFLAG_RW,
191 &optimized_invltlb, 0, "");
192 static int all_but_self_ipi_enable = 1;
193 SYSCTL_INT(_machdep, OID_AUTO, all_but_self_ipi_enable, CTLFLAG_RW,
194 &all_but_self_ipi_enable, 0, "");
196 /* Local data for detecting CPU TOPOLOGY */
197 static int core_bits = 0;
198 static int logical_CPU_bits = 0;
202 * Calculate usable address in base memory for AP trampoline code.
205 mp_bootaddress(u_int basemem)
207 POSTCODE(MP_BOOTADDRESS_POST);
209 bootMP_size = mptramp_end - mptramp_start;
210 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
211 if (((basemem * 1024) - boot_address) < bootMP_size)
212 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
213 /* 3 levels of page table pages */
214 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
216 return mptramp_pagetables;
220 * Print various information about the SMP system hardware and setup.
227 POSTCODE(MP_ANNOUNCE_POST);
229 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
230 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
231 for (x = 1; x <= naps; ++x)
232 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
235 kprintf(" Warning: APIC I/O disabled\n");
239 * AP cpu's call this to sync up protected mode.
241 * WARNING! %gs is not set up on entry. This routine sets up %gs.
247 int x, myid = bootAP;
249 struct mdglobaldata *md;
250 struct privatespace *ps;
252 ps = CPU_prvspace[myid];
254 gdt_segs[GPROC0_SEL].ssd_base =
255 (long) &ps->mdglobaldata.gd_common_tss;
256 ps->mdglobaldata.mi.gd_prvspace = ps;
258 /* We fill the 32-bit segment descriptors */
259 for (x = 0; x < NGDT; x++) {
260 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
261 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
263 /* And now a 64-bit one */
264 ssdtosyssd(&gdt_segs[GPROC0_SEL],
265 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
267 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
268 r_gdt.rd_base = (long) &gdt[myid * NGDT];
269 lgdt(&r_gdt); /* does magic intra-segment return */
271 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
272 wrmsr(MSR_FSBASE, 0); /* User value */
273 wrmsr(MSR_GSBASE, (u_int64_t)ps);
274 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
276 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]);
280 mdcpu->gd_currentldt = _default_ldt;
283 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
284 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
286 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
288 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
290 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
292 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
293 md->gd_common_tssd = *md->gd_tss_gdt;
295 /* double fault stack */
296 md->gd_common_tss.tss_ist1 =
297 (long)&md->mi.gd_prvspace->idlestack[
298 sizeof(md->mi.gd_prvspace->idlestack)];
303 * Set to a known state:
304 * Set by mpboot.s: CR0_PG, CR0_PE
305 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
308 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
311 /* Set up the fast syscall stuff */
312 msr = rdmsr(MSR_EFER) | EFER_SCE;
313 wrmsr(MSR_EFER, msr);
314 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
315 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
316 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
317 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
318 wrmsr(MSR_STAR, msr);
319 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
321 pmap_set_opt(); /* PSE/4MB pages, etc */
322 pmap_init_pat(); /* Page Attribute Table */
324 /* set up CPU registers and state */
327 /* set up SSE/NX registers */
330 /* set up FPU state on the AP */
333 /* disable the APIC, just to be SURE */
334 lapic->svr &= ~APIC_SVR_ENABLE;
337 /*******************************************************************
338 * local functions and data
342 * Start the SMP system
345 mp_start_aps(void *dummy __unused)
348 /* start each Application Processor */
349 start_all_aps(boot_address);
351 mp_bsp_simple_setup();
354 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL);
357 * start each AP in our list
360 start_all_aps(u_int boot_addr)
362 vm_offset_t va = boot_address + KERNBASE;
363 u_int64_t *pt4, *pt3, *pt2;
371 u_long mpbioswarmvec;
372 struct mdglobaldata *gd;
373 struct privatespace *ps;
376 POSTCODE(START_ALL_APS_POST);
378 /* install the AP 1st level boot code */
379 pmap_kenter(va, boot_address);
380 cpu_invlpg((void *)va); /* JG XXX */
381 bcopy(mptramp_start, (void *)va, bootMP_size);
383 /* Locate the page tables, they'll be below the trampoline */
384 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
385 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
386 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
388 /* Create the initial 1GB replicated page tables */
389 for (i = 0; i < 512; i++) {
390 /* Each slot of the level 4 pages points to the same level 3 page */
391 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
392 pt4[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
393 kernel_pmap.pmap_bits[PG_RW_IDX] |
394 kernel_pmap.pmap_bits[PG_U_IDX];
396 /* Each slot of the level 3 pages points to the same level 2 page */
397 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
398 pt3[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
399 kernel_pmap.pmap_bits[PG_RW_IDX] |
400 kernel_pmap.pmap_bits[PG_U_IDX];
402 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
403 pt2[i] = i * (2 * 1024 * 1024);
404 pt2[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
405 kernel_pmap.pmap_bits[PG_RW_IDX] |
406 kernel_pmap.pmap_bits[PG_PS_IDX] |
407 kernel_pmap.pmap_bits[PG_U_IDX];
410 /* save the current value of the warm-start vector */
411 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
412 outb(CMOS_REG, BIOS_RESET);
413 mpbiosreason = inb(CMOS_DATA);
415 /* setup a vector to our boot code */
416 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
417 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
418 outb(CMOS_REG, BIOS_RESET);
419 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
422 * If we have a TSC we can figure out the SMI interrupt rate.
423 * The SMI does not necessarily use a constant rate. Spend
424 * up to 250ms trying to figure it out.
427 if (cpu_feature & CPUID_TSC) {
428 set_apic_timer(275000);
429 smilast = read_apic_timer();
430 for (x = 0; x < 20 && read_apic_timer(); ++x) {
431 smicount = smitest();
432 if (smibest == 0 || smilast - smicount < smibest)
433 smibest = smilast - smicount;
436 if (smibest > 250000)
439 smibest = smibest * (int64_t)1000000 /
440 get_apic_timer_frequency();
444 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
445 1000000 / smibest, smibest);
448 for (x = 1; x <= naps; ++x) {
449 /* This is a bit verbose, it will go away soon. */
451 pssize = sizeof(struct privatespace);
452 ps = (void *)kmem_alloc(&kernel_map, pssize, VM_SUBSYS_GD);
453 CPU_prvspace[x] = ps;
455 kprintf("ps %d %p %d\n", x, ps, pssize);
458 gd = &ps->mdglobaldata;
459 gd->mi.gd_prvspace = ps;
461 /* prime data page for it to use */
462 mi_gdinit(&gd->mi, x);
464 ipiq_size = sizeof(struct lwkt_ipiq) * (naps + 1);
465 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size,
467 bzero(gd->mi.gd_ipiq, ipiq_size);
469 gd->gd_acpi_id = CPUID_TO_ACPIID(gd->mi.gd_cpuid);
471 /* setup a vector to our boot code */
472 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
473 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
474 outb(CMOS_REG, BIOS_RESET);
475 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
478 * Setup the AP boot stack
480 bootSTK = &ps->idlestack[UPAGES * PAGE_SIZE - PAGE_SIZE];
483 /* attempt to start the Application Processor */
484 CHECK_INIT(99); /* setup checkpoints */
485 if (!start_ap(gd, boot_addr, smibest)) {
486 kprintf("\nAP #%d (PHY# %d) failed!\n",
487 x, CPUID_TO_APICID(x));
488 CHECK_PRINT("trace"); /* show checkpoints */
489 /* better panic as the AP may be running loose */
490 kprintf("panic y/n? [y] ");
496 CHECK_PRINT("trace"); /* show checkpoints */
499 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
502 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
503 for (shift = 0; (1 << shift) <= ncpus; ++shift)
506 ncpus2_shift = shift;
508 ncpus2_mask = ncpus2 - 1;
510 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
511 if ((1 << shift) < ncpus)
513 ncpus_fit = 1 << shift;
514 ncpus_fit_mask = ncpus_fit - 1;
516 /* build our map of 'other' CPUs */
517 mycpu->gd_other_cpus = smp_startup_mask;
518 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
520 gd = (struct mdglobaldata *)mycpu;
521 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid);
523 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
524 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size,
526 bzero(mycpu->gd_ipiq, ipiq_size);
528 /* restore the warmstart vector */
529 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
530 outb(CMOS_REG, BIOS_RESET);
531 outb(CMOS_DATA, mpbiosreason);
534 * NOTE! The idlestack for the BSP was setup by locore. Finish
535 * up, clean out the P==V mapping we did earlier.
540 * Wait all APs to finish initializing LAPIC
543 kprintf("SMP: Waiting APs LAPIC initialization\n");
544 if (cpu_feature & CPUID_TSC)
545 tsc0_offset = rdtsc();
550 while (CPUMASK_CMPMASKNEQ(smp_lapic_mask, smp_startup_mask)) {
553 if (cpu_feature & CPUID_TSC)
554 tsc0_offset = rdtsc();
556 while (try_mplock() == 0) {
561 /* number of APs actually started */
567 * load the 1st level AP boot code into base memory.
570 /* targets for relocation */
571 extern void bigJump(void);
572 extern void bootCodeSeg(void);
573 extern void bootDataSeg(void);
574 extern void MPentry(void);
576 extern u_int mp_gdtbase;
581 install_ap_tramp(u_int boot_addr)
584 int size = *(int *) ((u_long) & bootMP_size);
585 u_char *src = (u_char *) ((u_long) bootMP);
586 u_char *dst = (u_char *) boot_addr + KERNBASE;
587 u_int boot_base = (u_int) bootMP;
592 POSTCODE(INSTALL_AP_TRAMP_POST);
594 for (x = 0; x < size; ++x)
598 * modify addresses in code we just moved to basemem. unfortunately we
599 * need fairly detailed info about mpboot.s for this to work. changes
600 * to mpboot.s might require changes here.
603 /* boot code is located in KERNEL space */
604 dst = (u_char *) boot_addr + KERNBASE;
606 /* modify the lgdt arg */
607 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
608 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
610 /* modify the ljmp target for MPentry() */
611 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
612 *dst32 = ((u_int) MPentry - KERNBASE);
614 /* modify the target for boot code segment */
615 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
616 dst8 = (u_int8_t *) (dst16 + 1);
617 *dst16 = (u_int) boot_addr & 0xffff;
618 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
620 /* modify the target for boot data segment */
621 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
622 dst8 = (u_int8_t *) (dst16 + 1);
623 *dst16 = (u_int) boot_addr & 0xffff;
624 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
630 * This function starts the AP (application processor) identified
631 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
632 * to accomplish this. This is necessary because of the nuances
633 * of the different hardware we might encounter. It ain't pretty,
634 * but it seems to work.
636 * NOTE: eventually an AP gets to ap_init(), which is called just
637 * before the AP goes into the LWKT scheduler's idle loop.
640 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
644 u_long icr_lo, icr_hi;
646 POSTCODE(START_AP_POST);
648 /* get the PHYSICAL APIC ID# */
649 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
651 /* calculate the vector */
652 vector = (boot_addr >> 12) & 0xff;
654 /* We don't want anything interfering */
657 /* Make sure the target cpu sees everything */
661 * Try to detect when a SMI has occurred, wait up to 200ms.
663 * If a SMI occurs during an AP reset but before we issue
664 * the STARTUP command, the AP may brick. To work around
665 * this problem we hold off doing the AP startup until
666 * after we have detected the SMI. Hopefully another SMI
667 * will not occur before we finish the AP startup.
669 * Retries don't seem to help. SMIs have a window of opportunity
670 * and if USB->legacy keyboard emulation is enabled in the BIOS
671 * the interrupt rate can be quite high.
673 * NOTE: Don't worry about the L1 cache load, it might bloat
674 * ldelta a little but ndelta will be so huge when the SMI
675 * occurs the detection logic will still work fine.
678 set_apic_timer(200000);
683 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
684 * and running the target CPU. OR this INIT IPI might be latched (P5
685 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
688 * see apic/apicreg.h for icr bit definitions.
690 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
694 * Setup the address for the target AP. We can setup
695 * icr_hi once and then just trigger operations with
698 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
699 icr_hi |= (physical_cpu << 24);
700 icr_lo = lapic->icr_lo & 0xfff00000;
701 lapic->icr_hi = icr_hi;
704 * Do an INIT IPI: assert RESET
706 * Use edge triggered mode to assert INIT
708 lapic->icr_lo = icr_lo | 0x00004500;
709 while (lapic->icr_lo & APIC_DELSTAT_MASK)
713 * The spec calls for a 10ms delay but we may have to use a
714 * MUCH lower delay to avoid bricking an AP due to a fast SMI
715 * interrupt. We have other loops here too and dividing by 2
716 * doesn't seem to be enough even after subtracting 350us,
719 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
720 * interrupt was detected we use the full 10ms.
724 else if (smibest < 150 * 4 + 350)
726 else if ((smibest - 350) / 4 < 10000)
727 u_sleep((smibest - 350) / 4);
732 * Do an INIT IPI: deassert RESET
734 * Use level triggered mode to deassert. It is unclear
735 * why we need to do this.
737 lapic->icr_lo = icr_lo | 0x00008500;
738 while (lapic->icr_lo & APIC_DELSTAT_MASK)
740 u_sleep(150); /* wait 150us */
743 * Next we do a STARTUP IPI: the previous INIT IPI might still be
744 * latched, (P5 bug) this 1st STARTUP would then terminate
745 * immediately, and the previously started INIT IPI would continue. OR
746 * the previous INIT IPI has already run. and this STARTUP IPI will
747 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
750 lapic->icr_lo = icr_lo | 0x00000600 | vector;
751 while (lapic->icr_lo & APIC_DELSTAT_MASK)
753 u_sleep(200); /* wait ~200uS */
756 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
757 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
758 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
759 * recognized after hardware RESET or INIT IPI.
761 lapic->icr_lo = icr_lo | 0x00000600 | vector;
762 while (lapic->icr_lo & APIC_DELSTAT_MASK)
765 /* Resume normal operation */
768 /* wait for it to start, see ap_init() */
769 set_apic_timer(5000000);/* == 5 seconds */
770 while (read_apic_timer()) {
771 if (CPUMASK_TESTBIT(smp_startup_mask, gd->mi.gd_cpuid))
772 return 1; /* return SUCCESS */
775 return 0; /* return FAILURE */
790 while (read_apic_timer()) {
792 for (count = 0; count < 100; ++count)
793 ntsc = rdtsc(); /* force loop to occur */
795 ndelta = ntsc - ltsc;
798 if (ndelta > ldelta * 2)
801 ldelta = ntsc - ltsc;
804 return(read_apic_timer());
808 * Synchronously flush the TLB on all other CPU's. The current cpu's
809 * TLB is not flushed. If the caller wishes to flush the current cpu's
810 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
812 * This routine may be called concurrently from multiple cpus. When this
813 * happens, smp_invltlb() can wind up sticking around in the confirmation
814 * while() loop at the end as additional cpus are added to the global
815 * cpumask, until they are acknowledged by another IPI.
817 * NOTE: If for some reason we were unable to start all cpus we cannot
818 * safely use broadcast IPIs.
821 cpumask_t smp_smurf_mask;
822 static cpumask_t smp_invltlb_mask;
825 cpumask_t smp_in_mask;
827 cpumask_t smp_invmask;
828 extern cpumask_t smp_idleinvl_mask;
829 extern cpumask_t smp_idleinvl_reqs;
832 * Atomically OR bits in *mask to smp_smurf_mask. Adjust *mask to remove
833 * bits that do not need to be IPId. These bits are still part of the command,
834 * but the target cpus have already been signalled and do not need to be
837 #include <sys/spinlock.h>
838 #include <sys/spinlock2.h>
842 smp_smurf_fetchset(cpumask_t *mask)
850 while (i < CPUMASK_ELEMENTS) {
851 obits = smp_smurf_mask.ary[i];
853 nbits = obits | mask->ary[i];
854 if (atomic_cmpset_long(&smp_smurf_mask.ary[i], obits, nbits)) {
855 omask.ary[i] = obits;
859 CPUMASK_NANDMASK(*mask, omask);
863 * This is a mechanism which guarantees that cpu_invltlb() will be executed
864 * on idle cpus without having to signal or wake them up. The invltlb will be
865 * executed when they wake up, prior to any scheduling or interrupt thread.
867 * (*mask) is modified to remove the cpus we successfully negotiate this
868 * function with. This function may only be used with semi-synchronous
869 * commands (typically invltlb's or semi-synchronous invalidations which
870 * are usually associated only with kernel memory).
873 smp_smurf_idleinvlclr(cpumask_t *mask)
875 if (optimized_invltlb) {
876 ATOMIC_CPUMASK_ORMASK(smp_idleinvl_reqs, *mask);
877 /* cpu_lfence() not needed */
878 CPUMASK_NANDMASK(*mask, smp_idleinvl_mask);
883 * Issue cpu_invltlb() across all cpus except the current cpu.
885 * This function will arrange to avoid idle cpus, but still gurantee that
886 * invltlb is run on them when they wake up prior to any scheduling or
892 struct mdglobaldata *md = mdcpu;
894 unsigned long rflags;
896 uint64_t tsc_base = rdtsc();
900 if (report_invltlb_src > 0) {
901 if (--report_invltlb_src <= 0)
906 * Disallow normal interrupts, set all active cpus except our own
907 * in the global smp_invltlb_mask.
909 ++md->mi.gd_cnt.v_smpinvltlb;
910 crit_enter_gd(&md->mi);
913 * Bits we want to set in smp_invltlb_mask. We do not want to signal
914 * our own cpu. Also try to remove bits associated with idle cpus
915 * that we can flag for auto-invltlb.
917 mask = smp_active_mask;
918 CPUMASK_NANDBIT(mask, md->mi.gd_cpuid);
919 smp_smurf_idleinvlclr(&mask);
921 rflags = read_rflags();
923 ATOMIC_CPUMASK_ORMASK(smp_invltlb_mask, mask);
926 * IPI non-idle cpus represented by mask. The omask calculation
927 * removes cpus from the mask which already have a Xinvltlb IPI
928 * pending (avoid double-queueing the IPI).
930 * We must disable real interrupts when setting the smurf flags or
931 * we might race a XINVLTLB before we manage to send the ipi's for
934 * NOTE: We are not signalling ourselves, mask already does NOT
935 * include our own cpu.
937 smp_smurf_fetchset(&mask);
940 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
941 * the critical section count on the target cpus.
943 CPUMASK_ORMASK(mask, md->mi.gd_cpumask);
944 if (all_but_self_ipi_enable &&
945 CPUMASK_CMPMASKEQ(smp_startup_mask, mask)) {
946 all_but_self_ipi(XINVLTLB_OFFSET);
948 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask);
949 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
953 * Wait for acknowledgement by all cpus. smp_inval_intr() will
954 * temporarily enable interrupts to avoid deadlocking the lapic,
955 * and will also handle running cpu_invltlb() and remote invlpg
956 * command son our cpu if some other cpu requests it of us.
958 * WARNING! I originally tried to implement this as a hard loop
959 * checking only smp_invltlb_mask (and issuing a local
960 * cpu_invltlb() if requested), with interrupts enabled
961 * and without calling smp_inval_intr(). This DID NOT WORK.
962 * It resulted in weird races where smurf bits would get
963 * cleared without any action being taken.
966 CPUMASK_ASSZERO(mask);
967 while (CPUMASK_CMPMASKNEQ(smp_invltlb_mask, mask)) {
971 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) {
972 kprintf("smp_invltlb %d: waited too long %08jx "
975 smp_invltlb_mask.ary[0],
976 smp_idleinvl_mask.ary[0],
977 smp_idleinvl_reqs.ary[0]);
978 mdcpu->gd_xinvaltlb = 0;
979 ATOMIC_CPUMASK_NANDMASK(smp_smurf_mask,
981 smp_invlpg(&smp_active_mask);
983 if (++repeats > 10) {
984 kprintf("smp_invltlb: giving up\n");
985 CPUMASK_ASSZERO(smp_invltlb_mask);
990 write_rflags(rflags);
991 crit_exit_gd(&md->mi);
995 * Called from a critical section with interrupts hard-disabled.
996 * This function issues an XINVLTLB IPI and then executes any pending
997 * command on the current cpu before returning.
1000 smp_invlpg(cpumask_t *cmdmask)
1002 struct mdglobaldata *md = mdcpu;
1005 if (report_invlpg_src > 0) {
1006 if (--report_invlpg_src <= 0)
1011 * Disallow normal interrupts, set all active cpus in the pmap,
1012 * plus our own for completion processing (it might or might not
1013 * be part of the set).
1015 mask = smp_active_mask;
1016 CPUMASK_ANDMASK(mask, *cmdmask);
1017 CPUMASK_ORMASK(mask, md->mi.gd_cpumask);
1020 * Avoid double-queuing IPIs, which can deadlock us. We must disable
1021 * real interrupts when setting the smurf flags or we might race a
1022 * XINVLTLB before we manage to send the ipi's for the bits we set.
1024 * NOTE: We might be including our own cpu in the smurf mask.
1026 smp_smurf_fetchset(&mask);
1029 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
1030 * the critical section count on the target cpus.
1032 * We do not include our own cpu when issuing the IPI.
1034 if (all_but_self_ipi_enable &&
1035 CPUMASK_CMPMASKEQ(smp_startup_mask, mask)) {
1036 all_but_self_ipi(XINVLTLB_OFFSET);
1038 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask);
1039 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1043 * This will synchronously wait for our command to complete,
1044 * as well as process commands from other cpus. It also handles
1047 * (interrupts are disabled and we are in a critical section here)
1055 globaldata_t gd = mycpu;
1059 * Ignore all_but_self_ipi_enable here and just use it.
1061 all_but_self_ipi(XSNIFF_OFFSET);
1062 gd->gd_sample_pc = smp_sniff;
1063 gd->gd_sample_sp = &dummy;
1067 * Called from Xinvltlb assembly with interrupts hard-disabled and in a
1068 * critical section. gd_intr_nesting_level may or may not be bumped
1069 * depending on entry.
1071 * THIS CODE IS INTENDED TO EXPLICITLY IGNORE THE CRITICAL SECTION COUNT.
1072 * THAT IS, THE INTERRUPT IS INTENDED TO FUNCTION EVEN WHEN MAINLINE CODE
1073 * IS IN A CRITICAL SECTION.
1076 smp_inval_intr(void)
1078 struct mdglobaldata *md = mdcpu;
1081 uint64_t tsc_base = rdtsc();
1086 * The idle code is in a critical section, but that doesn't stop
1087 * Xinvltlb from executing, so deal with the race which can occur
1088 * in that situation. Otherwise r-m-w operations by pmap_inval_intr()
1089 * may have problems.
1091 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs, md->mi.gd_cpuid)) {
1092 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask, md->mi.gd_cpuid);
1099 * This is a real mess. I'd like to just leave interrupts disabled
1100 * but it can cause the lapic to deadlock if too many interrupts queue
1101 * to it, due to the idiotic design of the lapic. So instead we have
1102 * to enter a critical section so normal interrupts are made pending
1103 * and track whether this one was reentered.
1105 if (md->gd_xinvaltlb) { /* reentrant on cpu */
1106 md->gd_xinvaltlb = 2;
1109 md->gd_xinvaltlb = 1;
1112 * Check only those cpus with active Xinvl* commands pending.
1114 * We are going to enable interrupts so make sure we are in a
1115 * critical section. This is necessary to avoid deadlocking
1116 * the lapic and to ensure that we execute our commands prior to
1117 * any nominal interrupt or preemption.
1119 * WARNING! It is very important that we only clear out but in
1120 * smp_smurf_mask once for each interrupt we take. In
1121 * this case, we clear it on initial entry and only loop
1122 * on the reentrancy detect (caused by another interrupt).
1124 cpumask = smp_invmask;
1128 ATOMIC_CPUMASK_ORBIT(smp_in_mask, md->mi.gd_cpuid);
1130 ATOMIC_CPUMASK_NANDBIT(smp_smurf_mask, md->mi.gd_cpuid);
1133 * Specific page request(s), and we can't return until all bits
1140 * Also execute any pending full invalidation request in
1143 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) {
1144 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask,
1151 if (tsc_frequency && rdtsc() - tsc_base > tsc_frequency) {
1152 kprintf("smp_inval_intr %d inv=%08jx tlbm=%08jx "
1153 "idle=%08jx/%08jx\n",
1156 smp_invltlb_mask.ary[0],
1157 smp_idleinvl_mask.ary[0],
1158 smp_idleinvl_reqs.ary[0]);
1169 * We can only add bits to the cpumask to test during the
1170 * loop because the smp_invmask bit is cleared once the
1171 * originator completes the command (the targets may still
1172 * be cycling their own completions in this loop, afterwords).
1174 * lfence required prior to all tests as this Xinvltlb
1175 * interrupt could race the originator (already be in progress
1176 * wnen the originator decides to issue, due to an issue by
1180 CPUMASK_ORMASK(cpumask, smp_invmask);
1181 /*cpumask = smp_active_mask;*/ /* XXX */
1183 if (pmap_inval_intr(&cpumask, toolong) == 0) {
1185 * Clear our smurf mask to allow new IPIs, but deal
1186 * with potential races.
1192 * Test if someone sent us another invalidation IPI, break
1193 * out so we can take it to avoid deadlocking the lapic
1194 * interrupt queue (? stupid intel, amd).
1196 if (md->gd_xinvaltlb == 2)
1199 if (CPUMASK_TESTBIT(smp_smurf_mask, md->mi.gd_cpuid))
1205 * Full invalidation request
1207 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) {
1208 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask,
1215 ATOMIC_CPUMASK_NANDBIT(smp_in_mask, md->mi.gd_cpuid);
1218 * Check to see if another Xinvltlb interrupt occurred and loop up
1222 if (md->gd_xinvaltlb == 2) {
1223 md->gd_xinvaltlb = 1;
1226 md->gd_xinvaltlb = 0;
1230 cpu_wbinvd_on_all_cpus_callback(void *arg)
1236 * When called the executing CPU will send an IPI to all other CPUs
1237 * requesting that they halt execution.
1239 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1241 * - Signals all CPUs in map to stop.
1242 * - Waits for each to stop.
1249 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1250 * from executing at same time.
1253 stop_cpus(cpumask_t map)
1257 CPUMASK_ANDMASK(map, smp_active_mask);
1259 /* send the Xcpustop IPI to all CPUs in map */
1260 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1263 mask = stopped_cpus;
1264 CPUMASK_ANDMASK(mask, map);
1266 } while (CPUMASK_CMPMASKNEQ(mask, map));
1273 * Called by a CPU to restart stopped CPUs.
1275 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1277 * - Signals all CPUs in map to restart.
1278 * - Waits for each to restart.
1286 restart_cpus(cpumask_t map)
1290 /* signal other cpus to restart */
1292 CPUMASK_ANDMASK(mask, smp_active_mask);
1294 started_cpus = mask;
1297 /* wait for each to clear its bit */
1298 while (CPUMASK_CMPMASKNEQ(stopped_cpus, map))
1305 * This is called once the mpboot code has gotten us properly relocated
1306 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1307 * and when it returns the scheduler will call the real cpu_idle() main
1308 * loop for the idlethread. Interrupts are disabled on entry and should
1309 * remain disabled at return.
1317 * Adjust smp_startup_mask to signal the BSP that we have started
1318 * up successfully. Note that we do not yet hold the BGL. The BSP
1319 * is waiting for our signal.
1321 * We can't set our bit in smp_active_mask yet because we are holding
1322 * interrupts physically disabled and remote cpus could deadlock
1323 * trying to send us an IPI.
1325 ATOMIC_CPUMASK_ORBIT(smp_startup_mask, mycpu->gd_cpuid);
1329 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1330 * non-zero, then get the MP lock.
1332 * Note: We are in a critical section.
1334 * Note: we are the idle thread, we can only spin.
1336 * Note: The load fence is memory volatile and prevents the compiler
1337 * from improperly caching mp_finish_lapic, and the cpu from improperly
1340 while (mp_finish_lapic == 0) {
1345 while (try_mplock() == 0) {
1351 if (cpu_feature & CPUID_TSC) {
1353 * The BSP is constantly updating tsc0_offset, figure out
1354 * the relative difference to synchronize ktrdump.
1356 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1359 /* BSP may have changed PTD while we're waiting for the lock */
1362 /* Build our map of 'other' CPUs. */
1363 mycpu->gd_other_cpus = smp_startup_mask;
1364 ATOMIC_CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
1366 /* A quick check from sanity claus */
1367 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1368 if (mycpu->gd_cpuid != cpu_id) {
1369 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1370 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1371 cpu_id, (lapic->id & 0xff000000) >> 24);
1373 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1375 panic("cpuid mismatch! boom!!");
1378 /* Initialize AP's local APIC for irq's */
1381 /* LAPIC initialization is done */
1382 ATOMIC_CPUMASK_ORBIT(smp_lapic_mask, mycpu->gd_cpuid);
1386 /* Let BSP move onto the next initialization stage */
1391 * Interlock for finalization. Wait until mp_finish is non-zero,
1392 * then get the MP lock.
1394 * Note: We are in a critical section.
1396 * Note: we are the idle thread, we can only spin.
1398 * Note: The load fence is memory volatile and prevents the compiler
1399 * from improperly caching mp_finish, and the cpu from improperly
1402 while (mp_finish == 0) {
1407 /* BSP may have changed PTD while we're waiting for the lock */
1410 /* Set memory range attributes for this CPU to match the BSP */
1411 mem_range_AP_init();
1414 * Once we go active we must process any IPIQ messages that may
1415 * have been queued, because no actual IPI will occur until we
1416 * set our bit in the smp_active_mask. If we don't the IPI
1417 * message interlock could be left set which would also prevent
1420 * The idle loop doesn't expect the BGL to be held and while
1421 * lwkt_switch() normally cleans things up this is a special case
1422 * because we returning almost directly into the idle loop.
1424 * The idle thread is never placed on the runq, make sure
1425 * nothing we've done put it there.
1429 * Hold a critical section and allow real interrupts to occur. Zero
1430 * any spurious interrupts which have accumulated, then set our
1431 * smp_active_mask indicating that we are fully operational.
1434 __asm __volatile("sti; pause; pause"::);
1435 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1436 ATOMIC_CPUMASK_ORBIT(smp_active_mask, mycpu->gd_cpuid);
1439 * Wait until all cpus have set their smp_active_mask and have fully
1440 * operational interrupts before proceeding.
1442 * We need a final cpu_invltlb() because we would not have received
1443 * any until we set our bit in smp_active_mask.
1445 while (mp_finish == 1) {
1452 * Initialize per-cpu clocks and do other per-cpu initialization.
1453 * At this point code is expected to be able to use the full kernel
1456 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1459 * Since we may have cleaned up the interrupt triggers, manually
1460 * process any pending IPIs before exiting our critical section.
1461 * Once the critical section has exited, normal interrupt processing
1464 atomic_swap_int(&mycpu->gd_npoll, 0);
1465 lwkt_process_ipiq();
1469 * Final final, allow the waiting BSP to resume the boot process,
1470 * return 'into' the idle thread bootstrap.
1472 ATOMIC_CPUMASK_ORBIT(smp_finalize_mask, mycpu->gd_cpuid);
1473 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1477 * Get SMP fully working before we start initializing devices.
1484 kprintf("Finish MP startup\n");
1488 * Wait for the active mask to complete, after which all cpus will
1489 * be accepting interrupts.
1492 while (CPUMASK_CMPMASKNEQ(smp_active_mask, smp_startup_mask)) {
1498 * Wait for the finalization mask to complete, after which all cpus
1499 * have completely finished initializing and are entering or are in
1500 * their idle thread.
1502 * BSP should have received all required invltlbs but do another
1507 while (CPUMASK_CMPMASKNEQ(smp_finalize_mask, smp_startup_mask)) {
1512 while (try_mplock() == 0) {
1518 kprintf("Active CPU Mask: %016jx\n",
1519 (uintmax_t)CPUMASK_LOWMASK(smp_active_mask));
1523 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL);
1526 cpu_send_ipiq(int dcpu)
1528 if (CPUMASK_TESTBIT(smp_active_mask, dcpu))
1529 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1532 #if 0 /* single_apic_ipi_passive() not working yet */
1534 * Returns 0 on failure, 1 on success
1537 cpu_send_ipiq_passive(int dcpu)
1540 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) {
1541 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1542 APIC_DELMODE_FIXED);
1549 mp_bsp_simple_setup(void)
1551 struct mdglobaldata *gd;
1554 /* build our map of 'other' CPUs */
1555 mycpu->gd_other_cpus = smp_startup_mask;
1556 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
1558 gd = (struct mdglobaldata *)mycpu;
1559 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid);
1561 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
1562 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size,
1564 bzero(mycpu->gd_ipiq, ipiq_size);
1568 if (cpu_feature & CPUID_TSC)
1569 tsc0_offset = rdtsc();
1574 * CPU TOPOLOGY DETECTION FUNCTIONS
1577 /* Detect intel topology using CPUID
1578 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41
1581 detect_intel_topology(int count_htt_cores)
1585 int core_plus_logical_bits = 0;
1586 int cores_per_package;
1587 int logical_per_package;
1588 int logical_per_core;
1591 if (cpu_high >= 0xb) {
1594 } else if (cpu_high >= 0x4) {
1599 for (shift = 0; (1 << shift) < count_htt_cores; ++shift)
1601 logical_CPU_bits = 1 << shift;
1606 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p);
1608 /* if 0xb not supported - fallback to 0x4 */
1609 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) {
1613 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]);
1615 ecx_index = FUNC_B_THREAD_LEVEL + 1;
1617 cpuid_count(0xb, ecx_index, p);
1619 /* Check for the Core type in the implemented sub leaves. */
1620 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) {
1621 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]);
1627 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE);
1629 core_bits = core_plus_logical_bits - logical_CPU_bits;
1634 cpuid_count(0x4, 0, p);
1635 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1;
1637 logical_per_package = count_htt_cores;
1638 logical_per_core = logical_per_package / cores_per_package;
1640 for (shift = 0; (1 << shift) < logical_per_core; ++shift)
1642 logical_CPU_bits = shift;
1644 for (shift = 0; (1 << shift) < cores_per_package; ++shift)
1651 /* Detect AMD topology using CPUID
1652 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page
1655 detect_amd_topology(int count_htt_cores)
1658 if ((cpu_feature & CPUID_HTT)
1659 && (amd_feature2 & AMDID2_CMP)) {
1661 if (cpu_procinfo2 & AMDID_COREID_SIZE) {
1662 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE)
1663 >> AMDID_COREID_SIZE_SHIFT;
1665 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
1666 for (shift = 0; (1 << shift) < core_bits; ++shift)
1671 logical_CPU_bits = count_htt_cores >> core_bits;
1672 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift)
1674 logical_CPU_bits = shift;
1676 for (shift = 0; (1 << shift) < count_htt_cores; ++shift)
1679 logical_CPU_bits = 0;
1684 amd_get_compute_unit_id(void *arg)
1688 do_cpuid(0x8000001e, regs);
1689 cpu_node_t * mynode = get_cpu_node_by_cpuid(mycpuid);
1691 * AMD - CPUID Specification September 2010
1692 * page 34 - //ComputeUnitID = ebx[0:7]//
1694 mynode->compute_unit_id = regs[1] & 0xff;
1698 fix_amd_topology(void)
1702 if (cpu_vendor_id != CPU_VENDOR_AMD)
1704 if ((amd_feature2 & AMDID2_TOPOEXT) == 0)
1707 CPUMASK_ASSALLONES(mask);
1708 lwkt_cpusync_simple(mask, amd_get_compute_unit_id, NULL);
1710 kprintf("Compute unit iDS:\n");
1712 for (i = 0; i < ncpus; i++) {
1713 kprintf("%d-%d; \n",
1714 i, get_cpu_node_by_cpuid(i)->compute_unit_id);
1721 * - logical_CPU_bits
1723 * With the values above (for AMD or INTEL) we are able to generally
1724 * detect the CPU topology (number of cores for each level):
1725 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1726 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf
1729 detect_cpu_topology(void)
1731 static int topology_detected = 0;
1734 if (topology_detected)
1736 if ((cpu_feature & CPUID_HTT) == 0) {
1738 logical_CPU_bits = 0;
1741 count = (cpu_procinfo & CPUID_HTT_CORES) >> CPUID_HTT_CORE_SHIFT;
1743 if (cpu_vendor_id == CPU_VENDOR_INTEL)
1744 detect_intel_topology(count);
1745 else if (cpu_vendor_id == CPU_VENDOR_AMD)
1746 detect_amd_topology(count);
1747 topology_detected = 1;
1751 kprintf("Bits within APICID: logical_CPU_bits: %d; core_bits: %d\n",
1752 logical_CPU_bits, core_bits);
1755 /* Interface functions to calculate chip_ID,
1756 * core_number and logical_number
1757 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1760 get_chip_ID(int cpuid)
1762 return get_apicid_from_cpuid(cpuid) >>
1763 (logical_CPU_bits + core_bits);
1767 get_core_number_within_chip(int cpuid)
1769 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) &
1770 ( (1 << core_bits) -1);
1774 get_logical_CPU_number_within_core(int cpuid)
1776 return get_apicid_from_cpuid(cpuid) &
1777 ( (1 << logical_CPU_bits) -1);