2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
46 #include <sys/machintr.h>
48 #include <machine/msi_machdep.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 extern struct dev_ops pcic_ops; /* XXX */
75 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
77 static uint32_t pci_mapbase(unsigned mapreg);
78 static const char *pci_maptype(unsigned mapreg);
79 static int pci_mapsize(unsigned testval);
80 static int pci_maprange(unsigned mapreg);
81 static void pci_fixancient(pcicfgregs *cfg);
83 static int pci_porten(device_t pcib, int b, int s, int f);
84 static int pci_memen(device_t pcib, int b, int s, int f);
85 static void pci_assign_interrupt(device_t bus, device_t dev,
87 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
88 int b, int s, int f, int reg,
89 struct resource_list *rl, int force, int prefetch);
90 static int pci_probe(device_t dev);
91 static int pci_attach(device_t dev);
92 static void pci_child_detached(device_t, device_t);
93 static void pci_load_vendor_data(void);
94 static int pci_describe_parse_line(char **ptr, int *vendor,
95 int *device, char **desc);
96 static char *pci_describe_device(device_t dev);
97 static int pci_modevent(module_t mod, int what, void *arg);
98 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
100 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
101 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t *data);
104 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
105 int reg, uint32_t data);
107 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
108 static void pci_disable_msi(device_t dev);
109 static void pci_enable_msi(device_t dev, uint64_t address,
111 static void pci_enable_msix(device_t dev, u_int index,
112 uint64_t address, uint32_t data);
113 static void pci_mask_msix(device_t dev, u_int index);
114 static void pci_unmask_msix(device_t dev, u_int index);
115 static int pci_msi_blacklisted(void);
116 static void pci_resume_msi(device_t dev);
117 static void pci_resume_msix(device_t dev);
118 static int pcie_slotimpl(const pcicfgregs *);
119 static void pci_print_verbose_expr(const pcicfgregs *);
121 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
122 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_subvendor(device_t, int, int,
128 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
129 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
131 static device_method_t pci_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, pci_probe),
134 DEVMETHOD(device_attach, pci_attach),
135 DEVMETHOD(device_detach, bus_generic_detach),
136 DEVMETHOD(device_shutdown, bus_generic_shutdown),
137 DEVMETHOD(device_suspend, pci_suspend),
138 DEVMETHOD(device_resume, pci_resume),
141 DEVMETHOD(bus_print_child, pci_print_child),
142 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
143 DEVMETHOD(bus_read_ivar, pci_read_ivar),
144 DEVMETHOD(bus_write_ivar, pci_write_ivar),
145 DEVMETHOD(bus_driver_added, pci_driver_added),
146 DEVMETHOD(bus_child_detached, pci_child_detached),
147 DEVMETHOD(bus_setup_intr, pci_setup_intr),
148 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
150 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
151 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
152 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
153 DEVMETHOD(bus_delete_resource, pci_delete_resource),
154 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
155 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
156 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
157 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
158 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
159 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
162 DEVMETHOD(pci_read_config, pci_read_config_method),
163 DEVMETHOD(pci_write_config, pci_write_config_method),
164 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
165 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
166 DEVMETHOD(pci_enable_io, pci_enable_io_method),
167 DEVMETHOD(pci_disable_io, pci_disable_io_method),
168 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
169 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
170 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
171 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
172 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
173 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
174 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
175 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
176 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
177 DEVMETHOD(pci_release_msi, pci_release_msi_method),
178 DEVMETHOD(pci_msi_count, pci_msi_count_method),
179 DEVMETHOD(pci_msix_count, pci_msix_count_method),
184 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
186 static devclass_t pci_devclass;
187 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
188 MODULE_VERSION(pci, 1);
190 static char *pci_vendordata;
191 static size_t pci_vendordata_size;
194 static const struct pci_read_cap {
196 pci_read_cap_t read_cap;
197 } pci_read_caps[] = {
198 { PCIY_PMG, pci_read_cap_pmgt },
199 { PCIY_HT, pci_read_cap_ht },
200 { PCIY_MSI, pci_read_cap_msi },
201 { PCIY_MSIX, pci_read_cap_msix },
202 { PCIY_VPD, pci_read_cap_vpd },
203 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
204 { PCIY_PCIX, pci_read_cap_pcix },
205 { PCIY_EXPRESS, pci_read_cap_express },
206 { 0, NULL } /* required last entry */
210 uint32_t devid; /* Vendor/device of the card */
212 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
213 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
218 struct pci_quirk pci_quirks[] = {
219 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
220 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
221 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 /* As does the Serverworks OSB4 (the SMBus mapping register) */
223 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
226 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
227 * or the CMIC-SL (AKA ServerWorks GC_LE).
229 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 * MSI doesn't work on earlier Intel chipsets including
234 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
236 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
245 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
248 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
253 /* map register information */
254 #define PCI_MAPMEM 0x01 /* memory map */
255 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
256 #define PCI_MAPPORT 0x04 /* port map */
258 struct devlist pci_devq;
259 uint32_t pci_generation;
260 uint32_t pci_numdevs = 0;
261 static int pcie_chipset, pcix_chipset;
264 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
266 static int pci_enable_io_modes = 1;
267 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
268 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
269 &pci_enable_io_modes, 1,
270 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
271 enable these bits correctly. We'd like to do this all the time, but there\n\
272 are some peripherals that this causes problems with.");
274 static int pci_do_power_nodriver = 0;
275 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
276 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
277 &pci_do_power_nodriver, 0,
278 "Place a function into D3 state when no driver attaches to it. 0 means\n\
279 disable. 1 means conservatively place devices into D3 state. 2 means\n\
280 aggressively place devices into D3 state. 3 means put absolutely everything\n\
283 static int pci_do_power_resume = 1;
284 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
285 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
286 &pci_do_power_resume, 1,
287 "Transition from D3 -> D0 on resume.");
289 static int pci_do_msi = 1;
290 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
291 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
292 "Enable support for MSI interrupts");
294 static int pci_do_msix = 0;
296 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
297 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
298 "Enable support for MSI-X interrupts");
301 static int pci_honor_msi_blacklist = 1;
302 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
303 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
304 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
306 /* Find a device_t by bus/slot/function in domain 0 */
309 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
312 return (pci_find_dbsf(0, bus, slot, func));
315 /* Find a device_t by domain/bus/slot/function */
318 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
320 struct pci_devinfo *dinfo;
322 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
323 if ((dinfo->cfg.domain == domain) &&
324 (dinfo->cfg.bus == bus) &&
325 (dinfo->cfg.slot == slot) &&
326 (dinfo->cfg.func == func)) {
327 return (dinfo->cfg.dev);
334 /* Find a device_t by vendor/device ID */
337 pci_find_device(uint16_t vendor, uint16_t device)
339 struct pci_devinfo *dinfo;
341 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
342 if ((dinfo->cfg.vendor == vendor) &&
343 (dinfo->cfg.device == device)) {
344 return (dinfo->cfg.dev);
351 /* return base address of memory or port map */
354 pci_mapbase(uint32_t mapreg)
357 if (PCI_BAR_MEM(mapreg))
358 return (mapreg & PCIM_BAR_MEM_BASE);
360 return (mapreg & PCIM_BAR_IO_BASE);
363 /* return map type of memory or port map */
366 pci_maptype(unsigned mapreg)
369 if (PCI_BAR_IO(mapreg))
371 if (mapreg & PCIM_BAR_MEM_PREFETCH)
372 return ("Prefetchable Memory");
376 /* return log2 of map size decoded for memory or port map */
379 pci_mapsize(uint32_t testval)
383 testval = pci_mapbase(testval);
386 while ((testval & 1) == 0)
395 /* return log2 of address range supported by map register */
398 pci_maprange(unsigned mapreg)
402 if (PCI_BAR_IO(mapreg))
405 switch (mapreg & PCIM_BAR_MEM_TYPE) {
406 case PCIM_BAR_MEM_32:
409 case PCIM_BAR_MEM_1MB:
412 case PCIM_BAR_MEM_64:
419 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
422 pci_fixancient(pcicfgregs *cfg)
424 if (cfg->hdrtype != 0)
427 /* PCI to PCI bridges use header type 1 */
428 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
432 /* extract header type specific config data */
435 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
437 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
438 switch (cfg->hdrtype) {
440 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
441 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
442 cfg->nummaps = PCI_MAXMAPS_0;
445 cfg->nummaps = PCI_MAXMAPS_1;
447 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
451 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
452 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
453 cfg->nummaps = PCI_MAXMAPS_2;
455 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
462 /* read configuration header into pcicfgregs structure */
464 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
466 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
467 pcicfgregs *cfg = NULL;
468 struct pci_devinfo *devlist_entry;
469 struct devlist *devlist_head;
471 devlist_head = &pci_devq;
473 devlist_entry = NULL;
475 if (REG(PCIR_DEVVENDOR, 4) != -1) {
476 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
478 cfg = &devlist_entry->cfg;
484 cfg->vendor = REG(PCIR_VENDOR, 2);
485 cfg->device = REG(PCIR_DEVICE, 2);
486 cfg->cmdreg = REG(PCIR_COMMAND, 2);
487 cfg->statreg = REG(PCIR_STATUS, 2);
488 cfg->baseclass = REG(PCIR_CLASS, 1);
489 cfg->subclass = REG(PCIR_SUBCLASS, 1);
490 cfg->progif = REG(PCIR_PROGIF, 1);
491 cfg->revid = REG(PCIR_REVID, 1);
492 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
493 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
494 cfg->lattimer = REG(PCIR_LATTIMER, 1);
495 cfg->intpin = REG(PCIR_INTPIN, 1);
496 cfg->intline = REG(PCIR_INTLINE, 1);
498 cfg->mingnt = REG(PCIR_MINGNT, 1);
499 cfg->maxlat = REG(PCIR_MAXLAT, 1);
501 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
502 cfg->hdrtype &= ~PCIM_MFDEV;
505 pci_hdrtypedata(pcib, b, s, f, cfg);
507 pci_read_capabilities(pcib, cfg);
509 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
511 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
512 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
513 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
514 devlist_entry->conf.pc_sel.pc_func = cfg->func;
515 devlist_entry->conf.pc_hdr = cfg->hdrtype;
517 devlist_entry->conf.pc_subvendor = cfg->subvendor;
518 devlist_entry->conf.pc_subdevice = cfg->subdevice;
519 devlist_entry->conf.pc_vendor = cfg->vendor;
520 devlist_entry->conf.pc_device = cfg->device;
522 devlist_entry->conf.pc_class = cfg->baseclass;
523 devlist_entry->conf.pc_subclass = cfg->subclass;
524 devlist_entry->conf.pc_progif = cfg->progif;
525 devlist_entry->conf.pc_revid = cfg->revid;
530 return (devlist_entry);
535 pci_fixup_nextptr(int *nextptr0)
537 int nextptr = *nextptr0;
539 /* "Next pointer" is only one byte */
540 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
544 * PCI local bus spec 3.0:
546 * "... The bottom two bits of all pointers are reserved
547 * and must be implemented as 00b although software must
548 * mask them to allow for future uses of these bits ..."
551 kprintf("Illegal PCI extended capability "
552 "offset, fixup 0x%02x -> 0x%02x\n",
553 nextptr, nextptr & ~0x3);
559 if (nextptr < 0x40) {
561 kprintf("Illegal PCI extended capability "
562 "offset 0x%02x", nextptr);
570 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
573 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
575 struct pcicfg_pp *pp = &cfg->pp;
580 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
581 pp->pp_status = ptr + PCIR_POWER_STATUS;
582 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
584 if ((nextptr - ptr) > PCIR_POWER_DATA) {
587 * We should write to data_select and read back from
588 * data_scale to determine whether data register is
592 pp->pp_data = ptr + PCIR_POWER_DATA;
602 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
604 #if defined(__i386__) || defined(__x86_64__)
607 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
609 struct pcicfg_ht *ht = &cfg->ht;
613 /* Determine HT-specific capability type. */
614 val = REG(ptr + PCIR_HT_COMMAND, 2);
616 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
617 cfg->ht.ht_slave = ptr;
619 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
622 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
623 /* Sanity check the mapping window. */
624 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
626 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
627 if (addr != MSI_X86_ADDR_BASE) {
628 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
629 "has non-default MSI window 0x%llx\n",
630 cfg->domain, cfg->bus, cfg->slot, cfg->func,
634 addr = MSI_X86_ADDR_BASE;
638 ht->ht_msictrl = val;
639 ht->ht_msiaddr = addr;
643 #endif /* __i386__ || __x86_64__ */
647 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
650 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
652 struct pcicfg_msi *msi = &cfg->msi;
654 msi->msi_location = ptr;
655 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
656 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
662 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
665 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
667 struct pcicfg_msix *msix = &cfg->msix;
670 msix->msix_location = ptr;
671 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
672 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
674 val = REG(ptr + PCIR_MSIX_TABLE, 4);
675 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
676 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
678 val = REG(ptr + PCIR_MSIX_PBA, 4);
679 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
680 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
686 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
688 cfg->vpd.vpd_reg = ptr;
692 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
695 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
697 /* Should always be true. */
698 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
701 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
702 cfg->subvendor = val & 0xffff;
703 cfg->subdevice = val >> 16;
710 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
713 * Assume we have a PCI-X chipset if we have
714 * at least one PCI-PCI bridge with a PCI-X
715 * capability. Note that some systems with
716 * PCI-express or HT chipsets might match on
717 * this check as well.
719 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
722 cfg->pcix.pcix_ptr = ptr;
726 pcie_slotimpl(const pcicfgregs *cfg)
728 const struct pcicfg_expr *expr = &cfg->expr;
732 * Only version 1 can be parsed currently
734 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
738 * - Slot implemented bit is meaningful iff current port is
739 * root port or down stream port.
740 * - Testing for root port or down stream port is meanningful
741 * iff PCI configure has type 1 header.
744 if (cfg->hdrtype != 1)
747 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
748 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
751 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
758 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
761 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
763 struct pcicfg_expr *expr = &cfg->expr;
766 * Assume we have a PCI-express chipset if we have
767 * at least one PCI-express device.
771 expr->expr_ptr = ptr;
772 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
775 * Only version 1 can be parsed currently
777 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
781 * Read slot capabilities. Slot capabilities exists iff
782 * current port's slot is implemented
784 if (pcie_slotimpl(cfg))
785 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
791 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
793 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
794 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
799 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
800 /* No capabilities */
804 switch (cfg->hdrtype & PCIM_HDRTYPE) {
807 ptrptr = PCIR_CAP_PTR;
810 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
813 return; /* no capabilities support */
815 nextptr = REG(ptrptr, 1); /* sanity check? */
818 * Read capability entries.
820 while (pci_fixup_nextptr(&nextptr)) {
821 const struct pci_read_cap *rc;
824 /* Find the next entry */
825 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
827 /* Process this entry */
828 val = REG(ptr + PCICAP_ID, 1);
829 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
830 if (rc->cap == val) {
831 rc->read_cap(pcib, ptr, nextptr, cfg);
837 #if defined(__i386__) || defined(__x86_64__)
839 * Enable the MSI mapping window for all HyperTransport
840 * slaves. PCI-PCI bridges have their windows enabled via
843 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
844 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
846 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
847 cfg->domain, cfg->bus, cfg->slot, cfg->func);
848 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
849 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
854 /* REG and WREG use carry through to next functions */
858 * PCI Vital Product Data
861 #define PCI_VPD_TIMEOUT 1000000
864 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
866 int count = PCI_VPD_TIMEOUT;
868 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
870 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
872 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
875 DELAY(1); /* limit looping */
877 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
884 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
886 int count = PCI_VPD_TIMEOUT;
888 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
890 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
891 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
892 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
895 DELAY(1); /* limit looping */
902 #undef PCI_VPD_TIMEOUT
904 struct vpd_readstate {
914 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
919 if (vrs->bytesinval == 0) {
920 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
922 vrs->val = le32toh(reg);
924 byte = vrs->val & 0xff;
927 vrs->val = vrs->val >> 8;
928 byte = vrs->val & 0xff;
938 pcie_slot_implemented(device_t dev)
940 struct pci_devinfo *dinfo = device_get_ivars(dev);
942 return pcie_slotimpl(&dinfo->cfg);
946 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
951 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
952 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
953 panic("%s: invalid max read request size 0x%02x\n",
954 device_get_nameunit(dev), rqsize);
957 expr_ptr = pci_get_pciecap_ptr(dev);
959 panic("%s: not PCIe device\n", device_get_nameunit(dev));
961 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
962 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
964 device_printf(dev, "adjust device control 0x%04x", val);
966 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
968 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
971 kprintf(" -> 0x%04x\n", val);
976 pcie_get_max_readrq(device_t dev)
981 expr_ptr = pci_get_pciecap_ptr(dev);
983 panic("%s: not PCIe device\n", device_get_nameunit(dev));
985 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
986 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
990 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
992 struct vpd_readstate vrs;
997 int alloc, off; /* alloc/off for RO/W arrays */
1003 /* init vpd reader */
1011 name = remain = i = 0; /* shut up stupid gcc */
1012 alloc = off = 0; /* shut up stupid gcc */
1013 dflen = 0; /* shut up stupid gcc */
1015 while (state >= 0) {
1016 if (vpd_nextbyte(&vrs, &byte)) {
1021 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1022 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1023 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1026 case 0: /* item name */
1028 if (vpd_nextbyte(&vrs, &byte2)) {
1033 if (vpd_nextbyte(&vrs, &byte2)) {
1037 remain |= byte2 << 8;
1038 if (remain > (0x7f*4 - vrs.off)) {
1041 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1042 cfg->domain, cfg->bus, cfg->slot,
1047 remain = byte & 0x7;
1048 name = (byte >> 3) & 0xf;
1051 case 0x2: /* String */
1052 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1053 M_DEVBUF, M_WAITOK);
1060 case 0x10: /* VPD-R */
1063 cfg->vpd.vpd_ros = kmalloc(alloc *
1064 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1068 case 0x11: /* VPD-W */
1071 cfg->vpd.vpd_w = kmalloc(alloc *
1072 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1076 default: /* Invalid data, abort */
1082 case 1: /* Identifier String */
1083 cfg->vpd.vpd_ident[i++] = byte;
1086 cfg->vpd.vpd_ident[i] = '\0';
1091 case 2: /* VPD-R Keyword Header */
1093 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1094 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1095 M_DEVBUF, M_WAITOK | M_ZERO);
1097 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1098 if (vpd_nextbyte(&vrs, &byte2)) {
1102 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1103 if (vpd_nextbyte(&vrs, &byte2)) {
1109 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1112 * if this happens, we can't trust the rest
1116 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1117 cfg->domain, cfg->bus, cfg->slot,
1122 } else if (dflen == 0) {
1123 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1124 sizeof(*cfg->vpd.vpd_ros[off].value),
1125 M_DEVBUF, M_WAITOK);
1126 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1128 cfg->vpd.vpd_ros[off].value = kmalloc(
1130 sizeof(*cfg->vpd.vpd_ros[off].value),
1131 M_DEVBUF, M_WAITOK);
1134 /* keep in sync w/ state 3's transistions */
1135 if (dflen == 0 && remain == 0)
1137 else if (dflen == 0)
1143 case 3: /* VPD-R Keyword Value */
1144 cfg->vpd.vpd_ros[off].value[i++] = byte;
1145 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1146 "RV", 2) == 0 && cksumvalid == -1) {
1152 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1153 cfg->domain, cfg->bus,
1154 cfg->slot, cfg->func,
1163 /* keep in sync w/ state 2's transistions */
1165 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1166 if (dflen == 0 && remain == 0) {
1167 cfg->vpd.vpd_rocnt = off;
1168 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1169 off * sizeof(*cfg->vpd.vpd_ros),
1170 M_DEVBUF, M_WAITOK | M_ZERO);
1172 } else if (dflen == 0)
1182 case 5: /* VPD-W Keyword Header */
1184 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1185 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1186 M_DEVBUF, M_WAITOK | M_ZERO);
1188 cfg->vpd.vpd_w[off].keyword[0] = byte;
1189 if (vpd_nextbyte(&vrs, &byte2)) {
1193 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1194 if (vpd_nextbyte(&vrs, &byte2)) {
1198 cfg->vpd.vpd_w[off].len = dflen = byte2;
1199 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1200 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1201 sizeof(*cfg->vpd.vpd_w[off].value),
1202 M_DEVBUF, M_WAITOK);
1205 /* keep in sync w/ state 6's transistions */
1206 if (dflen == 0 && remain == 0)
1208 else if (dflen == 0)
1214 case 6: /* VPD-W Keyword Value */
1215 cfg->vpd.vpd_w[off].value[i++] = byte;
1218 /* keep in sync w/ state 5's transistions */
1220 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1221 if (dflen == 0 && remain == 0) {
1222 cfg->vpd.vpd_wcnt = off;
1223 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1224 off * sizeof(*cfg->vpd.vpd_w),
1225 M_DEVBUF, M_WAITOK | M_ZERO);
1227 } else if (dflen == 0)
1232 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1233 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1240 if (cksumvalid == 0 || state < -1) {
1241 /* read-only data bad, clean up */
1242 if (cfg->vpd.vpd_ros != NULL) {
1243 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1244 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1245 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1246 cfg->vpd.vpd_ros = NULL;
1250 /* I/O error, clean up */
1251 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1252 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1253 if (cfg->vpd.vpd_ident != NULL) {
1254 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1255 cfg->vpd.vpd_ident = NULL;
1257 if (cfg->vpd.vpd_w != NULL) {
1258 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1259 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1260 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1261 cfg->vpd.vpd_w = NULL;
1264 cfg->vpd.vpd_cached = 1;
1270 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1272 struct pci_devinfo *dinfo = device_get_ivars(child);
1273 pcicfgregs *cfg = &dinfo->cfg;
1275 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1276 pci_read_vpd(device_get_parent(dev), cfg);
1278 *identptr = cfg->vpd.vpd_ident;
1280 if (*identptr == NULL)
1287 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1290 struct pci_devinfo *dinfo = device_get_ivars(child);
1291 pcicfgregs *cfg = &dinfo->cfg;
1294 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1295 pci_read_vpd(device_get_parent(dev), cfg);
1297 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1298 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1299 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1300 *vptr = cfg->vpd.vpd_ros[i].value;
1303 if (i != cfg->vpd.vpd_rocnt)
1311 * Return the offset in configuration space of the requested extended
1312 * capability entry or 0 if the specified capability was not found.
1315 pci_find_extcap_method(device_t dev, device_t child, int capability,
1318 struct pci_devinfo *dinfo = device_get_ivars(child);
1319 pcicfgregs *cfg = &dinfo->cfg;
1324 * Check the CAP_LIST bit of the PCI status register first.
1326 status = pci_read_config(child, PCIR_STATUS, 2);
1327 if (!(status & PCIM_STATUS_CAPPRESENT))
1331 * Determine the start pointer of the capabilities list.
1333 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1339 ptr = PCIR_CAP_PTR_2;
1343 return (ENXIO); /* no extended capabilities support */
1345 ptr = pci_read_config(child, ptr, 1);
1348 * Traverse the capabilities list.
1351 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1356 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1363 * Support for MSI-X message interrupts.
1366 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1368 struct pci_devinfo *dinfo = device_get_ivars(dev);
1369 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1372 KASSERT(msix->msix_table_len > index, ("bogus index"));
1373 offset = msix->msix_table_offset + index * 16;
1374 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1375 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1376 bus_write_4(msix->msix_table_res, offset + 8, data);
1378 /* Enable MSI -> HT mapping. */
1379 pci_ht_map_msi(dev, address);
1383 pci_mask_msix(device_t dev, u_int index)
1385 struct pci_devinfo *dinfo = device_get_ivars(dev);
1386 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1387 uint32_t offset, val;
1389 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1390 offset = msix->msix_table_offset + index * 16 + 12;
1391 val = bus_read_4(msix->msix_table_res, offset);
1392 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1393 val |= PCIM_MSIX_VCTRL_MASK;
1394 bus_write_4(msix->msix_table_res, offset, val);
1399 pci_unmask_msix(device_t dev, u_int index)
1401 struct pci_devinfo *dinfo = device_get_ivars(dev);
1402 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1403 uint32_t offset, val;
1405 KASSERT(msix->msix_table_len > index, ("bogus index"));
1406 offset = msix->msix_table_offset + index * 16 + 12;
1407 val = bus_read_4(msix->msix_table_res, offset);
1408 if (val & PCIM_MSIX_VCTRL_MASK) {
1409 val &= ~PCIM_MSIX_VCTRL_MASK;
1410 bus_write_4(msix->msix_table_res, offset, val);
1415 pci_pending_msix(device_t dev, u_int index)
1417 struct pci_devinfo *dinfo = device_get_ivars(dev);
1418 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1419 uint32_t offset, bit;
1421 KASSERT(msix->msix_table_len > index, ("bogus index"));
1422 offset = msix->msix_pba_offset + (index / 32) * 4;
1423 bit = 1 << index % 32;
1424 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1428 * Restore MSI-X registers and table during resume. If MSI-X is
1429 * enabled then walk the virtual table to restore the actual MSI-X
1433 pci_resume_msix(device_t dev)
1435 struct pci_devinfo *dinfo = device_get_ivars(dev);
1436 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1437 struct msix_table_entry *mte;
1438 struct msix_vector *mv;
1441 if (msix->msix_alloc > 0) {
1442 /* First, mask all vectors. */
1443 for (i = 0; i < msix->msix_msgnum; i++)
1444 pci_mask_msix(dev, i);
1446 /* Second, program any messages with at least one handler. */
1447 for (i = 0; i < msix->msix_table_len; i++) {
1448 mte = &msix->msix_table[i];
1449 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1451 mv = &msix->msix_vectors[mte->mte_vector - 1];
1452 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1453 pci_unmask_msix(dev, i);
1456 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1457 msix->msix_ctrl, 2);
1461 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1462 * returned in *count. After this function returns, each message will be
1463 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1466 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1468 struct pci_devinfo *dinfo = device_get_ivars(child);
1469 pcicfgregs *cfg = &dinfo->cfg;
1470 struct resource_list_entry *rle;
1471 int actual, error, i, irq, max;
1473 /* Don't let count == 0 get us into trouble. */
1477 /* If rid 0 is allocated, then fail. */
1478 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1479 if (rle != NULL && rle->res != NULL)
1482 /* Already have allocated messages? */
1483 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1486 /* If MSI is blacklisted for this system, fail. */
1487 if (pci_msi_blacklisted())
1490 /* MSI-X capability present? */
1491 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1494 /* Make sure the appropriate BARs are mapped. */
1495 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1496 cfg->msix.msix_table_bar);
1497 if (rle == NULL || rle->res == NULL ||
1498 !(rman_get_flags(rle->res) & RF_ACTIVE))
1500 cfg->msix.msix_table_res = rle->res;
1501 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1502 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1503 cfg->msix.msix_pba_bar);
1504 if (rle == NULL || rle->res == NULL ||
1505 !(rman_get_flags(rle->res) & RF_ACTIVE))
1508 cfg->msix.msix_pba_res = rle->res;
1511 device_printf(child,
1512 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1513 *count, cfg->msix.msix_msgnum);
1514 max = min(*count, cfg->msix.msix_msgnum);
1515 for (i = 0; i < max; i++) {
1516 /* Allocate a message. */
1517 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1520 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1527 device_printf(child,
1528 "could not allocate any MSI-X vectors\n");
1534 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1536 device_printf(child, "using IRQ %lu for MSI-X\n",
1542 * Be fancy and try to print contiguous runs of
1543 * IRQ values as ranges. 'irq' is the previous IRQ.
1544 * 'run' is true if we are in a range.
1546 device_printf(child, "using IRQs %lu", rle->start);
1549 for (i = 1; i < actual; i++) {
1550 rle = resource_list_find(&dinfo->resources,
1551 SYS_RES_IRQ, i + 1);
1553 /* Still in a run? */
1554 if (rle->start == irq + 1) {
1560 /* Finish previous range. */
1562 kprintf("-%d", irq);
1566 /* Start new range. */
1567 kprintf(",%lu", rle->start);
1571 /* Unfinished range? */
1573 kprintf("-%d", irq);
1574 kprintf(" for MSI-X\n");
1578 /* Mask all vectors. */
1579 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1580 pci_mask_msix(child, i);
1582 /* Allocate and initialize vector data and virtual table. */
1583 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1584 M_DEVBUF, M_WAITOK | M_ZERO);
1585 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1586 M_DEVBUF, M_WAITOK | M_ZERO);
1587 for (i = 0; i < actual; i++) {
1588 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1589 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1590 cfg->msix.msix_table[i].mte_vector = i + 1;
1593 /* Update control register to enable MSI-X. */
1594 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1595 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1596 cfg->msix.msix_ctrl, 2);
1598 /* Update counts of alloc'd messages. */
1599 cfg->msix.msix_alloc = actual;
1600 cfg->msix.msix_table_len = actual;
1606 * By default, pci_alloc_msix() will assign the allocated IRQ
1607 * resources consecutively to the first N messages in the MSI-X table.
1608 * However, device drivers may want to use different layouts if they
1609 * either receive fewer messages than they asked for, or they wish to
1610 * populate the MSI-X table sparsely. This method allows the driver
1611 * to specify what layout it wants. It must be called after a
1612 * successful pci_alloc_msix() but before any of the associated
1613 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1615 * The 'vectors' array contains 'count' message vectors. The array
1616 * maps directly to the MSI-X table in that index 0 in the array
1617 * specifies the vector for the first message in the MSI-X table, etc.
1618 * The vector value in each array index can either be 0 to indicate
1619 * that no vector should be assigned to a message slot, or it can be a
1620 * number from 1 to N (where N is the count returned from a
1621 * succcessful call to pci_alloc_msix()) to indicate which message
1622 * vector (IRQ) to be used for the corresponding message.
1624 * On successful return, each message with a non-zero vector will have
1625 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1626 * 1. Additionally, if any of the IRQs allocated via the previous
1627 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1628 * will be kfreed back to the system automatically.
1630 * For example, suppose a driver has a MSI-X table with 6 messages and
1631 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1632 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1633 * C. After the call to pci_alloc_msix(), the device will be setup to
1634 * have an MSI-X table of ABC--- (where - means no vector assigned).
1635 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1636 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1637 * be kfreed back to the system. This device will also have valid
1638 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1640 * In any case, the SYS_RES_IRQ rid X will always map to the message
1641 * at MSI-X table index X - 1 and will only be valid if a vector is
1642 * assigned to that table entry.
1645 pci_remap_msix_method(device_t dev, device_t child, int count,
1646 const u_int *vectors)
1648 struct pci_devinfo *dinfo = device_get_ivars(child);
1649 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1650 struct resource_list_entry *rle;
1651 int i, irq, j, *used;
1654 * Have to have at least one message in the table but the
1655 * table can't be bigger than the actual MSI-X table in the
1658 if (count == 0 || count > msix->msix_msgnum)
1661 /* Sanity check the vectors. */
1662 for (i = 0; i < count; i++)
1663 if (vectors[i] > msix->msix_alloc)
1667 * Make sure there aren't any holes in the vectors to be used.
1668 * It's a big pain to support it, and it doesn't really make
1669 * sense anyway. Also, at least one vector must be used.
1671 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1673 for (i = 0; i < count; i++)
1674 if (vectors[i] != 0)
1675 used[vectors[i] - 1] = 1;
1676 for (i = 0; i < msix->msix_alloc - 1; i++)
1677 if (used[i] == 0 && used[i + 1] == 1) {
1678 kfree(used, M_DEVBUF);
1682 kfree(used, M_DEVBUF);
1686 /* Make sure none of the resources are allocated. */
1687 for (i = 0; i < msix->msix_table_len; i++) {
1688 if (msix->msix_table[i].mte_vector == 0)
1690 if (msix->msix_table[i].mte_handlers > 0)
1692 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1693 KASSERT(rle != NULL, ("missing resource"));
1694 if (rle->res != NULL)
1698 /* Free the existing resource list entries. */
1699 for (i = 0; i < msix->msix_table_len; i++) {
1700 if (msix->msix_table[i].mte_vector == 0)
1702 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1706 * Build the new virtual table keeping track of which vectors are
1709 kfree(msix->msix_table, M_DEVBUF);
1710 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1711 M_DEVBUF, M_WAITOK | M_ZERO);
1712 for (i = 0; i < count; i++)
1713 msix->msix_table[i].mte_vector = vectors[i];
1714 msix->msix_table_len = count;
1716 /* Free any unused IRQs and resize the vectors array if necessary. */
1717 j = msix->msix_alloc - 1;
1719 struct msix_vector *vec;
1721 while (used[j] == 0) {
1722 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1723 msix->msix_vectors[j].mv_irq);
1726 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1728 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1730 kfree(msix->msix_vectors, M_DEVBUF);
1731 msix->msix_vectors = vec;
1732 msix->msix_alloc = j + 1;
1734 kfree(used, M_DEVBUF);
1736 /* Map the IRQs onto the rids. */
1737 for (i = 0; i < count; i++) {
1738 if (vectors[i] == 0)
1740 irq = msix->msix_vectors[vectors[i]].mv_irq;
1741 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1746 device_printf(child, "Remapped MSI-X IRQs as: ");
1747 for (i = 0; i < count; i++) {
1750 if (vectors[i] == 0)
1754 msix->msix_vectors[vectors[i]].mv_irq);
1763 pci_release_msix(device_t dev, device_t child)
1765 struct pci_devinfo *dinfo = device_get_ivars(child);
1766 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1767 struct resource_list_entry *rle;
1770 /* Do we have any messages to release? */
1771 if (msix->msix_alloc == 0)
1774 /* Make sure none of the resources are allocated. */
1775 for (i = 0; i < msix->msix_table_len; i++) {
1776 if (msix->msix_table[i].mte_vector == 0)
1778 if (msix->msix_table[i].mte_handlers > 0)
1780 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1781 KASSERT(rle != NULL, ("missing resource"));
1782 if (rle->res != NULL)
1786 /* Update control register to disable MSI-X. */
1787 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1788 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1789 msix->msix_ctrl, 2);
1791 /* Free the resource list entries. */
1792 for (i = 0; i < msix->msix_table_len; i++) {
1793 if (msix->msix_table[i].mte_vector == 0)
1795 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1797 kfree(msix->msix_table, M_DEVBUF);
1798 msix->msix_table_len = 0;
1800 /* Release the IRQs. */
1801 for (i = 0; i < msix->msix_alloc; i++)
1802 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1803 msix->msix_vectors[i].mv_irq);
1804 kfree(msix->msix_vectors, M_DEVBUF);
1805 msix->msix_alloc = 0;
1810 * Return the max supported MSI-X messages this device supports.
1811 * Basically, assuming the MD code can alloc messages, this function
1812 * should return the maximum value that pci_alloc_msix() can return.
1813 * Thus, it is subject to the tunables, etc.
1816 pci_msix_count_method(device_t dev, device_t child)
1818 struct pci_devinfo *dinfo = device_get_ivars(child);
1819 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1821 if (pci_do_msix && msix->msix_location != 0)
1822 return (msix->msix_msgnum);
1827 * HyperTransport MSI mapping control
1830 pci_ht_map_msi(device_t dev, uint64_t addr)
1832 struct pci_devinfo *dinfo = device_get_ivars(dev);
1833 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1838 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1839 ht->ht_msiaddr >> 20 == addr >> 20) {
1840 /* Enable MSI -> HT mapping. */
1841 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1842 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1846 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1847 /* Disable MSI -> HT mapping. */
1848 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1849 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1855 * Support for MSI message signalled interrupts.
1858 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1860 struct pci_devinfo *dinfo = device_get_ivars(dev);
1861 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1863 /* Write data and address values. */
1864 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1865 address & 0xffffffff, 4);
1866 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1867 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1869 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1872 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1875 /* Enable MSI in the control register. */
1876 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1877 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1880 /* Enable MSI -> HT mapping. */
1881 pci_ht_map_msi(dev, address);
1885 pci_disable_msi(device_t dev)
1887 struct pci_devinfo *dinfo = device_get_ivars(dev);
1888 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1890 /* Disable MSI -> HT mapping. */
1891 pci_ht_map_msi(dev, 0);
1893 /* Disable MSI in the control register. */
1894 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1895 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1900 * Restore MSI registers during resume. If MSI is enabled then
1901 * restore the data and address registers in addition to the control
1905 pci_resume_msi(device_t dev)
1907 struct pci_devinfo *dinfo = device_get_ivars(dev);
1908 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1912 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1913 address = msi->msi_addr;
1914 data = msi->msi_data;
1915 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1916 address & 0xffffffff, 4);
1917 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1918 pci_write_config(dev, msi->msi_location +
1919 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1920 pci_write_config(dev, msi->msi_location +
1921 PCIR_MSI_DATA_64BIT, data, 2);
1923 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1926 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1931 pci_remap_msi_irq(device_t dev, u_int irq)
1933 struct pci_devinfo *dinfo = device_get_ivars(dev);
1934 pcicfgregs *cfg = &dinfo->cfg;
1935 struct resource_list_entry *rle;
1936 struct msix_table_entry *mte;
1937 struct msix_vector *mv;
1943 bus = device_get_parent(dev);
1946 * Handle MSI first. We try to find this IRQ among our list
1947 * of MSI IRQs. If we find it, we request updated address and
1948 * data registers and apply the results.
1950 if (cfg->msi.msi_alloc > 0) {
1952 /* If we don't have any active handlers, nothing to do. */
1953 if (cfg->msi.msi_handlers == 0)
1955 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1956 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1958 if (rle->start == irq) {
1959 error = PCIB_MAP_MSI(device_get_parent(bus),
1960 dev, irq, &addr, &data, -1 /* XXX */);
1963 pci_disable_msi(dev);
1964 dinfo->cfg.msi.msi_addr = addr;
1965 dinfo->cfg.msi.msi_data = data;
1966 pci_enable_msi(dev, addr, data);
1974 * For MSI-X, we check to see if we have this IRQ. If we do,
1975 * we request the updated mapping info. If that works, we go
1976 * through all the slots that use this IRQ and update them.
1978 if (cfg->msix.msix_alloc > 0) {
1979 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1980 mv = &cfg->msix.msix_vectors[i];
1981 if (mv->mv_irq == irq) {
1982 error = PCIB_MAP_MSI(device_get_parent(bus),
1983 dev, irq, &addr, &data, -1 /* XXX */);
1986 mv->mv_address = addr;
1988 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1989 mte = &cfg->msix.msix_table[j];
1990 if (mte->mte_vector != i + 1)
1992 if (mte->mte_handlers == 0)
1994 pci_mask_msix(dev, j);
1995 pci_enable_msix(dev, j, addr, data);
1996 pci_unmask_msix(dev, j);
2007 * Returns true if the specified device is blacklisted because MSI
2011 pci_msi_device_blacklisted(device_t dev)
2013 struct pci_quirk *q;
2015 if (!pci_honor_msi_blacklist)
2018 for (q = &pci_quirks[0]; q->devid; q++) {
2019 if (q->devid == pci_get_devid(dev) &&
2020 q->type == PCI_QUIRK_DISABLE_MSI)
2027 * Determine if MSI is blacklisted globally on this sytem. Currently,
2028 * we just check for blacklisted chipsets as represented by the
2029 * host-PCI bridge at device 0:0:0. In the future, it may become
2030 * necessary to check other system attributes, such as the kenv values
2031 * that give the motherboard manufacturer and model number.
2034 pci_msi_blacklisted(void)
2038 if (!pci_honor_msi_blacklist)
2041 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2042 if (!(pcie_chipset || pcix_chipset))
2045 dev = pci_find_bsf(0, 0, 0);
2047 return (pci_msi_device_blacklisted(dev));
2052 * Attempt to allocate *count MSI messages. The actual number allocated is
2053 * returned in *count. After this function returns, each message will be
2054 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2057 pci_alloc_msi_method(device_t dev, device_t child, int *count, int cpuid)
2059 struct pci_devinfo *dinfo = device_get_ivars(child);
2060 pcicfgregs *cfg = &dinfo->cfg;
2061 struct resource_list_entry *rle;
2062 int actual, error, i, irqs[32];
2065 /* Don't let count == 0 get us into trouble. */
2069 /* If rid 0 is allocated, then fail. */
2070 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2071 if (rle != NULL && rle->res != NULL)
2074 /* Already have allocated messages? */
2075 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2078 /* If MSI is blacklisted for this system, fail. */
2079 if (pci_msi_blacklisted())
2082 /* MSI capability present? */
2083 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2087 device_printf(child,
2088 "attempting to allocate %d MSI vectors (%d supported)\n",
2089 *count, cfg->msi.msi_msgnum);
2091 /* Don't ask for more than the device supports. */
2092 actual = min(*count, cfg->msi.msi_msgnum);
2094 /* Don't ask for more than 32 messages. */
2095 actual = min(actual, 32);
2097 /* MSI requires power of 2 number of messages. */
2098 if (!powerof2(actual))
2102 /* Try to allocate N messages. */
2103 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2104 cfg->msi.msi_msgnum, irqs, cpuid);
2115 * We now have N actual messages mapped onto SYS_RES_IRQ
2116 * resources in the irqs[] array, so add new resources
2117 * starting at rid 1.
2119 for (i = 0; i < actual; i++)
2120 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2121 irqs[i], irqs[i], 1, cpuid);
2125 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2130 * Be fancy and try to print contiguous runs
2131 * of IRQ values as ranges. 'run' is true if
2132 * we are in a range.
2134 device_printf(child, "using IRQs %d", irqs[0]);
2136 for (i = 1; i < actual; i++) {
2138 /* Still in a run? */
2139 if (irqs[i] == irqs[i - 1] + 1) {
2144 /* Finish previous range. */
2146 kprintf("-%d", irqs[i - 1]);
2150 /* Start new range. */
2151 kprintf(",%d", irqs[i]);
2154 /* Unfinished range? */
2156 kprintf("-%d", irqs[actual - 1]);
2157 kprintf(" for MSI\n");
2161 /* Update control register with actual count. */
2162 ctrl = cfg->msi.msi_ctrl;
2163 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2164 ctrl |= (ffs(actual) - 1) << 4;
2165 cfg->msi.msi_ctrl = ctrl;
2166 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2168 /* Update counts of alloc'd messages. */
2169 cfg->msi.msi_alloc = actual;
2170 cfg->msi.msi_handlers = 0;
2175 /* Release the MSI messages associated with this device. */
2177 pci_release_msi_method(device_t dev, device_t child)
2179 struct pci_devinfo *dinfo = device_get_ivars(child);
2180 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2181 struct resource_list_entry *rle;
2182 int error, i, irqs[32], cpuid = -1;
2184 /* Try MSI-X first. */
2185 error = pci_release_msix(dev, child);
2186 if (error != ENODEV)
2189 /* Do we have any messages to release? */
2190 if (msi->msi_alloc == 0)
2192 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2194 /* Make sure none of the resources are allocated. */
2195 if (msi->msi_handlers > 0)
2197 for (i = 0; i < msi->msi_alloc; i++) {
2198 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2199 KASSERT(rle != NULL, ("missing MSI resource"));
2200 if (rle->res != NULL)
2204 KASSERT(cpuid >= 0 && cpuid < ncpus,
2205 ("invalid MSI target cpuid %d\n", cpuid));
2207 KASSERT(rle->cpuid == cpuid,
2208 ("MSI targets different cpus, "
2209 "was cpu%d, now cpu%d", cpuid, rle->cpuid));
2211 irqs[i] = rle->start;
2214 /* Update control register with 0 count. */
2215 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2216 ("%s: MSI still enabled", __func__));
2217 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2218 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2221 /* Release the messages. */
2222 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs,
2224 for (i = 0; i < msi->msi_alloc; i++)
2225 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2227 /* Update alloc count. */
2235 * Return the max supported MSI messages this device supports.
2236 * Basically, assuming the MD code can alloc messages, this function
2237 * should return the maximum value that pci_alloc_msi() can return.
2238 * Thus, it is subject to the tunables, etc.
2241 pci_msi_count_method(device_t dev, device_t child)
2243 struct pci_devinfo *dinfo = device_get_ivars(child);
2244 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2246 if (pci_do_msi && msi->msi_location != 0)
2247 return (msi->msi_msgnum);
2251 /* kfree pcicfgregs structure and all depending data structures */
2254 pci_freecfg(struct pci_devinfo *dinfo)
2256 struct devlist *devlist_head;
2259 devlist_head = &pci_devq;
2261 if (dinfo->cfg.vpd.vpd_reg) {
2262 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2263 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2264 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2265 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2266 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2267 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2268 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2270 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2271 kfree(dinfo, M_DEVBUF);
2273 /* increment the generation count */
2276 /* we're losing one device */
2282 * PCI power manangement
2285 pci_set_powerstate_method(device_t dev, device_t child, int state)
2287 struct pci_devinfo *dinfo = device_get_ivars(child);
2288 pcicfgregs *cfg = &dinfo->cfg;
2290 int result, oldstate, highest, delay;
2292 if (cfg->pp.pp_cap == 0)
2293 return (EOPNOTSUPP);
2296 * Optimize a no state change request away. While it would be OK to
2297 * write to the hardware in theory, some devices have shown odd
2298 * behavior when going from D3 -> D3.
2300 oldstate = pci_get_powerstate(child);
2301 if (oldstate == state)
2305 * The PCI power management specification states that after a state
2306 * transition between PCI power states, system software must
2307 * guarantee a minimal delay before the function accesses the device.
2308 * Compute the worst case delay that we need to guarantee before we
2309 * access the device. Many devices will be responsive much more
2310 * quickly than this delay, but there are some that don't respond
2311 * instantly to state changes. Transitions to/from D3 state require
2312 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2313 * is done below with DELAY rather than a sleeper function because
2314 * this function can be called from contexts where we cannot sleep.
2316 highest = (oldstate > state) ? oldstate : state;
2317 if (highest == PCI_POWERSTATE_D3)
2319 else if (highest == PCI_POWERSTATE_D2)
2323 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2324 & ~PCIM_PSTAT_DMASK;
2327 case PCI_POWERSTATE_D0:
2328 status |= PCIM_PSTAT_D0;
2330 case PCI_POWERSTATE_D1:
2331 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2332 return (EOPNOTSUPP);
2333 status |= PCIM_PSTAT_D1;
2335 case PCI_POWERSTATE_D2:
2336 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2337 return (EOPNOTSUPP);
2338 status |= PCIM_PSTAT_D2;
2340 case PCI_POWERSTATE_D3:
2341 status |= PCIM_PSTAT_D3;
2349 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2350 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2351 dinfo->cfg.func, oldstate, state);
2353 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2360 pci_get_powerstate_method(device_t dev, device_t child)
2362 struct pci_devinfo *dinfo = device_get_ivars(child);
2363 pcicfgregs *cfg = &dinfo->cfg;
2367 if (cfg->pp.pp_cap != 0) {
2368 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2369 switch (status & PCIM_PSTAT_DMASK) {
2371 result = PCI_POWERSTATE_D0;
2374 result = PCI_POWERSTATE_D1;
2377 result = PCI_POWERSTATE_D2;
2380 result = PCI_POWERSTATE_D3;
2383 result = PCI_POWERSTATE_UNKNOWN;
2387 /* No support, device is always at D0 */
2388 result = PCI_POWERSTATE_D0;
2394 * Some convenience functions for PCI device drivers.
2397 static __inline void
2398 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2402 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2404 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2407 static __inline void
2408 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2412 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2414 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2418 pci_enable_busmaster_method(device_t dev, device_t child)
2420 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2425 pci_disable_busmaster_method(device_t dev, device_t child)
2427 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2432 pci_enable_io_method(device_t dev, device_t child, int space)
2442 case SYS_RES_IOPORT:
2443 bit = PCIM_CMD_PORTEN;
2446 case SYS_RES_MEMORY:
2447 bit = PCIM_CMD_MEMEN;
2453 pci_set_command_bit(dev, child, bit);
2454 /* Some devices seem to need a brief stall here, what do to? */
2455 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2458 device_printf(child, "failed to enable %s mapping!\n", error);
2463 pci_disable_io_method(device_t dev, device_t child, int space)
2473 case SYS_RES_IOPORT:
2474 bit = PCIM_CMD_PORTEN;
2477 case SYS_RES_MEMORY:
2478 bit = PCIM_CMD_MEMEN;
2484 pci_clear_command_bit(dev, child, bit);
2485 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2486 if (command & bit) {
2487 device_printf(child, "failed to disable %s mapping!\n", error);
2494 * New style pci driver. Parent device is either a pci-host-bridge or a
2495 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2499 pci_print_verbose(struct pci_devinfo *dinfo)
2503 pcicfgregs *cfg = &dinfo->cfg;
2505 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2506 cfg->vendor, cfg->device, cfg->revid);
2507 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2508 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2509 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2510 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2512 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2513 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2514 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2515 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2516 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2517 if (cfg->intpin > 0)
2518 kprintf("\tintpin=%c, irq=%d\n",
2519 cfg->intpin +'a' -1, cfg->intline);
2520 if (cfg->pp.pp_cap) {
2523 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2524 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2525 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2526 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2527 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2528 status & PCIM_PSTAT_DMASK);
2530 if (cfg->msi.msi_location) {
2533 ctrl = cfg->msi.msi_ctrl;
2534 kprintf("\tMSI supports %d message%s%s%s\n",
2535 cfg->msi.msi_msgnum,
2536 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2537 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2538 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2540 if (cfg->msix.msix_location) {
2541 kprintf("\tMSI-X supports %d message%s ",
2542 cfg->msix.msix_msgnum,
2543 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2544 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2545 kprintf("in map 0x%x\n",
2546 cfg->msix.msix_table_bar);
2548 kprintf("in maps 0x%x and 0x%x\n",
2549 cfg->msix.msix_table_bar,
2550 cfg->msix.msix_pba_bar);
2552 pci_print_verbose_expr(cfg);
2557 pci_print_verbose_expr(const pcicfgregs *cfg)
2559 const struct pcicfg_expr *expr = &cfg->expr;
2560 const char *port_name;
2566 if (expr->expr_ptr == 0) /* No PCI Express capability */
2569 kprintf("\tPCI Express ver.%d cap=0x%04x",
2570 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2571 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2574 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2576 switch (port_type) {
2577 case PCIE_END_POINT:
2578 port_name = "DEVICE";
2580 case PCIE_LEG_END_POINT:
2581 port_name = "LEGDEV";
2583 case PCIE_ROOT_PORT:
2586 case PCIE_UP_STREAM_PORT:
2587 port_name = "UPSTREAM";
2589 case PCIE_DOWN_STREAM_PORT:
2590 port_name = "DOWNSTRM";
2592 case PCIE_PCIE2PCI_BRIDGE:
2593 port_name = "PCIE2PCI";
2595 case PCIE_PCI2PCIE_BRIDGE:
2596 port_name = "PCI2PCIE";
2602 if ((port_type == PCIE_ROOT_PORT ||
2603 port_type == PCIE_DOWN_STREAM_PORT) &&
2604 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2606 if (port_name != NULL)
2607 kprintf("[%s]", port_name);
2609 if (pcie_slotimpl(cfg)) {
2610 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2611 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2612 kprintf("[HOTPLUG]");
2619 pci_porten(device_t pcib, int b, int s, int f)
2621 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2622 & PCIM_CMD_PORTEN) != 0;
2626 pci_memen(device_t pcib, int b, int s, int f)
2628 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2629 & PCIM_CMD_MEMEN) != 0;
2633 * Add a resource based on a pci map register. Return 1 if the map
2634 * register is a 32bit map register or 2 if it is a 64bit register.
2637 pci_add_map(device_t pcib, device_t bus, device_t dev,
2638 int b, int s, int f, int reg, struct resource_list *rl, int force,
2643 pci_addr_t start, end, count;
2650 struct resource *res;
2652 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2653 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2654 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2655 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2657 if (PCI_BAR_MEM(map)) {
2658 type = SYS_RES_MEMORY;
2659 if (map & PCIM_BAR_MEM_PREFETCH)
2662 type = SYS_RES_IOPORT;
2663 ln2size = pci_mapsize(testval);
2664 ln2range = pci_maprange(testval);
2665 base = pci_mapbase(map);
2666 barlen = ln2range == 64 ? 2 : 1;
2669 * For I/O registers, if bottom bit is set, and the next bit up
2670 * isn't clear, we know we have a BAR that doesn't conform to the
2671 * spec, so ignore it. Also, sanity check the size of the data
2672 * areas to the type of memory involved. Memory must be at least
2673 * 16 bytes in size, while I/O ranges must be at least 4.
2675 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2677 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2678 (type == SYS_RES_IOPORT && ln2size < 2))
2682 /* Read the other half of a 64bit map register */
2683 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2685 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2686 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2687 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2688 kprintf(", port disabled\n");
2689 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2690 kprintf(", memory disabled\n");
2692 kprintf(", enabled\n");
2696 * If base is 0, then we have problems. It is best to ignore
2697 * such entries for the moment. These will be allocated later if
2698 * the driver specifically requests them. However, some
2699 * removable busses look better when all resources are allocated,
2700 * so allow '0' to be overriden.
2702 * Similarly treat maps whose values is the same as the test value
2703 * read back. These maps have had all f's written to them by the
2704 * BIOS in an attempt to disable the resources.
2706 if (!force && (base == 0 || map == testval))
2708 if ((u_long)base != base) {
2710 "pci%d:%d:%d:%d bar %#x too many address bits",
2711 pci_get_domain(dev), b, s, f, reg);
2716 * This code theoretically does the right thing, but has
2717 * undesirable side effects in some cases where peripherals
2718 * respond oddly to having these bits enabled. Let the user
2719 * be able to turn them off (since pci_enable_io_modes is 1 by
2722 if (pci_enable_io_modes) {
2723 /* Turn on resources that have been left off by a lazy BIOS */
2724 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2725 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2726 cmd |= PCIM_CMD_PORTEN;
2727 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2729 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2730 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2731 cmd |= PCIM_CMD_MEMEN;
2732 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2735 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2737 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2741 count = 1 << ln2size;
2742 if (base == 0 || base == pci_mapbase(testval)) {
2743 start = 0; /* Let the parent decide. */
2747 end = base + (1 << ln2size) - 1;
2749 resource_list_add(rl, type, reg, start, end, count, -1);
2752 * Try to allocate the resource for this BAR from our parent
2753 * so that this resource range is already reserved. The
2754 * driver for this device will later inherit this resource in
2755 * pci_alloc_resource().
2757 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2758 prefetch ? RF_PREFETCHABLE : 0, -1);
2761 * If the allocation fails, delete the resource list
2762 * entry to force pci_alloc_resource() to allocate
2763 * resources from the parent.
2765 resource_list_delete(rl, type, reg);
2766 #ifdef PCI_BAR_CLEAR
2769 #else /* !PCI_BAR_CLEAR */
2771 * Don't clear BAR here. Some BIOS lists HPET as a
2772 * PCI function, clearing the BAR causes HPET timer
2776 kprintf("pci:%d:%d:%d: resource reservation failed "
2777 "%#jx - %#jx\n", b, s, f,
2778 (intmax_t)start, (intmax_t)end);
2781 #endif /* PCI_BAR_CLEAR */
2783 start = rman_get_start(res);
2785 pci_write_config(dev, reg, start, 4);
2787 pci_write_config(dev, reg + 4, start >> 32, 4);
2792 * For ATA devices we need to decide early what addressing mode to use.
2793 * Legacy demands that the primary and secondary ATA ports sits on the
2794 * same addresses that old ISA hardware did. This dictates that we use
2795 * those addresses and ignore the BAR's if we cannot set PCI native
2799 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2800 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2802 int rid, type, progif;
2804 /* if this device supports PCI native addressing use it */
2805 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2806 if ((progif & 0x8a) == 0x8a) {
2807 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2808 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2809 kprintf("Trying ATA native PCI addressing mode\n");
2810 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2814 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2815 type = SYS_RES_IOPORT;
2816 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2817 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2818 prefetchmask & (1 << 0));
2819 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2820 prefetchmask & (1 << 1));
2823 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
2824 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2827 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
2828 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2831 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2832 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2833 prefetchmask & (1 << 2));
2834 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2835 prefetchmask & (1 << 3));
2838 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
2839 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2842 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
2843 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2846 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2847 prefetchmask & (1 << 4));
2848 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2849 prefetchmask & (1 << 5));
2853 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2855 struct pci_devinfo *dinfo = device_get_ivars(dev);
2856 pcicfgregs *cfg = &dinfo->cfg;
2857 char tunable_name[64];
2860 /* Has to have an intpin to have an interrupt. */
2861 if (cfg->intpin == 0)
2864 /* Let the user override the IRQ with a tunable. */
2865 irq = PCI_INVALID_IRQ;
2866 ksnprintf(tunable_name, sizeof(tunable_name),
2867 "hw.pci%d.%d.%d.INT%c.irq",
2868 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2869 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2870 irq = PCI_INVALID_IRQ;
2873 * If we didn't get an IRQ via the tunable, then we either use the
2874 * IRQ value in the intline register or we ask the bus to route an
2875 * interrupt for us. If force_route is true, then we only use the
2876 * value in the intline register if the bus was unable to assign an
2879 if (!PCI_INTERRUPT_VALID(irq)) {
2880 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2881 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2882 if (!PCI_INTERRUPT_VALID(irq))
2886 /* If after all that we don't have an IRQ, just bail. */
2887 if (!PCI_INTERRUPT_VALID(irq))
2890 /* Update the config register if it changed. */
2891 if (irq != cfg->intline) {
2893 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2896 /* Add this IRQ as rid 0 interrupt resource. */
2897 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1,
2898 machintr_intr_cpuid(irq));
2902 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2904 struct pci_devinfo *dinfo = device_get_ivars(dev);
2905 pcicfgregs *cfg = &dinfo->cfg;
2906 struct resource_list *rl = &dinfo->resources;
2907 struct pci_quirk *q;
2914 /* ATA devices needs special map treatment */
2915 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2916 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2917 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2918 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2919 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2920 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2922 for (i = 0; i < cfg->nummaps;)
2923 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2924 rl, force, prefetchmask & (1 << i));
2927 * Add additional, quirked resources.
2929 for (q = &pci_quirks[0]; q->devid; q++) {
2930 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2931 && q->type == PCI_QUIRK_MAP_REG)
2932 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2936 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2938 * Try to re-route interrupts. Sometimes the BIOS or
2939 * firmware may leave bogus values in these registers.
2940 * If the re-route fails, then just stick with what we
2943 pci_assign_interrupt(bus, dev, 1);
2948 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2950 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2951 device_t pcib = device_get_parent(dev);
2952 struct pci_devinfo *dinfo;
2954 int s, f, pcifunchigh;
2957 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2958 ("dinfo_size too small"));
2959 maxslots = PCIB_MAXSLOTS(pcib);
2960 for (s = 0; s <= maxslots; s++) {
2964 hdrtype = REG(PCIR_HDRTYPE, 1);
2965 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2967 if (hdrtype & PCIM_MFDEV)
2968 pcifunchigh = PCI_FUNCMAX;
2969 for (f = 0; f <= pcifunchigh; f++) {
2970 dinfo = pci_read_device(pcib, domain, busno, s, f,
2972 if (dinfo != NULL) {
2973 pci_add_child(dev, dinfo);
2981 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2985 pcib = device_get_parent(bus);
2986 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2987 device_set_ivars(dinfo->cfg.dev, dinfo);
2988 resource_list_init(&dinfo->resources);
2989 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2990 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2991 pci_print_verbose(dinfo);
2992 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2996 pci_probe(device_t dev)
2998 device_set_desc(dev, "PCI bus");
3000 /* Allow other subclasses to override this driver. */
3005 pci_attach(device_t dev)
3010 * Since there can be multiple independantly numbered PCI
3011 * busses on systems with multiple PCI domains, we can't use
3012 * the unit number to decide which bus we are probing. We ask
3013 * the parent pcib what our domain and bus numbers are.
3015 domain = pcib_get_domain(dev);
3016 busno = pcib_get_bus(dev);
3018 device_printf(dev, "domain=%d, physical bus=%d\n",
3021 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3023 return (bus_generic_attach(dev));
3027 pci_suspend(device_t dev)
3029 int dstate, error, i, numdevs;
3030 device_t acpi_dev, child, *devlist;
3031 struct pci_devinfo *dinfo;
3034 * Save the PCI configuration space for each child and set the
3035 * device in the appropriate power state for this sleep state.
3038 if (pci_do_power_resume)
3039 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3040 device_get_children(dev, &devlist, &numdevs);
3041 for (i = 0; i < numdevs; i++) {
3043 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3044 pci_cfg_save(child, dinfo, 0);
3047 /* Suspend devices before potentially powering them down. */
3048 error = bus_generic_suspend(dev);
3050 kfree(devlist, M_TEMP);
3055 * Always set the device to D3. If ACPI suggests a different
3056 * power state, use it instead. If ACPI is not present, the
3057 * firmware is responsible for managing device power. Skip
3058 * children who aren't attached since they are powered down
3059 * separately. Only manage type 0 devices for now.
3061 for (i = 0; acpi_dev && i < numdevs; i++) {
3063 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3064 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3065 dstate = PCI_POWERSTATE_D3;
3066 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3067 pci_set_powerstate(child, dstate);
3070 kfree(devlist, M_TEMP);
3075 pci_resume(device_t dev)
3078 device_t acpi_dev, child, *devlist;
3079 struct pci_devinfo *dinfo;
3082 * Set each child to D0 and restore its PCI configuration space.
3085 if (pci_do_power_resume)
3086 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3087 device_get_children(dev, &devlist, &numdevs);
3088 for (i = 0; i < numdevs; i++) {
3090 * Notify ACPI we're going to D0 but ignore the result. If
3091 * ACPI is not present, the firmware is responsible for
3092 * managing device power. Only manage type 0 devices for now.
3095 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3096 if (acpi_dev && device_is_attached(child) &&
3097 dinfo->cfg.hdrtype == 0) {
3098 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3099 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3102 /* Now the device is powered up, restore its config space. */
3103 pci_cfg_restore(child, dinfo);
3105 kfree(devlist, M_TEMP);
3106 return (bus_generic_resume(dev));
3110 pci_load_vendor_data(void)
3112 caddr_t vendordata, info;
3114 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3115 info = preload_search_info(vendordata, MODINFO_ADDR);
3116 pci_vendordata = *(char **)info;
3117 info = preload_search_info(vendordata, MODINFO_SIZE);
3118 pci_vendordata_size = *(size_t *)info;
3119 /* terminate the database */
3120 pci_vendordata[pci_vendordata_size] = '\n';
3125 pci_driver_added(device_t dev, driver_t *driver)
3130 struct pci_devinfo *dinfo;
3134 device_printf(dev, "driver added\n");
3135 DEVICE_IDENTIFY(driver, dev);
3136 device_get_children(dev, &devlist, &numdevs);
3137 for (i = 0; i < numdevs; i++) {
3139 if (device_get_state(child) != DS_NOTPRESENT)
3141 dinfo = device_get_ivars(child);
3142 pci_print_verbose(dinfo);
3144 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3145 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3147 pci_cfg_restore(child, dinfo);
3148 if (device_probe_and_attach(child) != 0)
3149 pci_cfg_save(child, dinfo, 1);
3151 kfree(devlist, M_TEMP);
3155 pci_child_detached(device_t parent __unused, device_t child)
3157 /* Turn child's power off */
3158 pci_cfg_save(child, device_get_ivars(child), 1);
3162 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3163 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3165 struct pci_devinfo *dinfo;
3166 struct msix_table_entry *mte;
3167 struct msix_vector *mv;
3173 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3174 arg, &cookie, serializer);
3178 /* If this is not a direct child, just bail out. */
3179 if (device_get_parent(child) != dev) {
3184 rid = rman_get_rid(irq);
3186 /* Make sure that INTx is enabled */
3187 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3190 * Check to see if the interrupt is MSI or MSI-X.
3191 * Ask our parent to map the MSI and give
3192 * us the address and data register values.
3193 * If we fail for some reason, teardown the
3194 * interrupt handler.
3196 dinfo = device_get_ivars(child);
3197 if (dinfo->cfg.msi.msi_alloc > 0) {
3198 if (dinfo->cfg.msi.msi_addr == 0) {
3199 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3200 ("MSI has handlers, but vectors not mapped"));
3201 error = PCIB_MAP_MSI(device_get_parent(dev),
3202 child, rman_get_start(irq), &addr, &data,
3203 rman_get_cpuid(irq));
3206 dinfo->cfg.msi.msi_addr = addr;
3207 dinfo->cfg.msi.msi_data = data;
3208 pci_enable_msi(child, addr, data);
3210 dinfo->cfg.msi.msi_handlers++;
3212 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3213 ("No MSI or MSI-X interrupts allocated"));
3214 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3215 ("MSI-X index too high"));
3216 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3217 KASSERT(mte->mte_vector != 0, ("no message vector"));
3218 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3219 KASSERT(mv->mv_irq == rman_get_start(irq),
3221 if (mv->mv_address == 0) {
3222 KASSERT(mte->mte_handlers == 0,
3223 ("MSI-X table entry has handlers, but vector not mapped"));
3224 error = PCIB_MAP_MSI(device_get_parent(dev),
3225 child, rman_get_start(irq), &addr, &data,
3226 rman_get_cpuid(irq));
3229 mv->mv_address = addr;
3232 if (mte->mte_handlers == 0) {
3233 pci_enable_msix(child, rid - 1, mv->mv_address,
3235 pci_unmask_msix(child, rid - 1);
3237 mte->mte_handlers++;
3240 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3241 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3244 (void)bus_generic_teardown_intr(dev, child, irq,
3254 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3257 struct msix_table_entry *mte;
3258 struct resource_list_entry *rle;
3259 struct pci_devinfo *dinfo;
3262 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3265 /* If this isn't a direct child, just bail out */
3266 if (device_get_parent(child) != dev)
3267 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3269 rid = rman_get_rid(irq);
3272 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3275 * Check to see if the interrupt is MSI or MSI-X. If so,
3276 * decrement the appropriate handlers count and mask the
3277 * MSI-X message, or disable MSI messages if the count
3280 dinfo = device_get_ivars(child);
3281 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3282 if (rle->res != irq)
3284 if (dinfo->cfg.msi.msi_alloc > 0) {
3285 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3286 ("MSI-X index too high"));
3287 if (dinfo->cfg.msi.msi_handlers == 0)
3289 dinfo->cfg.msi.msi_handlers--;
3290 if (dinfo->cfg.msi.msi_handlers == 0)
3291 pci_disable_msi(child);
3293 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3294 ("No MSI or MSI-X interrupts allocated"));
3295 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3296 ("MSI-X index too high"));
3297 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3298 if (mte->mte_handlers == 0)
3300 mte->mte_handlers--;
3301 if (mte->mte_handlers == 0)
3302 pci_mask_msix(child, rid - 1);
3305 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3308 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3313 pci_print_child(device_t dev, device_t child)
3315 struct pci_devinfo *dinfo;
3316 struct resource_list *rl;
3319 dinfo = device_get_ivars(child);
3320 rl = &dinfo->resources;
3322 retval += bus_print_child_header(dev, child);
3324 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3325 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3326 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3327 if (device_get_flags(dev))
3328 retval += kprintf(" flags %#x", device_get_flags(dev));
3330 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3331 pci_get_function(child));
3333 retval += bus_print_child_footer(dev, child);
3343 } pci_nomatch_tab[] = {
3344 {PCIC_OLD, -1, "old"},
3345 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3346 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3347 {PCIC_STORAGE, -1, "mass storage"},
3348 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3349 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3350 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3351 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3352 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3353 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3354 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3355 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3356 {PCIC_NETWORK, -1, "network"},
3357 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3358 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3359 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3360 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3361 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3362 {PCIC_DISPLAY, -1, "display"},
3363 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3364 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3365 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3366 {PCIC_MULTIMEDIA, -1, "multimedia"},
3367 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3368 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3369 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3370 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3371 {PCIC_MEMORY, -1, "memory"},
3372 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3373 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3374 {PCIC_BRIDGE, -1, "bridge"},
3375 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3376 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3377 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3378 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3379 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3380 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3381 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3382 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3383 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3384 {PCIC_SIMPLECOMM, -1, "simple comms"},
3385 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3386 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3387 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3388 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3389 {PCIC_BASEPERIPH, -1, "base peripheral"},
3390 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3391 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3392 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3393 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3394 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3395 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3396 {PCIC_INPUTDEV, -1, "input device"},
3397 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3398 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3399 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3400 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3401 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3402 {PCIC_DOCKING, -1, "docking station"},
3403 {PCIC_PROCESSOR, -1, "processor"},
3404 {PCIC_SERIALBUS, -1, "serial bus"},
3405 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3406 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3407 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3408 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3409 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3410 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3411 {PCIC_WIRELESS, -1, "wireless controller"},
3412 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3413 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3414 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3415 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3416 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3417 {PCIC_SATCOM, -1, "satellite communication"},
3418 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3419 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3420 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3421 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3422 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3423 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3424 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3425 {PCIC_DASP, -1, "dasp"},
3426 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3431 pci_probe_nomatch(device_t dev, device_t child)
3434 char *cp, *scp, *device;
3437 * Look for a listing for this device in a loaded device database.
3439 if ((device = pci_describe_device(child)) != NULL) {
3440 device_printf(dev, "<%s>", device);
3441 kfree(device, M_DEVBUF);
3444 * Scan the class/subclass descriptions for a general
3449 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3450 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3451 if (pci_nomatch_tab[i].subclass == -1) {
3452 cp = pci_nomatch_tab[i].desc;
3453 } else if (pci_nomatch_tab[i].subclass ==
3454 pci_get_subclass(child)) {
3455 scp = pci_nomatch_tab[i].desc;
3459 device_printf(dev, "<%s%s%s>",
3461 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3464 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3465 pci_get_vendor(child), pci_get_device(child),
3466 pci_get_slot(child), pci_get_function(child));
3467 if (pci_get_intpin(child) > 0) {
3470 irq = pci_get_irq(child);
3471 if (PCI_INTERRUPT_VALID(irq))
3472 kprintf(" irq %d", irq);
3476 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3480 * Parse the PCI device database, if loaded, and return a pointer to a
3481 * description of the device.
3483 * The database is flat text formatted as follows:
3485 * Any line not in a valid format is ignored.
3486 * Lines are terminated with newline '\n' characters.
3488 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3491 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3492 * - devices cannot be listed without a corresponding VENDOR line.
3493 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3494 * another TAB, then the device name.
3498 * Assuming (ptr) points to the beginning of a line in the database,
3499 * return the vendor or device and description of the next entry.
3500 * The value of (vendor) or (device) inappropriate for the entry type
3501 * is set to -1. Returns nonzero at the end of the database.
3503 * Note that this is slightly unrobust in the face of corrupt data;
3504 * we attempt to safeguard against this by spamming the end of the
3505 * database with a newline when we initialise.
3508 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3517 left = pci_vendordata_size - (cp - pci_vendordata);
3525 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3529 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3532 /* skip to next line */
3533 while (*cp != '\n' && left > 0) {
3542 /* skip to next line */
3543 while (*cp != '\n' && left > 0) {
3547 if (*cp == '\n' && left > 0)
3554 pci_describe_device(device_t dev)
3557 char *desc, *vp, *dp, *line;
3559 desc = vp = dp = NULL;
3562 * If we have no vendor data, we can't do anything.
3564 if (pci_vendordata == NULL)
3568 * Scan the vendor data looking for this device
3570 line = pci_vendordata;
3571 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3574 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3576 if (vendor == pci_get_vendor(dev))
3579 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3582 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3590 if (device == pci_get_device(dev))
3594 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3595 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3597 ksprintf(desc, "%s, %s", vp, dp);
3600 kfree(vp, M_DEVBUF);
3602 kfree(dp, M_DEVBUF);
3607 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3609 struct pci_devinfo *dinfo;
3612 dinfo = device_get_ivars(child);
3616 case PCI_IVAR_ETHADDR:
3618 * The generic accessor doesn't deal with failure, so
3619 * we set the return value, then return an error.
3621 *((uint8_t **) result) = NULL;
3623 case PCI_IVAR_SUBVENDOR:
3624 *result = cfg->subvendor;
3626 case PCI_IVAR_SUBDEVICE:
3627 *result = cfg->subdevice;
3629 case PCI_IVAR_VENDOR:
3630 *result = cfg->vendor;
3632 case PCI_IVAR_DEVICE:
3633 *result = cfg->device;
3635 case PCI_IVAR_DEVID:
3636 *result = (cfg->device << 16) | cfg->vendor;
3638 case PCI_IVAR_CLASS:
3639 *result = cfg->baseclass;
3641 case PCI_IVAR_SUBCLASS:
3642 *result = cfg->subclass;
3644 case PCI_IVAR_PROGIF:
3645 *result = cfg->progif;
3647 case PCI_IVAR_REVID:
3648 *result = cfg->revid;
3650 case PCI_IVAR_INTPIN:
3651 *result = cfg->intpin;
3654 *result = cfg->intline;
3656 case PCI_IVAR_DOMAIN:
3657 *result = cfg->domain;
3663 *result = cfg->slot;
3665 case PCI_IVAR_FUNCTION:
3666 *result = cfg->func;
3668 case PCI_IVAR_CMDREG:
3669 *result = cfg->cmdreg;
3671 case PCI_IVAR_CACHELNSZ:
3672 *result = cfg->cachelnsz;
3674 case PCI_IVAR_MINGNT:
3675 *result = cfg->mingnt;
3677 case PCI_IVAR_MAXLAT:
3678 *result = cfg->maxlat;
3680 case PCI_IVAR_LATTIMER:
3681 *result = cfg->lattimer;
3683 case PCI_IVAR_PCIXCAP_PTR:
3684 *result = cfg->pcix.pcix_ptr;
3686 case PCI_IVAR_PCIECAP_PTR:
3687 *result = cfg->expr.expr_ptr;
3689 case PCI_IVAR_VPDCAP_PTR:
3690 *result = cfg->vpd.vpd_reg;
3699 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3701 struct pci_devinfo *dinfo;
3703 dinfo = device_get_ivars(child);
3706 case PCI_IVAR_INTPIN:
3707 dinfo->cfg.intpin = value;
3709 case PCI_IVAR_ETHADDR:
3710 case PCI_IVAR_SUBVENDOR:
3711 case PCI_IVAR_SUBDEVICE:
3712 case PCI_IVAR_VENDOR:
3713 case PCI_IVAR_DEVICE:
3714 case PCI_IVAR_DEVID:
3715 case PCI_IVAR_CLASS:
3716 case PCI_IVAR_SUBCLASS:
3717 case PCI_IVAR_PROGIF:
3718 case PCI_IVAR_REVID:
3720 case PCI_IVAR_DOMAIN:
3723 case PCI_IVAR_FUNCTION:
3724 return (EINVAL); /* disallow for now */
3731 #include "opt_ddb.h"
3733 #include <ddb/ddb.h>
3734 #include <sys/cons.h>
3737 * List resources based on pci map registers, used for within ddb
3740 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3742 struct pci_devinfo *dinfo;
3743 struct devlist *devlist_head;
3746 int i, error, none_count;
3749 /* get the head of the device queue */
3750 devlist_head = &pci_devq;
3753 * Go through the list of devices and print out devices
3755 for (error = 0, i = 0,
3756 dinfo = STAILQ_FIRST(devlist_head);
3757 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3758 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3760 /* Populate pd_name and pd_unit */
3763 name = device_get_name(dinfo->cfg.dev);
3766 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3767 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3768 (name && *name) ? name : "none",
3769 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3771 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3772 p->pc_sel.pc_func, (p->pc_class << 16) |
3773 (p->pc_subclass << 8) | p->pc_progif,
3774 (p->pc_subdevice << 16) | p->pc_subvendor,
3775 (p->pc_device << 16) | p->pc_vendor,
3776 p->pc_revid, p->pc_hdr);
3782 static struct resource *
3783 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3784 u_long start, u_long end, u_long count, u_int flags)
3786 struct pci_devinfo *dinfo = device_get_ivars(child);
3787 struct resource_list *rl = &dinfo->resources;
3788 struct resource_list_entry *rle;
3789 struct resource *res;
3790 pci_addr_t map, testval;
3794 * Weed out the bogons, and figure out how large the BAR/map
3795 * is. Bars that read back 0 here are bogus and unimplemented.
3796 * Note: atapci in legacy mode are special and handled elsewhere
3797 * in the code. If you have a atapci device in legacy mode and
3798 * it fails here, that other code is broken.
3801 map = pci_read_config(child, *rid, 4);
3802 pci_write_config(child, *rid, 0xffffffff, 4);
3803 testval = pci_read_config(child, *rid, 4);
3804 if (pci_maprange(testval) == 64)
3805 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3806 if (pci_mapbase(testval) == 0)
3810 * Restore the original value of the BAR. We may have reprogrammed
3811 * the BAR of the low-level console device and when booting verbose,
3812 * we need the console device addressable.
3814 pci_write_config(child, *rid, map, 4);
3816 if (PCI_BAR_MEM(testval)) {
3817 if (type != SYS_RES_MEMORY) {
3820 "child %s requested type %d for rid %#x,"
3821 " but the BAR says it is an memio\n",
3822 device_get_nameunit(child), type, *rid);
3826 if (type != SYS_RES_IOPORT) {
3829 "child %s requested type %d for rid %#x,"
3830 " but the BAR says it is an ioport\n",
3831 device_get_nameunit(child), type, *rid);
3836 * For real BARs, we need to override the size that
3837 * the driver requests, because that's what the BAR
3838 * actually uses and we would otherwise have a
3839 * situation where we might allocate the excess to
3840 * another driver, which won't work.
3842 mapsize = pci_mapsize(testval);
3843 count = 1UL << mapsize;
3844 if (RF_ALIGNMENT(flags) < mapsize)
3845 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3846 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3847 flags |= RF_PREFETCHABLE;
3850 * Allocate enough resource, and then write back the
3851 * appropriate bar for that resource.
3853 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3854 start, end, count, flags, -1);
3856 device_printf(child,
3857 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3858 count, *rid, type, start, end);
3861 resource_list_add(rl, type, *rid, start, end, count, -1);
3862 rle = resource_list_find(rl, type, *rid);
3864 panic("pci_alloc_map: unexpectedly can't find resource.");
3866 rle->start = rman_get_start(res);
3867 rle->end = rman_get_end(res);
3870 device_printf(child,
3871 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3872 count, *rid, type, rman_get_start(res));
3873 map = rman_get_start(res);
3875 pci_write_config(child, *rid, map, 4);
3876 if (pci_maprange(testval) == 64)
3877 pci_write_config(child, *rid + 4, map >> 32, 4);
3883 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3884 u_long start, u_long end, u_long count, u_int flags, int cpuid)
3886 struct pci_devinfo *dinfo = device_get_ivars(child);
3887 struct resource_list *rl = &dinfo->resources;
3888 struct resource_list_entry *rle;
3889 pcicfgregs *cfg = &dinfo->cfg;
3892 * Perform lazy resource allocation
3894 if (device_get_parent(child) == dev) {
3898 * Can't alloc legacy interrupt once MSI messages
3899 * have been allocated.
3901 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3902 cfg->msix.msix_alloc > 0))
3905 * If the child device doesn't have an
3906 * interrupt routed and is deserving of an
3907 * interrupt, try to assign it one.
3909 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3911 pci_assign_interrupt(dev, child, 0);
3913 case SYS_RES_IOPORT:
3914 case SYS_RES_MEMORY:
3915 if (*rid < PCIR_BAR(cfg->nummaps)) {
3917 * Enable the I/O mode. We should
3918 * also be assigning resources too
3919 * when none are present. The
3920 * resource_list_alloc kind of sorta does
3923 if (PCI_ENABLE_IO(dev, child, type))
3926 rle = resource_list_find(rl, type, *rid);
3928 return (pci_alloc_map(dev, child, type, rid,
3929 start, end, count, flags));
3933 * If we've already allocated the resource, then
3934 * return it now. But first we may need to activate
3935 * it, since we don't allocate the resource as active
3936 * above. Normally this would be done down in the
3937 * nexus, but since we short-circuit that path we have
3938 * to do its job here. Not sure if we should kfree the
3939 * resource if it fails to activate.
3941 rle = resource_list_find(rl, type, *rid);
3942 if (rle != NULL && rle->res != NULL) {
3944 device_printf(child,
3945 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3946 rman_get_size(rle->res), *rid, type,
3947 rman_get_start(rle->res));
3948 if ((flags & RF_ACTIVE) &&
3949 bus_generic_activate_resource(dev, child, type,
3950 *rid, rle->res) != 0)
3955 return (resource_list_alloc(rl, dev, child, type, rid,
3956 start, end, count, flags, cpuid));
3960 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3962 struct pci_devinfo *dinfo;
3963 struct resource_list *rl;
3964 struct resource_list_entry *rle;
3966 if (device_get_parent(child) != dev)
3969 dinfo = device_get_ivars(child);
3970 rl = &dinfo->resources;
3971 rle = resource_list_find(rl, type, rid);
3974 if (rman_get_device(rle->res) != dev ||
3975 rman_get_flags(rle->res) & RF_ACTIVE) {
3976 device_printf(dev, "delete_resource: "
3977 "Resource still owned by child, oops. "
3978 "(type=%d, rid=%d, addr=%lx)\n",
3979 rle->type, rle->rid,
3980 rman_get_start(rle->res));
3983 bus_release_resource(dev, type, rid, rle->res);
3985 resource_list_delete(rl, type, rid);
3988 * Why do we turn off the PCI configuration BAR when we delete a
3991 pci_write_config(child, rid, 0, 4);
3992 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3995 struct resource_list *
3996 pci_get_resource_list (device_t dev, device_t child)
3998 struct pci_devinfo *dinfo = device_get_ivars(child);
4003 return (&dinfo->resources);
4007 pci_read_config_method(device_t dev, device_t child, int reg, int width)
4009 struct pci_devinfo *dinfo = device_get_ivars(child);
4010 pcicfgregs *cfg = &dinfo->cfg;
4012 return (PCIB_READ_CONFIG(device_get_parent(dev),
4013 cfg->bus, cfg->slot, cfg->func, reg, width));
4017 pci_write_config_method(device_t dev, device_t child, int reg,
4018 uint32_t val, int width)
4020 struct pci_devinfo *dinfo = device_get_ivars(child);
4021 pcicfgregs *cfg = &dinfo->cfg;
4023 PCIB_WRITE_CONFIG(device_get_parent(dev),
4024 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4028 pci_child_location_str_method(device_t dev, device_t child, char *buf,
4032 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4033 pci_get_function(child));
4038 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4041 struct pci_devinfo *dinfo;
4044 dinfo = device_get_ivars(child);
4046 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4047 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4048 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4054 pci_assign_interrupt_method(device_t dev, device_t child)
4056 struct pci_devinfo *dinfo = device_get_ivars(child);
4057 pcicfgregs *cfg = &dinfo->cfg;
4059 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4064 pci_modevent(module_t mod, int what, void *arg)
4066 static struct cdev *pci_cdev;
4070 STAILQ_INIT(&pci_devq);
4072 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
4074 pci_load_vendor_data();
4078 destroy_dev(pci_cdev);
4086 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4091 * Only do header type 0 devices. Type 1 devices are bridges,
4092 * which we know need special treatment. Type 2 devices are
4093 * cardbus bridges which also require special treatment.
4094 * Other types are unknown, and we err on the side of safety
4097 if (dinfo->cfg.hdrtype != 0)
4101 * Restore the device to full power mode. We must do this
4102 * before we restore the registers because moving from D3 to
4103 * D0 will cause the chip's BARs and some other registers to
4104 * be reset to some unknown power on reset values. Cut down
4105 * the noise on boot by doing nothing if we are already in
4108 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4109 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4111 for (i = 0; i < dinfo->cfg.nummaps; i++)
4112 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4113 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4114 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4115 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4116 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4117 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4118 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4119 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4120 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4121 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4122 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4124 /* Restore MSI and MSI-X configurations if they are present. */
4125 if (dinfo->cfg.msi.msi_location != 0)
4126 pci_resume_msi(dev);
4127 if (dinfo->cfg.msix.msix_location != 0)
4128 pci_resume_msix(dev);
4132 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4139 * Only do header type 0 devices. Type 1 devices are bridges, which
4140 * we know need special treatment. Type 2 devices are cardbus bridges
4141 * which also require special treatment. Other types are unknown, and
4142 * we err on the side of safety by ignoring them. Powering down
4143 * bridges should not be undertaken lightly.
4145 if (dinfo->cfg.hdrtype != 0)
4147 for (i = 0; i < dinfo->cfg.nummaps; i++)
4148 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4149 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4152 * Some drivers apparently write to these registers w/o updating our
4153 * cached copy. No harm happens if we update the copy, so do so here
4154 * so we can restore them. The COMMAND register is modified by the
4155 * bus w/o updating the cache. This should represent the normally
4156 * writable portion of the 'defined' part of type 0 headers. In
4157 * theory we also need to save/restore the PCI capability structures
4158 * we know about, but apart from power we don't know any that are
4161 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4162 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4163 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4164 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4165 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4166 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4167 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4168 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4169 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4170 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4171 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4172 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4173 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4174 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4175 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4178 * don't set the state for display devices, base peripherals and
4179 * memory devices since bad things happen when they are powered down.
4180 * We should (a) have drivers that can easily detach and (b) use
4181 * generic drivers for these devices so that some device actually
4182 * attaches. We need to make sure that when we implement (a) we don't
4183 * power the device down on a reattach.
4185 cls = pci_get_class(dev);
4188 switch (pci_do_power_nodriver)
4190 case 0: /* NO powerdown at all */
4192 case 1: /* Conservative about what to power down */
4193 if (cls == PCIC_STORAGE)
4196 case 2: /* Agressive about what to power down */
4197 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4198 cls == PCIC_BASEPERIPH)
4201 case 3: /* Power down everything */
4205 * PCI spec says we can only go into D3 state from D0 state.
4206 * Transition from D[12] into D0 before going to D3 state.
4208 ps = pci_get_powerstate(dev);
4209 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4210 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4211 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4212 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4215 #ifdef COMPAT_OLDPCI
4218 * Locate the parent of a PCI device by scanning the PCI devlist
4219 * and return the entry for the parent.
4220 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4221 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4224 pci_devlist_get_parent(pcicfgregs *cfg)
4226 struct devlist *devlist_head;
4227 struct pci_devinfo *dinfo;
4228 pcicfgregs *bridge_cfg;
4231 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4233 /* If the device is on PCI bus 0, look for the host */
4234 if (cfg->bus == 0) {
4235 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4236 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4237 bridge_cfg = &dinfo->cfg;
4238 if (bridge_cfg->baseclass == PCIC_BRIDGE
4239 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4240 && bridge_cfg->bus == cfg->bus) {
4246 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4248 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4249 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4250 bridge_cfg = &dinfo->cfg;
4251 if (bridge_cfg->baseclass == PCIC_BRIDGE
4252 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4253 && bridge_cfg->secondarybus == cfg->bus) {
4262 #endif /* COMPAT_OLDPCI */