sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_ifpoll.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67
  68 #include <bus/pci/pcivar.h>
  69 #include <bus/pci/pcireg.h>
  70
  71 #include <dev/netif/ig_hal/e1000_api.h>
  72 #include <dev/netif/ig_hal/e1000_82575.h>
  73 #include <dev/netif/ig_hal/e1000_dragonfly.h>
  74 #include <dev/netif/igb/if_igb.h>
  75
  76 #ifdef IGB_RSS_DEBUG
  77 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  78 do { \
  79         if (sc->rss_debug >= lvl) \
  80                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  81 } while (0)
  82 #else   /* !IGB_RSS_DEBUG */
  83 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  84 #endif  /* IGB_RSS_DEBUG */
  85
  86 #define IGB_NAME        "Intel(R) PRO/1000 "
  87 #define IGB_DEVICE(id)  \
  88         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  89 #define IGB_DEVICE_NULL { 0, 0, NULL }
  90
  91 static struct igb_device {
  92         uint16_t        vid;
  93         uint16_t        did;
  94         const char      *desc;
  95 } igb_devices[] = {
  96         IGB_DEVICE(82575EB_COPPER),
  97         IGB_DEVICE(82575EB_FIBER_SERDES),
  98         IGB_DEVICE(82575GB_QUAD_COPPER),
  99         IGB_DEVICE(82576),
 100         IGB_DEVICE(82576_NS),
 101         IGB_DEVICE(82576_NS_SERDES),
 102         IGB_DEVICE(82576_FIBER),
 103         IGB_DEVICE(82576_SERDES),
 104         IGB_DEVICE(82576_SERDES_QUAD),
 105         IGB_DEVICE(82576_QUAD_COPPER),
 106         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 107         IGB_DEVICE(82576_VF),
 108         IGB_DEVICE(82580_COPPER),
 109         IGB_DEVICE(82580_FIBER),
 110         IGB_DEVICE(82580_SERDES),
 111         IGB_DEVICE(82580_SGMII),
 112         IGB_DEVICE(82580_COPPER_DUAL),
 113         IGB_DEVICE(82580_QUAD_FIBER),
 114         IGB_DEVICE(DH89XXCC_SERDES),
 115         IGB_DEVICE(DH89XXCC_SGMII),
 116         IGB_DEVICE(DH89XXCC_SFP),
 117         IGB_DEVICE(DH89XXCC_BACKPLANE),
 118         IGB_DEVICE(I350_COPPER),
 119         IGB_DEVICE(I350_FIBER),
 120         IGB_DEVICE(I350_SERDES),
 121         IGB_DEVICE(I350_SGMII),
 122         IGB_DEVICE(I350_VF),
 123         IGB_DEVICE(I210_COPPER),
 124         IGB_DEVICE(I210_COPPER_IT),
 125         IGB_DEVICE(I210_COPPER_OEM1),
 126         IGB_DEVICE(I210_COPPER_FLASHLESS),
 127         IGB_DEVICE(I210_SERDES_FLASHLESS),
 128         IGB_DEVICE(I210_FIBER),
 129         IGB_DEVICE(I210_SERDES),
 130         IGB_DEVICE(I210_SGMII),
 131         IGB_DEVICE(I211_COPPER),
 132         IGB_DEVICE(I354_BACKPLANE_1GBPS),
 133         IGB_DEVICE(I354_SGMII),
 134
 135         /* required last entry */
 136         IGB_DEVICE_NULL
 137 };
 138
 139 static int      igb_probe(device_t);
 140 static int      igb_attach(device_t);
 141 static int      igb_detach(device_t);
 142 static int      igb_shutdown(device_t);
 143 static int      igb_suspend(device_t);
 144 static int      igb_resume(device_t);
 145
 146 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 147 static void     igb_setup_ifp(struct igb_softc *);
 148 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
 149 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
 150 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
 151 static void     igb_add_sysctl(struct igb_softc *);
 152 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 153 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
 154 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 155 static int      igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 156 static int      igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 157 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
 158 static int      igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
 159 static int      igb_get_txring_inuse(const struct igb_softc *, boolean_t);
 160 static void     igb_set_timer_cpuid(struct igb_softc *, boolean_t);
 161 #ifdef IFPOLL_ENABLE
 162 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 163 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 164 #endif
 165
 166 static void     igb_vf_init_stats(struct igb_softc *);
 167 static void     igb_reset(struct igb_softc *);
 168 static void     igb_update_stats_counters(struct igb_softc *);
 169 static void     igb_update_vf_stats_counters(struct igb_softc *);
 170 static void     igb_update_link_status(struct igb_softc *);
 171 static void     igb_init_tx_unit(struct igb_softc *);
 172 static void     igb_init_rx_unit(struct igb_softc *);
 173
 174 static void     igb_set_vlan(struct igb_softc *);
 175 static void     igb_set_multi(struct igb_softc *);
 176 static void     igb_set_promisc(struct igb_softc *);
 177 static void     igb_disable_promisc(struct igb_softc *);
 178
 179 static int      igb_alloc_rings(struct igb_softc *);
 180 static void     igb_free_rings(struct igb_softc *);
 181 static int      igb_create_tx_ring(struct igb_tx_ring *);
 182 static int      igb_create_rx_ring(struct igb_rx_ring *);
 183 static void     igb_free_tx_ring(struct igb_tx_ring *);
 184 static void     igb_free_rx_ring(struct igb_rx_ring *);
 185 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 186 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 187 static void     igb_init_tx_ring(struct igb_tx_ring *);
 188 static int      igb_init_rx_ring(struct igb_rx_ring *);
 189 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 190 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
 191 static void     igb_rx_refresh(struct igb_rx_ring *, int);
 192 static void     igb_setup_serializer(struct igb_softc *);
 193
 194 static void     igb_stop(struct igb_softc *);
 195 static void     igb_init(void *);
 196 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 197 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 198 static int      igb_media_change(struct ifnet *);
 199 static void     igb_timer(void *);
 200 static void     igb_watchdog(struct ifaltq_subque *);
 201 static void     igb_start(struct ifnet *, struct ifaltq_subque *);
 202 #ifdef IFPOLL_ENABLE
 203 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
 204 static void     igb_npoll_rx(struct ifnet *, void *, int);
 205 static void     igb_npoll_tx(struct ifnet *, void *, int);
 206 static void     igb_npoll_status(struct ifnet *);
 207 #endif
 208 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 209 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 210 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 211 #ifdef INVARIANTS
 212 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 213                     boolean_t);
 214 #endif
 215
 216 static void     igb_intr(void *);
 217 static void     igb_intr_shared(void *);
 218 static void     igb_rxeof(struct igb_rx_ring *, int);
 219 static void     igb_txeof(struct igb_tx_ring *);
 220 static void     igb_set_eitr(struct igb_softc *, int, int);
 221 static void     igb_enable_intr(struct igb_softc *);
 222 static void     igb_disable_intr(struct igb_softc *);
 223 static void     igb_init_unshared_intr(struct igb_softc *);
 224 static void     igb_init_intr(struct igb_softc *);
 225 static int      igb_setup_intr(struct igb_softc *);
 226 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
 227 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
 228 static void     igb_set_intr_mask(struct igb_softc *);
 229 static int      igb_alloc_intr(struct igb_softc *);
 230 static void     igb_free_intr(struct igb_softc *);
 231 static void     igb_teardown_intr(struct igb_softc *);
 232 static void     igb_msix_try_alloc(struct igb_softc *);
 233 static void     igb_msix_rx_conf(struct igb_softc *, int, int *, int);
 234 static void     igb_msix_tx_conf(struct igb_softc *, int, int *, int);
 235 static void     igb_msix_free(struct igb_softc *, boolean_t);
 236 static int      igb_msix_setup(struct igb_softc *);
 237 static void     igb_msix_teardown(struct igb_softc *, int);
 238 static void     igb_msix_rx(void *);
 239 static void     igb_msix_tx(void *);
 240 static void     igb_msix_status(void *);
 241 static void     igb_msix_rxtx(void *);
 242
 243 /* Management and WOL Support */
 244 static void     igb_get_mgmt(struct igb_softc *);
 245 static void     igb_rel_mgmt(struct igb_softc *);
 246 static void     igb_get_hw_control(struct igb_softc *);
 247 static void     igb_rel_hw_control(struct igb_softc *);
 248 static void     igb_enable_wol(device_t);
 249
 250 static device_method_t igb_methods[] = {
 251         /* Device interface */
 252         DEVMETHOD(device_probe,         igb_probe),
 253         DEVMETHOD(device_attach,        igb_attach),
 254         DEVMETHOD(device_detach,        igb_detach),
 255         DEVMETHOD(device_shutdown,      igb_shutdown),
 256         DEVMETHOD(device_suspend,       igb_suspend),
 257         DEVMETHOD(device_resume,        igb_resume),
 258         DEVMETHOD_END
 259 };
 260
 261 static driver_t igb_driver = {
 262         "igb",
 263         igb_methods,
 264         sizeof(struct igb_softc),
 265 };
 266
 267 static devclass_t igb_devclass;
 268
 269 DECLARE_DUMMY_MODULE(if_igb);
 270 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 271 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 272
 273 static int      igb_rxd = IGB_DEFAULT_RXD;
 274 static int      igb_txd = IGB_DEFAULT_TXD;
 275 static int      igb_rxr = 0;
 276 static int      igb_txr = 0;
 277 static int      igb_msi_enable = 1;
 278 static int      igb_msix_enable = 1;
 279 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 280
 281 static char     igb_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_RXPAUSE;
 282
 283 /*
 284  * DMA Coalescing, only for i350 - default to off,
 285  * this feature is for power savings
 286  */
 287 static int      igb_dma_coalesce = 0;
 288
 289 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 290 TUNABLE_INT("hw.igb.txd", &igb_txd);
 291 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 292 TUNABLE_INT("hw.igb.txr", &igb_txr);
 293 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 294 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 295 TUNABLE_STR("hw.igb.flow_ctrl", igb_flowctrl, sizeof(igb_flowctrl));
 296
 297 /* i350 specific */
 298 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 299 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 300
 301 static __inline void
 302 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 303 {
 304         /* Ignore Checksum bit is set */
 305         if (staterr & E1000_RXD_STAT_IXSM)
 306                 return;
 307
 308         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 309             E1000_RXD_STAT_IPCS)
 310                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 311
 312         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 313                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 314                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 315                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 316                         mp->m_pkthdr.csum_data = htons(0xffff);
 317                 }
 318         }
 319 }
 320
 321 static __inline struct pktinfo *
 322 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 323     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 324 {
 325         switch (hashtype) {
 326         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 327                 pi->pi_netisr = NETISR_IP;
 328                 pi->pi_flags = 0;
 329                 pi->pi_l3proto = IPPROTO_TCP;
 330                 break;
 331
 332         case E1000_RXDADV_RSSTYPE_IPV4:
 333                 if (staterr & E1000_RXD_STAT_IXSM)
 334                         return NULL;
 335
 336                 if ((staterr &
 337                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 338                     E1000_RXD_STAT_TCPCS) {
 339                         pi->pi_netisr = NETISR_IP;
 340                         pi->pi_flags = 0;
 341                         pi->pi_l3proto = IPPROTO_UDP;
 342                         break;
 343                 }
 344                 /* FALL THROUGH */
 345         default:
 346                 return NULL;
 347         }
 348
 349         m->m_flags |= M_HASH;
 350         m->m_pkthdr.hash = toeplitz_hash(hash);
 351         return pi;
 352 }
 353
 354 static int
 355 igb_probe(device_t dev)
 356 {
 357         const struct igb_device *d;
 358         uint16_t vid, did;
 359
 360         vid = pci_get_vendor(dev);
 361         did = pci_get_device(dev);
 362
 363         for (d = igb_devices; d->desc != NULL; ++d) {
 364                 if (vid == d->vid && did == d->did) {
 365                         device_set_desc(dev, d->desc);
 366                         return 0;
 367                 }
 368         }
 369         return ENXIO;
 370 }
 371
 372 static int
 373 igb_attach(device_t dev)
 374 {
 375         struct igb_softc *sc = device_get_softc(dev);
 376         uint16_t eeprom_data;
 377         int error = 0, ring_max;
 378         char flowctrl[IFM_ETH_FC_STRLEN];
 379 #ifdef IFPOLL_ENABLE
 380         int offset, offset_def;
 381 #endif
 382
 383 #ifdef notyet
 384         /* SYSCTL stuff */
 385         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 386             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 387             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 388             igb_sysctl_nvm_info, "I", "NVM Information");
 389         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 390             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 391             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 392             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 393 #endif
 394
 395         callout_init_mp(&sc->timer);
 396         lwkt_serialize_init(&sc->main_serialize);
 397
 398         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
 399             device_get_unit(dev));
 400         sc->dev = sc->osdep.dev = dev;
 401
 402         /*
 403          * Determine hardware and mac type
 404          */
 405         sc->hw.vendor_id = pci_get_vendor(dev);
 406         sc->hw.device_id = pci_get_device(dev);
 407         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 408         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 409         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 410
 411         if (e1000_set_mac_type(&sc->hw))
 412                 return ENXIO;
 413
 414         /* Are we a VF device? */
 415         if (sc->hw.mac.type == e1000_vfadapt ||
 416             sc->hw.mac.type == e1000_vfadapt_i350)
 417                 sc->vf_ifp = 1;
 418         else
 419                 sc->vf_ifp = 0;
 420
 421         /*
 422          * Configure total supported RX/TX ring count
 423          */
 424         switch (sc->hw.mac.type) {
 425         case e1000_82575:
 426                 ring_max = IGB_MAX_RING_82575;
 427                 break;
 428
 429         case e1000_82576:
 430                 ring_max = IGB_MAX_RING_82576;
 431                 break;
 432
 433         case e1000_82580:
 434                 ring_max = IGB_MAX_RING_82580;
 435                 break;
 436
 437         case e1000_i350:
 438                 ring_max = IGB_MAX_RING_I350;
 439                 break;
 440
 441         case e1000_i354:
 442                 ring_max = IGB_MAX_RING_I354;
 443                 break;
 444
 445         case e1000_i210:
 446                 ring_max = IGB_MAX_RING_I210;
 447                 break;
 448
 449         case e1000_i211:
 450                 ring_max = IGB_MAX_RING_I211;
 451                 break;
 452
 453         default:
 454                 ring_max = IGB_MIN_RING;
 455                 break;
 456         }
 457
 458         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 459         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 460 #ifdef IGB_RSS_DEBUG
 461         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 462 #endif
 463         sc->rx_ring_inuse = sc->rx_ring_cnt;
 464
 465         sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
 466         sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, ring_max);
 467 #ifdef IGB_TSS_DEBUG
 468         sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
 469 #endif
 470         sc->tx_ring_inuse = sc->tx_ring_cnt;
 471
 472         /* Setup flow control. */
 473         device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl),
 474             igb_flowctrl);
 475         sc->ifm_flowctrl = ifmedia_str2ethfc(flowctrl);
 476
 477         /* Enable bus mastering */
 478         pci_enable_busmaster(dev);
 479
 480         /*
 481          * Allocate IO memory
 482          */
 483         sc->mem_rid = PCIR_BAR(0);
 484         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 485             RF_ACTIVE);
 486         if (sc->mem_res == NULL) {
 487                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 488                 error = ENXIO;
 489                 goto failed;
 490         }
 491         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 492         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 493
 494         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 495
 496         /* Save PCI command register for Shared Code */
 497         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 498         sc->hw.back = &sc->osdep;
 499
 500         /* Do Shared Code initialization */
 501         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 502                 device_printf(dev, "Setup of Shared code failed\n");
 503                 error = ENXIO;
 504                 goto failed;
 505         }
 506
 507         e1000_get_bus_info(&sc->hw);
 508
 509         sc->hw.mac.autoneg = DO_AUTO_NEG;
 510         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 511         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 512
 513         /* Copper options */
 514         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 515                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 516                 sc->hw.phy.disable_polarity_correction = FALSE;
 517                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 518         }
 519
 520         /* Set the frame limits assuming  standard ethernet sized frames. */
 521         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 522
 523         /* Allocate RX/TX rings */
 524         error = igb_alloc_rings(sc);
 525         if (error)
 526                 goto failed;
 527
 528 #ifdef IFPOLL_ENABLE
 529         /*
 530          * NPOLLING RX CPU offset
 531          */
 532         if (sc->rx_ring_cnt == ncpus2) {
 533                 offset = 0;
 534         } else {
 535                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
 536                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
 537                 if (offset >= ncpus2 ||
 538                     offset % sc->rx_ring_cnt != 0) {
 539                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
 540                             offset, offset_def);
 541                         offset = offset_def;
 542                 }
 543         }
 544         sc->rx_npoll_off = offset;
 545
 546         /*
 547          * NPOLLING TX CPU offset
 548          */
 549         if (sc->tx_ring_cnt == ncpus2) {
 550                 offset = 0;
 551         } else {
 552                 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
 553                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
 554                 if (offset >= ncpus2 ||
 555                     offset % sc->tx_ring_cnt != 0) {
 556                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
 557                             offset, offset_def);
 558                         offset = offset_def;
 559                 }
 560         }
 561         sc->tx_npoll_off = offset;
 562 #endif
 563
 564         /* Allocate interrupt */
 565         error = igb_alloc_intr(sc);
 566         if (error)
 567                 goto failed;
 568
 569         /* Setup serializers */
 570         igb_setup_serializer(sc);
 571
 572         /* Allocate the appropriate stats memory */
 573         if (sc->vf_ifp) {
 574                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 575                     M_WAITOK | M_ZERO);
 576                 igb_vf_init_stats(sc);
 577         } else {
 578                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 579                     M_WAITOK | M_ZERO);
 580         }
 581
 582         /* Allocate multicast array memory. */
 583         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 584             M_DEVBUF, M_WAITOK);
 585
 586         /* Some adapter-specific advanced features */
 587         if (sc->hw.mac.type >= e1000_i350) {
 588 #ifdef notyet
 589                 igb_set_sysctl_value(adapter, "dma_coalesce",
 590                     "configure dma coalesce",
 591                     &adapter->dma_coalesce, igb_dma_coalesce);
 592                 igb_set_sysctl_value(adapter, "eee_disabled",
 593                     "enable Energy Efficient Ethernet",
 594                     &adapter->hw.dev_spec._82575.eee_disable,
 595                     igb_eee_disabled);
 596 #else
 597                 sc->dma_coalesce = igb_dma_coalesce;
 598                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 599 #endif
 600                 if (sc->hw.phy.media_type == e1000_media_type_copper) {
 601                         if (sc->hw.mac.type == e1000_i354)
 602                                 e1000_set_eee_i354(&sc->hw);
 603                         else
 604                                 e1000_set_eee_i350(&sc->hw);
 605                 }
 606         }
 607
 608         /*
 609          * Start from a known state, this is important in reading the nvm and
 610          * mac from that.
 611          */
 612         e1000_reset_hw(&sc->hw);
 613
 614         /* Make sure we have a good EEPROM before we read from it */
 615         if (sc->hw.mac.type != e1000_i210 && sc->hw.mac.type != e1000_i211 &&
 616             e1000_validate_nvm_checksum(&sc->hw) < 0) {
 617                 /*
 618                  * Some PCI-E parts fail the first check due to
 619                  * the link being in sleep state, call it again,
 620                  * if it fails a second time its a real issue.
 621                  */
 622                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 623                         device_printf(dev,
 624                             "The EEPROM Checksum Is Not Valid\n");
 625                         error = EIO;
 626                         goto failed;
 627                 }
 628         }
 629
 630         /* Copy the permanent MAC address out of the EEPROM */
 631         if (e1000_read_mac_addr(&sc->hw) < 0) {
 632                 device_printf(dev, "EEPROM read error while reading MAC"
 633                     " address\n");
 634                 error = EIO;
 635                 goto failed;
 636         }
 637         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 638                 device_printf(dev, "Invalid MAC address\n");
 639                 error = EIO;
 640                 goto failed;
 641         }
 642
 643         /* Setup OS specific network interface */
 644         igb_setup_ifp(sc);
 645
 646         /* Add sysctl tree, must after igb_setup_ifp() */
 647         igb_add_sysctl(sc);
 648
 649         /* Now get a good starting state */
 650         igb_reset(sc);
 651
 652         /* Initialize statistics */
 653         igb_update_stats_counters(sc);
 654
 655         sc->hw.mac.get_link_status = 1;
 656         igb_update_link_status(sc);
 657
 658         /* Indicate SOL/IDER usage */
 659         if (e1000_check_reset_block(&sc->hw)) {
 660                 device_printf(dev,
 661                     "PHY reset is blocked due to SOL/IDER session.\n");
 662         }
 663
 664         /* Determine if we have to control management hardware */
 665         if (e1000_enable_mng_pass_thru(&sc->hw))
 666                 sc->flags |= IGB_FLAG_HAS_MGMT;
 667
 668         /*
 669          * Setup Wake-on-Lan
 670          */
 671         /* APME bit in EEPROM is mapped to WUC.APME */
 672         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 673         if (eeprom_data)
 674                 sc->wol = E1000_WUFC_MAG;
 675         /* XXX disable WOL */
 676         sc->wol = 0;
 677
 678 #ifdef notyet
 679         /* Register for VLAN events */
 680         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 681              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 682         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 683              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 684 #endif
 685
 686 #ifdef notyet
 687         igb_add_hw_stats(adapter);
 688 #endif
 689
 690         /*
 691          * Disable interrupt to prevent spurious interrupts (line based
 692          * interrupt, MSI or even MSI-X), which had been observed on
 693          * several types of LOMs, from being handled.
 694          */
 695         igb_disable_intr(sc);
 696
 697         error = igb_setup_intr(sc);
 698         if (error) {
 699                 ether_ifdetach(&sc->arpcom.ac_if);
 700                 goto failed;
 701         }
 702         return 0;
 703
 704 failed:
 705         igb_detach(dev);
 706         return error;
 707 }
 708
 709 static int
 710 igb_detach(device_t dev)
 711 {
 712         struct igb_softc *sc = device_get_softc(dev);
 713
 714         if (device_is_attached(dev)) {
 715                 struct ifnet *ifp = &sc->arpcom.ac_if;
 716
 717                 ifnet_serialize_all(ifp);
 718
 719                 igb_stop(sc);
 720
 721                 e1000_phy_hw_reset(&sc->hw);
 722
 723                 /* Give control back to firmware */
 724                 igb_rel_mgmt(sc);
 725                 igb_rel_hw_control(sc);
 726
 727                 if (sc->wol) {
 728                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 729                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 730                         igb_enable_wol(dev);
 731                 }
 732
 733                 igb_teardown_intr(sc);
 734
 735                 ifnet_deserialize_all(ifp);
 736
 737                 ether_ifdetach(ifp);
 738         } else if (sc->mem_res != NULL) {
 739                 igb_rel_hw_control(sc);
 740         }
 741         bus_generic_detach(dev);
 742
 743         igb_free_intr(sc);
 744
 745         if (sc->msix_mem_res != NULL) {
 746                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
 747                     sc->msix_mem_res);
 748         }
 749         if (sc->mem_res != NULL) {
 750                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 751                     sc->mem_res);
 752         }
 753
 754         igb_free_rings(sc);
 755
 756         if (sc->mta != NULL)
 757                 kfree(sc->mta, M_DEVBUF);
 758         if (sc->stats != NULL)
 759                 kfree(sc->stats, M_DEVBUF);
 760         if (sc->serializes != NULL)
 761                 kfree(sc->serializes, M_DEVBUF);
 762
 763         return 0;
 764 }
 765
 766 static int
 767 igb_shutdown(device_t dev)
 768 {
 769         return igb_suspend(dev);
 770 }
 771
 772 static int
 773 igb_suspend(device_t dev)
 774 {
 775         struct igb_softc *sc = device_get_softc(dev);
 776         struct ifnet *ifp = &sc->arpcom.ac_if;
 777
 778         ifnet_serialize_all(ifp);
 779
 780         igb_stop(sc);
 781
 782         igb_rel_mgmt(sc);
 783         igb_rel_hw_control(sc);
 784
 785         if (sc->wol) {
 786                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 787                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 788                 igb_enable_wol(dev);
 789         }
 790
 791         ifnet_deserialize_all(ifp);
 792
 793         return bus_generic_suspend(dev);
 794 }
 795
 796 static int
 797 igb_resume(device_t dev)
 798 {
 799         struct igb_softc *sc = device_get_softc(dev);
 800         struct ifnet *ifp = &sc->arpcom.ac_if;
 801         int i;
 802
 803         ifnet_serialize_all(ifp);
 804
 805         igb_init(sc);
 806         igb_get_mgmt(sc);
 807
 808         for (i = 0; i < sc->tx_ring_inuse; ++i)
 809                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
 810
 811         ifnet_deserialize_all(ifp);
 812
 813         return bus_generic_resume(dev);
 814 }
 815
 816 static int
 817 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 818 {
 819         struct igb_softc *sc = ifp->if_softc;
 820         struct ifreq *ifr = (struct ifreq *)data;
 821         int max_frame_size, mask, reinit;
 822         int error = 0;
 823
 824         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 825
 826         switch (command) {
 827         case SIOCSIFMTU:
 828                 max_frame_size = 9234;
 829                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 830                     ETHER_CRC_LEN) {
 831                         error = EINVAL;
 832                         break;
 833                 }
 834
 835                 ifp->if_mtu = ifr->ifr_mtu;
 836                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 837                     ETHER_CRC_LEN;
 838
 839                 if (ifp->if_flags & IFF_RUNNING)
 840                         igb_init(sc);
 841                 break;
 842
 843         case SIOCSIFFLAGS:
 844                 if (ifp->if_flags & IFF_UP) {
 845                         if (ifp->if_flags & IFF_RUNNING) {
 846                                 if ((ifp->if_flags ^ sc->if_flags) &
 847                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 848                                         igb_disable_promisc(sc);
 849                                         igb_set_promisc(sc);
 850                                 }
 851                         } else {
 852                                 igb_init(sc);
 853                         }
 854                 } else if (ifp->if_flags & IFF_RUNNING) {
 855                         igb_stop(sc);
 856                 }
 857                 sc->if_flags = ifp->if_flags;
 858                 break;
 859
 860         case SIOCADDMULTI:
 861         case SIOCDELMULTI:
 862                 if (ifp->if_flags & IFF_RUNNING) {
 863                         igb_disable_intr(sc);
 864                         igb_set_multi(sc);
 865 #ifdef IFPOLL_ENABLE
 866                         if (!(ifp->if_flags & IFF_NPOLLING))
 867 #endif
 868                                 igb_enable_intr(sc);
 869                 }
 870                 break;
 871
 872         case SIOCSIFMEDIA:
 873                 /* Check SOL/IDER usage */
 874                 if (e1000_check_reset_block(&sc->hw)) {
 875                         if_printf(ifp, "Media change is "
 876                             "blocked due to SOL/IDER session.\n");
 877                         break;
 878                 }
 879                 /* FALL THROUGH */
 880
 881         case SIOCGIFMEDIA:
 882                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 883                 break;
 884
 885         case SIOCSIFCAP:
 886                 reinit = 0;
 887                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 888                 if (mask & IFCAP_RXCSUM) {
 889                         ifp->if_capenable ^= IFCAP_RXCSUM;
 890                         reinit = 1;
 891                 }
 892                 if (mask & IFCAP_VLAN_HWTAGGING) {
 893                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 894                         reinit = 1;
 895                 }
 896                 if (mask & IFCAP_TXCSUM) {
 897                         ifp->if_capenable ^= IFCAP_TXCSUM;
 898                         if (ifp->if_capenable & IFCAP_TXCSUM)
 899                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
 900                         else
 901                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
 902                 }
 903                 if (mask & IFCAP_TSO) {
 904                         ifp->if_capenable ^= IFCAP_TSO;
 905                         if (ifp->if_capenable & IFCAP_TSO)
 906                                 ifp->if_hwassist |= CSUM_TSO;
 907                         else
 908                                 ifp->if_hwassist &= ~CSUM_TSO;
 909                 }
 910                 if (mask & IFCAP_RSS)
 911                         ifp->if_capenable ^= IFCAP_RSS;
 912                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 913                         igb_init(sc);
 914                 break;
 915
 916         default:
 917                 error = ether_ioctl(ifp, command, data);
 918                 break;
 919         }
 920         return error;
 921 }
 922
 923 static void
 924 igb_init(void *xsc)
 925 {
 926         struct igb_softc *sc = xsc;
 927         struct ifnet *ifp = &sc->arpcom.ac_if;
 928         boolean_t polling;
 929         int i;
 930
 931         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 932
 933         igb_stop(sc);
 934
 935         /* Get the latest mac address, User can use a LAA */
 936         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 937
 938         /* Put the address into the Receive Address Array */
 939         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 940
 941         igb_reset(sc);
 942         igb_update_link_status(sc);
 943
 944         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 945
 946         /* Configure for OS presence */
 947         igb_get_mgmt(sc);
 948
 949         polling = FALSE;
 950 #ifdef IFPOLL_ENABLE
 951         if (ifp->if_flags & IFF_NPOLLING)
 952                 polling = TRUE;
 953 #endif
 954
 955         /* Configured used RX/TX rings */
 956         igb_set_ring_inuse(sc, polling);
 957         ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
 958
 959         /* Initialize interrupt */
 960         igb_init_intr(sc);
 961
 962         /* Prepare transmit descriptors and buffers */
 963         for (i = 0; i < sc->tx_ring_inuse; ++i)
 964                 igb_init_tx_ring(&sc->tx_rings[i]);
 965         igb_init_tx_unit(sc);
 966
 967         /* Setup Multicast table */
 968         igb_set_multi(sc);
 969
 970 #if 0
 971         /*
 972          * Figure out the desired mbuf pool
 973          * for doing jumbo/packetsplit
 974          */
 975         if (adapter->max_frame_size <= 2048)
 976                 adapter->rx_mbuf_sz = MCLBYTES;
 977         else if (adapter->max_frame_size <= 4096)
 978                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 979         else
 980                 adapter->rx_mbuf_sz = MJUM9BYTES;
 981 #endif
 982
 983         /* Prepare receive descriptors and buffers */
 984         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 985                 int error;
 986
 987                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 988                 if (error) {
 989                         if_printf(ifp, "Could not setup receive structures\n");
 990                         igb_stop(sc);
 991                         return;
 992                 }
 993         }
 994         igb_init_rx_unit(sc);
 995
 996         /* Enable VLAN support */
 997         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 998                 igb_set_vlan(sc);
 999
1000         /* Don't lose promiscuous settings */
1001         igb_set_promisc(sc);
1002
1003         ifp->if_flags |= IFF_RUNNING;
1004         for (i = 0; i < sc->tx_ring_inuse; ++i) {
1005                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1006                 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
1007         }
1008
1009         igb_set_timer_cpuid(sc, polling);
1010         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1011         e1000_clear_hw_cntrs_base_generic(&sc->hw);
1012
1013         /* This clears any pending interrupts */
1014         E1000_READ_REG(&sc->hw, E1000_ICR);
1015
1016         /*
1017          * Only enable interrupts if we are not polling, make sure
1018          * they are off otherwise.
1019          */
1020         if (polling) {
1021                 igb_disable_intr(sc);
1022         } else {
1023                 igb_enable_intr(sc);
1024                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1025         }
1026
1027         /* Set Energy Efficient Ethernet */
1028         if (sc->hw.phy.media_type == e1000_media_type_copper) {
1029                 if (sc->hw.mac.type == e1000_i354)
1030                         e1000_set_eee_i354(&sc->hw);
1031                 else
1032                         e1000_set_eee_i350(&sc->hw);
1033         }
1034 }
1035
1036 static void
1037 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1038 {
1039         struct igb_softc *sc = ifp->if_softc;
1040
1041         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1042
1043         if ((ifp->if_flags & IFF_RUNNING) == 0)
1044                 sc->hw.mac.get_link_status = 1;
1045         igb_update_link_status(sc);
1046
1047         ifmr->ifm_status = IFM_AVALID;
1048         ifmr->ifm_active = IFM_ETHER;
1049
1050         if (!sc->link_active) {
1051                 ifmr->ifm_active |= IFM_NONE;
1052                 return;
1053         }
1054
1055         ifmr->ifm_status |= IFM_ACTIVE;
1056         if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1057                 ifmr->ifm_active |= IFM_ETH_FORCEPAUSE;
1058
1059         switch (sc->link_speed) {
1060         case 10:
1061                 ifmr->ifm_active |= IFM_10_T;
1062                 break;
1063
1064         case 100:
1065                 /*
1066                  * Support for 100Mb SFP - these are Fiber
1067                  * but the media type appears as serdes
1068                  */
1069                 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1070                     sc->hw.phy.media_type == e1000_media_type_internal_serdes)
1071                         ifmr->ifm_active |= IFM_100_FX;
1072                 else
1073                         ifmr->ifm_active |= IFM_100_TX;
1074                 break;
1075
1076         case 1000:
1077                 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1078                     sc->hw.phy.media_type == e1000_media_type_internal_serdes)
1079                         ifmr->ifm_active |= IFM_1000_SX;
1080                 else
1081                         ifmr->ifm_active |= IFM_1000_T;
1082                 break;
1083         }
1084
1085         if (sc->link_duplex == FULL_DUPLEX)
1086                 ifmr->ifm_active |= IFM_FDX;
1087         else
1088                 ifmr->ifm_active |= IFM_HDX;
1089
1090         if (sc->link_duplex == FULL_DUPLEX)
1091                 ifmr->ifm_active |= e1000_fc2ifmedia(sc->hw.fc.current_mode);
1092 }
1093
1094 static int
1095 igb_media_change(struct ifnet *ifp)
1096 {
1097         struct igb_softc *sc = ifp->if_softc;
1098         struct ifmedia *ifm = &sc->media;
1099
1100         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1101
1102         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1103                 return EINVAL;
1104
1105         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1106         case IFM_AUTO:
1107                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1108                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1109                 break;
1110
1111         case IFM_1000_SX:
1112         case IFM_1000_T:
1113                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1114                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1115                 break;
1116
1117         case IFM_100_TX:
1118                 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1119                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1120                 } else {
1121                         if (IFM_OPTIONS(ifm->ifm_media) &
1122                             (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1123                                 if (bootverbose) {
1124                                         if_printf(ifp, "Flow control is not "
1125                                             "allowed for half-duplex\n");
1126                                 }
1127                                 return EINVAL;
1128                         }
1129                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1130                 }
1131                 sc->hw.mac.autoneg = FALSE;
1132                 sc->hw.phy.autoneg_advertised = 0;
1133                 break;
1134
1135         case IFM_10_T:
1136                 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1137                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1138                 } else {
1139                         if (IFM_OPTIONS(ifm->ifm_media) &
1140                             (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1141                                 if (bootverbose) {
1142                                         if_printf(ifp, "Flow control is not "
1143                                             "allowed for half-duplex\n");
1144                                 }
1145                                 return EINVAL;
1146                         }
1147                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1148                 }
1149                 sc->hw.mac.autoneg = FALSE;
1150                 sc->hw.phy.autoneg_advertised = 0;
1151                 break;
1152
1153         default:
1154                 if (bootverbose) {
1155                         if_printf(ifp, "Unsupported media type %d\n",
1156                             IFM_SUBTYPE(ifm->ifm_media));
1157                 }
1158                 return EINVAL;
1159         }
1160         sc->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK;
1161
1162         if (ifp->if_flags & IFF_RUNNING)
1163                 igb_init(sc);
1164
1165         return 0;
1166 }
1167
1168 static void
1169 igb_set_promisc(struct igb_softc *sc)
1170 {
1171         struct ifnet *ifp = &sc->arpcom.ac_if;
1172         struct e1000_hw *hw = &sc->hw;
1173         uint32_t reg;
1174
1175         if (sc->vf_ifp) {
1176                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1177                 return;
1178         }
1179
1180         reg = E1000_READ_REG(hw, E1000_RCTL);
1181         if (ifp->if_flags & IFF_PROMISC) {
1182                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1183                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1184         } else if (ifp->if_flags & IFF_ALLMULTI) {
1185                 reg |= E1000_RCTL_MPE;
1186                 reg &= ~E1000_RCTL_UPE;
1187                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1188         }
1189 }
1190
1191 static void
1192 igb_disable_promisc(struct igb_softc *sc)
1193 {
1194         struct e1000_hw *hw = &sc->hw;
1195         struct ifnet *ifp = &sc->arpcom.ac_if;
1196         uint32_t reg;
1197         int mcnt = 0;
1198
1199         if (sc->vf_ifp) {
1200                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1201                 return;
1202         }
1203         reg = E1000_READ_REG(hw, E1000_RCTL);
1204         reg &= ~E1000_RCTL_UPE;
1205         if (ifp->if_flags & IFF_ALLMULTI) {
1206                 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1207         } else {
1208                 struct  ifmultiaddr *ifma;
1209                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1210                         if (ifma->ifma_addr->sa_family != AF_LINK)
1211                                 continue;
1212                         if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1213                                 break;
1214                         mcnt++;
1215                 }
1216         }
1217         /* Don't disable if in MAX groups */
1218         if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1219                 reg &= ~E1000_RCTL_MPE;
1220         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1221 }
1222
1223 static void
1224 igb_set_multi(struct igb_softc *sc)
1225 {
1226         struct ifnet *ifp = &sc->arpcom.ac_if;
1227         struct ifmultiaddr *ifma;
1228         uint32_t reg_rctl = 0;
1229         uint8_t *mta;
1230         int mcnt = 0;
1231
1232         mta = sc->mta;
1233         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1234
1235         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1236                 if (ifma->ifma_addr->sa_family != AF_LINK)
1237                         continue;
1238
1239                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1240                         break;
1241
1242                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1243                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1244                 mcnt++;
1245         }
1246
1247         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1248                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1249                 reg_rctl |= E1000_RCTL_MPE;
1250                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1251         } else {
1252                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1253         }
1254 }
1255
1256 static void
1257 igb_timer(void *xsc)
1258 {
1259         struct igb_softc *sc = xsc;
1260
1261         lwkt_serialize_enter(&sc->main_serialize);
1262
1263         igb_update_link_status(sc);
1264         igb_update_stats_counters(sc);
1265
1266         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1267
1268         lwkt_serialize_exit(&sc->main_serialize);
1269 }
1270
1271 static void
1272 igb_update_link_status(struct igb_softc *sc)
1273 {
1274         struct ifnet *ifp = &sc->arpcom.ac_if;
1275         struct e1000_hw *hw = &sc->hw;
1276         uint32_t link_check, thstat, ctrl;
1277
1278         link_check = thstat = ctrl = 0;
1279
1280         /* Get the cached link value or read for real */
1281         switch (hw->phy.media_type) {
1282         case e1000_media_type_copper:
1283                 if (hw->mac.get_link_status) {
1284                         /* Do the work to read phy */
1285                         e1000_check_for_link(hw);
1286                         link_check = !hw->mac.get_link_status;
1287                 } else {
1288                         link_check = TRUE;
1289                 }
1290                 break;
1291
1292         case e1000_media_type_fiber:
1293                 e1000_check_for_link(hw);
1294                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1295                 break;
1296
1297         case e1000_media_type_internal_serdes:
1298                 e1000_check_for_link(hw);
1299                 link_check = hw->mac.serdes_has_link;
1300                 break;
1301
1302         /* VF device is type_unknown */
1303         case e1000_media_type_unknown:
1304                 e1000_check_for_link(hw);
1305                 link_check = !hw->mac.get_link_status;
1306                 /* Fall thru */
1307         default:
1308                 break;
1309         }
1310
1311         /* Check for thermal downshift or shutdown */
1312         if (hw->mac.type == e1000_i350) {
1313                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1314                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1315         }
1316
1317         /* Now we check if a transition has happened */
1318         if (link_check && sc->link_active == 0) {
1319                 e1000_get_speed_and_duplex(hw,
1320                     &sc->link_speed, &sc->link_duplex);
1321                 if (bootverbose) {
1322                         char flowctrl[IFM_ETH_FC_STRLEN];
1323
1324                         /* Get the flow control for display */
1325                         e1000_fc2str(hw->fc.current_mode, flowctrl,
1326                             sizeof(flowctrl));
1327
1328                         if_printf(ifp, "Link is up %d Mbps %s, "
1329                             "Flow control: %s\n",
1330                             sc->link_speed,
1331                             sc->link_duplex == FULL_DUPLEX ?
1332                             "Full Duplex" : "Half Duplex",
1333                             flowctrl);
1334                 }
1335                 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE) {
1336                         enum e1000_fc_mode fc;
1337
1338                         fc = e1000_ifmedia2fc(sc->ifm_flowctrl);
1339                         if (hw->fc.current_mode != fc) {
1340                                 hw->fc.requested_mode = fc;
1341                                 hw->fc.current_mode = fc;
1342                                 e1000_force_mac_fc(hw);
1343                         }
1344                 }
1345                 sc->link_active = 1;
1346
1347                 ifp->if_baudrate = sc->link_speed * 1000000;
1348                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1349                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1350                         if_printf(ifp, "Link: thermal downshift\n");
1351                 /* Delay Link Up for Phy update */
1352                 if ((hw->mac.type == e1000_i210 ||
1353                      hw->mac.type == e1000_i211) &&
1354                     hw->phy.id == I210_I_PHY_ID)
1355                         msec_delay(IGB_I210_LINK_DELAY);
1356                 /* This can sleep */
1357                 ifp->if_link_state = LINK_STATE_UP;
1358                 if_link_state_change(ifp);
1359         } else if (!link_check && sc->link_active == 1) {
1360                 ifp->if_baudrate = sc->link_speed = 0;
1361                 sc->link_duplex = 0;
1362                 if (bootverbose)
1363                         if_printf(ifp, "Link is Down\n");
1364                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1365                     (thstat & E1000_THSTAT_PWR_DOWN))
1366                         if_printf(ifp, "Link: thermal shutdown\n");
1367                 sc->link_active = 0;
1368                 /* This can sleep */
1369                 ifp->if_link_state = LINK_STATE_DOWN;
1370                 if_link_state_change(ifp);
1371         }
1372 }
1373
1374 static void
1375 igb_stop(struct igb_softc *sc)
1376 {
1377         struct ifnet *ifp = &sc->arpcom.ac_if;
1378         int i;
1379
1380         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1381
1382         igb_disable_intr(sc);
1383
1384         callout_stop(&sc->timer);
1385
1386         ifp->if_flags &= ~IFF_RUNNING;
1387         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1388                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1389                 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1390                 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
1391         }
1392
1393         e1000_reset_hw(&sc->hw);
1394         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1395
1396         e1000_led_off(&sc->hw);
1397         e1000_cleanup_led(&sc->hw);
1398
1399         for (i = 0; i < sc->tx_ring_cnt; ++i)
1400                 igb_free_tx_ring(&sc->tx_rings[i]);
1401         for (i = 0; i < sc->rx_ring_cnt; ++i)
1402                 igb_free_rx_ring(&sc->rx_rings[i]);
1403 }
1404
1405 static void
1406 igb_reset(struct igb_softc *sc)
1407 {
1408         struct ifnet *ifp = &sc->arpcom.ac_if;
1409         struct e1000_hw *hw = &sc->hw;
1410         struct e1000_fc_info *fc = &hw->fc;
1411         uint32_t pba = 0;
1412         uint16_t hwm;
1413
1414         /* Let the firmware know the OS is in control */
1415         igb_get_hw_control(sc);
1416
1417         /*
1418          * Packet Buffer Allocation (PBA)
1419          * Writing PBA sets the receive portion of the buffer
1420          * the remainder is used for the transmit buffer.
1421          */
1422         switch (hw->mac.type) {
1423         case e1000_82575:
1424                 pba = E1000_PBA_32K;
1425                 break;
1426
1427         case e1000_82576:
1428         case e1000_vfadapt:
1429                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1430                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1431                 break;
1432
1433         case e1000_82580:
1434         case e1000_i350:
1435         case e1000_i354:
1436         case e1000_vfadapt_i350:
1437                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1438                 pba = e1000_rxpbs_adjust_82580(pba);
1439                 break;
1440
1441         case e1000_i210:
1442         case e1000_i211:
1443                 pba = E1000_PBA_34K;
1444                 break;
1445
1446         default:
1447                 break;
1448         }
1449
1450         /* Special needs in case of Jumbo frames */
1451         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1452                 uint32_t tx_space, min_tx, min_rx;
1453
1454                 pba = E1000_READ_REG(hw, E1000_PBA);
1455                 tx_space = pba >> 16;
1456                 pba &= 0xffff;
1457
1458                 min_tx = (sc->max_frame_size +
1459                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1460                 min_tx = roundup2(min_tx, 1024);
1461                 min_tx >>= 10;
1462                 min_rx = sc->max_frame_size;
1463                 min_rx = roundup2(min_rx, 1024);
1464                 min_rx >>= 10;
1465                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1466                         pba = pba - (min_tx - tx_space);
1467                         /*
1468                          * if short on rx space, rx wins
1469                          * and must trump tx adjustment
1470                          */
1471                         if (pba < min_rx)
1472                                 pba = min_rx;
1473                 }
1474                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1475         }
1476
1477         /*
1478          * These parameters control the automatic generation (Tx) and
1479          * response (Rx) to Ethernet PAUSE frames.
1480          * - High water mark should allow for at least two frames to be
1481          *   received after sending an XOFF.
1482          * - Low water mark works best when it is very near the high water mark.
1483          *   This allows the receiver to restart by sending XON when it has
1484          *   drained a bit.
1485          */
1486         hwm = min(((pba << 10) * 9 / 10),
1487             ((pba << 10) - 2 * sc->max_frame_size));
1488
1489         if (hw->mac.type < e1000_82576) {
1490                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1491                 fc->low_water = fc->high_water - 8;
1492         } else {
1493                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1494                 fc->low_water = fc->high_water - 16;
1495         }
1496         fc->pause_time = IGB_FC_PAUSE_TIME;
1497         fc->send_xon = TRUE;
1498         fc->requested_mode = e1000_ifmedia2fc(sc->ifm_flowctrl);
1499
1500         /* Issue a global reset */
1501         e1000_reset_hw(hw);
1502         E1000_WRITE_REG(hw, E1000_WUC, 0);
1503
1504         if (e1000_init_hw(hw) < 0)
1505                 if_printf(ifp, "Hardware Initialization Failed\n");
1506
1507         /* Setup DMA Coalescing */
1508         if (hw->mac.type > e1000_82580 && hw->mac.type != e1000_i211) {
1509                 uint32_t dmac;
1510                 uint32_t reg;
1511
1512                 if (sc->dma_coalesce == 0) {
1513                         /*
1514                          * Disabled
1515                          */
1516                         reg = E1000_READ_REG(hw, E1000_DMACR);
1517                         reg &= ~E1000_DMACR_DMAC_EN;
1518                         E1000_WRITE_REG(hw, E1000_DMACR, reg);
1519                         goto reset_out;
1520                 }
1521
1522                 /* Set starting thresholds */
1523                 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
1524                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1525
1526                 hwm = 64 * pba - sc->max_frame_size / 16;
1527                 if (hwm < 64 * (pba - 6))
1528                         hwm = 64 * (pba - 6);
1529                 reg = E1000_READ_REG(hw, E1000_FCRTC);
1530                 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
1531                 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
1532                     & E1000_FCRTC_RTH_COAL_MASK);
1533                 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
1534
1535                 dmac = pba - sc->max_frame_size / 512;
1536                 if (dmac < pba - 10)
1537                         dmac = pba - 10;
1538                 reg = E1000_READ_REG(hw, E1000_DMACR);
1539                 reg &= ~E1000_DMACR_DMACTHR_MASK;
1540                 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT)
1541                     & E1000_DMACR_DMACTHR_MASK);
1542                 /* Transition to L0x or L1 if available.. */
1543                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1544                 /* timer = value in sc->dma_coalesce in 32usec intervals */
1545                 reg |= (sc->dma_coalesce >> 5);
1546                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1547
1548                 /* Set the interval before transition */
1549                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1550                 reg |= 0x80000004;
1551                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1552
1553                 /* Free space in tx packet buffer to wake from DMA coal */
1554                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1555                     (20480 - (2 * sc->max_frame_size)) >> 6);
1556
1557                 /* Make low power state decision controlled by DMA coal */
1558                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1559                 reg &= ~E1000_PCIEMISC_LX_DECISION;
1560                 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
1561                 if_printf(ifp, "DMA Coalescing enabled\n");
1562         } else if (hw->mac.type == e1000_82580) {
1563                 uint32_t reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1564
1565                 E1000_WRITE_REG(hw, E1000_DMACR, 0);
1566                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1567                     reg & ~E1000_PCIEMISC_LX_DECISION);
1568         }
1569
1570 reset_out:
1571         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1572         e1000_get_phy_info(hw);
1573         e1000_check_for_link(hw);
1574 }
1575
1576 static void
1577 igb_setup_ifp(struct igb_softc *sc)
1578 {
1579         struct ifnet *ifp = &sc->arpcom.ac_if;
1580         int i;
1581
1582         ifp->if_softc = sc;
1583         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1584         ifp->if_init = igb_init;
1585         ifp->if_ioctl = igb_ioctl;
1586         ifp->if_start = igb_start;
1587         ifp->if_serialize = igb_serialize;
1588         ifp->if_deserialize = igb_deserialize;
1589         ifp->if_tryserialize = igb_tryserialize;
1590 #ifdef INVARIANTS
1591         ifp->if_serialize_assert = igb_serialize_assert;
1592 #endif
1593 #ifdef IFPOLL_ENABLE
1594         ifp->if_npoll = igb_npoll;
1595 #endif
1596
1597         ifp->if_nmbclusters = sc->rx_ring_cnt * sc->rx_rings[0].num_rx_desc;
1598
1599         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1600         ifq_set_ready(&ifp->if_snd);
1601         ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1602
1603         ifp->if_mapsubq = ifq_mapsubq_mask;
1604         ifq_set_subq_mask(&ifp->if_snd, 0);
1605
1606         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1607
1608         ifp->if_capabilities =
1609             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1610         if (IGB_ENABLE_HWRSS(sc))
1611                 ifp->if_capabilities |= IFCAP_RSS;
1612         ifp->if_capenable = ifp->if_capabilities;
1613         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1614
1615         /*
1616          * Tell the upper layer(s) we support long frames
1617          */
1618         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1619
1620         /* Setup TX rings and subqueues */
1621         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1622                 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
1623                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1624
1625                 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
1626                 ifsq_set_priv(ifsq, txr);
1627                 ifsq_set_hw_serialize(ifsq, &txr->tx_serialize);
1628                 txr->ifsq = ifsq;
1629
1630                 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
1631         }
1632
1633         /*
1634          * Specify the media types supported by this adapter and register
1635          * callbacks to update media and link information
1636          */
1637         ifmedia_init(&sc->media, IFM_IMASK | IFM_ETH_FCMASK,
1638             igb_media_change, igb_media_status);
1639         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1640             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1641                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1642                     0, NULL);
1643         } else {
1644                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1645                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1646                     0, NULL);
1647                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1648                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1649                     0, NULL);
1650                 if (sc->hw.phy.type != e1000_phy_ife) {
1651                         ifmedia_add(&sc->media,
1652                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1653                 }
1654         }
1655         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1656         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO | sc->ifm_flowctrl);
1657 }
1658
1659 static void
1660 igb_add_sysctl(struct igb_softc *sc)
1661 {
1662         struct sysctl_ctx_list *ctx;
1663         struct sysctl_oid *tree;
1664         char node[32];
1665         int i;
1666
1667         ctx = device_get_sysctl_ctx(sc->dev);
1668         tree = device_get_sysctl_tree(sc->dev);
1669         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1670             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1671         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1672             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1673             "# of RX rings used");
1674         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1675             OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1676         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1677             OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1678             "# of TX rings used");
1679         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1680             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1681             "# of RX descs");
1682         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1683             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1684             "# of TX descs");
1685
1686         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1687                 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1688                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1689                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1690         } else {
1691                 for (i = 0; i < sc->msix_cnt; ++i) {
1692                         struct igb_msix_data *msix = &sc->msix_data[i];
1693
1694                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1695                         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1696                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1697                             msix, 0, igb_sysctl_msix_rate, "I",
1698                             msix->msix_rate_desc);
1699                 }
1700         }
1701
1702         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1703             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1704             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1705             "# of segments per TX interrupt");
1706
1707         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1708             OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1709             sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
1710             "# of segments sent before write to hardware register");
1711
1712         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1713             OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1714             sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1715             "# of segments received before write to hardware register");
1716
1717 #ifdef IFPOLL_ENABLE
1718         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1719             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1720             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1721         SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1722             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1723             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1724 #endif
1725
1726 #ifdef IGB_RSS_DEBUG
1727         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1728             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1729             "RSS debug level");
1730         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1731                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1732                 SYSCTL_ADD_ULONG(ctx,
1733                     SYSCTL_CHILDREN(tree), OID_AUTO, node,
1734                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1735         }
1736 #endif
1737 #ifdef IGB_TSS_DEBUG
1738         for  (i = 0; i < sc->tx_ring_cnt; ++i) {
1739                 ksnprintf(node, sizeof(node), "tx%d_pkt", i);
1740                 SYSCTL_ADD_ULONG(ctx,
1741                     SYSCTL_CHILDREN(tree), OID_AUTO, node,
1742                     CTLFLAG_RW, &sc->tx_rings[i].tx_packets, "TXed packets");
1743         }
1744 #endif
1745 }
1746
1747 static int
1748 igb_alloc_rings(struct igb_softc *sc)
1749 {
1750         int error, i;
1751
1752         /*
1753          * Create top level busdma tag
1754          */
1755         error = bus_dma_tag_create(NULL, 1, 0,
1756             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1757             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1758             &sc->parent_tag);
1759         if (error) {
1760                 device_printf(sc->dev, "could not create top level DMA tag\n");
1761                 return error;
1762         }
1763
1764         /*
1765          * Allocate TX descriptor rings and buffers
1766          */
1767         sc->tx_rings = kmalloc_cachealign(
1768             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1769             M_DEVBUF, M_WAITOK | M_ZERO);
1770         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1771                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1772
1773                 /* Set up some basics */
1774                 txr->sc = sc;
1775                 txr->me = i;
1776                 lwkt_serialize_init(&txr->tx_serialize);
1777
1778                 error = igb_create_tx_ring(txr);
1779                 if (error)
1780                         return error;
1781         }
1782
1783         /*
1784          * Allocate RX descriptor rings and buffers
1785          */
1786         sc->rx_rings = kmalloc_cachealign(
1787             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1788             M_DEVBUF, M_WAITOK | M_ZERO);
1789         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1790                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1791
1792                 /* Set up some basics */
1793                 rxr->sc = sc;
1794                 rxr->me = i;
1795                 lwkt_serialize_init(&rxr->rx_serialize);
1796
1797                 error = igb_create_rx_ring(rxr);
1798                 if (error)
1799                         return error;
1800         }
1801
1802         return 0;
1803 }
1804
1805 static void
1806 igb_free_rings(struct igb_softc *sc)
1807 {
1808         int i;
1809
1810         if (sc->tx_rings != NULL) {
1811                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1812                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1813
1814                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1815                 }
1816                 kfree(sc->tx_rings, M_DEVBUF);
1817         }
1818
1819         if (sc->rx_rings != NULL) {
1820                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1821                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1822
1823                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1824                 }
1825                 kfree(sc->rx_rings, M_DEVBUF);
1826         }
1827 }
1828
1829 static int
1830 igb_create_tx_ring(struct igb_tx_ring *txr)
1831 {
1832         int tsize, error, i, ntxd;
1833
1834         /*
1835          * Validate number of transmit descriptors. It must not exceed
1836          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1837          */
1838         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1839         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1840             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1841                 device_printf(txr->sc->dev,
1842                     "Using %d TX descriptors instead of %d!\n",
1843                     IGB_DEFAULT_TXD, ntxd);
1844                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1845         } else {
1846                 txr->num_tx_desc = ntxd;
1847         }
1848
1849         /*
1850          * Allocate TX descriptor ring
1851          */
1852         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1853             IGB_DBA_ALIGN);
1854         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1855             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1856             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1857         if (txr->txdma.dma_vaddr == NULL) {
1858                 device_printf(txr->sc->dev,
1859                     "Unable to allocate TX Descriptor memory\n");
1860                 return ENOMEM;
1861         }
1862         txr->tx_base = txr->txdma.dma_vaddr;
1863         bzero(txr->tx_base, tsize);
1864
1865         tsize = __VM_CACHELINE_ALIGN(
1866             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1867         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1868
1869         /*
1870          * Allocate TX head write-back buffer
1871          */
1872         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1873             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1874             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1875         if (txr->tx_hdr == NULL) {
1876                 device_printf(txr->sc->dev,
1877                     "Unable to allocate TX head write-back buffer\n");
1878                 return ENOMEM;
1879         }
1880
1881         /*
1882          * Create DMA tag for TX buffers
1883          */
1884         error = bus_dma_tag_create(txr->sc->parent_tag,
1885             1, 0,               /* alignment, bounds */
1886             BUS_SPACE_MAXADDR,  /* lowaddr */
1887             BUS_SPACE_MAXADDR,  /* highaddr */
1888             NULL, NULL,         /* filter, filterarg */
1889             IGB_TSO_SIZE,       /* maxsize */
1890             IGB_MAX_SCATTER,    /* nsegments */
1891             PAGE_SIZE,          /* maxsegsize */
1892             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1893             BUS_DMA_ONEBPAGE,   /* flags */
1894             &txr->tx_tag);
1895         if (error) {
1896                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1897                 kfree(txr->tx_buf, M_DEVBUF);
1898                 txr->tx_buf = NULL;
1899                 return error;
1900         }
1901
1902         /*
1903          * Create DMA maps for TX buffers
1904          */
1905         for (i = 0; i < txr->num_tx_desc; ++i) {
1906                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1907
1908                 error = bus_dmamap_create(txr->tx_tag,
1909                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1910                 if (error) {
1911                         device_printf(txr->sc->dev,
1912                             "Unable to create TX DMA map\n");
1913                         igb_destroy_tx_ring(txr, i);
1914                         return error;
1915                 }
1916         }
1917
1918         if (txr->sc->hw.mac.type == e1000_82575)
1919                 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1920
1921         /*
1922          * Initialize various watermark
1923          */
1924         txr->spare_desc = IGB_TX_SPARE;
1925         txr->intr_nsegs = txr->num_tx_desc / 16;
1926         txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
1927         txr->oact_hi_desc = txr->num_tx_desc / 2;
1928         txr->oact_lo_desc = txr->num_tx_desc / 8;
1929         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1930                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1931         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1932                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1933
1934         return 0;
1935 }
1936
1937 static void
1938 igb_free_tx_ring(struct igb_tx_ring *txr)
1939 {
1940         int i;
1941
1942         for (i = 0; i < txr->num_tx_desc; ++i) {
1943                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1944
1945                 if (txbuf->m_head != NULL) {
1946                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1947                         m_freem(txbuf->m_head);
1948                         txbuf->m_head = NULL;
1949                 }
1950         }
1951 }
1952
1953 static void
1954 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1955 {
1956         int i;
1957
1958         if (txr->txdma.dma_vaddr != NULL) {
1959                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1960                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1961                     txr->txdma.dma_map);
1962                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1963                 txr->txdma.dma_vaddr = NULL;
1964         }
1965
1966         if (txr->tx_hdr != NULL) {
1967                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1968                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1969                     txr->tx_hdr_dmap);
1970                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1971                 txr->tx_hdr = NULL;
1972         }
1973
1974         if (txr->tx_buf == NULL)
1975                 return;
1976
1977         for (i = 0; i < ndesc; ++i) {
1978                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1979
1980                 KKASSERT(txbuf->m_head == NULL);
1981                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1982         }
1983         bus_dma_tag_destroy(txr->tx_tag);
1984
1985         kfree(txr->tx_buf, M_DEVBUF);
1986         txr->tx_buf = NULL;
1987 }
1988
1989 static void
1990 igb_init_tx_ring(struct igb_tx_ring *txr)
1991 {
1992         /* Clear the old descriptor contents */
1993         bzero(txr->tx_base,
1994             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1995
1996         /* Clear TX head write-back buffer */
1997         *(txr->tx_hdr) = 0;
1998
1999         /* Reset indices */
2000         txr->next_avail_desc = 0;
2001         txr->next_to_clean = 0;
2002         txr->tx_nsegs = 0;
2003
2004         /* Set number of descriptors available */
2005         txr->tx_avail = txr->num_tx_desc;
2006
2007         /* Enable this TX ring */
2008         txr->tx_flags |= IGB_TXFLAG_ENABLED;
2009 }
2010
2011 static void
2012 igb_init_tx_unit(struct igb_softc *sc)
2013 {
2014         struct e1000_hw *hw = &sc->hw;
2015         uint32_t tctl;
2016         int i;
2017
2018         /* Setup the Tx Descriptor Rings */
2019         for (i = 0; i < sc->tx_ring_inuse; ++i) {
2020                 struct igb_tx_ring *txr = &sc->tx_rings[i];
2021                 uint64_t bus_addr = txr->txdma.dma_paddr;
2022                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
2023                 uint32_t txdctl = 0;
2024                 uint32_t dca_txctrl;
2025
2026                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2027                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
2028                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2029                     (uint32_t)(bus_addr >> 32));
2030                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
2031                     (uint32_t)bus_addr);
2032
2033                 /* Setup the HW Tx Head and Tail descriptor pointers */
2034                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2035                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2036
2037                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
2038                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2039                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
2040
2041                 /*
2042                  * Don't set WB_on_EITR:
2043                  * - 82575 does not have it
2044                  * - It almost has no effect on 82576, see:
2045                  *   82576 specification update errata #26
2046                  * - It causes unnecessary bus traffic
2047                  */
2048                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
2049                     (uint32_t)(hdr_paddr >> 32));
2050                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
2051                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
2052
2053                 /*
2054                  * WTHRESH is ignored by the hardware, since header
2055                  * write back mode is used.
2056                  */
2057                 txdctl |= IGB_TX_PTHRESH;
2058                 txdctl |= IGB_TX_HTHRESH << 8;
2059                 txdctl |= IGB_TX_WTHRESH << 16;
2060                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2061                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2062         }
2063
2064         if (sc->vf_ifp)
2065                 return;
2066
2067         e1000_config_collision_dist(hw);
2068
2069         /* Program the Transmit Control Register */
2070         tctl = E1000_READ_REG(hw, E1000_TCTL);
2071         tctl &= ~E1000_TCTL_CT;
2072         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2073             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2074
2075         /* This write will effectively turn on the transmit unit. */
2076         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2077 }
2078
2079 static boolean_t
2080 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
2081 {
2082         struct e1000_adv_tx_context_desc *TXD;
2083         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
2084         int ehdrlen, ctxd, ip_hlen = 0;
2085         boolean_t offload = TRUE;
2086
2087         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
2088                 offload = FALSE;
2089
2090         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
2091
2092         ctxd = txr->next_avail_desc;
2093         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
2094
2095         /*
2096          * In advanced descriptors the vlan tag must
2097          * be placed into the context descriptor, thus
2098          * we need to be here just for that setup.
2099          */
2100         if (mp->m_flags & M_VLANTAG) {
2101                 uint16_t vlantag;
2102
2103                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
2104                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
2105         } else if (!offload) {
2106                 return FALSE;
2107         }
2108
2109         ehdrlen = mp->m_pkthdr.csum_lhlen;
2110         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
2111
2112         /* Set the ether header length */
2113         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
2114         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
2115                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
2116                 ip_hlen = mp->m_pkthdr.csum_iphlen;
2117                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
2118         }
2119         vlan_macip_lens |= ip_hlen;
2120
2121         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
2122         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
2123                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
2124         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
2125                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
2126
2127         /*
2128          * 82575 needs the TX context index added; the queue
2129          * index is used as TX context index here.
2130          */
2131         if (txr->sc->hw.mac.type == e1000_82575)
2132                 mss_l4len_idx = txr->me << 4;
2133
2134         /* Now copy bits into descriptor */
2135         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
2136         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
2137         TXD->seqnum_seed = htole32(0);
2138         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
2139
2140         /* We've consumed the first desc, adjust counters */
2141         if (++ctxd == txr->num_tx_desc)
2142                 ctxd = 0;
2143         txr->next_avail_desc = ctxd;
2144         --txr->tx_avail;
2145
2146         return offload;
2147 }
2148
2149 static void
2150 igb_txeof(struct igb_tx_ring *txr)
2151 {
2152         int first, hdr, avail;
2153
2154         if (txr->tx_avail == txr->num_tx_desc)
2155                 return;
2156
2157         first = txr->next_to_clean;
2158         hdr = *(txr->tx_hdr);
2159
2160         if (first == hdr)
2161                 return;
2162
2163         avail = txr->tx_avail;
2164         while (first != hdr) {
2165                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2166
2167                 ++avail;
2168                 if (txbuf->m_head) {
2169                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
2170                         m_freem(txbuf->m_head);
2171                         txbuf->m_head = NULL;
2172                 }
2173                 if (++first == txr->num_tx_desc)
2174                         first = 0;
2175         }
2176         txr->next_to_clean = first;
2177         txr->tx_avail = avail;
2178
2179         /*
2180          * If we have a minimum free, clear OACTIVE
2181          * to tell the stack that it is OK to send packets.
2182          */
2183         if (IGB_IS_NOT_OACTIVE(txr)) {
2184                 ifsq_clr_oactive(txr->ifsq);
2185
2186                 /*
2187                  * We have enough TX descriptors, turn off
2188                  * the watchdog.  We allow small amount of
2189                  * packets (roughly intr_nsegs) pending on
2190                  * the transmit ring.
2191                  */
2192                 txr->tx_watchdog.wd_timer = 0;
2193         }
2194 }
2195
2196 static int
2197 igb_create_rx_ring(struct igb_rx_ring *rxr)
2198 {
2199         int rsize, i, error, nrxd;
2200
2201         /*
2202          * Validate number of receive descriptors. It must not exceed
2203          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2204          */
2205         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2206         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2207             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2208                 device_printf(rxr->sc->dev,
2209                     "Using %d RX descriptors instead of %d!\n",
2210                     IGB_DEFAULT_RXD, nrxd);
2211                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2212         } else {
2213                 rxr->num_rx_desc = nrxd;
2214         }
2215
2216         /*
2217          * Allocate RX descriptor ring
2218          */
2219         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2220             IGB_DBA_ALIGN);
2221         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2222             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2223             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2224             &rxr->rxdma.dma_paddr);
2225         if (rxr->rxdma.dma_vaddr == NULL) {
2226                 device_printf(rxr->sc->dev,
2227                     "Unable to allocate RxDescriptor memory\n");
2228                 return ENOMEM;
2229         }
2230         rxr->rx_base = rxr->rxdma.dma_vaddr;
2231         bzero(rxr->rx_base, rsize);
2232
2233         rsize = __VM_CACHELINE_ALIGN(
2234             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2235         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2236
2237         /*
2238          * Create DMA tag for RX buffers
2239          */
2240         error = bus_dma_tag_create(rxr->sc->parent_tag,
2241             1, 0,               /* alignment, bounds */
2242             BUS_SPACE_MAXADDR,  /* lowaddr */
2243             BUS_SPACE_MAXADDR,  /* highaddr */
2244             NULL, NULL,         /* filter, filterarg */
2245             MCLBYTES,           /* maxsize */
2246             1,                  /* nsegments */
2247             MCLBYTES,           /* maxsegsize */
2248             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2249             &rxr->rx_tag);
2250         if (error) {
2251                 device_printf(rxr->sc->dev,
2252                     "Unable to create RX payload DMA tag\n");
2253                 kfree(rxr->rx_buf, M_DEVBUF);
2254                 rxr->rx_buf = NULL;
2255                 return error;
2256         }
2257
2258         /*
2259          * Create spare DMA map for RX buffers
2260          */
2261         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2262             &rxr->rx_sparemap);
2263         if (error) {
2264                 device_printf(rxr->sc->dev,
2265                     "Unable to create spare RX DMA maps\n");
2266                 bus_dma_tag_destroy(rxr->rx_tag);
2267                 kfree(rxr->rx_buf, M_DEVBUF);
2268                 rxr->rx_buf = NULL;
2269                 return error;
2270         }
2271
2272         /*
2273          * Create DMA maps for RX buffers
2274          */
2275         for (i = 0; i < rxr->num_rx_desc; i++) {
2276                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2277
2278                 error = bus_dmamap_create(rxr->rx_tag,
2279                     BUS_DMA_WAITOK, &rxbuf->map);
2280                 if (error) {
2281                         device_printf(rxr->sc->dev,
2282                             "Unable to create RX DMA maps\n");
2283                         igb_destroy_rx_ring(rxr, i);
2284                         return error;
2285                 }
2286         }
2287
2288         /*
2289          * Initialize various watermark
2290          */
2291         rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
2292
2293         return 0;
2294 }
2295
2296 static void
2297 igb_free_rx_ring(struct igb_rx_ring *rxr)
2298 {
2299         int i;
2300
2301         for (i = 0; i < rxr->num_rx_desc; ++i) {
2302                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2303
2304                 if (rxbuf->m_head != NULL) {
2305                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2306                         m_freem(rxbuf->m_head);
2307                         rxbuf->m_head = NULL;
2308                 }
2309         }
2310
2311         if (rxr->fmp != NULL)
2312                 m_freem(rxr->fmp);
2313         rxr->fmp = NULL;
2314         rxr->lmp = NULL;
2315 }
2316
2317 static void
2318 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2319 {
2320         int i;
2321
2322         if (rxr->rxdma.dma_vaddr != NULL) {
2323                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2324                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2325                     rxr->rxdma.dma_map);
2326                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2327                 rxr->rxdma.dma_vaddr = NULL;
2328         }
2329
2330         if (rxr->rx_buf == NULL)
2331                 return;
2332
2333         for (i = 0; i < ndesc; ++i) {
2334                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2335
2336                 KKASSERT(rxbuf->m_head == NULL);
2337                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2338         }
2339         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2340         bus_dma_tag_destroy(rxr->rx_tag);
2341
2342         kfree(rxr->rx_buf, M_DEVBUF);
2343         rxr->rx_buf = NULL;
2344 }
2345
2346 static void
2347 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2348 {
2349         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2350         rxd->wb.upper.status_error = 0;
2351 }
2352
2353 static int
2354 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2355 {
2356         struct mbuf *m;
2357         bus_dma_segment_t seg;
2358         bus_dmamap_t map;
2359         struct igb_rx_buf *rxbuf;
2360         int error, nseg;
2361
2362         m = m_getcl(wait ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2363         if (m == NULL) {
2364                 if (wait) {
2365                         if_printf(&rxr->sc->arpcom.ac_if,
2366                             "Unable to allocate RX mbuf\n");
2367                 }
2368                 return ENOBUFS;
2369         }
2370         m->m_len = m->m_pkthdr.len = MCLBYTES;
2371
2372         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2373                 m_adj(m, ETHER_ALIGN);
2374
2375         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2376             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2377         if (error) {
2378                 m_freem(m);
2379                 if (wait) {
2380                         if_printf(&rxr->sc->arpcom.ac_if,
2381                             "Unable to load RX mbuf\n");
2382                 }
2383                 return error;
2384         }
2385
2386         rxbuf = &rxr->rx_buf[i];
2387         if (rxbuf->m_head != NULL)
2388                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2389
2390         map = rxbuf->map;
2391         rxbuf->map = rxr->rx_sparemap;
2392         rxr->rx_sparemap = map;
2393
2394         rxbuf->m_head = m;
2395         rxbuf->paddr = seg.ds_addr;
2396
2397         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2398         return 0;
2399 }
2400
2401 static int
2402 igb_init_rx_ring(struct igb_rx_ring *rxr)
2403 {
2404         int i;
2405
2406         /* Clear the ring contents */
2407         bzero(rxr->rx_base,
2408             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2409
2410         /* Now replenish the ring mbufs */
2411         for (i = 0; i < rxr->num_rx_desc; ++i) {
2412                 int error;
2413
2414                 error = igb_newbuf(rxr, i, TRUE);
2415                 if (error)
2416                         return error;
2417         }
2418
2419         /* Setup our descriptor indices */
2420         rxr->next_to_check = 0;
2421
2422         rxr->fmp = NULL;
2423         rxr->lmp = NULL;
2424         rxr->discard = FALSE;
2425
2426         return 0;
2427 }
2428
2429 static void
2430 igb_init_rx_unit(struct igb_softc *sc)
2431 {
2432         struct ifnet *ifp = &sc->arpcom.ac_if;
2433         struct e1000_hw *hw = &sc->hw;
2434         uint32_t rctl, rxcsum, srrctl = 0;
2435         int i;
2436
2437         /*
2438          * Make sure receives are disabled while setting
2439          * up the descriptor ring
2440          */
2441         rctl = E1000_READ_REG(hw, E1000_RCTL);
2442         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2443
2444 #if 0
2445         /*
2446         ** Set up for header split
2447         */
2448         if (igb_header_split) {
2449                 /* Use a standard mbuf for the header */
2450                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2451                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2452         } else
2453 #endif
2454                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2455
2456         /*
2457         ** Set up for jumbo frames
2458         */
2459         if (ifp->if_mtu > ETHERMTU) {
2460                 rctl |= E1000_RCTL_LPE;
2461 #if 0
2462                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2463                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2464                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2465                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2466                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2467                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2468                 }
2469                 /* Set maximum packet len */
2470                 psize = adapter->max_frame_size;
2471                 /* are we on a vlan? */
2472                 if (adapter->ifp->if_vlantrunk != NULL)
2473                         psize += VLAN_TAG_SIZE;
2474                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2475 #else
2476                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2477                 rctl |= E1000_RCTL_SZ_2048;
2478 #endif
2479         } else {
2480                 rctl &= ~E1000_RCTL_LPE;
2481                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2482                 rctl |= E1000_RCTL_SZ_2048;
2483         }
2484
2485         /* Setup the Base and Length of the Rx Descriptor Rings */
2486         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2487                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2488                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2489                 uint32_t rxdctl;
2490
2491                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2492                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2493                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2494                     (uint32_t)(bus_addr >> 32));
2495                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2496                     (uint32_t)bus_addr);
2497                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2498                 /* Enable this Queue */
2499                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2500                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2501                 rxdctl &= 0xFFF00000;
2502                 rxdctl |= IGB_RX_PTHRESH;
2503                 rxdctl |= IGB_RX_HTHRESH << 8;
2504                 /*
2505                  * Don't set WTHRESH to a value above 1 on 82576, see:
2506                  * 82576 specification update errata #26
2507                  */
2508                 rxdctl |= IGB_RX_WTHRESH << 16;
2509                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2510         }
2511
2512         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2513         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2514
2515         /*
2516          * Receive Checksum Offload for TCP and UDP
2517          *
2518          * Checksum offloading is also enabled if multiple receive
2519          * queue is to be supported, since we need it to figure out
2520          * fragments.
2521          */
2522         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2523                 /*
2524                  * NOTE:
2525                  * PCSD must be enabled to enable multiple
2526                  * receive queues.
2527                  */
2528                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2529                     E1000_RXCSUM_PCSD;
2530         } else {
2531                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2532                     E1000_RXCSUM_PCSD);
2533         }
2534         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2535
2536         if (IGB_ENABLE_HWRSS(sc)) {
2537                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2538                 uint32_t reta_shift;
2539                 int j, r;
2540
2541                 /*
2542                  * NOTE:
2543                  * When we reach here, RSS has already been disabled
2544                  * in igb_stop(), so we could safely configure RSS key
2545                  * and redirect table.
2546                  */
2547
2548                 /*
2549                  * Configure RSS key
2550                  */
2551                 toeplitz_get_key(key, sizeof(key));
2552                 for (i = 0; i < IGB_NRSSRK; ++i) {
2553                         uint32_t rssrk;
2554
2555                         rssrk = IGB_RSSRK_VAL(key, i);
2556                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2557
2558                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2559                 }
2560
2561                 /*
2562                  * Configure RSS redirect table in following fashion:
2563                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2564                  */
2565                 reta_shift = IGB_RETA_SHIFT;
2566                 if (hw->mac.type == e1000_82575)
2567                         reta_shift = IGB_RETA_SHIFT_82575;
2568
2569                 r = 0;
2570                 for (j = 0; j < IGB_NRETA; ++j) {
2571                         uint32_t reta = 0;
2572
2573                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2574                                 uint32_t q;
2575
2576                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2577                                 reta |= q << (8 * i);
2578                                 ++r;
2579                         }
2580                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2581                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2582                 }
2583
2584                 /*
2585                  * Enable multiple receive queues.
2586                  * Enable IPv4 RSS standard hash functions.
2587                  * Disable RSS interrupt on 82575
2588                  */
2589                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2590                                 E1000_MRQC_ENABLE_RSS_4Q |
2591                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2592                                 E1000_MRQC_RSS_FIELD_IPV4);
2593         }
2594
2595         /* Setup the Receive Control Register */
2596         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2597         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2598             E1000_RCTL_RDMTS_HALF |
2599             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2600         /* Strip CRC bytes. */
2601         rctl |= E1000_RCTL_SECRC;
2602         /* Make sure VLAN Filters are off */
2603         rctl &= ~E1000_RCTL_VFE;
2604         /* Don't store bad packets */
2605         rctl &= ~E1000_RCTL_SBP;
2606
2607         /* Enable Receives */
2608         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2609
2610         /*
2611          * Setup the HW Rx Head and Tail Descriptor Pointers
2612          *   - needs to be after enable
2613          */
2614         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2615                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2616
2617                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2618                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2619         }
2620 }
2621
2622 static void
2623 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2624 {
2625         if (--i < 0)
2626                 i = rxr->num_rx_desc - 1;
2627         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2628 }
2629
2630 static void
2631 igb_rxeof(struct igb_rx_ring *rxr, int count)
2632 {
2633         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2634         union e1000_adv_rx_desc *cur;
2635         uint32_t staterr;
2636         int i, ncoll = 0, cpuid = mycpuid;
2637
2638         i = rxr->next_to_check;
2639         cur = &rxr->rx_base[i];
2640         staterr = le32toh(cur->wb.upper.status_error);
2641
2642         if ((staterr & E1000_RXD_STAT_DD) == 0)
2643                 return;
2644
2645         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2646                 struct pktinfo *pi = NULL, pi0;
2647                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2648                 struct mbuf *m = NULL;
2649                 boolean_t eop;
2650
2651                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2652                 if (eop)
2653                         --count;
2654
2655                 ++ncoll;
2656                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2657                     !rxr->discard) {
2658                         struct mbuf *mp = rxbuf->m_head;
2659                         uint32_t hash, hashtype;
2660                         uint16_t vlan;
2661                         int len;
2662
2663                         len = le16toh(cur->wb.upper.length);
2664                         if ((rxr->sc->hw.mac.type == e1000_i350 ||
2665                              rxr->sc->hw.mac.type == e1000_i354) &&
2666                             (staterr & E1000_RXDEXT_STATERR_LB))
2667                                 vlan = be16toh(cur->wb.upper.vlan);
2668                         else
2669                                 vlan = le16toh(cur->wb.upper.vlan);
2670
2671                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2672                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2673                             E1000_RXDADV_RSSTYPE_MASK;
2674
2675                         IGB_RSS_DPRINTF(rxr->sc, 10,
2676                             "ring%d, hash 0x%08x, hashtype %u\n",
2677                             rxr->me, hash, hashtype);
2678
2679                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2680                             BUS_DMASYNC_POSTREAD);
2681
2682                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2683                                 IFNET_STAT_INC(ifp, iqdrops, 1);
2684                                 goto discard;
2685                         }
2686
2687                         mp->m_len = len;
2688                         if (rxr->fmp == NULL) {
2689                                 mp->m_pkthdr.len = len;
2690                                 rxr->fmp = mp;
2691                                 rxr->lmp = mp;
2692                         } else {
2693                                 rxr->lmp->m_next = mp;
2694                                 rxr->lmp = rxr->lmp->m_next;
2695                                 rxr->fmp->m_pkthdr.len += len;
2696                         }
2697
2698                         if (eop) {
2699                                 m = rxr->fmp;
2700                                 rxr->fmp = NULL;
2701                                 rxr->lmp = NULL;
2702
2703                                 m->m_pkthdr.rcvif = ifp;
2704                                 IFNET_STAT_INC(ifp, ipackets, 1);
2705
2706                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2707                                         igb_rxcsum(staterr, m);
2708
2709                                 if (staterr & E1000_RXD_STAT_VP) {
2710                                         m->m_pkthdr.ether_vlantag = vlan;
2711                                         m->m_flags |= M_VLANTAG;
2712                                 }
2713
2714                                 if (ifp->if_capenable & IFCAP_RSS) {
2715                                         pi = igb_rssinfo(m, &pi0,
2716                                             hash, hashtype, staterr);
2717                                 }
2718 #ifdef IGB_RSS_DEBUG
2719                                 rxr->rx_packets++;
2720 #endif
2721                         }
2722                 } else {
2723                         IFNET_STAT_INC(ifp, ierrors, 1);
2724 discard:
2725                         igb_setup_rxdesc(cur, rxbuf);
2726                         if (!eop)
2727                                 rxr->discard = TRUE;
2728                         else
2729                                 rxr->discard = FALSE;
2730                         if (rxr->fmp != NULL) {
2731                                 m_freem(rxr->fmp);
2732                                 rxr->fmp = NULL;
2733                                 rxr->lmp = NULL;
2734                         }
2735                         m = NULL;
2736                 }
2737
2738                 if (m != NULL)
2739                         ifp->if_input(ifp, m, pi, cpuid);
2740
2741                 /* Advance our pointers to the next descriptor. */
2742                 if (++i == rxr->num_rx_desc)
2743                         i = 0;
2744
2745                 if (ncoll >= rxr->wreg_nsegs) {
2746                         igb_rx_refresh(rxr, i);
2747                         ncoll = 0;
2748                 }
2749
2750                 cur = &rxr->rx_base[i];
2751                 staterr = le32toh(cur->wb.upper.status_error);
2752         }
2753         rxr->next_to_check = i;
2754
2755         if (ncoll > 0)
2756                 igb_rx_refresh(rxr, i);
2757 }
2758
2759
2760 static void
2761 igb_set_vlan(struct igb_softc *sc)
2762 {
2763         struct e1000_hw *hw = &sc->hw;
2764         uint32_t reg;
2765 #if 0
2766         struct ifnet *ifp = sc->arpcom.ac_if;
2767 #endif
2768
2769         if (sc->vf_ifp) {
2770                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2771                 return;
2772         }
2773
2774         reg = E1000_READ_REG(hw, E1000_CTRL);
2775         reg |= E1000_CTRL_VME;
2776         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2777
2778 #if 0
2779         /* Enable the Filter Table */
2780         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2781                 reg = E1000_READ_REG(hw, E1000_RCTL);
2782                 reg &= ~E1000_RCTL_CFIEN;
2783                 reg |= E1000_RCTL_VFE;
2784                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2785         }
2786 #endif
2787
2788         /* Update the frame size */
2789         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2790             sc->max_frame_size + VLAN_TAG_SIZE);
2791
2792 #if 0
2793         /* Don't bother with table if no vlans */
2794         if ((adapter->num_vlans == 0) ||
2795             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2796                 return;
2797         /*
2798         ** A soft reset zero's out the VFTA, so
2799         ** we need to repopulate it now.
2800         */
2801         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2802                 if (adapter->shadow_vfta[i] != 0) {
2803                         if (adapter->vf_ifp)
2804                                 e1000_vfta_set_vf(hw,
2805                                     adapter->shadow_vfta[i], TRUE);
2806                         else
2807                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2808                                  i, adapter->shadow_vfta[i]);
2809                 }
2810 #endif
2811 }
2812
2813 static void
2814 igb_enable_intr(struct igb_softc *sc)
2815 {
2816         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2817                 lwkt_serialize_handler_enable(&sc->main_serialize);
2818         } else {
2819                 int i;
2820
2821                 for (i = 0; i < sc->msix_cnt; ++i) {
2822                         lwkt_serialize_handler_enable(
2823                             sc->msix_data[i].msix_serialize);
2824                 }
2825         }
2826
2827         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2828                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2829                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2830                 else
2831                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2832                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2833                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2834                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2835         } else {
2836                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2837         }
2838         E1000_WRITE_FLUSH(&sc->hw);
2839 }
2840
2841 static void
2842 igb_disable_intr(struct igb_softc *sc)
2843 {
2844         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2845                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2846                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2847         }
2848         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2849         E1000_WRITE_FLUSH(&sc->hw);
2850
2851         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2852                 lwkt_serialize_handler_disable(&sc->main_serialize);
2853         } else {
2854                 int i;
2855
2856                 for (i = 0; i < sc->msix_cnt; ++i) {
2857                         lwkt_serialize_handler_disable(
2858                             sc->msix_data[i].msix_serialize);
2859                 }
2860         }
2861 }
2862
2863 /*
2864  * Bit of a misnomer, what this really means is
2865  * to enable OS management of the system... aka
2866  * to disable special hardware management features
2867  */
2868 static void
2869 igb_get_mgmt(struct igb_softc *sc)
2870 {
2871         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2872                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2873                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2874
2875                 /* disable hardware interception of ARP */
2876                 manc &= ~E1000_MANC_ARP_EN;
2877
2878                 /* enable receiving management packets to the host */
2879                 manc |= E1000_MANC_EN_MNG2HOST;
2880                 manc2h |= 1 << 5; /* Mng Port 623 */
2881                 manc2h |= 1 << 6; /* Mng Port 664 */
2882                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2883                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2884         }
2885 }
2886
2887 /*
2888  * Give control back to hardware management controller
2889  * if there is one.
2890  */
2891 static void
2892 igb_rel_mgmt(struct igb_softc *sc)
2893 {
2894         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2895                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2896
2897                 /* Re-enable hardware interception of ARP */
2898                 manc |= E1000_MANC_ARP_EN;
2899                 manc &= ~E1000_MANC_EN_MNG2HOST;
2900
2901                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2902         }
2903 }
2904
2905 /*
2906  * Sets CTRL_EXT:DRV_LOAD bit.
2907  *
2908  * For ASF and Pass Through versions of f/w this means that
2909  * the driver is loaded.
2910  */
2911 static void
2912 igb_get_hw_control(struct igb_softc *sc)
2913 {
2914         uint32_t ctrl_ext;
2915
2916         if (sc->vf_ifp)
2917                 return;
2918
2919         /* Let firmware know the driver has taken over */
2920         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2921         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2922             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2923 }
2924
2925 /*
2926  * Resets CTRL_EXT:DRV_LOAD bit.
2927  *
2928  * For ASF and Pass Through versions of f/w this means that the
2929  * driver is no longer loaded.
2930  */
2931 static void
2932 igb_rel_hw_control(struct igb_softc *sc)
2933 {
2934         uint32_t ctrl_ext;
2935
2936         if (sc->vf_ifp)
2937                 return;
2938
2939         /* Let firmware taken over control of h/w */
2940         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2941         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2942             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2943 }
2944
2945 static boolean_t
2946 igb_is_valid_ether_addr(const uint8_t *addr)
2947 {
2948         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2949
2950         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2951                 return FALSE;
2952         return TRUE;
2953 }
2954
2955 /*
2956  * Enable PCI Wake On Lan capability
2957  */
2958 static void
2959 igb_enable_wol(device_t dev)
2960 {
2961         uint16_t cap, status;
2962         uint8_t id;
2963
2964         /* First find the capabilities pointer*/
2965         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2966
2967         /* Read the PM Capabilities */
2968         id = pci_read_config(dev, cap, 1);
2969         if (id != PCIY_PMG)     /* Something wrong */
2970                 return;
2971
2972         /*
2973          * OK, we have the power capabilities,
2974          * so now get the status register
2975          */
2976         cap += PCIR_POWER_STATUS;
2977         status = pci_read_config(dev, cap, 2);
2978         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2979         pci_write_config(dev, cap, status, 2);
2980 }
2981
2982 static void
2983 igb_update_stats_counters(struct igb_softc *sc)
2984 {
2985         struct e1000_hw *hw = &sc->hw;
2986         struct e1000_hw_stats *stats;
2987         struct ifnet *ifp = &sc->arpcom.ac_if;
2988
2989         /*
2990          * The virtual function adapter has only a
2991          * small controlled set of stats, do only
2992          * those and return.
2993          */
2994         if (sc->vf_ifp) {
2995                 igb_update_vf_stats_counters(sc);
2996                 return;
2997         }
2998         stats = sc->stats;
2999
3000         if (sc->hw.phy.media_type == e1000_media_type_copper ||
3001             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
3002                 stats->symerrs +=
3003                     E1000_READ_REG(hw,E1000_SYMERRS);
3004                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
3005         }
3006
3007         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
3008         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
3009         stats->scc += E1000_READ_REG(hw, E1000_SCC);
3010         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
3011
3012         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
3013         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
3014         stats->colc += E1000_READ_REG(hw, E1000_COLC);
3015         stats->dc += E1000_READ_REG(hw, E1000_DC);
3016         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
3017         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
3018         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
3019
3020         /*
3021          * For watchdog management we need to know if we have been
3022          * paused during the last interval, so capture that here.
3023          */
3024         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
3025         stats->xoffrxc += sc->pause_frames;
3026         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
3027         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
3028         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
3029         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
3030         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
3031         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
3032         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
3033         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
3034         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
3035         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
3036         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
3037         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
3038
3039         /* For the 64-bit byte counters the low dword must be read first. */
3040         /* Both registers clear on the read of the high dword */
3041
3042         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
3043             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
3044         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
3045             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
3046
3047         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
3048         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
3049         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
3050         stats->roc += E1000_READ_REG(hw, E1000_ROC);
3051         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
3052
3053         stats->tor += E1000_READ_REG(hw, E1000_TORH);
3054         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
3055
3056         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
3057         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
3058         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
3059         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
3060         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
3061         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
3062         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
3063         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
3064         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
3065         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
3066
3067         /* Interrupt Counts */
3068
3069         stats->iac += E1000_READ_REG(hw, E1000_IAC);
3070         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
3071         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
3072         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
3073         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
3074         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
3075         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
3076         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
3077         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
3078
3079         /* Host to Card Statistics */
3080
3081         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
3082         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
3083         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
3084         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
3085         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
3086         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
3087         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
3088         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
3089             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
3090         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
3091             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
3092         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
3093         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
3094         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
3095
3096         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
3097         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
3098         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
3099         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
3100         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
3101         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
3102
3103         IFNET_STAT_SET(ifp, collisions, stats->colc);
3104
3105         /* Rx Errors */
3106         IFNET_STAT_SET(ifp, ierrors,
3107             stats->rxerrc + stats->crcerrs + stats->algnerrc +
3108             stats->ruc + stats->roc + stats->mpc + stats->cexterr);
3109
3110         /* Tx Errors */
3111         IFNET_STAT_SET(ifp, oerrors,
3112             stats->ecol + stats->latecol + sc->watchdog_events);
3113
3114         /* Driver specific counters */
3115         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
3116         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
3117         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
3118         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
3119         sc->packet_buf_alloc_tx =
3120             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
3121         sc->packet_buf_alloc_rx =
3122             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
3123 }
3124
3125 static void
3126 igb_vf_init_stats(struct igb_softc *sc)
3127 {
3128         struct e1000_hw *hw = &sc->hw;
3129         struct e1000_vf_stats *stats;
3130
3131         stats = sc->stats;
3132         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
3133         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
3134         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
3135         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
3136         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
3137 }
3138
3139 static void
3140 igb_update_vf_stats_counters(struct igb_softc *sc)
3141 {
3142         struct e1000_hw *hw = &sc->hw;
3143         struct e1000_vf_stats *stats;
3144
3145         if (sc->link_speed == 0)
3146                 return;
3147
3148         stats = sc->stats;
3149         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3150         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3151         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3152         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3153         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3154 }
3155
3156 #ifdef IFPOLL_ENABLE
3157
3158 static void
3159 igb_npoll_status(struct ifnet *ifp)
3160 {
3161         struct igb_softc *sc = ifp->if_softc;
3162         uint32_t reg_icr;
3163
3164         ASSERT_SERIALIZED(&sc->main_serialize);
3165
3166         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3167         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3168                 sc->hw.mac.get_link_status = 1;
3169                 igb_update_link_status(sc);
3170         }
3171 }
3172
3173 static void
3174 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3175 {
3176         struct igb_tx_ring *txr = arg;
3177
3178         ASSERT_SERIALIZED(&txr->tx_serialize);
3179
3180         igb_txeof(txr);
3181         if (!ifsq_is_empty(txr->ifsq))
3182                 ifsq_devstart(txr->ifsq);
3183 }
3184
3185 static void
3186 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3187 {
3188         struct igb_rx_ring *rxr = arg;
3189
3190         ASSERT_SERIALIZED(&rxr->rx_serialize);
3191
3192         igb_rxeof(rxr, cycle);
3193 }
3194
3195 static void
3196 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3197 {
3198         struct igb_softc *sc = ifp->if_softc;
3199         int i, txr_cnt, rxr_cnt;
3200
3201         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3202
3203         if (info) {
3204                 int off;
3205
3206                 info->ifpi_status.status_func = igb_npoll_status;
3207                 info->ifpi_status.serializer = &sc->main_serialize;
3208
3209                 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3210                 off = sc->tx_npoll_off;
3211                 for (i = 0; i < txr_cnt; ++i) {
3212                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3213                         int idx = i + off;
3214
3215                         KKASSERT(idx < ncpus2);
3216                         info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3217                         info->ifpi_tx[idx].arg = txr;
3218                         info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3219                         ifsq_set_cpuid(txr->ifsq, idx);
3220                 }
3221
3222                 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3223                 off = sc->rx_npoll_off;
3224                 for (i = 0; i < rxr_cnt; ++i) {
3225                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3226                         int idx = i + off;
3227
3228                         KKASSERT(idx < ncpus2);
3229                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3230                         info->ifpi_rx[idx].arg = rxr;
3231                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3232                 }
3233
3234                 if (ifp->if_flags & IFF_RUNNING) {
3235                         if (rxr_cnt == sc->rx_ring_inuse &&
3236                             txr_cnt == sc->tx_ring_inuse) {
3237                                 igb_set_timer_cpuid(sc, TRUE);
3238                                 igb_disable_intr(sc);
3239                         } else {
3240                                 igb_init(sc);
3241                         }
3242                 }
3243         } else {
3244                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3245                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3246
3247                         ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3248                 }
3249
3250                 if (ifp->if_flags & IFF_RUNNING) {
3251                         txr_cnt = igb_get_txring_inuse(sc, FALSE);
3252                         rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3253
3254                         if (rxr_cnt == sc->rx_ring_inuse &&
3255                             txr_cnt == sc->tx_ring_inuse) {
3256                                 igb_set_timer_cpuid(sc, FALSE);
3257                                 igb_enable_intr(sc);
3258                         } else {
3259                                 igb_init(sc);
3260                         }
3261                 }
3262         }
3263 }
3264
3265 #endif /* IFPOLL_ENABLE */
3266
3267 static void
3268 igb_intr(void *xsc)
3269 {
3270         struct igb_softc *sc = xsc;
3271         struct ifnet *ifp = &sc->arpcom.ac_if;
3272         uint32_t eicr;
3273
3274         ASSERT_SERIALIZED(&sc->main_serialize);
3275
3276         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3277
3278         if (eicr == 0)
3279                 return;
3280
3281         if (ifp->if_flags & IFF_RUNNING) {
3282                 struct igb_tx_ring *txr = &sc->tx_rings[0];
3283                 int i;
3284
3285                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3286                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3287
3288                         if (eicr & rxr->rx_intr_mask) {
3289                                 lwkt_serialize_enter(&rxr->rx_serialize);
3290                                 igb_rxeof(rxr, -1);
3291                                 lwkt_serialize_exit(&rxr->rx_serialize);
3292                         }
3293                 }
3294
3295                 if (eicr & txr->tx_intr_mask) {
3296                         lwkt_serialize_enter(&txr->tx_serialize);
3297                         igb_txeof(txr);
3298                         if (!ifsq_is_empty(txr->ifsq))
3299                                 ifsq_devstart(txr->ifsq);
3300                         lwkt_serialize_exit(&txr->tx_serialize);
3301                 }
3302         }
3303
3304         if (eicr & E1000_EICR_OTHER) {
3305                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3306
3307                 /* Link status change */
3308                 if (icr & E1000_ICR_LSC) {
3309                         sc->hw.mac.get_link_status = 1;
3310                         igb_update_link_status(sc);
3311                 }
3312         }
3313
3314         /*
3315          * Reading EICR has the side effect to clear interrupt mask,
3316          * so all interrupts need to be enabled here.
3317          */
3318         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3319 }
3320
3321 static void
3322 igb_intr_shared(void *xsc)
3323 {
3324         struct igb_softc *sc = xsc;
3325         struct ifnet *ifp = &sc->arpcom.ac_if;
3326         uint32_t reg_icr;
3327
3328         ASSERT_SERIALIZED(&sc->main_serialize);
3329
3330         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3331
3332         /* Hot eject?  */
3333         if (reg_icr == 0xffffffff)
3334                 return;
3335
3336         /* Definitely not our interrupt.  */
3337         if (reg_icr == 0x0)
3338                 return;
3339
3340         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3341                 return;
3342
3343         if (ifp->if_flags & IFF_RUNNING) {
3344                 if (reg_icr &
3345                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3346                         int i;
3347
3348                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3349                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3350
3351                                 lwkt_serialize_enter(&rxr->rx_serialize);
3352                                 igb_rxeof(rxr, -1);
3353                                 lwkt_serialize_exit(&rxr->rx_serialize);
3354                         }
3355                 }
3356
3357                 if (reg_icr & E1000_ICR_TXDW) {
3358                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3359
3360                         lwkt_serialize_enter(&txr->tx_serialize);
3361                         igb_txeof(txr);
3362                         if (!ifsq_is_empty(txr->ifsq))
3363                                 ifsq_devstart(txr->ifsq);
3364                         lwkt_serialize_exit(&txr->tx_serialize);
3365                 }
3366         }
3367
3368         /* Link status change */
3369         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3370                 sc->hw.mac.get_link_status = 1;
3371                 igb_update_link_status(sc);
3372         }
3373
3374         if (reg_icr & E1000_ICR_RXO)
3375                 sc->rx_overruns++;
3376 }
3377
3378 static int
3379 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3380     int *segs_used, int *idx)
3381 {
3382         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3383         bus_dmamap_t map;
3384         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3385         union e1000_adv_tx_desc *txd = NULL;
3386         struct mbuf *m_head = *m_headp;
3387         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3388         int maxsegs, nsegs, i, j, error;
3389         uint32_t hdrlen = 0;
3390
3391         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3392                 error = igb_tso_pullup(txr, m_headp);
3393                 if (error)
3394                         return error;
3395                 m_head = *m_headp;
3396         }
3397
3398         /* Set basic descriptor constants */
3399         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3400         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3401         if (m_head->m_flags & M_VLANTAG)
3402                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3403
3404         /*
3405          * Map the packet for DMA.
3406          */
3407         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3408         tx_buf_mapped = tx_buf;
3409         map = tx_buf->map;
3410
3411         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3412         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3413         if (maxsegs > IGB_MAX_SCATTER)
3414                 maxsegs = IGB_MAX_SCATTER;
3415
3416         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3417             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3418         if (error) {
3419                 if (error == ENOBUFS)
3420                         txr->sc->mbuf_defrag_failed++;
3421                 else
3422                         txr->sc->no_tx_dma_setup++;
3423
3424                 m_freem(*m_headp);
3425                 *m_headp = NULL;
3426                 return error;
3427         }
3428         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3429
3430         m_head = *m_headp;
3431
3432         /*
3433          * Set up the TX context descriptor, if any hardware offloading is
3434          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3435          * TX descriptor.
3436          *
3437          * Unlike these chips' predecessors (em/emx), TX context descriptor
3438          * will _not_ interfere TX data fetching pipelining.
3439          */
3440         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3441                 igb_tso_ctx(txr, m_head, &hdrlen);
3442                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3443                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3444                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3445                 txr->tx_nsegs++;
3446                 (*segs_used)++;
3447         } else if (igb_txcsum_ctx(txr, m_head)) {
3448                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3449                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3450                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3451                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3452                 txr->tx_nsegs++;
3453                 (*segs_used)++;
3454         }
3455
3456         *segs_used += nsegs;
3457         txr->tx_nsegs += nsegs;
3458         if (txr->tx_nsegs >= txr->intr_nsegs) {
3459                 /*
3460                  * Report Status (RS) is turned on every intr_nsegs
3461                  * descriptors (roughly).
3462                  */
3463                 txr->tx_nsegs = 0;
3464                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3465         }
3466
3467         /* Calculate payload length */
3468         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3469             << E1000_ADVTXD_PAYLEN_SHIFT);
3470
3471         /*
3472          * 82575 needs the TX context index added; the queue
3473          * index is used as TX context index here.
3474          */
3475         if (txr->sc->hw.mac.type == e1000_82575)
3476                 olinfo_status |= txr->me << 4;
3477
3478         /* Set up our transmit descriptors */
3479         i = txr->next_avail_desc;
3480         for (j = 0; j < nsegs; j++) {
3481                 bus_size_t seg_len;
3482                 bus_addr_t seg_addr;
3483
3484                 tx_buf = &txr->tx_buf[i];
3485                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3486                 seg_addr = segs[j].ds_addr;
3487                 seg_len = segs[j].ds_len;
3488
3489                 txd->read.buffer_addr = htole64(seg_addr);
3490                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3491                 txd->read.olinfo_status = htole32(olinfo_status);
3492                 if (++i == txr->num_tx_desc)
3493                         i = 0;
3494                 tx_buf->m_head = NULL;
3495         }
3496
3497         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3498         txr->next_avail_desc = i;
3499         txr->tx_avail -= nsegs;
3500
3501         tx_buf->m_head = m_head;
3502         tx_buf_mapped->map = tx_buf->map;
3503         tx_buf->map = map;
3504
3505         /*
3506          * Last Descriptor of Packet needs End Of Packet (EOP)
3507          */
3508         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3509
3510         /*
3511          * Defer TDT updating, until enough descrptors are setup
3512          */
3513         *idx = i;
3514 #ifdef IGB_TSS_DEBUG
3515         ++txr->tx_packets;
3516 #endif
3517
3518         return 0;
3519 }
3520
3521 static void
3522 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3523 {
3524         struct igb_softc *sc = ifp->if_softc;
3525         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3526         struct mbuf *m_head;
3527         int idx = -1, nsegs = 0;
3528
3529         KKASSERT(txr->ifsq == ifsq);
3530         ASSERT_SERIALIZED(&txr->tx_serialize);
3531
3532         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3533                 return;
3534
3535         if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
3536                 ifsq_purge(ifsq);
3537                 return;
3538         }
3539
3540         if (!IGB_IS_NOT_OACTIVE(txr))
3541                 igb_txeof(txr);
3542
3543         while (!ifsq_is_empty(ifsq)) {
3544                 if (IGB_IS_OACTIVE(txr)) {
3545                         ifsq_set_oactive(ifsq);
3546                         /* Set watchdog on */
3547                         txr->tx_watchdog.wd_timer = 5;
3548                         break;
3549                 }
3550
3551                 m_head = ifsq_dequeue(ifsq);
3552                 if (m_head == NULL)
3553                         break;
3554
3555                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3556                         IFNET_STAT_INC(ifp, oerrors, 1);
3557                         continue;
3558                 }
3559
3560                 /*
3561                  * TX interrupt are aggressively aggregated, so increasing
3562                  * opackets at TX interrupt time will make the opackets
3563                  * statistics vastly inaccurate; we do the opackets increment
3564                  * now.
3565                  */
3566                 IFNET_STAT_INC(ifp, opackets, 1);
3567
3568                 if (nsegs >= txr->wreg_nsegs) {
3569                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3570                         idx = -1;
3571                         nsegs = 0;
3572                 }
3573
3574                 /* Send a copy of the frame to the BPF listener */
3575                 ETHER_BPF_MTAP(ifp, m_head);
3576         }
3577         if (idx >= 0)
3578                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3579 }
3580
3581 static void
3582 igb_watchdog(struct ifaltq_subque *ifsq)
3583 {
3584         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3585         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3586         struct igb_softc *sc = ifp->if_softc;
3587         int i;
3588
3589         KKASSERT(txr->ifsq == ifsq);
3590         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3591
3592         /*
3593          * If flow control has paused us since last checking
3594          * it invalidates the watchdog timing, so dont run it.
3595          */
3596         if (sc->pause_frames) {
3597                 sc->pause_frames = 0;
3598                 txr->tx_watchdog.wd_timer = 5;
3599                 return;
3600         }
3601
3602         if_printf(ifp, "Watchdog timeout -- resetting\n");
3603         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3604             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3605             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3606         if_printf(ifp, "TX(%d) desc avail = %d, "
3607             "Next TX to Clean = %d\n",
3608             txr->me, txr->tx_avail, txr->next_to_clean);
3609
3610         IFNET_STAT_INC(ifp, oerrors, 1);
3611         sc->watchdog_events++;
3612
3613         igb_init(sc);
3614         for (i = 0; i < sc->tx_ring_inuse; ++i)
3615                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3616 }
3617
3618 static void
3619 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3620 {
3621         uint32_t eitr = 0;
3622
3623         if (rate > 0) {
3624                 if (sc->hw.mac.type == e1000_82575) {
3625                         eitr = 1000000000 / 256 / rate;
3626                         /*
3627                          * NOTE:
3628                          * Document is wrong on the 2 bits left shift
3629                          */
3630                 } else {
3631                         eitr = 1000000 / rate;
3632                         eitr <<= IGB_EITR_INTVL_SHIFT;
3633                 }
3634
3635                 if (eitr == 0) {
3636                         /* Don't disable it */
3637                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3638                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3639                         /* Don't allow it to be too large */
3640                         eitr = IGB_EITR_INTVL_MASK;
3641                 }
3642         }
3643         if (sc->hw.mac.type == e1000_82575)
3644                 eitr |= eitr << 16;
3645         else
3646                 eitr |= E1000_EITR_CNT_IGNR;
3647         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3648 }
3649
3650 static int
3651 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3652 {
3653         struct igb_softc *sc = (void *)arg1;
3654         struct ifnet *ifp = &sc->arpcom.ac_if;
3655         int error, intr_rate;
3656
3657         intr_rate = sc->intr_rate;
3658         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3659         if (error || req->newptr == NULL)
3660                 return error;
3661         if (intr_rate < 0)
3662                 return EINVAL;
3663
3664         ifnet_serialize_all(ifp);
3665
3666         sc->intr_rate = intr_rate;
3667         if (ifp->if_flags & IFF_RUNNING)
3668                 igb_set_eitr(sc, 0, sc->intr_rate);
3669
3670         if (bootverbose)
3671                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3672
3673         ifnet_deserialize_all(ifp);
3674
3675         return 0;
3676 }
3677
3678 static int
3679 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3680 {
3681         struct igb_msix_data *msix = (void *)arg1;
3682         struct igb_softc *sc = msix->msix_sc;
3683         struct ifnet *ifp = &sc->arpcom.ac_if;
3684         int error, msix_rate;
3685
3686         msix_rate = msix->msix_rate;
3687         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3688         if (error || req->newptr == NULL)
3689                 return error;
3690         if (msix_rate < 0)
3691                 return EINVAL;
3692
3693         lwkt_serialize_enter(msix->msix_serialize);
3694
3695         msix->msix_rate = msix_rate;
3696         if (ifp->if_flags & IFF_RUNNING)
3697                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3698
3699         if (bootverbose) {
3700                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3701                     msix->msix_rate);
3702         }
3703
3704         lwkt_serialize_exit(msix->msix_serialize);
3705
3706         return 0;
3707 }
3708
3709 static int
3710 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3711 {
3712         struct igb_softc *sc = (void *)arg1;
3713         struct ifnet *ifp = &sc->arpcom.ac_if;
3714         struct igb_tx_ring *txr = &sc->tx_rings[0];
3715         int error, nsegs;
3716
3717         nsegs = txr->intr_nsegs;
3718         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3719         if (error || req->newptr == NULL)
3720                 return error;
3721         if (nsegs <= 0)
3722                 return EINVAL;
3723
3724         ifnet_serialize_all(ifp);
3725
3726         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3727             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3728                 error = EINVAL;
3729         } else {
3730                 int i;
3731
3732                 error = 0;
3733                 for (i = 0; i < sc->tx_ring_cnt; ++i)
3734                         sc->tx_rings[i].intr_nsegs = nsegs;
3735         }
3736
3737         ifnet_deserialize_all(ifp);
3738
3739         return error;
3740 }
3741
3742 static int
3743 igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3744 {
3745         struct igb_softc *sc = (void *)arg1;
3746         struct ifnet *ifp = &sc->arpcom.ac_if;
3747         int error, nsegs, i;
3748
3749         nsegs = sc->rx_rings[0].wreg_nsegs;
3750         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3751         if (error || req->newptr == NULL)
3752                 return error;
3753
3754         ifnet_serialize_all(ifp);
3755         for (i = 0; i < sc->rx_ring_cnt; ++i)
3756                 sc->rx_rings[i].wreg_nsegs =nsegs;
3757         ifnet_deserialize_all(ifp);
3758
3759         return 0;
3760 }
3761
3762 static int
3763 igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3764 {
3765         struct igb_softc *sc = (void *)arg1;
3766         struct ifnet *ifp = &sc->arpcom.ac_if;
3767         int error, nsegs, i;
3768
3769         nsegs = sc->tx_rings[0].wreg_nsegs;
3770         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3771         if (error || req->newptr == NULL)
3772                 return error;
3773
3774         ifnet_serialize_all(ifp);
3775         for (i = 0; i < sc->tx_ring_cnt; ++i)
3776                 sc->tx_rings[i].wreg_nsegs =nsegs;
3777         ifnet_deserialize_all(ifp);
3778
3779         return 0;
3780 }
3781
3782 #ifdef IFPOLL_ENABLE
3783
3784 static int
3785 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3786 {
3787         struct igb_softc *sc = (void *)arg1;
3788         struct ifnet *ifp = &sc->arpcom.ac_if;
3789         int error, off;
3790
3791         off = sc->rx_npoll_off;
3792         error = sysctl_handle_int(oidp, &off, 0, req);
3793         if (error || req->newptr == NULL)
3794                 return error;
3795         if (off < 0)
3796                 return EINVAL;
3797
3798         ifnet_serialize_all(ifp);
3799         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3800                 error = EINVAL;
3801         } else {
3802                 error = 0;
3803                 sc->rx_npoll_off = off;
3804         }
3805         ifnet_deserialize_all(ifp);
3806
3807         return error;
3808 }
3809
3810 static int
3811 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3812 {
3813         struct igb_softc *sc = (void *)arg1;
3814         struct ifnet *ifp = &sc->arpcom.ac_if;
3815         int error, off;
3816
3817         off = sc->tx_npoll_off;
3818         error = sysctl_handle_int(oidp, &off, 0, req);
3819         if (error || req->newptr == NULL)
3820                 return error;
3821         if (off < 0)
3822                 return EINVAL;
3823
3824         ifnet_serialize_all(ifp);
3825         if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3826                 error = EINVAL;
3827         } else {
3828                 error = 0;
3829                 sc->tx_npoll_off = off;
3830         }
3831         ifnet_deserialize_all(ifp);
3832
3833         return error;
3834 }
3835
3836 #endif  /* IFPOLL_ENABLE */
3837
3838 static void
3839 igb_init_intr(struct igb_softc *sc)
3840 {
3841         igb_set_intr_mask(sc);
3842
3843         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3844                 igb_init_unshared_intr(sc);
3845
3846         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3847                 igb_set_eitr(sc, 0, sc->intr_rate);
3848         } else {
3849                 int i;
3850
3851                 for (i = 0; i < sc->msix_cnt; ++i)
3852                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3853         }
3854 }
3855
3856 static void
3857 igb_init_unshared_intr(struct igb_softc *sc)
3858 {
3859         struct e1000_hw *hw = &sc->hw;
3860         const struct igb_rx_ring *rxr;
3861         const struct igb_tx_ring *txr;
3862         uint32_t ivar, index;
3863         int i;
3864
3865         /*
3866          * Enable extended mode
3867          */
3868         if (sc->hw.mac.type != e1000_82575) {
3869                 uint32_t gpie;
3870                 int ivar_max;
3871
3872                 gpie = E1000_GPIE_NSICR;
3873                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3874                         gpie |= E1000_GPIE_MSIX_MODE |
3875                             E1000_GPIE_EIAME |
3876                             E1000_GPIE_PBA;
3877                 }
3878                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3879
3880                 /*
3881                  * Clear IVARs
3882                  */
3883                 switch (sc->hw.mac.type) {
3884                 case e1000_82576:
3885                         ivar_max = IGB_MAX_IVAR_82576;
3886                         break;
3887
3888                 case e1000_82580:
3889                         ivar_max = IGB_MAX_IVAR_82580;
3890                         break;
3891
3892                 case e1000_i350:
3893                         ivar_max = IGB_MAX_IVAR_I350;
3894                         break;
3895
3896                 case e1000_i354:
3897                         ivar_max = IGB_MAX_IVAR_I354;
3898                         break;
3899
3900                 case e1000_vfadapt:
3901                 case e1000_vfadapt_i350:
3902                         ivar_max = IGB_MAX_IVAR_VF;
3903                         break;
3904
3905                 case e1000_i210:
3906                         ivar_max = IGB_MAX_IVAR_I210;
3907                         break;
3908
3909                 case e1000_i211:
3910                         ivar_max = IGB_MAX_IVAR_I211;
3911                         break;
3912
3913                 default:
3914                         panic("unknown mac type %d\n", sc->hw.mac.type);
3915                 }
3916                 for (i = 0; i < ivar_max; ++i)
3917                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3918                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3919         } else {
3920                 uint32_t tmp;
3921
3922                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3923                     ("82575 w/ MSI-X"));
3924                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3925                 tmp |= E1000_CTRL_EXT_IRCA;
3926                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3927         }
3928
3929         /*
3930          * Map TX/RX interrupts to EICR
3931          */
3932         switch (sc->hw.mac.type) {
3933         case e1000_82580:
3934         case e1000_i350:
3935         case e1000_i354:
3936         case e1000_vfadapt:
3937         case e1000_vfadapt_i350:
3938         case e1000_i210:
3939         case e1000_i211:
3940                 /* RX entries */
3941                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3942                         rxr = &sc->rx_rings[i];
3943
3944                         index = i >> 1;
3945                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3946
3947                         if (i & 1) {
3948                                 ivar &= 0xff00ffff;
3949                                 ivar |=
3950                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3951                         } else {
3952                                 ivar &= 0xffffff00;
3953                                 ivar |=
3954                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3955                         }
3956                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3957                 }
3958                 /* TX entries */
3959                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3960                         txr = &sc->tx_rings[i];
3961
3962                         index = i >> 1;
3963                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3964
3965                         if (i & 1) {
3966                                 ivar &= 0x00ffffff;
3967                                 ivar |=
3968                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3969                         } else {
3970                                 ivar &= 0xffff00ff;
3971                                 ivar |=
3972                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3973                         }
3974                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3975                 }
3976                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3977                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3978                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3979                 }
3980                 break;
3981
3982         case e1000_82576:
3983                 /* RX entries */
3984                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3985                         rxr = &sc->rx_rings[i];
3986
3987                         index = i & 0x7; /* Each IVAR has two entries */
3988                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3989
3990                         if (i < 8) {
3991                                 ivar &= 0xffffff00;
3992                                 ivar |=
3993                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3994                         } else {
3995                                 ivar &= 0xff00ffff;
3996                                 ivar |=
3997                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3998                         }
3999                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4000                 }
4001                 /* TX entries */
4002                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
4003                         txr = &sc->tx_rings[i];
4004
4005                         index = i & 0x7; /* Each IVAR has two entries */
4006                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4007
4008                         if (i < 8) {
4009                                 ivar &= 0xffff00ff;
4010                                 ivar |=
4011                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
4012                         } else {
4013                                 ivar &= 0x00ffffff;
4014                                 ivar |=
4015                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
4016                         }
4017                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4018                 }
4019                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
4020                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
4021                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4022                 }
4023                 break;
4024
4025         case e1000_82575:
4026                 /*
4027                  * Enable necessary interrupt bits.
4028                  *
4029                  * The name of the register is confusing; in addition to
4030                  * configuring the first vector of MSI-X, it also configures
4031                  * which bits of EICR could be set by the hardware even when
4032                  * MSI or line interrupt is used; it thus controls interrupt
4033                  * generation.  It MUST be configured explicitly; the default
4034                  * value mentioned in the datasheet is wrong: RX queue0 and
4035                  * TX queue0 are NOT enabled by default.
4036                  */
4037                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
4038                 break;
4039
4040         default:
4041                 panic("unknown mac type %d\n", sc->hw.mac.type);
4042         }
4043 }
4044
4045 static int
4046 igb_setup_intr(struct igb_softc *sc)
4047 {
4048         int error;
4049
4050         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4051                 return igb_msix_setup(sc);
4052
4053         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
4054             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
4055             sc, &sc->intr_tag, &sc->main_serialize);
4056         if (error) {
4057                 device_printf(sc->dev, "Failed to register interrupt handler");
4058                 return error;
4059         }
4060         return 0;
4061 }
4062
4063 static void
4064 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
4065 {
4066         if (txr->sc->hw.mac.type == e1000_82575) {
4067                 txr->tx_intr_bit = 0;   /* unused */
4068                 switch (txr->me) {
4069                 case 0:
4070                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
4071                         break;
4072                 case 1:
4073                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
4074                         break;
4075                 case 2:
4076                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
4077                         break;
4078                 case 3:
4079                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
4080                         break;
4081                 default:
4082                         panic("unsupported # of TX ring, %d\n", txr->me);
4083                 }
4084         } else {
4085                 int intr_bit = *intr_bit0;
4086
4087                 txr->tx_intr_bit = intr_bit % intr_bitmax;
4088                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
4089
4090                 *intr_bit0 = intr_bit + 1;
4091         }
4092 }
4093
4094 static void
4095 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
4096 {
4097         if (rxr->sc->hw.mac.type == e1000_82575) {
4098                 rxr->rx_intr_bit = 0;   /* unused */
4099                 switch (rxr->me) {
4100                 case 0:
4101                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
4102                         break;
4103                 case 1:
4104                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
4105                         break;
4106                 case 2:
4107                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
4108                         break;
4109                 case 3:
4110                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
4111                         break;
4112                 default:
4113                         panic("unsupported # of RX ring, %d\n", rxr->me);
4114                 }
4115         } else {
4116                 int intr_bit = *intr_bit0;
4117
4118                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
4119                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
4120
4121                 *intr_bit0 = intr_bit + 1;
4122         }
4123 }
4124
4125 static void
4126 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4127 {
4128         struct igb_softc *sc = ifp->if_softc;
4129
4130         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt, slz);
4131 }
4132
4133 static void
4134 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4135 {
4136         struct igb_softc *sc = ifp->if_softc;
4137
4138         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt, slz);
4139 }
4140
4141 static int
4142 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4143 {
4144         struct igb_softc *sc = ifp->if_softc;
4145
4146         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
4147             slz);
4148 }
4149
4150 #ifdef INVARIANTS
4151
4152 static void
4153 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4154     boolean_t serialized)
4155 {
4156         struct igb_softc *sc = ifp->if_softc;
4157
4158         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
4159             slz, serialized);
4160 }
4161
4162 #endif  /* INVARIANTS */
4163
4164 static void
4165 igb_set_intr_mask(struct igb_softc *sc)
4166 {
4167         int i;
4168
4169         sc->intr_mask = sc->sts_intr_mask;
4170         for (i = 0; i < sc->rx_ring_inuse; ++i)
4171                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
4172         for (i = 0; i < sc->tx_ring_inuse; ++i)
4173                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
4174         if (bootverbose) {
4175                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
4176                     sc->intr_mask);
4177         }
4178 }
4179
4180 static int
4181 igb_alloc_intr(struct igb_softc *sc)
4182 {
4183         int i, intr_bit, intr_bitmax;
4184         u_int intr_flags;
4185
4186         igb_msix_try_alloc(sc);
4187         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4188                 goto done;
4189
4190         /*
4191          * Allocate MSI/legacy interrupt resource
4192          */
4193         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
4194             &sc->intr_rid, &intr_flags);
4195
4196         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
4197                 int unshared;
4198
4199                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
4200                 if (!unshared) {
4201                         sc->flags |= IGB_FLAG_SHARED_INTR;
4202                         if (bootverbose)
4203                                 device_printf(sc->dev, "IRQ shared\n");
4204                 } else {
4205                         intr_flags &= ~RF_SHAREABLE;
4206                         if (bootverbose)
4207                                 device_printf(sc->dev, "IRQ unshared\n");
4208                 }
4209         }
4210
4211         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4212             &sc->intr_rid, intr_flags);
4213         if (sc->intr_res == NULL) {
4214                 device_printf(sc->dev, "Unable to allocate bus resource: "
4215                     "interrupt\n");
4216                 return ENXIO;
4217         }
4218
4219         for (i = 0; i < sc->tx_ring_cnt; ++i)
4220                 sc->tx_rings[i].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
4221
4222         /*
4223          * Setup MSI/legacy interrupt mask
4224          */
4225         switch (sc->hw.mac.type) {
4226         case e1000_82575:
4227                 intr_bitmax = IGB_MAX_TXRXINT_82575;
4228                 break;
4229
4230         case e1000_82576:
4231                 intr_bitmax = IGB_MAX_TXRXINT_82576;
4232                 break;
4233
4234         case e1000_82580:
4235                 intr_bitmax = IGB_MAX_TXRXINT_82580;
4236                 break;
4237
4238         case e1000_i350:
4239                 intr_bitmax = IGB_MAX_TXRXINT_I350;
4240                 break;
4241
4242         case e1000_i354:
4243                 intr_bitmax = IGB_MAX_TXRXINT_I354;
4244                 break;
4245
4246         case e1000_i210:
4247                 intr_bitmax = IGB_MAX_TXRXINT_I210;
4248                 break;
4249
4250         case e1000_i211:
4251                 intr_bitmax = IGB_MAX_TXRXINT_I211;
4252                 break;
4253
4254         default:
4255                 intr_bitmax = IGB_MIN_TXRXINT;
4256                 break;
4257         }
4258         intr_bit = 0;
4259         for (i = 0; i < sc->tx_ring_cnt; ++i)
4260                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4261         for (i = 0; i < sc->rx_ring_cnt; ++i)
4262                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4263         sc->sts_intr_bit = 0;
4264         sc->sts_intr_mask = E1000_EICR_OTHER;
4265
4266         /* Initialize interrupt rate */
4267         sc->intr_rate = IGB_INTR_RATE;
4268 done:
4269         igb_set_ring_inuse(sc, FALSE);
4270         igb_set_intr_mask(sc);
4271         return 0;
4272 }
4273
4274 static void
4275 igb_free_intr(struct igb_softc *sc)
4276 {
4277         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4278                 if (sc->intr_res != NULL) {
4279                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4280                             sc->intr_res);
4281                 }
4282                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4283                         pci_release_msi(sc->dev);
4284         } else {
4285                 igb_msix_free(sc, TRUE);
4286         }
4287 }
4288
4289 static void
4290 igb_teardown_intr(struct igb_softc *sc)
4291 {
4292         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4293                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4294         else
4295                 igb_msix_teardown(sc, sc->msix_cnt);
4296 }
4297
4298 static void
4299 igb_msix_try_alloc(struct igb_softc *sc)
4300 {
4301         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4302         int i, x, error;
4303         int offset, offset_def;
4304         struct igb_msix_data *msix;
4305         boolean_t aggregate, setup = FALSE;
4306
4307         /*
4308          * Don't enable MSI-X on 82575, see:
4309          * 82575 specification update errata #25
4310          */
4311         if (sc->hw.mac.type == e1000_82575)
4312                 return;
4313
4314         /* Don't enable MSI-X on VF */
4315         if (sc->vf_ifp)
4316                 return;
4317
4318         msix_enable = device_getenv_int(sc->dev, "msix.enable",
4319             igb_msix_enable);
4320         if (!msix_enable)
4321                 return;
4322
4323         msix_cnt = pci_msix_count(sc->dev);
4324 #ifdef IGB_MSIX_DEBUG
4325         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4326 #endif
4327         if (msix_cnt <= 1) {
4328                 /* One MSI-X model does not make sense */
4329                 return;
4330         }
4331
4332         i = 0;
4333         while ((1 << (i + 1)) <= msix_cnt)
4334                 ++i;
4335         msix_cnt2 = 1 << i;
4336
4337         if (bootverbose) {
4338                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4339                     msix_cnt2, msix_cnt);
4340         }
4341
4342         KKASSERT(msix_cnt2 <= msix_cnt);
4343         if (msix_cnt == msix_cnt2) {
4344                 /* We need at least one MSI-X for link status */
4345                 msix_cnt2 >>= 1;
4346                 if (msix_cnt2 <= 1) {
4347                         /* One MSI-X for RX/TX does not make sense */
4348                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4349                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4350                         return;
4351                 }
4352                 KKASSERT(msix_cnt > msix_cnt2);
4353
4354                 if (bootverbose) {
4355                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4356                             msix_cnt2, msix_cnt);
4357                 }
4358         }
4359
4360         sc->rx_ring_msix = sc->rx_ring_cnt;
4361         if (sc->rx_ring_msix > msix_cnt2)
4362                 sc->rx_ring_msix = msix_cnt2;
4363
4364         sc->tx_ring_msix = sc->tx_ring_cnt;
4365         if (sc->tx_ring_msix > msix_cnt2)
4366                 sc->tx_ring_msix = msix_cnt2;
4367
4368         if (msix_cnt >= sc->tx_ring_msix + sc->rx_ring_msix + 1) {
4369                 /*
4370                  * Independent TX/RX MSI-X
4371                  */
4372                 aggregate = FALSE;
4373                 if (bootverbose)
4374                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4375                 alloc_cnt = sc->tx_ring_msix + sc->rx_ring_msix;
4376         } else {
4377                 /*
4378                  * Aggregate TX/RX MSI-X
4379                  */
4380                 aggregate = TRUE;
4381                 if (bootverbose)
4382                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4383                 alloc_cnt = msix_cnt2;
4384                 if (alloc_cnt > ncpus2)
4385                         alloc_cnt = ncpus2;
4386                 if (sc->rx_ring_msix > alloc_cnt)
4387                         sc->rx_ring_msix = alloc_cnt;
4388                 if (sc->tx_ring_msix > alloc_cnt)
4389                         sc->tx_ring_msix = alloc_cnt;
4390         }
4391         ++alloc_cnt;    /* For link status */
4392
4393         if (bootverbose) {
4394                 device_printf(sc->dev, "MSI-X alloc %d, "
4395                     "RX ring %d, TX ring %d\n", alloc_cnt,
4396                     sc->rx_ring_msix, sc->tx_ring_msix);
4397         }
4398
4399         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4400         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4401             &sc->msix_mem_rid, RF_ACTIVE);
4402         if (sc->msix_mem_res == NULL) {
4403                 sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR_ALT);
4404                 sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4405                     &sc->msix_mem_rid, RF_ACTIVE);
4406                 if (sc->msix_mem_res == NULL) {
4407                         device_printf(sc->dev, "Unable to map MSI-X table\n");
4408                         return;
4409                 }
4410         }
4411
4412         sc->msix_cnt = alloc_cnt;
4413         sc->msix_data = kmalloc_cachealign(
4414             sizeof(struct igb_msix_data) * sc->msix_cnt,
4415             M_DEVBUF, M_WAITOK | M_ZERO);
4416         for (x = 0; x < sc->msix_cnt; ++x) {
4417                 msix = &sc->msix_data[x];
4418
4419                 lwkt_serialize_init(&msix->msix_serialize0);
4420                 msix->msix_sc = sc;
4421                 msix->msix_rid = -1;
4422                 msix->msix_vector = x;
4423                 msix->msix_mask = 1 << msix->msix_vector;
4424                 msix->msix_rate = IGB_INTR_RATE;
4425         }
4426
4427         x = 0;
4428         if (!aggregate) {
4429                 /*
4430                  * RX rings
4431                  */
4432                 if (sc->rx_ring_msix == ncpus2) {
4433                         offset = 0;
4434                 } else {
4435                         offset_def = (sc->rx_ring_msix *
4436                             device_get_unit(sc->dev)) % ncpus2;
4437
4438                         offset = device_getenv_int(sc->dev,
4439                             "msix.rxoff", offset_def);
4440                         if (offset >= ncpus2 ||
4441                             offset % sc->rx_ring_msix != 0) {
4442                                 device_printf(sc->dev,
4443                                     "invalid msix.rxoff %d, use %d\n",
4444                                     offset, offset_def);
4445                                 offset = offset_def;
4446                         }
4447                 }
4448                 igb_msix_rx_conf(sc, 0, &x, offset);
4449
4450                 /*
4451                  * TX rings
4452                  */
4453                 if (sc->tx_ring_msix == ncpus2) {
4454                         offset = 0;
4455                 } else {
4456                         offset_def = (sc->tx_ring_msix *
4457                             device_get_unit(sc->dev)) % ncpus2;
4458
4459                         offset = device_getenv_int(sc->dev,
4460                             "msix.txoff", offset_def);
4461                         if (offset >= ncpus2 ||
4462                             offset % sc->tx_ring_msix != 0) {
4463                                 device_printf(sc->dev,
4464                                     "invalid msix.txoff %d, use %d\n",
4465                                     offset, offset_def);
4466                                 offset = offset_def;
4467                         }
4468                 }
4469                 igb_msix_tx_conf(sc, 0, &x, offset);
4470         } else {
4471                 int ring_agg, ring_max;
4472
4473                 ring_agg = sc->rx_ring_msix;
4474                 if (ring_agg > sc->tx_ring_msix)
4475                         ring_agg = sc->tx_ring_msix;
4476
4477                 ring_max = sc->rx_ring_msix;
4478                 if (ring_max < sc->tx_ring_msix)
4479                         ring_max = sc->tx_ring_msix;
4480
4481                 if (ring_max == ncpus2) {
4482                         offset = 0;
4483                 } else {
4484                         offset_def = (ring_max * device_get_unit(sc->dev)) %
4485                             ncpus2;
4486
4487                         offset = device_getenv_int(sc->dev, "msix.off",
4488                             offset_def);
4489                         if (offset >= ncpus2 || offset % ring_max != 0) {
4490                                 device_printf(sc->dev,
4491                                     "invalid msix.off %d, use %d\n",
4492                                     offset, offset_def);
4493                                 offset = offset_def;
4494                         }
4495                 }
4496
4497                 for (i = 0; i < ring_agg; ++i) {
4498                         struct igb_tx_ring *txr = &sc->tx_rings[i];
4499                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
4500
4501                         KKASSERT(x < sc->msix_cnt);
4502                         msix = &sc->msix_data[x++];
4503
4504                         txr->tx_intr_bit = msix->msix_vector;
4505                         txr->tx_intr_mask = msix->msix_mask;
4506                         rxr->rx_intr_bit = msix->msix_vector;
4507                         rxr->rx_intr_mask = msix->msix_mask;
4508
4509                         msix->msix_serialize = &msix->msix_serialize0;
4510                         msix->msix_func = igb_msix_rxtx;
4511                         msix->msix_arg = msix;
4512                         msix->msix_rx = rxr;
4513                         msix->msix_tx = txr;
4514
4515                         msix->msix_cpuid = i + offset;
4516                         KKASSERT(msix->msix_cpuid < ncpus2);
4517                         txr->tx_intr_cpuid = msix->msix_cpuid;
4518
4519                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4520                             "%s rxtx%d", device_get_nameunit(sc->dev), i);
4521                         msix->msix_rate = IGB_MSIX_RX_RATE;
4522                         ksnprintf(msix->msix_rate_desc,
4523                             sizeof(msix->msix_rate_desc),
4524                             "RXTX%d interrupt rate", i);
4525                 }
4526
4527                 if (ring_agg != ring_max) {
4528                         if (ring_max == sc->tx_ring_msix)
4529                                 igb_msix_tx_conf(sc, i, &x, offset);
4530                         else
4531                                 igb_msix_rx_conf(sc, i, &x, offset);
4532                 }
4533         }
4534
4535         /*
4536          * Link status
4537          */
4538         KKASSERT(x < sc->msix_cnt);
4539         msix = &sc->msix_data[x++];
4540         sc->sts_intr_bit = msix->msix_vector;
4541         sc->sts_intr_mask = msix->msix_mask;
4542
4543         msix->msix_serialize = &sc->main_serialize;
4544         msix->msix_func = igb_msix_status;
4545         msix->msix_arg = sc;
4546         msix->msix_cpuid = 0;
4547         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4548             device_get_nameunit(sc->dev));
4549         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4550             "status interrupt rate");
4551
4552         KKASSERT(x == sc->msix_cnt);
4553
4554         error = pci_setup_msix(sc->dev);
4555         if (error) {
4556                 device_printf(sc->dev, "Setup MSI-X failed\n");
4557                 goto back;
4558         }
4559         setup = TRUE;
4560
4561         for (i = 0; i < sc->msix_cnt; ++i) {
4562                 msix = &sc->msix_data[i];
4563
4564                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4565                     &msix->msix_rid, msix->msix_cpuid);
4566                 if (error) {
4567                         device_printf(sc->dev,
4568                             "Unable to allocate MSI-X %d on cpu%d\n",
4569                             msix->msix_vector, msix->msix_cpuid);
4570                         goto back;
4571                 }
4572
4573                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4574                     &msix->msix_rid, RF_ACTIVE);
4575                 if (msix->msix_res == NULL) {
4576                         device_printf(sc->dev,
4577                             "Unable to allocate MSI-X %d resource\n",
4578                             msix->msix_vector);
4579                         error = ENOMEM;
4580                         goto back;
4581                 }
4582         }
4583
4584         pci_enable_msix(sc->dev);
4585         sc->intr_type = PCI_INTR_TYPE_MSIX;
4586 back:
4587         if (error)
4588                 igb_msix_free(sc, setup);
4589 }
4590
4591 static void
4592 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4593 {
4594         int i;
4595
4596         KKASSERT(sc->msix_cnt > 1);
4597
4598         for (i = 0; i < sc->msix_cnt; ++i) {
4599                 struct igb_msix_data *msix = &sc->msix_data[i];
4600
4601                 if (msix->msix_res != NULL) {
4602                         bus_release_resource(sc->dev, SYS_RES_IRQ,
4603                             msix->msix_rid, msix->msix_res);
4604                 }
4605                 if (msix->msix_rid >= 0)
4606                         pci_release_msix_vector(sc->dev, msix->msix_rid);
4607         }
4608         if (setup)
4609                 pci_teardown_msix(sc->dev);
4610
4611         sc->msix_cnt = 0;
4612         kfree(sc->msix_data, M_DEVBUF);
4613         sc->msix_data = NULL;
4614 }
4615
4616 static int
4617 igb_msix_setup(struct igb_softc *sc)
4618 {
4619         int i;
4620
4621         for (i = 0; i < sc->msix_cnt; ++i) {
4622                 struct igb_msix_data *msix = &sc->msix_data[i];
4623                 int error;
4624
4625                 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4626                     INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4627                     &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4628                 if (error) {
4629                         device_printf(sc->dev, "could not set up %s "
4630                             "interrupt handler.\n", msix->msix_desc);
4631                         igb_msix_teardown(sc, i);
4632                         return error;
4633                 }
4634         }
4635         return 0;
4636 }
4637
4638 static void
4639 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4640 {
4641         int i;
4642
4643         for (i = 0; i < msix_cnt; ++i) {
4644                 struct igb_msix_data *msix = &sc->msix_data[i];
4645
4646                 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4647         }
4648 }
4649
4650 static void
4651 igb_msix_rx(void *arg)
4652 {
4653         struct igb_rx_ring *rxr = arg;
4654
4655         ASSERT_SERIALIZED(&rxr->rx_serialize);
4656         igb_rxeof(rxr, -1);
4657
4658         E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4659 }
4660
4661 static void
4662 igb_msix_tx(void *arg)
4663 {
4664         struct igb_tx_ring *txr = arg;
4665
4666         ASSERT_SERIALIZED(&txr->tx_serialize);
4667
4668         igb_txeof(txr);
4669         if (!ifsq_is_empty(txr->ifsq))
4670                 ifsq_devstart(txr->ifsq);
4671
4672         E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4673 }
4674
4675 static void
4676 igb_msix_status(void *arg)
4677 {
4678         struct igb_softc *sc = arg;
4679         uint32_t icr;
4680
4681         ASSERT_SERIALIZED(&sc->main_serialize);
4682
4683         icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4684         if (icr & E1000_ICR_LSC) {
4685                 sc->hw.mac.get_link_status = 1;
4686                 igb_update_link_status(sc);
4687         }
4688
4689         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4690 }
4691
4692 static void
4693 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4694 {
4695         sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4696         sc->tx_ring_inuse = igb_get_txring_inuse(sc, polling);
4697         if (bootverbose) {
4698                 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d, TX rings %d/%d\n",
4699                     sc->rx_ring_inuse, sc->rx_ring_cnt,
4700                     sc->tx_ring_inuse, sc->tx_ring_cnt);
4701         }
4702 }
4703
4704 static int
4705 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4706 {
4707         if (!IGB_ENABLE_HWRSS(sc))
4708                 return 1;
4709
4710         if (polling)
4711                 return sc->rx_ring_cnt;
4712         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4713                 return IGB_MIN_RING_RSS;
4714         else
4715                 return sc->rx_ring_msix;
4716 }
4717
4718 static int
4719 igb_get_txring_inuse(const struct igb_softc *sc, boolean_t polling)
4720 {
4721         if (!IGB_ENABLE_HWTSS(sc))
4722                 return 1;
4723
4724         if (polling)
4725                 return sc->tx_ring_cnt;
4726         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4727                 return IGB_MIN_RING;
4728         else
4729                 return sc->tx_ring_msix;
4730 }
4731
4732 static int
4733 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4734 {
4735         int hoff, iphlen, thoff;
4736         struct mbuf *m;
4737
4738         m = *mp;
4739         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4740
4741         iphlen = m->m_pkthdr.csum_iphlen;
4742         thoff = m->m_pkthdr.csum_thlen;
4743         hoff = m->m_pkthdr.csum_lhlen;
4744
4745         KASSERT(iphlen > 0, ("invalid ip hlen"));
4746         KASSERT(thoff > 0, ("invalid tcp hlen"));
4747         KASSERT(hoff > 0, ("invalid ether hlen"));
4748
4749         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4750                 m = m_pullup(m, hoff + iphlen + thoff);
4751                 if (m == NULL) {
4752                         *mp = NULL;
4753                         return ENOBUFS;
4754                 }
4755                 *mp = m;
4756         }
4757         if (txr->tx_flags & IGB_TXFLAG_TSO_IPLEN0) {
4758                 struct ip *ip;
4759
4760                 ip = mtodoff(m, struct ip *, hoff);
4761                 ip->ip_len = 0;
4762         }
4763
4764         return 0;
4765 }
4766
4767 static void
4768 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4769 {
4770         struct e1000_adv_tx_context_desc *TXD;
4771         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4772         int hoff, ctxd, iphlen, thoff;
4773
4774         iphlen = m->m_pkthdr.csum_iphlen;
4775         thoff = m->m_pkthdr.csum_thlen;
4776         hoff = m->m_pkthdr.csum_lhlen;
4777
4778         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4779
4780         ctxd = txr->next_avail_desc;
4781         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4782
4783         if (m->m_flags & M_VLANTAG) {
4784                 uint16_t vlantag;
4785
4786                 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4787                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4788         }
4789
4790         vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4791         vlan_macip_lens |= iphlen;
4792
4793         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4794         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4795         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4796
4797         mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4798         mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4799
4800         /*
4801          * 82575 needs the TX context index added; the queue
4802          * index is used as TX context index here.
4803          */
4804         if (txr->sc->hw.mac.type == e1000_82575)
4805                 mss_l4len_idx |= txr->me << 4;
4806
4807         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4808         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4809         TXD->seqnum_seed = htole32(0);
4810         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4811
4812         /* We've consumed the first desc, adjust counters */
4813         if (++ctxd == txr->num_tx_desc)
4814                 ctxd = 0;
4815         txr->next_avail_desc = ctxd;
4816         --txr->tx_avail;
4817
4818         *hlen = hoff + iphlen + thoff;
4819 }
4820
4821 static void
4822 igb_setup_serializer(struct igb_softc *sc)
4823 {
4824         const struct igb_msix_data *msix;
4825         int i, j;
4826
4827         /*
4828          * Allocate serializer array
4829          */
4830
4831         /* Main + TX + RX */
4832         sc->serialize_cnt = 1 + sc->tx_ring_cnt + sc->rx_ring_cnt;
4833
4834         /* Aggregate TX/RX MSI-X */
4835         for (i = 0; i < sc->msix_cnt; ++i) {
4836                 msix = &sc->msix_data[i];
4837                 if (msix->msix_serialize == &msix->msix_serialize0)
4838                         sc->serialize_cnt++;
4839         }
4840
4841         sc->serializes =
4842             kmalloc(sc->serialize_cnt * sizeof(struct lwkt_serialize *),
4843                 M_DEVBUF, M_WAITOK | M_ZERO);
4844
4845         /*
4846          * Setup serializers
4847          *
4848          * NOTE: Order is critical
4849          */
4850
4851         i = 0;
4852
4853         KKASSERT(i < sc->serialize_cnt);
4854         sc->serializes[i++] = &sc->main_serialize;
4855
4856         for (j = 0; j < sc->msix_cnt; ++j) {
4857                 msix = &sc->msix_data[j];
4858                 if (msix->msix_serialize == &msix->msix_serialize0) {
4859                         KKASSERT(i < sc->serialize_cnt);
4860                         sc->serializes[i++] = msix->msix_serialize;
4861                 }
4862         }
4863
4864         for (j = 0; j < sc->tx_ring_cnt; ++j) {
4865                 KKASSERT(i < sc->serialize_cnt);
4866                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
4867         }
4868
4869         for (j = 0; j < sc->rx_ring_cnt; ++j) {
4870                 KKASSERT(i < sc->serialize_cnt);
4871                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
4872         }
4873
4874         KKASSERT(i == sc->serialize_cnt);
4875 }
4876
4877 static void
4878 igb_msix_rx_conf(struct igb_softc *sc, int i, int *x0, int offset)
4879 {
4880         int x = *x0;
4881
4882         for (; i < sc->rx_ring_msix; ++i) {
4883                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4884                 struct igb_msix_data *msix;
4885
4886                 KKASSERT(x < sc->msix_cnt);
4887                 msix = &sc->msix_data[x++];
4888
4889                 rxr->rx_intr_bit = msix->msix_vector;
4890                 rxr->rx_intr_mask = msix->msix_mask;
4891
4892                 msix->msix_serialize = &rxr->rx_serialize;
4893                 msix->msix_func = igb_msix_rx;
4894                 msix->msix_arg = rxr;
4895
4896                 msix->msix_cpuid = i + offset;
4897                 KKASSERT(msix->msix_cpuid < ncpus2);
4898
4899                 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s rx%d",
4900                     device_get_nameunit(sc->dev), i);
4901
4902                 msix->msix_rate = IGB_MSIX_RX_RATE;
4903                 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4904                     "RX%d interrupt rate", i);
4905         }
4906         *x0 = x;
4907 }
4908
4909 static void
4910 igb_msix_tx_conf(struct igb_softc *sc, int i, int *x0, int offset)
4911 {
4912         int x = *x0;
4913
4914         for (; i < sc->tx_ring_msix; ++i) {
4915                 struct igb_tx_ring *txr = &sc->tx_rings[i];
4916                 struct igb_msix_data *msix;
4917
4918                 KKASSERT(x < sc->msix_cnt);
4919                 msix = &sc->msix_data[x++];
4920
4921                 txr->tx_intr_bit = msix->msix_vector;
4922                 txr->tx_intr_mask = msix->msix_mask;
4923
4924                 msix->msix_serialize = &txr->tx_serialize;
4925                 msix->msix_func = igb_msix_tx;
4926                 msix->msix_arg = txr;
4927
4928                 msix->msix_cpuid = i + offset;
4929                 KKASSERT(msix->msix_cpuid < ncpus2);
4930                 txr->tx_intr_cpuid = msix->msix_cpuid;
4931
4932                 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s tx%d",
4933                     device_get_nameunit(sc->dev), i);
4934
4935                 msix->msix_rate = IGB_MSIX_TX_RATE;
4936                 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4937                     "TX%d interrupt rate", i);
4938         }
4939         *x0 = x;
4940 }
4941
4942 static void
4943 igb_msix_rxtx(void *arg)
4944 {
4945         struct igb_msix_data *msix = arg;
4946         struct igb_rx_ring *rxr = msix->msix_rx;
4947         struct igb_tx_ring *txr = msix->msix_tx;
4948
4949         ASSERT_SERIALIZED(&msix->msix_serialize0);
4950
4951         lwkt_serialize_enter(&rxr->rx_serialize);
4952         igb_rxeof(rxr, -1);
4953         lwkt_serialize_exit(&rxr->rx_serialize);
4954
4955         lwkt_serialize_enter(&txr->tx_serialize);
4956         igb_txeof(txr);
4957         if (!ifsq_is_empty(txr->ifsq))
4958                 ifsq_devstart(txr->ifsq);
4959         lwkt_serialize_exit(&txr->tx_serialize);
4960
4961         E1000_WRITE_REG(&msix->msix_sc->hw, E1000_EIMS, msix->msix_mask);
4962 }
4963
4964 static void
4965 igb_set_timer_cpuid(struct igb_softc *sc, boolean_t polling)
4966 {
4967         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
4968                 sc->timer_cpuid = 0; /* XXX fixed */
4969         else
4970                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
4971 }