2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
27 * $FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.3.2.12 2003/01/20 03:59:42 orion Exp $
28 * $DragonFly: src/sys/dev/sound/pci/ich.c,v 1.5 2003/08/24 17:55:21 drhodus Exp $
31 #include <dev/sound/pcm/sound.h>
32 #include <dev/sound/pcm/ac97.h>
33 #include <dev/sound/pci/ich.h>
35 #include <bus/pci/pcireg.h>
36 #include <bus/pci/pcivar.h>
38 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/ich.c,v 1.5 2003/08/24 17:55:21 drhodus Exp $");
40 /* -------------------------------------------------------------------- */
42 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
43 #define ICH_DTBL_LENGTH 32
44 #define ICH_DEFAULT_BUFSZ 16384
45 #define ICH_MAX_BUFSZ 65536
47 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */
48 #define ICH4ID 0x24c58086 /* ICH4 needs special handling too */
49 #define ICH5ID 0x24d58086 /* ICH5 needs to be treated as ICH4 */
51 /* buffer descriptor */
53 volatile u_int32_t buffer;
54 volatile u_int32_t length;
59 /* channel registers */
61 u_int32_t num:8, run:1, run_save:1;
62 u_int32_t blksz, blkcnt, spd;
63 u_int32_t regbase, spdreg;
67 struct snd_dbuf *buffer;
68 struct pcm_channel *channel;
69 struct sc_info *parent;
71 struct ich_desc *dtbl;
74 /* device private data */
77 int hasvra, hasvrm, hasmic;
78 unsigned int chnum, bufsz;
79 int sample_size, swap_reg;
81 struct resource *nambar, *nabmbar, *irq;
82 int regtype, nambarid, nabmbarid, irqid;
83 bus_space_tag_t nambart, nabmbart;
84 bus_space_handle_t nambarh, nabmbarh;
89 struct ac97_info *codec;
90 struct sc_chinfo ch[3];
92 struct ich_desc *dtbl;
93 struct intr_config_hook intrhook;
97 /* -------------------------------------------------------------------- */
99 static u_int32_t ich_fmt[] = {
100 AFMT_STEREO | AFMT_S16_LE,
103 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
104 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
106 /* -------------------------------------------------------------------- */
109 ich_rd(struct sc_info *sc, int regno, int size)
113 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno);
115 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno);
117 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno);
124 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
128 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
131 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
134 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
141 ich_waitcd(void *devinfo)
145 struct sc_info *sc = (struct sc_info *)devinfo;
147 for (i = 0; i < ICH_TIMEOUT; i++) {
148 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
149 if ((data & 0x01) == 0)
152 device_printf(sc->dev, "CODEC semaphore timeout\n");
157 ich_rdcd(kobj_t obj, void *devinfo, int regno)
159 struct sc_info *sc = (struct sc_info *)devinfo;
164 return bus_space_read_2(sc->nambart, sc->nambarh, regno);
168 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data)
170 struct sc_info *sc = (struct sc_info *)devinfo;
174 bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
179 static kobj_method_t ich_ac97_methods[] = {
180 KOBJMETHOD(ac97_read, ich_rdcd),
181 KOBJMETHOD(ac97_write, ich_wrcd),
184 AC97_DECLARE(ich_ac97);
186 /* -------------------------------------------------------------------- */
187 /* common routines */
190 ich_filldtbl(struct sc_chinfo *ch)
195 base = vtophys(sndbuf_getbuf(ch->buffer));
196 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz;
197 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) {
199 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt;
202 for (i = 0; i < ICH_DTBL_LENGTH; i++) {
203 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
204 ch->dtbl[i].length = ICH_BDC_IOC
205 | (ch->blksz / ch->parent->sample_size);
210 ich_resetchan(struct sc_info *sc, int num)
215 regbase = ICH_REG_PO_BASE;
217 regbase = ICH_REG_PI_BASE;
219 regbase = ICH_REG_MC_BASE;
223 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
225 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
226 for (i = 0; i < ICH_TIMEOUT; i++) {
227 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
232 device_printf(sc->dev, "cannot reset channel %d\n", num);
236 /* -------------------------------------------------------------------- */
237 /* channel interface */
240 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
242 struct sc_info *sc = devinfo;
243 struct sc_chinfo *ch;
253 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
255 ch->blksz = sc->bufsz / ch->blkcnt;
259 KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
260 ch->regbase = ICH_REG_PO_BASE;
261 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0;
262 ch->imask = ICH_GLOB_STA_POINT;
266 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
267 ch->regbase = ICH_REG_PI_BASE;
268 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0;
269 ch->imask = ICH_GLOB_STA_PIINT;
273 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
274 ch->regbase = ICH_REG_MC_BASE;
275 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0;
276 ch->imask = ICH_GLOB_STA_MINT;
283 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz))
286 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
292 ichchan_setformat(kobj_t obj, void *data, u_int32_t format)
298 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
300 struct sc_chinfo *ch = data;
301 struct sc_info *sc = ch->parent;
305 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
306 sc->ac97rate = 48000;
307 r = (speed * 48000) / sc->ac97rate;
309 * Cast the return value of ac97_setrate() to u_int so that
310 * the math don't overflow into the negative range.
312 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) *
313 sc->ac97rate) / 48000;
321 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
323 struct sc_chinfo *ch = data;
324 struct sc_info *sc = ch->parent;
326 ch->blksz = blocksize;
328 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
334 ichchan_trigger(kobj_t obj, void *data, int go)
336 struct sc_chinfo *ch = data;
337 struct sc_info *sc = ch->parent;
342 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
343 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
347 ich_resetchan(sc, ch->num);
355 ichchan_getptr(kobj_t obj, void *data)
357 struct sc_chinfo *ch = data;
358 struct sc_info *sc = ch->parent;
361 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
363 pos = ch->civ * ch->blksz;
368 static struct pcmchan_caps *
369 ichchan_getcaps(kobj_t obj, void *data)
371 struct sc_chinfo *ch = data;
373 return ch->spdreg? &ich_vrcaps : &ich_caps;
376 static kobj_method_t ichchan_methods[] = {
377 KOBJMETHOD(channel_init, ichchan_init),
378 KOBJMETHOD(channel_setformat, ichchan_setformat),
379 KOBJMETHOD(channel_setspeed, ichchan_setspeed),
380 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
381 KOBJMETHOD(channel_trigger, ichchan_trigger),
382 KOBJMETHOD(channel_getptr, ichchan_getptr),
383 KOBJMETHOD(channel_getcaps, ichchan_getcaps),
386 CHANNEL_DECLARE(ichchan);
388 /* -------------------------------------------------------------------- */
389 /* The interrupt handler */
394 struct sc_info *sc = (struct sc_info *)p;
395 struct sc_chinfo *ch;
396 u_int32_t cbi, lbi, lvi, st, gs;
399 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
400 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
401 /* Clear resume interrupt(s) - nothing doing with them */
402 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
404 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
406 for (i = 0; i < 3; i++) {
408 if ((ch->imask & gs) == 0)
411 st = ich_rd(sc, ch->regbase +
412 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
414 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
415 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
416 /* block complete - update buffer */
418 chn_intr(ch->channel);
419 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
420 cbi = ch->civ % ch->blkcnt;
422 cbi = ch->blkcnt - 1;
425 lbi = lvi % ch->blkcnt;
429 lvi += cbi + ch->blkcnt - lbi;
430 lvi %= ICH_DTBL_LENGTH;
431 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
434 /* clear status bit */
435 ich_wr(sc, ch->regbase +
436 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
440 device_printf(sc->dev,
441 "Unhandled interrupt, gs_intr = %x\n", gs);
445 /* ------------------------------------------------------------------------- */
447 * Sysctl to control ac97 speed (some boards appear to end up using
448 * XTAL_IN rather than BIT_CLK for link timing).
453 ich_initsys(struct sc_info* sc)
456 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
457 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
458 OID_AUTO, "ac97rate", CTLFLAG_RW,
459 &sc->ac97rate, 48000,
460 "AC97 link rate (default = 48000)");
461 #endif /* SND_DYNSYSCTL */
465 /* -------------------------------------------------------------------- */
466 /* Calibrate card to determine the clock source. The source maybe a
467 * function of the ac97 codec initialization code (to be investigated).
471 void ich_calibrate(void *arg)
474 struct sc_chinfo *ch;
475 struct timeval t1, t2;
477 u_int32_t wait_us, actual_48k_rate, bytes;
479 sc = (struct sc_info *)arg;
482 if (sc->use_intrhook)
483 config_intrhook_disestablish(&sc->intrhook);
486 * Grab audio from input for fixed interval and compare how
487 * much we actually get with what we expect. Interval needs
488 * to be sufficiently short that no interrupts are
492 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
494 bytes = sndbuf_getsize(ch->buffer) / 2;
495 ichchan_setblocksize(0, ch, bytes);
498 * our data format is stereo, 16 bit so each sample is 4 bytes.
499 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
500 * we're going to start recording with interrupts disabled and measure
501 * the time taken for one block to complete. we know the block size,
502 * we know the time in microseconds, we calculate the sample rate:
504 * actual_rate [bps] = bytes / (time [s] * 4)
505 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
506 * actual_rate [Hz] = (bytes * 250000) / time [us]
510 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
512 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
516 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
519 while (nciv == ociv) {
521 if (t2.tv_sec - t1.tv_sec > 1)
523 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
528 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
532 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
534 /* turn time delta into us */
535 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
538 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
542 actual_48k_rate = (bytes * 250000) / wait_us;
544 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
545 sc->ac97rate = actual_48k_rate;
547 sc->ac97rate = 48000;
550 if (bootverbose || sc->ac97rate != 48000) {
551 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
552 if (sc->ac97rate != actual_48k_rate)
553 printf(", will use %d Hz", sc->ac97rate);
559 /* -------------------------------------------------------------------- */
560 /* Probe and attach the card */
563 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
569 ich_init(struct sc_info *sc)
574 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
576 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
578 if ((stat & ICH_GLOB_STA_PCR) == 0) {
579 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */
580 if ((pci_get_devid(sc->dev) != ICH4ID) &&
581 (pci_get_devid(sc->dev) != ICH5ID)) {
586 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
588 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
590 if (sc->hasmic && ich_resetchan(sc, 2))
593 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap))
596 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3;
597 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) {
598 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap);
606 ich_pci_probe(device_t dev)
608 switch(pci_get_devid(dev)) {
610 device_set_desc(dev, "Intel 443MX");
614 device_set_desc(dev, "Intel ICH (82801AA)");
618 device_set_desc(dev, "Intel ICH (82801AB)");
622 device_set_desc(dev, "Intel ICH2 (82801BA)");
626 device_set_desc(dev, "Intel ICH3 (82801CA)");
630 device_set_desc(dev, "Intel ICH4 (82801DB)");
631 return -1000; /* allow a better driver to override us */
634 device_set_desc(dev, "Intel ICH5 (82801EB)");
635 return -1000; /* allow a better driver to override us */
638 device_set_desc(dev, "SiS 7012");
642 device_set_desc(dev, "Nvidia nForce");
646 device_set_desc(dev, "Nvidia nForce2");
650 device_set_desc(dev, "AMD-768");
659 ich_pci_attach(device_t dev)
663 char status[SND_STATUSLEN];
665 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
666 device_printf(dev, "cannot allocate softc\n");
670 bzero(sc, sizeof(*sc));
674 * The SiS 7012 register set isn't quite like the standard ich.
675 * There really should be a general "quirks" mechanism.
677 if (pci_get_devid(dev) == SIS7012ID) {
686 * Enable bus master. On ich4/5 this may prevent the detection of
687 * the primary codec becoming ready in ich_init().
689 pci_enable_busmaster(dev);
691 if ((pci_get_devid(dev) == ICH4ID) || (pci_get_devid(dev) == ICH5ID)) {
692 sc->nambarid = PCIR_MMBAR;
693 sc->nabmbarid = PCIR_MBBAR;
694 sc->regtype = SYS_RES_MEMORY;
695 pci_enable_io(dev, SYS_RES_MEMORY);
697 sc->nambarid = PCIR_NAMBAR;
698 sc->nabmbarid = PCIR_NABMBAR;
699 sc->regtype = SYS_RES_IOPORT;
700 pci_enable_io(dev, SYS_RES_IOPORT);
703 sc->nambar = bus_alloc_resource(dev, sc->regtype, &sc->nambarid, 0, ~0, 1, RF_ACTIVE);
704 sc->nabmbar = bus_alloc_resource(dev, sc->regtype, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE);
706 if (!sc->nambar || !sc->nabmbar) {
707 device_printf(dev, "unable to map IO port space\n");
711 sc->nambart = rman_get_bustag(sc->nambar);
712 sc->nambarh = rman_get_bushandle(sc->nambar);
713 sc->nabmbart = rman_get_bustag(sc->nabmbar);
714 sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
716 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
717 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
718 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) {
719 device_printf(dev, "unable to create dma tag\n");
724 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
725 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) {
726 device_printf(dev, "unable to map interrupt\n");
731 device_printf(dev, "unable to initialize the card\n");
735 sc->codec = AC97_CREATE(dev, sc, ich_ac97);
736 if (sc->codec == NULL)
738 mixer_init(dev, ac97_getmixerclass(), sc->codec);
740 /* check and set VRA function */
741 extcaps = ac97_getextcaps(sc->codec);
742 sc->hasvra = extcaps & AC97_EXTCAP_VRA;
743 sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
744 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL;
745 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
747 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1))
750 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
751 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
753 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
755 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u",
756 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz);
758 pcm_setstatus(dev, status);
762 sc->intrhook.ich_func = ich_calibrate;
763 sc->intrhook.ich_arg = sc;
764 sc->use_intrhook = 1;
765 if (config_intrhook_establish(&sc->intrhook) != 0) {
766 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n");
767 sc->use_intrhook = 0;
775 ac97_destroy(sc->codec);
777 bus_teardown_intr(dev, sc->irq, sc->ih);
779 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
781 bus_release_resource(dev, sc->regtype,
782 sc->nambarid, sc->nambar);
784 bus_release_resource(dev, sc->regtype,
785 sc->nabmbarid, sc->nabmbar);
791 ich_pci_detach(device_t dev)
796 r = pcm_unregister(dev);
799 sc = pcm_getdevinfo(dev);
801 bus_teardown_intr(dev, sc->irq, sc->ih);
802 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
803 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
804 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
805 bus_dma_tag_destroy(sc->dmat);
811 ich_pci_suspend(device_t dev)
816 sc = pcm_getdevinfo(dev);
817 for (i = 0 ; i < 3; i++) {
818 sc->ch[i].run_save = sc->ch[i].run;
820 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
827 ich_pci_resume(device_t dev)
832 sc = pcm_getdevinfo(dev);
834 /* Reinit audio device */
835 if (ich_init(sc) == -1) {
836 device_printf(dev, "unable to reinitialize the card\n");
840 if (mixer_reinit(dev) == -1) {
841 device_printf(dev, "unable to reinitialize the mixer\n");
844 /* Re-start DMA engines */
845 for (i = 0 ; i < 3; i++) {
846 struct sc_chinfo *ch = &sc->ch[i];
847 if (sc->ch[i].run_save) {
848 ichchan_setblocksize(0, ch, ch->blksz);
849 ichchan_setspeed(0, ch, ch->spd);
850 ichchan_trigger(0, ch, PCMTRIG_START);
856 static device_method_t ich_methods[] = {
857 /* Device interface */
858 DEVMETHOD(device_probe, ich_pci_probe),
859 DEVMETHOD(device_attach, ich_pci_attach),
860 DEVMETHOD(device_detach, ich_pci_detach),
861 DEVMETHOD(device_suspend, ich_pci_suspend),
862 DEVMETHOD(device_resume, ich_pci_resume),
866 static driver_t ich_driver = {
872 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
873 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
874 MODULE_VERSION(snd_ich, 1);